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Handle function aliases better (PR gdb/19487, errno printing)
[deliverable/binutils-gdb.git] / opcodes / ppc-opc.c
CommitLineData
252b5132 1/* ppc-opc.c -- PowerPC opcode list
2571583a 2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
252b5132
RH		 3 Written by Ian Lance Taylor, Cygnus Support
4
9b201bb5 5 This file is part of the GNU opcodes library.
252b5132 6
9b201bb5
NC		 7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
252b5132 11
9b201bb5
NC		 12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
252b5132 16
112290ab 17 You should have received a copy of the GNU General Public License
9b201bb5
NC		 18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
252b5132 21
0d8dfecf 22#include "sysdep.h"
df7b86aa 23#include <stdio.h>
252b5132
RH		 24#include "opcode/ppc.h"
25#include "opintl.h"
26
27/* This file holds the PowerPC opcode table. The opcode table
28 includes almost all of the extended instruction mnemonics. This
29 permits the disassembler to use them, and simplifies the assembler
30 logic, at the cost of increasing the table size. The table is
31 strictly constant data, so the compiler should be able to put it in
32 the .text section.
33
34 This file also holds the operand table. All knowledge about
35 inserting operands into instructions and vice-versa is kept in this
36 file. */
37\f
38/* Local insertion and extraction functions. */
39
b9c361e0
JL		 40static unsigned long insert_arx (unsigned long, long, ppc_cpu_t, const char **);
41static long extract_arx (unsigned long, ppc_cpu_t, int *);
42static unsigned long insert_ary (unsigned long, long, ppc_cpu_t, const char **);
43static long extract_ary (unsigned long, ppc_cpu_t, int *);
fa452fa6
PB		 44static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **);
45static long extract_bat (unsigned long, ppc_cpu_t, int *);
46static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **);
47static long extract_bba (unsigned long, ppc_cpu_t, int *);
48static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **);
49static long extract_bdm (unsigned long, ppc_cpu_t, int *);
50static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **);
51static long extract_bdp (unsigned long, ppc_cpu_t, int *);
52static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **);
53static long extract_bo (unsigned long, ppc_cpu_t, int *);
54static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **);
55static long extract_boe (unsigned long, ppc_cpu_t, int *);
7b934113 56static unsigned long insert_esync (unsigned long, long, ppc_cpu_t, const char **);
73f07bff 57static long extract_esync (unsigned long, ppc_cpu_t, int *);
a680de9a
PB		 58static unsigned long insert_dcmxs (unsigned long, long, ppc_cpu_t, const char **);
59static long extract_dcmxs (unsigned long, ppc_cpu_t, int *);
60static unsigned long insert_dxd (unsigned long, long, ppc_cpu_t, const char **);
61static long extract_dxd (unsigned long, ppc_cpu_t, int *);
62static unsigned long insert_dxdn (unsigned long, long, ppc_cpu_t, const char **);
63static long extract_dxdn (unsigned long, ppc_cpu_t, int *);
fa452fa6
PB		 64static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
65static long extract_fxm (unsigned long, ppc_cpu_t, int *);
b9c361e0
JL		 66static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **);
67static long extract_li20 (unsigned long, ppc_cpu_t, int *);
aea77599 68static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **);
73f07bff 69static long extract_ls (unsigned long, ppc_cpu_t, int *);
fa452fa6
PB		 70static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **);
71static long extract_mbe (unsigned long, ppc_cpu_t, int *);
72static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **);
73static long extract_mb6 (unsigned long, ppc_cpu_t, int *);
74static long extract_nb (unsigned long, ppc_cpu_t, int *);
989993d8 75static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t, const char **);
fa452fa6
PB		 76static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **);
77static long extract_nsi (unsigned long, ppc_cpu_t, int *);
b9c361e0
JL		 78static unsigned long insert_oimm (unsigned long, long, ppc_cpu_t, const char **);
79static long extract_oimm (unsigned long, ppc_cpu_t, int *);
fa452fa6 80static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **);
73f07bff 81static long extract_ral (unsigned long, ppc_cpu_t, int *);
fa452fa6 82static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **);
73f07bff 83static long extract_ram (unsigned long, ppc_cpu_t, int *);
fa452fa6 84static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **);
73f07bff 85static long extract_raq (unsigned long, ppc_cpu_t, int *);
fa452fa6 86static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **);
73f07bff 87static long extract_ras (unsigned long, ppc_cpu_t, int *);
fa452fa6
PB		 88static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **);
89static long extract_rbs (unsigned long, ppc_cpu_t, int *);
989993d8 90static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t, const char **);
73f07bff 91static long extract_rbx (unsigned long, ppc_cpu_t, int *);
b9c361e0
JL		 92static unsigned long insert_rx (unsigned long, long, ppc_cpu_t, const char **);
93static long extract_rx (unsigned long, ppc_cpu_t, int *);
94static unsigned long insert_ry (unsigned long, long, ppc_cpu_t, const char **);
95static long extract_ry (unsigned long, ppc_cpu_t, int *);
fa452fa6
PB		 96static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **);
97static long extract_sh6 (unsigned long, ppc_cpu_t, int *);
b9c361e0
JL		 98static unsigned long insert_sci8 (unsigned long, long, ppc_cpu_t, const char **);
99static long extract_sci8 (unsigned long, ppc_cpu_t, int *);
100static unsigned long insert_sci8n (unsigned long, long, ppc_cpu_t, const char **);
101static long extract_sci8n (unsigned long, ppc_cpu_t, int *);
102static unsigned long insert_sd4h (unsigned long, long, ppc_cpu_t, const char **);
103static long extract_sd4h (unsigned long, ppc_cpu_t, int *);
104static unsigned long insert_sd4w (unsigned long, long, ppc_cpu_t, const char **);
105static long extract_sd4w (unsigned long, ppc_cpu_t, int *);
fa452fa6
PB		 106static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **);
107static long extract_spr (unsigned long, ppc_cpu_t, int *);
108static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **);
109static long extract_sprg (unsigned long, ppc_cpu_t, int *);
110static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **);
111static long extract_tbr (unsigned long, ppc_cpu_t, int *);
9b4e5766
PB		 112static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **);
113static long extract_xt6 (unsigned long, ppc_cpu_t, int *);
a680de9a
PB		 114static unsigned long insert_xtq6 (unsigned long, long, ppc_cpu_t, const char **);
115static long extract_xtq6 (unsigned long, ppc_cpu_t, int *);
9b4e5766
PB		 116static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **);
117static long extract_xa6 (unsigned long, ppc_cpu_t, int *);
118static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **);
119static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
120static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
121static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
066be9f7
PB		 122static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **);
123static long extract_xc6 (unsigned long, ppc_cpu_t, int *);
124static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **);
125static long extract_dm (unsigned long, ppc_cpu_t, int *);
b9c361e0
JL		 126static unsigned long insert_vlesi (unsigned long, long, ppc_cpu_t, const char **);
127static long extract_vlesi (unsigned long, ppc_cpu_t, int *);
128static unsigned long insert_vlensi (unsigned long, long, ppc_cpu_t, const char **);
129static long extract_vlensi (unsigned long, ppc_cpu_t, int *);
130static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t, const char **);
131static long extract_vleui (unsigned long, ppc_cpu_t, int *);
132static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t, const char **);
133static long extract_vleil (unsigned long, ppc_cpu_t, int *);
252b5132
RH		 134\f
135/* The operands table.
136
717bbdf1 137 The fields are bitm, shift, insert, extract, flags.
252b5132
RH		 138
139 We used to put parens around the various additions, like the one
140 for BA just below. However, that caused trouble with feeble
141 compilers with a limit on depth of a parenthesized expression, like
142 (reportedly) the compiler in Microsoft Developer Studio 5. So we
143 omit the parens, since the macros are never used in a context where
144 the addition will be ambiguous. */
145
146const struct powerpc_operand powerpc_operands[] =
147{
148 /* The zero index is used to indicate the end of the list of
149 operands. */
150#define UNUSED 0
bbac1f2a 151 { 0, 0, NULL, NULL, 0 },
252b5132
RH		 152
153 /* The BA field in an XL form instruction. */
154#define BA UNUSED + 1
717bbdf1
AM		 155 /* The BI field in a B form or XL form instruction. */
156#define BI BA
157#define BI_MASK (0x1f << 16)
b9c361e0 158 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
252b5132
RH		 159
160 /* The BA field in an XL form instruction when it must be the same
161 as the BT field in the same instruction. */
162#define BAT BA + 1
b84bf58a 163 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
252b5132
RH		 164
165 /* The BB field in an XL form instruction. */
166#define BB BAT + 1
167#define BB_MASK (0x1f << 11)
b9c361e0 168 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT },
252b5132
RH		 169
170 /* The BB field in an XL form instruction when it must be the same
171 as the BA field in the same instruction. */
172#define BBA BB + 1
c7a5aa9c
PB		 173 /* The VB field in a VX form instruction when it must be the same
174 as the VA field in the same instruction. */
175#define VBA BBA
b84bf58a 176 { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
252b5132
RH		 177
178 /* The BD field in a B form instruction. The lower two bits are
179 forced to zero. */
180#define BD BBA + 1
b84bf58a 181 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 182
183 /* The BD field in a B form instruction when absolute addressing is
184 used. */
185#define BDA BD + 1
b84bf58a 186 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 187
188 /* The BD field in a B form instruction when the - modifier is used.
189 This sets the y bit of the BO field appropriately. */
190#define BDM BDA + 1
b84bf58a 191 { 0xfffc, 0, insert_bdm, extract_bdm,
e43de63c 192 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 193
194 /* The BD field in a B form instruction when the - modifier is used
195 and absolute address is used. */
196#define BDMA BDM + 1
b84bf58a 197 { 0xfffc, 0, insert_bdm, extract_bdm,
e43de63c 198 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 199
200 /* The BD field in a B form instruction when the + modifier is used.
201 This sets the y bit of the BO field appropriately. */
202#define BDP BDMA + 1
b84bf58a 203 { 0xfffc, 0, insert_bdp, extract_bdp,
e43de63c 204 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 205
206 /* The BD field in a B form instruction when the + modifier is used
207 and absolute addressing is used. */
208#define BDPA BDP + 1
b84bf58a 209 { 0xfffc, 0, insert_bdp, extract_bdp,
e43de63c 210 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 211
212 /* The BF field in an X or XL form instruction. */
213#define BF BDPA + 1
717bbdf1
AM		 214 /* The CRFD field in an X form instruction. */
215#define CRFD BF
b9c361e0
JL		 216 /* The CRD field in an XL form instruction. */
217#define CRD BF
218 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG },
252b5132 219
ea192fa3
PB		 220 /* The BF field in an X or XL form instruction. */
221#define BFF BF + 1
222 { 0x7, 23, NULL, NULL, 0 },
223
252b5132
RH		 224 /* An optional BF field. This is used for comparison instructions,
225 in which an omitted BF field is taken as zero. */
ea192fa3 226#define OBF BFF + 1
b9c361e0 227 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
252b5132
RH		 228
229 /* The BFA field in an X or XL form instruction. */
230#define BFA OBF + 1
b9c361e0 231 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG },
252b5132 232
252b5132
RH		 233 /* The BO field in a B form instruction. Certain values are
234 illegal. */
717bbdf1 235#define BO BFA + 1
252b5132 236#define BO_MASK (0x1f << 21)
b84bf58a 237 { 0x1f, 21, insert_bo, extract_bo, 0 },
252b5132
RH		 238
239 /* The BO field in a B form instruction when the + or - modifier is
240 used. This is like the BO field, but it must be even. */
241#define BOE BO + 1
b84bf58a 242 { 0x1e, 21, insert_boe, extract_boe, 0 },
252b5132 243
6fd3a02d
PB		 244 /* The RM field in an X form instruction. */
245#define RM BOE + 1
246 { 0x3, 11, NULL, NULL, 0 },
247
248#define BH RM + 1
b84bf58a 249 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
d0618d1c 250
252b5132 251 /* The BT field in an X or XL form instruction. */
d0618d1c 252#define BT BH + 1
b9c361e0
JL		 253 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT },
254
255 /* The BI16 field in a BD8 form instruction. */
256#define BI16 BT + 1
257 { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT },
258
259 /* The BI32 field in a BD15 form instruction. */
260#define BI32 BI16 + 1
261 { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
262
263 /* The BO32 field in a BD15 form instruction. */
264#define BO32 BI32 + 1
265 { 0x3, 20, NULL, NULL, 0 },
266
267 /* The B8 field in a BD8 form instruction. */
268#define B8 BO32 + 1
269 { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
270
271 /* The B15 field in a BD15 form instruction. The lowest bit is
272 forced to zero. */
273#define B15 B8 + 1
274 { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
275
276 /* The B24 field in a BD24 form instruction. The lowest bit is
277 forced to zero. */
278#define B24 B15 + 1
279 { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 280
281 /* The condition register number portion of the BI field in a B form
282 or XL form instruction. This is used for the extended
283 conditional branch mnemonics, which set the lower two bits of the
284 BI field. This field is optional. */
b9c361e0
JL		 285#define CR B24 + 1
286 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
252b5132 287
23976049
EZ		 288 /* The CRB field in an X form instruction. */
289#define CRB CR + 1
717bbdf1
AM		 290 /* The MB field in an M form instruction. */
291#define MB CRB
292#define MB_MASK (0x1f << 6)
b84bf58a 293 { 0x1f, 6, NULL, NULL, 0 },
23976049 294
b9c361e0
JL		 295 /* The CRD32 field in an XL form instruction. */
296#define CRD32 CRB + 1
297 { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG },
298
23976049 299 /* The CRFS field in an X form instruction. */
b9c361e0
JL		 300#define CRFS CRD32 + 1
301 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG },
302
303#define CRS CRFS + 1
304 { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
23976049 305
418c1742 306 /* The CT field in an X form instruction. */
b9c361e0 307#define CT CRS + 1
717bbdf1
AM		 308 /* The MO field in an mbar instruction. */
309#define MO CT
b84bf58a 310 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
418c1742 311
252b5132
RH		 312 /* The D field in a D form instruction. This is a displacement off
313 a register, and implies that the next operand is a register in
314 parentheses. */
418c1742 315#define D CT + 1
b84bf58a 316 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
252b5132 317
b9c361e0
JL		 318 /* The D8 field in a D form instruction. This is a displacement off
319 a register, and implies that the next operand is a register in
320 parentheses. */
321#define D8 D + 1
322 { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
323
a680de9a
PB		 324 /* The DCMX field in an X form instruction. */
325#define DCMX D8 + 1
326 { 0x7f, 16, NULL, NULL, 0 },
327
328 /* The split DCMX field in an X form instruction. */
329#define DCMXS DCMX + 1
330 { 0x7f, PPC_OPSHIFT_INV, insert_dcmxs, extract_dcmxs, 0 },
331
adadcc0c
AM		 332 /* The DQ field in a DQ form instruction. This is like D, but the
333 lower four bits are forced to zero. */
a680de9a 334#define DQ DCMXS + 1
b84bf58a
AM		 335 { 0xfff0, 0, NULL, NULL,
336 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
adadcc0c 337
252b5132
RH		 338 /* The DS field in a DS form instruction. This is like D, but the
339 lower two bits are forced to zero. */
adadcc0c 340#define DS DQ + 1
b84bf58a
AM		 341 { 0xfffc, 0, NULL, NULL,
342 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
252b5132 343
c0637f3a
PB		 344 /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits
345 unsigned imediate */
19a6653c 346#define DUIS DS + 1
c0637f3a 347#define BHRBE DUIS
19a6653c
AM		 348 { 0x3ff, 11, NULL, NULL, 0 },
349
a680de9a
PB		 350 /* The split D field in a DX form instruction. */
351#define DXD DUIS + 1
352 { 0xffff, PPC_OPSHIFT_INV, insert_dxd, extract_dxd,
353 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
354
355 /* The split ND field in a DX form instruction.
356 This is the same as the DX field, only negated. */
357#define NDXD DXD + 1
358 { 0xffff, PPC_OPSHIFT_INV, insert_dxdn, extract_dxdn,
359 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
360
252b5132 361 /* The E field in a wrteei instruction. */
c3d65c1c 362 /* And the W bit in the pair singles instructions. */
c0637f3a 363 /* And the ST field in a VX form instruction. */
a680de9a 364#define E NDXD + 1
c3d65c1c 365#define PSW E
c0637f3a 366#define ST E
b84bf58a 367 { 0x1, 15, NULL, NULL, 0 },
252b5132
RH		 368
369 /* The FL1 field in a POWER SC form instruction. */
370#define FL1 E + 1
717bbdf1
AM		 371 /* The U field in an X form instruction. */
372#define U FL1
b84bf58a 373 { 0xf, 12, NULL, NULL, 0 },
252b5132
RH		 374
375 /* The FL2 field in a POWER SC form instruction. */
376#define FL2 FL1 + 1
b84bf58a 377 { 0x7, 2, NULL, NULL, 0 },
252b5132
RH		 378
379 /* The FLM field in an XFL form instruction. */
380#define FLM FL2 + 1
b84bf58a 381 { 0xff, 17, NULL, NULL, 0 },
252b5132
RH		 382
383 /* The FRA field in an X or A form instruction. */
384#define FRA FLM + 1
385#define FRA_MASK (0x1f << 16)
b84bf58a 386 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
252b5132 387
989993d8
JB		 388 /* The FRAp field of DFP instructions. */
389#define FRAp FRA + 1
390 { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR },
391
252b5132 392 /* The FRB field in an X or A form instruction. */
989993d8 393#define FRB FRAp + 1
252b5132 394#define FRB_MASK (0x1f << 11)
b84bf58a 395 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
252b5132 396
989993d8
JB		 397 /* The FRBp field of DFP instructions. */
398#define FRBp FRB + 1
399 { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR },
400
252b5132 401 /* The FRC field in an A form instruction. */
989993d8 402#define FRC FRBp + 1
252b5132 403#define FRC_MASK (0x1f << 6)
b84bf58a 404 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 405
406 /* The FRS field in an X form instruction or the FRT field in a D, X
407 or A form instruction. */
408#define FRS FRC + 1
409#define FRT FRS
b84bf58a 410 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
252b5132 411
989993d8
JB		 412 /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
413 instructions. */
414#define FRSp FRS + 1
415#define FRTp FRSp
416 { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR },
417
252b5132 418 /* The FXM field in an XFX instruction. */
989993d8 419#define FXM FRSp + 1
b84bf58a 420 { 0xff, 12, insert_fxm, extract_fxm, 0 },
c168870a
AM		 421
422 /* Power4 version for mfcr. */
423#define FXM4 FXM + 1
e43de63c
AM		 424 { 0xff, 12, insert_fxm, extract_fxm,
425 PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
11a0cf2e
PB		 426 /* If the FXM4 operand is ommitted, use the sentinel value -1. */
427 { -1, -1, NULL, NULL, 0},
252b5132 428
b9c361e0 429 /* The IMM20 field in an LI instruction. */
11a0cf2e 430#define IMM20 FXM4 + 2
b9c361e0
JL		 431 { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED},
432
252b5132 433 /* The L field in a D or X form instruction. */
b9c361e0 434#define L IMM20 + 1
a5721ba2
AM		 435 { 0x1, 21, NULL, NULL, 0 },
436
437 /* The optional L field in tlbie and tlbiel instructions. */
438#define LOPT L + 1
5817ffd1 439 /* The R field in a HTM X form instruction. */
a5721ba2 440#define HTM_R LOPT
b84bf58a 441 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
252b5132 442
a5721ba2
AM		 443 /* The optional (for 32-bit) L field in cmp[l][i] instructions. */
444#define L32OPT LOPT + 1
445 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL32 },
a680de9a 446
a5721ba2
AM		 447 /* The L field in dcbf instruction. */
448#define L2OPT L32OPT + 1
449 { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
a680de9a 450
dce75bf9 451 /* The LEV field in a POWER SVC / POWER9 SCV form instruction. */
a5721ba2 452#define SVC_LEV L2OPT + 1
b84bf58a 453 { 0x7f, 5, NULL, NULL, 0 },
252b5132 454
1ed8e1e4
AM		 455 /* The LEV field in an SC form instruction. */
456#define LEV SVC_LEV + 1
b84bf58a 457 { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
1ed8e1e4 458
252b5132
RH		 459 /* The LI field in an I form instruction. The lower two bits are
460 forced to zero. */
461#define LI LEV + 1
b84bf58a 462 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 463
464 /* The LI field in an I form instruction when used as an absolute
465 address. */
466#define LIA LI + 1
b84bf58a 467 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132 468
066be9f7 469 /* The LS or WC field in an X (sync or wait) form instruction. */
6ba045b1 470#define LS LIA + 1
066be9f7 471#define WC LS
73f07bff 472 { 0x3, 21, insert_ls, extract_ls, PPC_OPERAND_OPTIONAL },
6ba045b1 473
252b5132 474 /* The ME field in an M form instruction. */
717bbdf1 475#define ME LS + 1
252b5132 476#define ME_MASK (0x1f << 1)
b84bf58a 477 { 0x1f, 1, NULL, NULL, 0 },
252b5132
RH		 478
479 /* The MB and ME fields in an M form instruction expressed a single
480 operand which is a bitmask indicating which bits to select. This
481 is a two operand form using PPC_OPERAND_NEXT. See the
482 description in opcode/ppc.h for what this means. */
483#define MBE ME + 1
b84bf58a 484 { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
eb42fac1 485 { -1, 0, insert_mbe, extract_mbe, 0 },
252b5132
RH		 486
487 /* The MB or ME field in an MD or MDS form instruction. The high
488 bit is wrapped to the low end. */
489#define MB6 MBE + 2
490#define ME6 MB6
491#define MB6_MASK (0x3f << 5)
b84bf58a 492 { 0x3f, 5, insert_mb6, extract_mb6, 0 },
252b5132
RH		 493
494 /* The NB field in an X form instruction. The value 32 is stored as
495 0. */
717bbdf1 496#define NB MB6 + 1
b84bf58a 497 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
252b5132 498
989993d8
JB		 499 /* The NBI field in an lswi instruction, which has special value
500 restrictions. The value 32 is stored as 0. */
501#define NBI NB + 1
502 { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 },
503
252b5132
RH		 504 /* The NSI field in a D form instruction. This is the same as the
505 SI field, only negated. */
989993d8 506#define NSI NBI + 1
b84bf58a 507 { 0xffff, 0, insert_nsi, extract_nsi,
e43de63c
AM		 508 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
509
510 /* The NSI field in a D form instruction when we accept a wide range
511 of positive values. */
512#define NSISIGNOPT NSI + 1
514e58b7 513 { 0xffff, 0, insert_nsi, extract_nsi,
e43de63c 514 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
252b5132 515
adadcc0c 516 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
e43de63c 517#define RA NSISIGNOPT + 1
252b5132 518#define RA_MASK (0x1f << 16)
b84bf58a 519 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
252b5132 520
fdd12ef3
AM		 521 /* As above, but 0 in the RA field means zero, not r0. */
522#define RA0 RA + 1
b84bf58a 523 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
fdd12ef3 524
989993d8 525 /* The RA field in the DQ form lq or an lswx instruction, which have special
adadcc0c 526 value restrictions. */
fdd12ef3 527#define RAQ RA0 + 1
989993d8 528#define RAX RAQ
73f07bff 529 { 0x1f, 16, insert_raq, extract_raq, PPC_OPERAND_GPR_0 },
adadcc0c 530
252b5132
RH		 531 /* The RA field in a D or X form instruction which is an updating
532 load, which means that the RA field may not be zero and may not
533 equal the RT field. */
adadcc0c 534#define RAL RAQ + 1
73f07bff 535 { 0x1f, 16, insert_ral, extract_ral, PPC_OPERAND_GPR_0 },
252b5132
RH		 536
537 /* The RA field in an lmw instruction, which has special value
538 restrictions. */
539#define RAM RAL + 1
73f07bff 540 { 0x1f, 16, insert_ram, extract_ram, PPC_OPERAND_GPR_0 },
252b5132
RH		 541
542 /* The RA field in a D or X form instruction which is an updating
543 store or an updating floating point load, which means that the RA
544 field may not be zero. */
545#define RAS RAM + 1
73f07bff 546 { 0x1f, 16, insert_ras, extract_ras, PPC_OPERAND_GPR_0 },
252b5132 547
cee62821
PB		 548 /* The RA field of the tlbwe, dccci and iccci instructions,
549 which are optional. */
fdd12ef3 550#define RAOPT RAS + 1
b84bf58a 551 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
1f6c9eb0 552
252b5132 553 /* The RB field in an X, XO, M, or MDS form instruction. */
fdd12ef3 554#define RB RAOPT + 1
252b5132 555#define RB_MASK (0x1f << 11)
b84bf58a 556 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
252b5132
RH		 557
558 /* The RB field in an X form instruction when it must be the same as
559 the RS field in the instruction. This is used for extended
560 mnemonics like mr. */
561#define RBS RB + 1
b84bf58a 562 { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
252b5132 563
989993d8
JB		 564 /* The RB field in an lswx instruction, which has special value
565 restrictions. */
566#define RBX RBS + 1
73f07bff 567 { 0x1f, 11, insert_rbx, extract_rbx, PPC_OPERAND_GPR },
989993d8 568
cee62821 569 /* The RB field of the dccci and iccci instructions, which are optional. */
989993d8 570#define RBOPT RBX + 1
cee62821
PB		 571 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
572
a680de9a
PB		 573 /* The RC register field in an maddld, maddhd or maddhdu instruction. */
574#define RC RBOPT + 1
575 { 0x1f, 6, NULL, NULL, PPC_OPERAND_GPR },
576
252b5132
RH		 577 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
578 instruction or the RT field in a D, DS, X, XFX or XO form
579 instruction. */
a680de9a 580#define RS RC + 1
252b5132
RH		 581#define RT RS
582#define RT_MASK (0x1f << 21)
b9c361e0 583#define RD RS
b84bf58a 584 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
252b5132 585
588925d0
PB		 586 /* The RS and RT fields of the DS form stq and DQ form lq instructions,
587 which have special value restrictions. */
adadcc0c 588#define RSQ RS + 1
717bbdf1 589#define RTQ RSQ
73f07bff 590#define Q_MASK (1 << 21)
588925d0 591 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR },
adadcc0c 592
1f6c9eb0 593 /* The RS field of the tlbwe instruction, which is optional. */
717bbdf1 594#define RSO RSQ + 1
eed0d89a 595#define RTO RSO
b84bf58a 596 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
1f6c9eb0 597
b9c361e0
JL		 598 /* The RX field of the SE_RR form instruction. */
599#define RX RSO + 1
600 { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR },
601
602 /* The ARX field of the SE_RR form instruction. */
603#define ARX RX + 1
604 { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR },
605
606 /* The RY field of the SE_RR form instruction. */
607#define RY ARX + 1
608#define RZ RY
609 { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR },
610
611 /* The ARY field of the SE_RR form instruction. */
612#define ARY RY + 1
613 { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR },
614
615 /* The SCLSCI8 field in a D form instruction. */
616#define SCLSCI8 ARY + 1
617 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 },
618
619 /* The SCLSCI8N field in a D form instruction. This is the same as the
620 SCLSCI8 field, only negated. */
621#define SCLSCI8N SCLSCI8 + 1
622 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n,
e43de63c 623 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
b9c361e0
JL		 624
625 /* The SD field of the SD4 form instruction. */
626#define SE_SD SCLSCI8N + 1
627 { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS },
628
629 /* The SD field of the SD4 form instruction, for halfword. */
630#define SE_SDH SE_SD + 1
631 { 0x1e, PPC_OPSHIFT_INV, insert_sd4h, extract_sd4h, PPC_OPERAND_PARENS },
632
633 /* The SD field of the SD4 form instruction, for word. */
634#define SE_SDW SE_SDH + 1
635 { 0x3c, PPC_OPSHIFT_INV, insert_sd4w, extract_sd4w, PPC_OPERAND_PARENS },
636
252b5132 637 /* The SH field in an X or M form instruction. */
b9c361e0 638#define SH SE_SDW + 1
252b5132 639#define SH_MASK (0x1f << 11)
717bbdf1
AM		 640 /* The other UIMM field in a EVX form instruction. */
641#define EVUIMM SH
a680de9a
PB		 642 /* The FC field in an atomic X form instruction. */
643#define FC SH
b84bf58a 644 { 0x1f, 11, NULL, NULL, 0 },
252b5132 645
5817ffd1
PB		 646 /* The SI field in a HTM X form instruction. */
647#define HTM_SI SH + 1
648 { 0x1f, 11, NULL, NULL, PPC_OPERAND_SIGNED },
649
252b5132 650 /* The SH field in an MD form instruction. This is split. */
5817ffd1 651#define SH6 HTM_SI + 1
252b5132 652#define SH6_MASK ((0x1f << 11) | (1 << 1))
b9c361e0 653 { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 },
252b5132 654
a8cc8a54
AM		 655 /* The SH field of some variants of the tlbre and tlbwe
656 instructions, and the ELEV field of the e_sc instruction. */
1f6c9eb0 657#define SHO SH6 + 1
a8cc8a54 658#define ELEV SHO
b84bf58a 659 { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
1f6c9eb0 660
252b5132 661 /* The SI field in a D form instruction. */
1f6c9eb0 662#define SI SHO + 1
b84bf58a 663 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
252b5132
RH		 664
665 /* The SI field in a D form instruction when we accept a wide range
666 of positive values. */
667#define SISIGNOPT SI + 1
b84bf58a 668 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
252b5132 669
b9c361e0
JL		 670 /* The SI8 field in a D form instruction. */
671#define SI8 SISIGNOPT + 1
672 { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
673
252b5132
RH		 674 /* The SPR field in an XFX form instruction. This is flipped--the
675 lower 5 bits are stored in the upper 5 and vice- versa. */
b9c361e0 676#define SPR SI8 + 1
914749f6 677#define PMR SPR
aea77599 678#define TMR SPR
252b5132 679#define SPR_MASK (0x3ff << 11)
7e0de605 680 { 0x3ff, 11, insert_spr, extract_spr, PPC_OPERAND_SPR },
252b5132
RH		 681
682 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
683#define SPRBAT SPR + 1
684#define SPRBAT_MASK (0x3 << 17)
b84bf58a 685 { 0x3, 17, NULL, NULL, 0 },
252b5132
RH		 686
687 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
688#define SPRG SPRBAT + 1
7e0de605 689 { 0x1f, 16, insert_sprg, extract_sprg, PPC_OPERAND_SPR },
252b5132
RH		 690
691 /* The SR field in an X form instruction. */
692#define SR SPRG + 1
fb048c26
PB		 693 /* The 4-bit UIMM field in a VX form instruction. */
694#define UIMM4 SR
b84bf58a 695 { 0xf, 16, NULL, NULL, 0 },
252b5132 696
f5c120c5
MG		 697 /* The STRM field in an X AltiVec form instruction. */
698#define STRM SR + 1
19a6653c
AM		 699 /* The T field in a tlbilx form instruction. */
700#define T STRM
a5721ba2
AM		 701 /* The L field in wclr instructions. */
702#define L2 STRM
b84bf58a 703 { 0x3, 21, NULL, NULL, 0 },
f5c120c5 704
aea77599
AM		 705 /* The ESYNC field in an X (sync) form instruction. */
706#define ESYNC STRM + 1
73f07bff 707 { 0xf, 16, insert_esync, extract_esync, PPC_OPERAND_OPTIONAL },
aea77599 708
252b5132 709 /* The SV field in a POWER SC form instruction. */
aea77599 710#define SV ESYNC + 1
b84bf58a 711 { 0x3fff, 2, NULL, NULL, 0 },
252b5132
RH		 712
713 /* The TBR field in an XFX form instruction. This is like the SPR
714 field, but it is optional. */
715#define TBR SV + 1
e43de63c 716 { 0x3ff, 11, insert_tbr, extract_tbr,
7e0de605 717 PPC_OPERAND_SPR | PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
11a0cf2e
PB		 718 /* If the TBR operand is ommitted, use the value 268. */
719 { -1, 268, NULL, NULL, 0},
252b5132
RH		 720
721 /* The TO field in a D or X form instruction. */
11a0cf2e 722#define TO TBR + 2
19a6653c 723#define DUI TO
252b5132 724#define TO_MASK (0x1f << 21)
b84bf58a 725 { 0x1f, 21, NULL, NULL, 0 },
252b5132 726
252b5132 727 /* The UI field in a D form instruction. */
717bbdf1 728#define UI TO + 1
b84bf58a 729 { 0xffff, 0, NULL, NULL, 0 },
786e2c0f 730
a47622ac
AM		 731#define UISIGNOPT UI + 1
732 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNOPT },
733
b9c361e0 734 /* The IMM field in an SE_IM5 instruction. */
a47622ac 735#define UI5 UISIGNOPT + 1
b9c361e0
JL		 736 { 0x1f, 4, NULL, NULL, 0 },
737
738 /* The OIMM field in an SE_OIM5 instruction. */
739#define OIMM5 UI5 + 1
740 { 0x1f, PPC_OPSHIFT_INV, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 },
741
742 /* The UI7 field in an SE_LI instruction. */
743#define UI7 OIMM5 + 1
744 { 0x7f, 4, NULL, NULL, 0 },
745
112290ab 746 /* The VA field in a VA, VX or VXR form instruction. */
b9c361e0 747#define VA UI7 + 1
b84bf58a 748 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 749
112290ab 750 /* The VB field in a VA, VX or VXR form instruction. */
786e2c0f 751#define VB VA + 1
b84bf58a 752 { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 753
112290ab 754 /* The VC field in a VA form instruction. */
786e2c0f 755#define VC VB + 1
b84bf58a 756 { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 757
112290ab 758 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
786e2c0f
C		 759#define VD VC + 1
760#define VS VD
b84bf58a 761 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 762
8dbcd839 763 /* The SIMM field in a VX form instruction, and TE in Z form. */
786e2c0f 764#define SIMM VD + 1
8dbcd839 765#define TE SIMM
b84bf58a 766 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
786e2c0f 767
8dbcd839 768 /* The UIMM field in a VX form instruction. */
786e2c0f 769#define UIMM SIMM + 1
aea77599 770#define DCTL UIMM
b84bf58a 771 { 0x1f, 16, NULL, NULL, 0 },
786e2c0f 772
fb048c26
PB		 773 /* The 3-bit UIMM field in a VX form instruction. */
774#define UIMM3 UIMM + 1
775 { 0x7, 16, NULL, NULL, 0 },
776
a680de9a
PB		 777 /* The 6-bit UIM field in a X form instruction. */
778#define UIM6 UIMM3 + 1
779 { 0x3f, 16, NULL, NULL, 0 },
780
c0637f3a 781 /* The SIX field in a VX form instruction. */
a680de9a 782#define SIX UIM6 + 1
c0637f3a
PB		 783 { 0xf, 11, NULL, NULL, 0 },
784
785 /* The PS field in a VX form instruction. */
786#define PS SIX + 1
787 { 0x1, 9, NULL, NULL, 0 },
788
112290ab 789 /* The SHB field in a VA form instruction. */
c0637f3a 790#define SHB PS + 1
b84bf58a 791 { 0xf, 6, NULL, NULL, 0 },
ff3a6ee3 792
112290ab 793 /* The other UIMM field in a half word EVX form instruction. */
717bbdf1 794#define EVUIMM_2 SHB + 1
b84bf58a 795 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
23976049 796
112290ab 797 /* The other UIMM field in a word EVX form instruction. */
23976049 798#define EVUIMM_4 EVUIMM_2 + 1
b84bf58a 799 { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
23976049 800
112290ab 801 /* The other UIMM field in a double EVX form instruction. */
23976049 802#define EVUIMM_8 EVUIMM_4 + 1
b84bf58a 803 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
23976049 804
6fd3a02d 805 /* The WS or DRM field in an X form instruction. */
23976049 806#define WS EVUIMM_8 + 1
6fd3a02d 807#define DRM WS
b84bf58a 808 { 0x7, 11, NULL, NULL, 0 },
ff3a6ee3 809
c3d65c1c
BE		 810 /* PowerPC paired singles extensions. */
811 /* W bit in the pair singles instructions for x type instructions. */
812#define PSWM WS + 1
b9c361e0
JL		 813 /* The BO16 field in a BD8 form instruction. */
814#define BO16 PSWM
c3d65c1c
BE		 815 { 0x1, 10, 0, 0, 0 },
816
817 /* IDX bits for quantization in the pair singles instructions. */
818#define PSQ PSWM + 1
7e0de605 819 { 0x7, 12, 0, 0, PPC_OPERAND_GQR },
c3d65c1c
BE		 820
821 /* IDX bits for quantization in the pair singles x-type instructions. */
822#define PSQM PSQ + 1
7e0de605 823 { 0x7, 7, 0, 0, PPC_OPERAND_GQR },
c3d65c1c
BE		 824
825 /* Smaller D field for quantization in the pair singles instructions. */
826#define PSD PSQM + 1
827 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
828
a680de9a 829 /* The L field in an mtmsrd or A form instruction or R or W in an X form. */
c3d65c1c 830#define A_L PSD + 1
ea192fa3 831#define W A_L
a680de9a 832#define X_R A_L
b84bf58a 833 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
5ae2e65e 834
19dfcc89 835 /* The RMC or CY field in a Z23 form instruction. */
99a2c561 836#define RMC A_L + 1
19dfcc89 837#define CY RMC
b84bf58a 838 { 0x3, 9, NULL, NULL, 0 },
702f0fb4
PB		 839
840#define R RMC + 1
b84bf58a 841 { 0x1, 16, NULL, NULL, 0 },
702f0fb4 842
a680de9a
PB		 843#define RIC R + 1
844 { 0x3, 18, NULL, NULL, PPC_OPERAND_OPTIONAL },
845
846#define PRS RIC + 1
847 { 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL },
848
849#define SP PRS + 1
b84bf58a 850 { 0x3, 19, NULL, NULL, 0 },
702f0fb4
PB		 851
852#define S SP + 1
b84bf58a 853 { 0x1, 20, NULL, NULL, 0 },
702f0fb4 854
c0637f3a
PB		 855 /* The S field in a XL form instruction. */
856#define SXL S + 1
11a0cf2e
PB		 857 { 0x1, 11, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
858 /* If the SXL operand is ommitted, use the value 1. */
859 { -1, 1, NULL, NULL, 0},
c0637f3a 860
702f0fb4 861 /* SH field starting at bit position 16. */
11a0cf2e 862#define SH16 SXL + 2
0bbdef92
AM		 863 /* The DCM and DGM fields in a Z form instruction. */
864#define DCM SH16
865#define DGM DCM
b84bf58a 866 { 0x3f, 10, NULL, NULL, 0 },
702f0fb4 867
702f0fb4 868 /* The EH field in larx instruction. */
717bbdf1 869#define EH SH16 + 1
b84bf58a 870 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
ea192fa3
PB		 871
872 /* The L field in an mtfsf or XFL form instruction. */
5817ffd1 873 /* The A field in a HTM X form instruction. */
ea192fa3 874#define XFL_L EH + 1
5817ffd1 875#define HTM_A XFL_L
ea192fa3 876 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
081ba1b3
AM		 877
878 /* Xilinx APU related masks and macros */
879#define FCRT XFL_L + 1
880#define FCRT_MASK (0x1f << 21)
881 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
882
43e65147 883 /* Xilinx FSL related masks and macros */
081ba1b3
AM		 884#define FSL FCRT + 1
885#define FSL_MASK (0x1f << 11)
43e65147 886 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
081ba1b3 887
43e65147 888 /* Xilinx UDI related masks and macros */
081ba1b3
AM		 889#define URT FSL + 1
890 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
891
892#define URA URT + 1
893 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
894
895#define URB URA + 1
896 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
897
898#define URC URB + 1
899 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
900
b9c361e0
JL		 901 /* The VLESIMM field in a D form instruction. */
902#define VLESIMM URC + 1
903 { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi,
e43de63c 904 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
b9c361e0
JL		 905
906 /* The VLENSIMM field in a D form instruction. */
907#define VLENSIMM VLESIMM + 1
908 { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi,
e43de63c 909 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
b9c361e0
JL		 910
911 /* The VLEUIMM field in a D form instruction. */
912#define VLEUIMM VLENSIMM + 1
913 { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 },
914
915 /* The VLEUIMML field in a D form instruction. */
916#define VLEUIMML VLEUIMM + 1
917 { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 },
918
9b4e5766 919 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
b9c361e0 920#define XS6 VLEUIMML + 1
9b4e5766 921#define XT6 XS6
b9c361e0 922 { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
9b4e5766 923
a680de9a
PB		 924 /* The XT and XS fields in an DQ form VSX instruction. This is split. */
925#define XSQ6 XT6 + 1
926#define XTQ6 XSQ6
927 { 0x3f, PPC_OPSHIFT_INV, insert_xtq6, extract_xtq6, PPC_OPERAND_VSR },
928
9b4e5766 929 /* The XA field in an XX3 form instruction. This is split. */
a680de9a 930#define XA6 XTQ6 + 1
b9c361e0 931 { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
9b4e5766 932
066be9f7 933 /* The XB field in an XX2 or XX3 form instruction. This is split. */
9b4e5766 934#define XB6 XA6 + 1
b9c361e0 935 { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
9b4e5766
PB		 936
937 /* The XB field in an XX3 form instruction when it must be the same as
938 the XA field in the instruction. This is used in extended mnemonics
939 like xvmovdp. This is split. */
940#define XB6S XB6 + 1
b9c361e0 941 { 0x3f, PPC_OPSHIFT_INV, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
9b4e5766 942
066be9f7
PB		 943 /* The XC field in an XX4 form instruction. This is split. */
944#define XC6 XB6S + 1
b9c361e0 945 { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
066be9f7
PB		 946
947 /* The DM or SHW field in an XX3 form instruction. */
948#define DM XC6 + 1
949#define SHW DM
9b4e5766 950 { 0x3, 8, NULL, NULL, 0 },
066be9f7
PB		 951
952 /* The DM field in an extended mnemonic XX3 form instruction. */
953#define DMEX DM + 1
954 { 0x3, 8, insert_dm, extract_dm, 0 },
955
956 /* The UIM field in an XX2 form instruction. */
957#define UIM DMEX + 1
fb048c26
PB		 958 /* The 2-bit UIMM field in a VX form instruction. */
959#define UIMM2 UIM
a680de9a
PB		 960 /* The 2-bit L field in a darn instruction. */
961#define LRAND UIM
066be9f7 962 { 0x3, 16, NULL, NULL, 0 },
e0d602ec
BE		 963
964#define ERAT_T UIM + 1
965 { 0x7, 21, NULL, NULL, 0 },
4bc0608a
PB		 966
967#define IH ERAT_T + 1
968 { 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
a680de9a
PB		 969
970 /* The 8-bit IMM8 field in a XX1 form instruction. */
971#define IMM8 IH + 1
1178da44 972 { 0xff, 11, NULL, NULL, PPC_OPERAND_SIGNOPT },
252b5132
RH		 973};
974
b84bf58a
AM		 975const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
976 / sizeof (powerpc_operands[0]));
977
252b5132
RH		 978/* The functions used to insert and extract complicated operands. */
979
b9c361e0
JL		 980/* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
981
982static unsigned long
983insert_arx (unsigned long insn,
984 long value,
985 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
986 const char **errmsg ATTRIBUTE_UNUSED)
987{
988 if (value >= 8 && value < 24)
989 return insn | ((value - 8) & 0xf);
990 else
991 {
992 *errmsg = _("invalid register");
993 return 0;
994 }
995}
996
997static long
998extract_arx (unsigned long insn,
999 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1000 int *invalid ATTRIBUTE_UNUSED)
43e65147 1001{
b9c361e0
JL		 1002 return (insn & 0xf) + 8;
1003}
1004
1005static unsigned long
1006insert_ary (unsigned long insn,
1007 long value,
1008 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1009 const char **errmsg ATTRIBUTE_UNUSED)
1010{
1011 if (value >= 8 && value < 24)
1012 return insn | (((value - 8) & 0xf) << 4);
1013 else
1014 {
1015 *errmsg = _("invalid register");
1016 return 0;
1017 }
1018}
1019
1020static long
1021extract_ary (unsigned long insn,
1022 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1023 int *invalid ATTRIBUTE_UNUSED)
1024{
1025 return ((insn >> 4) & 0xf) + 8;
1026}
1027
1028static unsigned long
1029insert_rx (unsigned long insn,
1030 long value,
1031 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1032 const char **errmsg)
1033{
1034 if (value >= 0 && value < 8)
1035 return insn | value;
1036 else if (value >= 24 && value <= 31)
1037 return insn | (value - 16);
1038 else
1039 {
1040 *errmsg = _("invalid register");
1041 return 0;
1042 }
1043}
1044
1045static long
1046extract_rx (unsigned long insn,
1047 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1048 int *invalid ATTRIBUTE_UNUSED)
1049{
1050 int value = insn & 0xf;
1051 if (value >= 0 && value < 8)
1052 return value;
1053 else
1054 return value + 16;
1055}
1056
1057static unsigned long
1058insert_ry (unsigned long insn,
1059 long value,
1060 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1061 const char **errmsg)
1062{
1063 if (value >= 0 && value < 8)
1064 return insn | (value << 4);
1065 else if (value >= 24 && value <= 31)
1066 return insn | ((value - 16) << 4);
1067 else
1068 {
1069 *errmsg = _("invalid register");
1070 return 0;
1071 }
1072}
1073
1074static long
1075extract_ry (unsigned long insn,
1076 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1077 int *invalid ATTRIBUTE_UNUSED)
1078{
1079 int value = (insn >> 4) & 0xf;
1080 if (value >= 0 && value < 8)
1081 return value;
1082 else
1083 return value + 16;
1084}
1085
252b5132
RH		 1086/* The BA field in an XL form instruction when it must be the same as
1087 the BT field in the same instruction. This operand is marked FAKE.
1088 The insertion function just copies the BT field into the BA field,
1089 and the extraction function just checks that the fields are the
1090 same. */
1091
252b5132 1092static unsigned long
2fbfdc41
AM		 1093insert_bat (unsigned long insn,
1094 long value ATTRIBUTE_UNUSED,
fa452fa6 1095 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1096 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1097{
1098 return insn | (((insn >> 21) & 0x1f) << 16);
1099}
1100
1101static long
2fbfdc41 1102extract_bat (unsigned long insn,
fa452fa6 1103 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1104 int *invalid)
252b5132 1105{
8427c424 1106 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
252b5132
RH		 1107 *invalid = 1;
1108 return 0;
1109}
1110
1111/* The BB field in an XL form instruction when it must be the same as
1112 the BA field in the same instruction. This operand is marked FAKE.
1113 The insertion function just copies the BA field into the BB field,
1114 and the extraction function just checks that the fields are the
1115 same. */
1116
252b5132 1117static unsigned long
2fbfdc41
AM		 1118insert_bba (unsigned long insn,
1119 long value ATTRIBUTE_UNUSED,
fa452fa6 1120 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1121 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1122{
1123 return insn | (((insn >> 16) & 0x1f) << 11);
1124}
1125
1126static long
2fbfdc41 1127extract_bba (unsigned long insn,
fa452fa6 1128 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1129 int *invalid)
252b5132 1130{
8427c424 1131 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
252b5132
RH		 1132 *invalid = 1;
1133 return 0;
1134}
1135
252b5132
RH		 1136/* The BD field in a B form instruction when the - modifier is used.
1137 This modifier means that the branch is not expected to be taken.
94efba12
AM		 1138 For chips built to versions of the architecture prior to version 2
1139 (ie. not Power4 compatible), we set the y bit of the BO field to 1
1140 if the offset is negative. When extracting, we require that the y
1141 bit be 1 and that the offset be positive, since if the y bit is 0
1142 we just want to print the normal form of the instruction.
1143 Power4 compatible targets use two bits, "a", and "t", instead of
1144 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
1145 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
1146 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
ba4e851b
AM		 1147 for branch on CTR. We only handle the taken/not-taken hint here.
1148 Note that we don't relax the conditions tested here when
1149 disassembling with -Many because insns using extract_bdm and
1150 extract_bdp always occur in pairs. One or the other will always
1151 be valid. */
252b5132 1152
8ebac3aa
AM		 1153#define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
1154
252b5132 1155static unsigned long
2fbfdc41
AM		 1156insert_bdm (unsigned long insn,
1157 long value,
fa452fa6 1158 ppc_cpu_t dialect,
2fbfdc41 1159 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 1160{
8ebac3aa 1161 if ((dialect & ISA_V2) == 0)
802a735e
AM		 1162 {
1163 if ((value & 0x8000) != 0)
1164 insn |= 1 << 21;
1165 }
1166 else
1167 {
1168 if ((insn & (0x14 << 21)) == (0x04 << 21))
1169 insn |= 0x02 << 21;
1170 else if ((insn & (0x14 << 21)) == (0x10 << 21))
1171 insn |= 0x08 << 21;
1172 }
252b5132
RH		 1173 return insn | (value & 0xfffc);
1174}
1175
1176static long
2fbfdc41 1177extract_bdm (unsigned long insn,
fa452fa6 1178 ppc_cpu_t dialect,
2fbfdc41 1179 int *invalid)
252b5132 1180{
8ebac3aa 1181 if ((dialect & ISA_V2) == 0)
802a735e 1182 {
8427c424
AM		 1183 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
1184 *invalid = 1;
802a735e 1185 }
8427c424
AM		 1186 else
1187 {
1188 if ((insn & (0x17 << 21)) != (0x06 << 21)
1189 && (insn & (0x1d << 21)) != (0x18 << 21))
1190 *invalid = 1;
1191 }
1192
802a735e 1193 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 1194}
1195
1196/* The BD field in a B form instruction when the + modifier is used.
1197 This is like BDM, above, except that the branch is expected to be
1198 taken. */
1199
252b5132 1200static unsigned long
2fbfdc41
AM		 1201insert_bdp (unsigned long insn,
1202 long value,
fa452fa6 1203 ppc_cpu_t dialect,
2fbfdc41 1204 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 1205{
8ebac3aa 1206 if ((dialect & ISA_V2) == 0)
802a735e
AM		 1207 {
1208 if ((value & 0x8000) == 0)
1209 insn |= 1 << 21;
1210 }
1211 else
1212 {
1213 if ((insn & (0x14 << 21)) == (0x04 << 21))
1214 insn |= 0x03 << 21;
1215 else if ((insn & (0x14 << 21)) == (0x10 << 21))
1216 insn |= 0x09 << 21;
1217 }
252b5132
RH		 1218 return insn | (value & 0xfffc);
1219}
1220
1221static long
2fbfdc41 1222extract_bdp (unsigned long insn,
fa452fa6 1223 ppc_cpu_t dialect,
2fbfdc41 1224 int *invalid)
252b5132 1225{
8ebac3aa 1226 if ((dialect & ISA_V2) == 0)
802a735e 1227 {
8427c424
AM		 1228 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
1229 *invalid = 1;
1230 }
1231 else
1232 {
1233 if ((insn & (0x17 << 21)) != (0x07 << 21)
1234 && (insn & (0x1d << 21)) != (0x19 << 21))
1235 *invalid = 1;
802a735e 1236 }
8427c424 1237
802a735e 1238 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 1239}
1240
8ebac3aa
AM		 1241static inline int
1242valid_bo_pre_v2 (long value)
252b5132 1243{
8ebac3aa
AM		 1244 /* Certain encodings have bits that are required to be zero.
1245 These are (z must be zero, y may be anything):
43e65147
L		 1246 0000y
1247 0001y
8ebac3aa 1248 001zy
43e65147
L		 1249 0100y
1250 0101y
8ebac3aa
AM		 1251 011zy
1252 1z00y
1253 1z01y
1254 1z1zz
1255 */
1256 if ((value & 0x14) == 0)
1257 return 1;
1258 else if ((value & 0x14) == 0x4)
1259 return (value & 0x2) == 0;
1260 else if ((value & 0x14) == 0x10)
1261 return (value & 0x8) == 0;
1262 else
1263 return value == 0x14;
1264}
ba4e851b 1265
8ebac3aa
AM		 1266static inline int
1267valid_bo_post_v2 (long value)
1268{
ba4e851b
AM		 1269 /* Certain encodings have bits that are required to be zero.
1270 These are (z must be zero, a & t may be anything):
1271 0000z
1272 0001z
8ebac3aa 1273 001at
ba4e851b
AM		 1274 0100z
1275 0101z
ba4e851b
AM		 1276 011at
1277 1a00t
1278 1a01t
1279 1z1zz
1280 */
1281 if ((value & 0x14) == 0)
1282 return (value & 0x1) == 0;
1283 else if ((value & 0x14) == 0x14)
1284 return value == 0x14;
802a735e 1285 else
ba4e851b 1286 return 1;
252b5132
RH		 1287}
1288
8ebac3aa
AM		 1289/* Check for legal values of a BO field. */
1290
1291static int
1292valid_bo (long value, ppc_cpu_t dialect, int extract)
1293{
1294 int valid_y = valid_bo_pre_v2 (value);
1295 int valid_at = valid_bo_post_v2 (value);
1296
1297 /* When disassembling with -Many, accept either encoding on the
1298 second pass through opcodes. */
1299 if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY)
1300 return valid_y || valid_at;
1301 if ((dialect & ISA_V2) == 0)
1302 return valid_y;
1303 else
1304 return valid_at;
1305}
1306
252b5132
RH		 1307/* The BO field in a B form instruction. Warn about attempts to set
1308 the field to an illegal value. */
1309
1310static unsigned long
2fbfdc41
AM		 1311insert_bo (unsigned long insn,
1312 long value,
fa452fa6 1313 ppc_cpu_t dialect,
2fbfdc41 1314 const char **errmsg)
252b5132 1315{
ba4e851b 1316 if (!valid_bo (value, dialect, 0))
252b5132 1317 *errmsg = _("invalid conditional option");
989993d8
JB		 1318 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1319 *errmsg = _("invalid counter access");
252b5132
RH		 1320 return insn | ((value & 0x1f) << 21);
1321}
1322
1323static long
2fbfdc41 1324extract_bo (unsigned long insn,
fa452fa6 1325 ppc_cpu_t dialect,
2fbfdc41 1326 int *invalid)
252b5132
RH		 1327{
1328 long value;
1329
1330 value = (insn >> 21) & 0x1f;
ba4e851b 1331 if (!valid_bo (value, dialect, 1))
252b5132
RH		 1332 *invalid = 1;
1333 return value;
1334}
1335
1336/* The BO field in a B form instruction when the + or - modifier is
1337 used. This is like the BO field, but it must be even. When
1338 extracting it, we force it to be even. */
1339
1340static unsigned long
2fbfdc41
AM		 1341insert_boe (unsigned long insn,
1342 long value,
fa452fa6 1343 ppc_cpu_t dialect,
2fbfdc41 1344 const char **errmsg)
252b5132 1345{
ba4e851b 1346 if (!valid_bo (value, dialect, 0))
8427c424 1347 *errmsg = _("invalid conditional option");
989993d8
JB		 1348 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1349 *errmsg = _("invalid counter access");
8427c424
AM		 1350 else if ((value & 1) != 0)
1351 *errmsg = _("attempt to set y bit when using + or - modifier");
1352
252b5132
RH		 1353 return insn | ((value & 0x1f) << 21);
1354}
1355
1356static long
2fbfdc41 1357extract_boe (unsigned long insn,
fa452fa6 1358 ppc_cpu_t dialect,
2fbfdc41 1359 int *invalid)
252b5132
RH		 1360{
1361 long value;
1362
1363 value = (insn >> 21) & 0x1f;
ba4e851b 1364 if (!valid_bo (value, dialect, 1))
252b5132
RH		 1365 *invalid = 1;
1366 return value & 0x1e;
1367}
1368
a680de9a
PB		 1369/* The DCMX field in a X form instruction when the field is split
1370 into separate DC, DM and DX fields. */
1371
1372static unsigned long
1373insert_dcmxs (unsigned long insn,
1374 long value,
1375 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1376 const char **errmsg ATTRIBUTE_UNUSED)
1377{
1378 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3) | (value & 0x40);
1379}
1380
1381static long
1382extract_dcmxs (unsigned long insn,
1383 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1384 int *invalid ATTRIBUTE_UNUSED)
1385{
1386 return (insn & 0x40) | ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
1387}
1388
1389/* The D field in a DX form instruction when the field is split
1390 into separate D0, D1 and D2 fields. */
1391
1392static unsigned long
1393insert_dxd (unsigned long insn,
1394 long value,
1395 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1396 const char **errmsg ATTRIBUTE_UNUSED)
1397{
1398 return insn | (value & 0xffc1) | ((value & 0x3e) << 15);
1399}
1400
1401static long
1402extract_dxd (unsigned long insn,
1403 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1404 int *invalid ATTRIBUTE_UNUSED)
1405{
1406 unsigned long dxd = (insn & 0xffc1) | ((insn >> 15) & 0x3e);
1407 return (dxd ^ 0x8000) - 0x8000;
1408}
1409
1410static unsigned long
1411insert_dxdn (unsigned long insn,
1412 long value,
1413 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1414 const char **errmsg ATTRIBUTE_UNUSED)
1415{
1416 return insert_dxd (insn, -value, dialect, errmsg);
1417}
1418
1419static long
1420extract_dxdn (unsigned long insn,
1421 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1422 int *invalid ATTRIBUTE_UNUSED)
1423{
1424 return -extract_dxd (insn, dialect, invalid);
1425}
1426
2fbfdc41
AM		 1427/* FXM mask in mfcr and mtcrf instructions. */
1428
1429static unsigned long
1430insert_fxm (unsigned long insn,
1431 long value,
fa452fa6 1432 ppc_cpu_t dialect,
2fbfdc41 1433 const char **errmsg)
c168870a 1434{
98e69875
AM		 1435 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1436 one bit of the mask field is set. */
1437 if ((insn & (1 << 20)) != 0)
1438 {
1439 if (value == 0 || (value & -value) != value)
1440 {
1441 *errmsg = _("invalid mask field");
1442 value = 0;
1443 }
1444 }
1445
c168870a 1446 /* If only one bit of the FXM field is set, we can use the new form
661bd698 1447 of the instruction, which is faster. Unlike the Power4 branch hint
a30e9cc4
AM		 1448 encoding, this is not backward compatible. Do not generate the
1449 new form unless -mpower4 has been given, or -many and the two
1450 operand form of mfcr was used. */
11a0cf2e
PB		 1451 else if (value > 0
1452 && (value & -value) == value
a30e9cc4
AM		 1453 && ((dialect & PPC_OPCODE_POWER4) != 0
1454 || ((dialect & PPC_OPCODE_ANY) != 0
1455 && (insn & (0x3ff << 1)) == 19 << 1)))
c168870a
AM		 1456 insn |= 1 << 20;
1457
1458 /* Any other value on mfcr is an error. */
1459 else if ((insn & (0x3ff << 1)) == 19 << 1)
1460 {
11a0cf2e
PB		 1461 /* A value of -1 means we used the one operand form of
1462 mfcr which is valid. */
1463 if (value != -1)
b817670b 1464 *errmsg = _("invalid mfcr mask");
c168870a
AM		 1465 value = 0;
1466 }
1467
1468 return insn | ((value & 0xff) << 12);
1469}
1470
2fbfdc41
AM		 1471static long
1472extract_fxm (unsigned long insn,
fa452fa6 1473 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1474 int *invalid)
c168870a
AM		 1475{
1476 long mask = (insn >> 12) & 0xff;
1477
1478 /* Is this a Power4 insn? */
1479 if ((insn & (1 << 20)) != 0)
1480 {
98e69875
AM		 1481 /* Exactly one bit of MASK should be set. */
1482 if (mask == 0 || (mask & -mask) != mask)
8427c424 1483 *invalid = 1;
c168870a
AM		 1484 }
1485
1486 /* Check that non-power4 form of mfcr has a zero MASK. */
1487 else if ((insn & (0x3ff << 1)) == 19 << 1)
1488 {
8427c424 1489 if (mask != 0)
c168870a 1490 *invalid = 1;
11a0cf2e
PB		 1491 else
1492 mask = -1;
c168870a
AM		 1493 }
1494
1495 return mask;
1496}
1497
b9c361e0
JL		 1498static unsigned long
1499insert_li20 (unsigned long insn,
1500 long value,
1501 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1502 const char **errmsg ATTRIBUTE_UNUSED)
1503{
1504 return insn | ((value & 0xf0000) >> 5) | ((value & 0x0f800) << 5) | (value & 0x7ff);
1505}
1506
1507static long
1508extract_li20 (unsigned long insn,
1509 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1510 int *invalid ATTRIBUTE_UNUSED)
1511{
1512 long ext = ((insn & 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000;
1513
1514 return ext
1515 | (((insn >> 11) & 0xf) << 16)
1516 | (((insn >> 17) & 0xf) << 12)
1517 | (((insn >> 16) & 0x1) << 11)
1518 | (insn & 0x7ff);
1519}
1520
7b934113
PB		 1521/* The 2-bit L field in a SYNC or WC field in a WAIT instruction.
1522 For SYNC, some L values are reserved:
1523 * Value 3 is reserved on newer server cpus.
1524 * Values 2 and 3 are reserved on all other cpus. */
aea77599
AM		 1525
1526static unsigned long
1527insert_ls (unsigned long insn,
1528 long value,
7b934113
PB		 1529 ppc_cpu_t dialect,
1530 const char **errmsg)
1531{
1532 /* For SYNC, some L values are illegal. */
1533 if (((insn >> 1) & 0x3ff) == 598)
1534 {
1535 long max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1;
1536 if (value > max_lvalue)
1537 {
1538 *errmsg = _("illegal L operand value");
1539 return insn;
1540 }
1541 }
1542
1543 return insn | ((value & 0x3) << 21);
1544}
1545
73f07bff
AM		 1546static long
1547extract_ls (unsigned long insn,
1548 ppc_cpu_t dialect,
1549 int *invalid)
1550{
1551 unsigned long lvalue = (insn >> 21) & 3;
1552
1553 if (((insn >> 1) & 0x3ff) == 598)
1554 {
1555 unsigned long max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1;
1556 if (lvalue > max_lvalue)
1557 *invalid = 1;
1558 }
1559 return lvalue;
1560}
1561
7b934113
PB		 1562/* The 4-bit E field in a sync instruction that accepts 2 operands.
1563 If ESYNC is non-zero, then the L field must be either 0 or 1 and
1564 the complement of ESYNC-bit2. */
1565
1566static unsigned long
1567insert_esync (unsigned long insn,
1568 long value,
a680de9a 1569 ppc_cpu_t dialect,
7b934113 1570 const char **errmsg)
aea77599 1571{
a680de9a 1572 unsigned long ls = (insn >> 21) & 0x03;
aea77599 1573
aea77599
AM		 1574 if (value == 0)
1575 {
a680de9a
PB		 1576 if (((dialect & PPC_OPCODE_E6500) != 0 && ls > 1)
1577 || ((dialect & PPC_OPCODE_POWER9) != 0 && ls > 2))
1578 *errmsg = _("illegal L operand value");
aea77599
AM		 1579 return insn;
1580 }
7b934113
PB		 1581
1582 if ((ls & ~0x1)
1583 || (((value >> 1) & 0x1) ^ ls) == 0)
1584 *errmsg = _("incompatible L operand value");
1585
1586 return insn | ((value & 0xf) << 16);
aea77599
AM		 1587}
1588
73f07bff
AM		 1589static long
1590extract_esync (unsigned long insn,
1591 ppc_cpu_t dialect,
1592 int *invalid)
1593{
1594 unsigned long ls = (insn >> 21) & 0x3;
1595 unsigned long lvalue = (insn >> 16) & 0xf;
1596
1597 if (lvalue == 0)
1598 {
1599 if (((dialect & PPC_OPCODE_E6500) != 0 && ls > 1)
1600 || ((dialect & PPC_OPCODE_POWER9) != 0 && ls > 2))
1601 *invalid = 1;
1602 }
1603 else if ((ls & ~0x1)
1604 || (((lvalue >> 1) & 0x1) ^ ls) == 0)
1605 *invalid = 1;
1606
1607 return lvalue;
1608}
1609
252b5132
RH		 1610/* The MB and ME fields in an M form instruction expressed as a single
1611 operand which is itself a bitmask. The extraction function always
1612 marks it as invalid, since we never want to recognize an
1613 instruction which uses a field of this type. */
1614
1615static unsigned long
2fbfdc41
AM		 1616insert_mbe (unsigned long insn,
1617 long value,
fa452fa6 1618 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1619 const char **errmsg)
252b5132
RH		 1620{
1621 unsigned long uval, mask;
1622 int mb, me, mx, count, last;
1623
1624 uval = value;
1625
1626 if (uval == 0)
1627 {
8427c424 1628 *errmsg = _("illegal bitmask");
252b5132
RH		 1629 return insn;
1630 }
1631
1632 mb = 0;
1633 me = 32;
1634 if ((uval & 1) != 0)
1635 last = 1;
1636 else
1637 last = 0;
1638 count = 0;
1639
1640 /* mb: location of last 0->1 transition */
1641 /* me: location of last 1->0 transition */
1642 /* count: # transitions */
1643
0deb7ac5 1644 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
252b5132
RH		 1645 {
1646 if ((uval & mask) && !last)
1647 {
1648 ++count;
1649 mb = mx;
1650 last = 1;
1651 }
1652 else if (!(uval & mask) && last)
1653 {
1654 ++count;
1655 me = mx;
1656 last = 0;
1657 }
1658 }
1659 if (me == 0)
1660 me = 32;
1661
1662 if (count != 2 && (count != 0 || ! last))
8427c424 1663 *errmsg = _("illegal bitmask");
252b5132
RH		 1664
1665 return insn | (mb << 6) | ((me - 1) << 1);
1666}
1667
1668static long
2fbfdc41 1669extract_mbe (unsigned long insn,
fa452fa6 1670 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1671 int *invalid)
252b5132
RH		 1672{
1673 long ret;
1674 int mb, me;
1675 int i;
1676
8427c424 1677 *invalid = 1;
252b5132
RH		 1678
1679 mb = (insn >> 6) & 0x1f;
1680 me = (insn >> 1) & 0x1f;
1681 if (mb < me + 1)
1682 {
1683 ret = 0;
1684 for (i = mb; i <= me; i++)
0deb7ac5 1685 ret |= 1L << (31 - i);
252b5132
RH		 1686 }
1687 else if (mb == me + 1)
8427c424 1688 ret = ~0;
252b5132
RH		 1689 else /* (mb > me + 1) */
1690 {
2fbfdc41 1691 ret = ~0;
252b5132 1692 for (i = me + 1; i < mb; i++)
0deb7ac5 1693 ret &= ~(1L << (31 - i));
252b5132
RH		 1694 }
1695 return ret;
1696}
1697
1698/* The MB or ME field in an MD or MDS form instruction. The high bit
1699 is wrapped to the low end. */
1700
252b5132 1701static unsigned long
2fbfdc41
AM		 1702insert_mb6 (unsigned long insn,
1703 long value,
fa452fa6 1704 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1705 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1706{
1707 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1708}
1709
252b5132 1710static long
2fbfdc41 1711extract_mb6 (unsigned long insn,
fa452fa6 1712 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1713 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1714{
1715 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1716}
1717
1718/* The NB field in an X form instruction. The value 32 is stored as
1719 0. */
1720
252b5132 1721static long
2fbfdc41 1722extract_nb (unsigned long insn,
fa452fa6 1723 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1724 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1725{
1726 long ret;
1727
1728 ret = (insn >> 11) & 0x1f;
1729 if (ret == 0)
1730 ret = 32;
1731 return ret;
1732}
1733
989993d8
JB		 1734/* The NB field in an lswi instruction, which has special value
1735 restrictions. The value 32 is stored as 0. */
1736
1737static unsigned long
1738insert_nbi (unsigned long insn,
1739 long value,
1740 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1741 const char **errmsg ATTRIBUTE_UNUSED)
1742{
1743 long rtvalue = (insn & RT_MASK) >> 21;
1744 long ravalue = (insn & RA_MASK) >> 16;
1745
1746 if (value == 0)
1747 value = 32;
1748 if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32
1749 : ravalue))
1750 *errmsg = _("address register in load range");
1751 return insn | ((value & 0x1f) << 11);
1752}
1753
252b5132
RH		 1754/* The NSI field in a D form instruction. This is the same as the SI
1755 field, only negated. The extraction function always marks it as
1756 invalid, since we never want to recognize an instruction which uses
1757 a field of this type. */
1758
252b5132 1759static unsigned long
2fbfdc41
AM		 1760insert_nsi (unsigned long insn,
1761 long value,
fa452fa6 1762 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1763 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 1764{
2fbfdc41 1765 return insn | (-value & 0xffff);
252b5132
RH		 1766}
1767
1768static long
2fbfdc41 1769extract_nsi (unsigned long insn,
fa452fa6 1770 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1771 int *invalid)
252b5132 1772{
8427c424 1773 *invalid = 1;
2fbfdc41 1774 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
252b5132
RH		 1775}
1776
1777/* The RA field in a D or X form instruction which is an updating
1778 load, which means that the RA field may not be zero and may not
1779 equal the RT field. */
1780
1781static unsigned long
2fbfdc41
AM		 1782insert_ral (unsigned long insn,
1783 long value,
fa452fa6 1784 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1785 const char **errmsg)
252b5132
RH		 1786{
1787 if (value == 0
1788 || (unsigned long) value == ((insn >> 21) & 0x1f))
1789 *errmsg = "invalid register operand when updating";
1790 return insn | ((value & 0x1f) << 16);
1791}
1792
73f07bff
AM		 1793static long
1794extract_ral (unsigned long insn,
1795 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1796 int *invalid)
1797{
1798 long rtvalue = (insn >> 21) & 0x1f;
1799 long ravalue = (insn >> 16) & 0x1f;
1800
1801 if (rtvalue == ravalue || ravalue == 0)
1802 *invalid = 1;
1803 return ravalue;
1804}
1805
252b5132
RH		 1806/* The RA field in an lmw instruction, which has special value
1807 restrictions. */
1808
1809static unsigned long
2fbfdc41
AM		 1810insert_ram (unsigned long insn,
1811 long value,
fa452fa6 1812 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1813 const char **errmsg)
252b5132
RH		 1814{
1815 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1816 *errmsg = _("index register in load range");
1817 return insn | ((value & 0x1f) << 16);
1818}
1819
73f07bff
AM		 1820static long
1821extract_ram (unsigned long insn,
1822 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1823 int *invalid)
1824{
1825 unsigned long rtvalue = (insn >> 21) & 0x1f;
1826 unsigned long ravalue = (insn >> 16) & 0x1f;
1827
1828 if (ravalue >= rtvalue)
1829 *invalid = 1;
1830 return ravalue;
1831}
1832
989993d8 1833/* The RA field in the DQ form lq or an lswx instruction, which have special
8427c424 1834 value restrictions. */
adadcc0c 1835
adadcc0c 1836static unsigned long
2fbfdc41
AM		 1837insert_raq (unsigned long insn,
1838 long value,
fa452fa6 1839 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1840 const char **errmsg)
adadcc0c
AM		 1841{
1842 long rtvalue = (insn & RT_MASK) >> 21;
1843
8427c424 1844 if (value == rtvalue)
adadcc0c
AM		 1845 *errmsg = _("source and target register operands must be different");
1846 return insn | ((value & 0x1f) << 16);
1847}
1848
73f07bff
AM		 1849static long
1850extract_raq (unsigned long insn,
1851 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1852 int *invalid)
1853{
1854 unsigned long rtvalue = (insn >> 21) & 0x1f;
1855 unsigned long ravalue = (insn >> 16) & 0x1f;
1856
1857 if (ravalue == rtvalue)
1858 *invalid = 1;
1859 return ravalue;
1860}
1861
252b5132
RH		 1862/* The RA field in a D or X form instruction which is an updating
1863 store or an updating floating point load, which means that the RA
1864 field may not be zero. */
1865
1866static unsigned long
2fbfdc41
AM		 1867insert_ras (unsigned long insn,
1868 long value,
fa452fa6 1869 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1870 const char **errmsg)
252b5132
RH		 1871{
1872 if (value == 0)
1873 *errmsg = _("invalid register operand when updating");
1874 return insn | ((value & 0x1f) << 16);
1875}
1876
73f07bff
AM		 1877static long
1878extract_ras (unsigned long insn,
1879 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1880 int *invalid)
1881{
1882 unsigned long ravalue = (insn >> 16) & 0x1f;
1883
1884 if (ravalue == 0)
1885 *invalid = 1;
1886 return ravalue;
1887}
1888
252b5132
RH		 1889/* The RB field in an X form instruction when it must be the same as
1890 the RS field in the instruction. This is used for extended
1891 mnemonics like mr. This operand is marked FAKE. The insertion
1892 function just copies the BT field into the BA field, and the
1893 extraction function just checks that the fields are the same. */
1894
252b5132 1895static unsigned long
2fbfdc41
AM		 1896insert_rbs (unsigned long insn,
1897 long value ATTRIBUTE_UNUSED,
fa452fa6 1898 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1899 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1900{
1901 return insn | (((insn >> 21) & 0x1f) << 11);
1902}
1903
1904static long
2fbfdc41 1905extract_rbs (unsigned long insn,
fa452fa6 1906 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1907 int *invalid)
252b5132 1908{
8427c424 1909 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
252b5132
RH		 1910 *invalid = 1;
1911 return 0;
1912}
1913
989993d8
JB		 1914/* The RB field in an lswx instruction, which has special value
1915 restrictions. */
1916
1917static unsigned long
1918insert_rbx (unsigned long insn,
1919 long value,
1920 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1921 const char **errmsg)
1922{
1923 long rtvalue = (insn & RT_MASK) >> 21;
1924
1925 if (value == rtvalue)
1926 *errmsg = _("source and target register operands must be different");
1927 return insn | ((value & 0x1f) << 11);
1928}
1929
73f07bff
AM		 1930static long
1931extract_rbx (unsigned long insn,
1932 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1933 int *invalid)
1934{
1935 unsigned long rtvalue = (insn >> 21) & 0x1f;
1936 unsigned long rbvalue = (insn >> 11) & 0x1f;
1937
1938 if (rbvalue == rtvalue)
1939 *invalid = 1;
1940 return rbvalue;
1941}
1942
b9c361e0
JL		 1943/* The SCI8 field is made up of SCL and {U,N}I8 fields. */
1944static unsigned long
1945insert_sci8 (unsigned long insn,
1946 long value,
1947 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1948 const char **errmsg)
1949{
943d398f
AM		 1950 unsigned int fill_scale = 0;
1951 unsigned long ui8 = value;
b9c361e0 1952
943d398f
AM		 1953 if ((ui8 & 0xffffff00) == 0)
1954 ;
1955 else if ((ui8 & 0xffffff00) == 0xffffff00)
1956 fill_scale = 0x400;
1957 else if ((ui8 & 0xffff00ff) == 0)
b9c361e0 1958 {
943d398f
AM		 1959 fill_scale = 1 << 8;
1960 ui8 >>= 8;
b9c361e0 1961 }
943d398f 1962 else if ((ui8 & 0xffff00ff) == 0xffff00ff)
b9c361e0 1963 {
943d398f
AM		 1964 fill_scale = 0x400 | (1 << 8);
1965 ui8 >>= 8;
b9c361e0 1966 }
943d398f 1967 else if ((ui8 & 0xff00ffff) == 0)
b9c361e0 1968 {
943d398f
AM		 1969 fill_scale = 2 << 8;
1970 ui8 >>= 16;
b9c361e0 1971 }
943d398f 1972 else if ((ui8 & 0xff00ffff) == 0xff00ffff)
b9c361e0 1973 {
943d398f
AM		 1974 fill_scale = 0x400 | (2 << 8);
1975 ui8 >>= 16;
b9c361e0 1976 }
943d398f 1977 else if ((ui8 & 0x00ffffff) == 0)
b9c361e0 1978 {
943d398f
AM		 1979 fill_scale = 3 << 8;
1980 ui8 >>= 24;
b9c361e0 1981 }
943d398f 1982 else if ((ui8 & 0x00ffffff) == 0x00ffffff)
b9c361e0 1983 {
943d398f
AM		 1984 fill_scale = 0x400 | (3 << 8);
1985 ui8 >>= 24;
b9c361e0 1986 }
943d398f 1987 else
b9c361e0 1988 {
943d398f
AM		 1989 *errmsg = _("illegal immediate value");
1990 ui8 = 0;
b9c361e0 1991 }
b9c361e0 1992
943d398f 1993 return insn | fill_scale | (ui8 & 0xff);
b9c361e0
JL		 1994}
1995
1996static long
1997extract_sci8 (unsigned long insn,
1998 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1999 int *invalid ATTRIBUTE_UNUSED)
2000{
943d398f
AM		 2001 int fill = insn & 0x400;
2002 int scale_factor = (insn & 0x300) >> 5;
2003 long value = (insn & 0xff) << scale_factor;
2004
2005 if (fill != 0)
2006 value |= ~((long) 0xff << scale_factor);
2007 return value;
b9c361e0
JL		 2008}
2009
2010static unsigned long
2011insert_sci8n (unsigned long insn,
2012 long value,
943d398f 2013 ppc_cpu_t dialect,
b9c361e0
JL		 2014 const char **errmsg)
2015{
943d398f 2016 return insert_sci8 (insn, -value, dialect, errmsg);
b9c361e0
JL		 2017}
2018
2019static long
2020extract_sci8n (unsigned long insn,
943d398f
AM		 2021 ppc_cpu_t dialect,
2022 int *invalid)
b9c361e0 2023{
943d398f 2024 return -extract_sci8 (insn, dialect, invalid);
b9c361e0
JL		 2025}
2026
2027static unsigned long
2028insert_sd4h (unsigned long insn,
2029 long value,
2030 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2031 const char **errmsg ATTRIBUTE_UNUSED)
2032{
2033 return insn | ((value & 0x1e) << 7);
2034}
2035
2036static long
2037extract_sd4h (unsigned long insn,
2038 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2039 int *invalid ATTRIBUTE_UNUSED)
2040{
2041 return ((insn >> 8) & 0xf) << 1;
2042}
2043
2044static unsigned long
2045insert_sd4w (unsigned long insn,
2046 long value,
2047 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2048 const char **errmsg ATTRIBUTE_UNUSED)
2049{
2050 return insn | ((value & 0x3c) << 6);
2051}
2052
2053static long
2054extract_sd4w (unsigned long insn,
2055 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2056 int *invalid ATTRIBUTE_UNUSED)
2057{
2058 return ((insn >> 8) & 0xf) << 2;
2059}
2060
2061static unsigned long
2062insert_oimm (unsigned long insn,
2063 long value,
2064 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2065 const char **errmsg ATTRIBUTE_UNUSED)
2066{
2067 return insn | (((value - 1) & 0x1f) << 4);
2068}
2069
2070static long
2071extract_oimm (unsigned long insn,
2072 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2073 int *invalid ATTRIBUTE_UNUSED)
2074{
2075 return ((insn >> 4) & 0x1f) + 1;
2076}
2077
252b5132
RH		 2078/* The SH field in an MD form instruction. This is split. */
2079
252b5132 2080static unsigned long
2fbfdc41
AM		 2081insert_sh6 (unsigned long insn,
2082 long value,
fa452fa6 2083 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 2084 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 2085{
6fd3a02d
PB		 2086 /* SH6 operand in the rldixor instructions. */
2087 if (PPC_OP (insn) == 4)
2088 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 5);
2089 else
2090 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
252b5132
RH		 2091}
2092
252b5132 2093static long
2fbfdc41 2094extract_sh6 (unsigned long insn,
fa452fa6 2095 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 2096 int *invalid ATTRIBUTE_UNUSED)
252b5132 2097{
6fd3a02d
PB		 2098 /* SH6 operand in the rldixor instructions. */
2099 if (PPC_OP (insn) == 4)
2100 return ((insn >> 6) & 0x1f) | ((insn << 5) & 0x20);
2101 else
2102 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
252b5132
RH		 2103}
2104
2105/* The SPR field in an XFX form instruction. This is flipped--the
2106 lower 5 bits are stored in the upper 5 and vice- versa. */
2107
2108static unsigned long
2fbfdc41
AM		 2109insert_spr (unsigned long insn,
2110 long value,
fa452fa6 2111 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 2112 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 2113{
2114 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
2115}
2116
2117static long
2fbfdc41 2118extract_spr (unsigned long insn,
fa452fa6 2119 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 2120 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 2121{
2122 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
2123}
2124
da99ee72 2125/* Some dialects have 8 SPRG registers instead of the standard 4. */
14b57c7c 2126#define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405)
da99ee72
AM		 2127
2128static unsigned long
2129insert_sprg (unsigned long insn,
2130 long value,
fa452fa6 2131 ppc_cpu_t dialect,
da99ee72
AM		 2132 const char **errmsg)
2133{
da99ee72 2134 if (value > 7
98c76446 2135 || (value > 3 && (dialect & ALLOW8_SPRG) == 0))
da99ee72
AM		 2136 *errmsg = _("invalid sprg number");
2137
2138 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
2139 user mode. Anything else must use spr 272..279. */
2140 if (value <= 3 || (insn & 0x100) != 0)
2141 value |= 0x10;
2142
2143 return insn | ((value & 0x17) << 16);
2144}
2145
2146static long
2147extract_sprg (unsigned long insn,
fa452fa6 2148 ppc_cpu_t dialect,
da99ee72
AM		 2149 int *invalid)
2150{
2151 unsigned long val = (insn >> 16) & 0x1f;
2152
2153 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
98c76446
AM		 2154 If not BOOKE, 405 or VLE, then both use only 272..275. */
2155 if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0)
e1c93c69
AM		 2156 || (val - 0x10 > 7 && (insn & 0x100) != 0)
2157 || val <= 3
2158 || (val & 8) != 0)
da99ee72
AM		 2159 *invalid = 1;
2160 return val & 7;
2161}
2162
252b5132 2163/* The TBR field in an XFX instruction. This is just like SPR, but it
11a0cf2e 2164 is optional. */
252b5132 2165
252b5132 2166static unsigned long
2fbfdc41
AM		 2167insert_tbr (unsigned long insn,
2168 long value,
fa452fa6 2169 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
8514e4db 2170 const char **errmsg)
252b5132 2171{
8514e4db
AM		 2172 if (value != 268 && value != 269)
2173 *errmsg = _("invalid tbr number");
252b5132
RH		 2174 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
2175}
2176
2177static long
2fbfdc41 2178extract_tbr (unsigned long insn,
fa452fa6 2179 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
8514e4db 2180 int *invalid)
252b5132
RH		 2181{
2182 long ret;
2183
2184 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
8514e4db
AM		 2185 if (ret != 268 && ret != 269)
2186 *invalid = 1;
252b5132
RH		 2187 return ret;
2188}
9b4e5766
PB		 2189
2190/* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
2191
2192static unsigned long
2193insert_xt6 (unsigned long insn,
2194 long value,
2195 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2196 const char **errmsg ATTRIBUTE_UNUSED)
2197{
2198 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5);
2199}
2200
2201static long
2202extract_xt6 (unsigned long insn,
2203 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2204 int *invalid ATTRIBUTE_UNUSED)
2205{
2206 return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
2207}
2208
a680de9a
PB		 2209/* The XT and XS fields in an DQ form VSX instruction. This is split. */
2210static unsigned long
2211insert_xtq6 (unsigned long insn,
2212 long value,
2213 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2214 const char **errmsg ATTRIBUTE_UNUSED)
2215{
2216 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 2);
2217}
2218
2219static long
2220extract_xtq6 (unsigned long insn,
2221 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2222 int *invalid ATTRIBUTE_UNUSED)
2223{
2224 return ((insn << 2) & 0x20) | ((insn >> 21) & 0x1f);
2225}
2226
9b4e5766
PB		 2227/* The XA field in an XX3 form instruction. This is split. */
2228
2229static unsigned long
2230insert_xa6 (unsigned long insn,
2231 long value,
2232 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2233 const char **errmsg ATTRIBUTE_UNUSED)
2234{
2235 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3);
2236}
2237
2238static long
2239extract_xa6 (unsigned long insn,
2240 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2241 int *invalid ATTRIBUTE_UNUSED)
2242{
2243 return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
2244}
2245
2246/* The XB field in an XX3 form instruction. This is split. */
2247
2248static unsigned long
2249insert_xb6 (unsigned long insn,
2250 long value,
2251 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2252 const char **errmsg ATTRIBUTE_UNUSED)
2253{
2254 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
2255}
2256
2257static long
2258extract_xb6 (unsigned long insn,
2259 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2260 int *invalid ATTRIBUTE_UNUSED)
2261{
2262 return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f);
2263}
2264
2265/* The XB field in an XX3 form instruction when it must be the same as
2266 the XA field in the instruction. This is used for extended
2267 mnemonics like xvmovdp. This operand is marked FAKE. The insertion
2268 function just copies the XA field into the XB field, and the
2269 extraction function just checks that the fields are the same. */
2270
2271static unsigned long
2272insert_xb6s (unsigned long insn,
2273 long value ATTRIBUTE_UNUSED,
2274 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2275 const char **errmsg ATTRIBUTE_UNUSED)
2276{
2277 return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1);
2278}
2279
2280static long
2281extract_xb6s (unsigned long insn,
2282 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2283 int *invalid)
2284{
2285 if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
2286 || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1)))
2287 *invalid = 1;
2288 return 0;
2289}
066be9f7
PB		 2290
2291/* The XC field in an XX4 form instruction. This is split. */
2292
2293static unsigned long
2294insert_xc6 (unsigned long insn,
2295 long value,
2296 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2297 const char **errmsg ATTRIBUTE_UNUSED)
2298{
2299 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2);
2300}
2301
2302static long
2303extract_xc6 (unsigned long insn,
2304 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2305 int *invalid ATTRIBUTE_UNUSED)
2306{
2307 return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f);
2308}
2309
2310static unsigned long
2311insert_dm (unsigned long insn,
2312 long value,
2313 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2314 const char **errmsg)
2315{
2316 if (value != 0 && value != 1)
2317 *errmsg = _("invalid constant");
2318 return insn | (((value) ? 3 : 0) << 8);
2319}
2320
2321static long
2322extract_dm (unsigned long insn,
2323 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2324 int *invalid)
2325{
2326 long value;
2327
2328 value = (insn >> 8) & 3;
2329 if (value != 0 && value != 3)
2330 *invalid = 1;
2331 return (value) ? 1 : 0;
2332}
7b934113 2333
b9c361e0
JL		 2334/* The VLESIMM field in an I16A form instruction. This is split. */
2335
2336static unsigned long
2337insert_vlesi (unsigned long insn,
2338 long value,
2339 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2340 const char **errmsg ATTRIBUTE_UNUSED)
2341{
2342 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2343}
2344
2345static long
2346extract_vlesi (unsigned long insn,
2347 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2348 int *invalid ATTRIBUTE_UNUSED)
2349{
b9c361e0 2350 long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
9f0682fe 2351 value = (value ^ 0x8000) - 0x8000;
b9c361e0
JL		 2352 return value;
2353}
2354
2355static unsigned long
2356insert_vlensi (unsigned long insn,
2357 long value,
2358 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2359 const char **errmsg ATTRIBUTE_UNUSED)
2360{
2361 value = -value;
2362 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2363}
2364static long
2365extract_vlensi (unsigned long insn,
2366 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2367 int *invalid ATTRIBUTE_UNUSED)
2368{
2369 long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
9f0682fe
AM		 2370 value = (value ^ 0x8000) - 0x8000;
2371 /* Don't use for disassembly. */
b9c361e0
JL		 2372 *invalid = 1;
2373 return -value;
2374}
2375
2376/* The VLEUIMM field in an I16A form instruction. This is split. */
2377
2378static unsigned long
2379insert_vleui (unsigned long insn,
2380 long value,
2381 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2382 const char **errmsg ATTRIBUTE_UNUSED)
2383{
2384 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2385}
2386
2387static long
2388extract_vleui (unsigned long insn,
2389 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2390 int *invalid ATTRIBUTE_UNUSED)
2391{
2392 return ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2393}
2394
2395/* The VLEUIMML field in an I16L form instruction. This is split. */
2396
2397static unsigned long
2398insert_vleil (unsigned long insn,
2399 long value,
2400 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2401 const char **errmsg ATTRIBUTE_UNUSED)
2402{
2403 return insn | ((value & 0xf800) << 5) | (value & 0x7ff);
2404}
2405
2406static long
2407extract_vleil (unsigned long insn,
2408 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2409 int *invalid ATTRIBUTE_UNUSED)
2410{
2411 return ((insn >> 5) & 0xf800) | (insn & 0x7ff);
2412}
2413
252b5132
RH		 2414\f
2415/* Macros used to form opcodes. */
2416
2417/* The main opcode. */
2418#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
2419#define OP_MASK OP (0x3f)
2420
2421/* The main opcode combined with a trap code in the TO field of a D
2422 form instruction. Used for extended mnemonics for the trap
2423 instructions. */
2424#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
2425#define OPTO_MASK (OP_MASK | TO_MASK)
2426
2427/* The main opcode combined with a comparison size bit in the L field
2428 of a D form or X form instruction. Used for extended mnemonics for
2429 the comparison instructions. */
2430#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
2431#define OPL_MASK OPL (0x3f,1)
2432
b9c361e0
JL		 2433/* The main opcode combined with an update code in D form instruction.
2434 Used for extended mnemonics for VLE memory instructions. */
2435#define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8))
2436#define OPVUP_MASK OPVUP (0x3f, 0xff)
2437
dfdaec14
AJ		 2438/* The main opcode combined with an update code and the RT fields specified in
2439 D form instruction. Used for VLE volatile context save/restore
2440 instructions. */
2441#define OPVUPRT(x,vup,rt) (OPVUP (x, vup) | ((((unsigned long)(rt)) & 0x1f) << 21))
2442#define OPVUPRT_MASK OPVUPRT (0x3f, 0xff, 0x1f)
2443
252b5132
RH		 2444/* An A form instruction. */
2445#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
2446#define A_MASK A (0x3f, 0x1f, 1)
2447
2448/* An A_MASK with the FRB field fixed. */
2449#define AFRB_MASK (A_MASK | FRB_MASK)
2450
2451/* An A_MASK with the FRC field fixed. */
2452#define AFRC_MASK (A_MASK | FRC_MASK)
2453
2454/* An A_MASK with the FRA and FRC fields fixed. */
2455#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
2456
702f0fb4
PB		 2457/* An AFRAFRC_MASK, but with L bit clear. */
2458#define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
2459
252b5132
RH		 2460/* A B form instruction. */
2461#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
2462#define B_MASK B (0x3f, 1, 1)
2463
b9c361e0
JL		 2464/* A BD8 form instruction. This is a 16-bit instruction. */
2465#define BD8(op, aa, lk) (((((unsigned long)(op)) & 0x3f) << 10) | (((aa) & 1) << 9) | (((lk) & 1) << 8))
2466#define BD8_MASK BD8 (0x3f, 1, 1)
2467
2468/* Another BD8 form instruction. This is a 16-bit instruction. */
2469#define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11)
2470#define BD8IO_MASK BD8IO (0x1f)
2471
2472/* A BD8 form instruction for simplified mnemonics. */
2473#define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
2474/* A mask that excludes BO32 and BI32. */
2475#define EBD8IO1_MASK 0xf800
2476/* A mask that includes BO32 and excludes BI32. */
2477#define EBD8IO2_MASK 0xfc00
2478/* A mask that include BO32 AND BI32. */
2479#define EBD8IO3_MASK 0xff00
2480
2481/* A BD15 form instruction. */
2482#define BD15(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 0xf) << 22) | ((lk) & 1))
2483#define BD15_MASK BD15 (0x3f, 0xf, 1)
2484
2485/* A BD15 form instruction for extended conditional branch mnemonics. */
2486#define EBD15(op, aa, bo, lk) (((op) & 0x3f) << 26) | (((aa) & 0xf) << 22) | (((bo) & 0x3) << 20) | ((lk) & 1)
2487#define EBD15_MASK 0xfff00001
2488
2489/* A BD15 form instruction for extended conditional branch mnemonics with BI. */
2490#define EBD15BI(op, aa, bo, bi, lk) (((op) & 0x3f) << 26) \
2491 | (((aa) & 0xf) << 22) \
2492 | (((bo) & 0x3) << 20) \
2493 | (((bi) & 0x3) << 16) \
2494 | ((lk) & 1)
2495#define EBD15BI_MASK 0xfff30001
2496
2497/* A BD24 form instruction. */
2498#define BD24(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 25) | ((lk) & 1))
2499#define BD24_MASK BD24 (0x3f, 1, 1)
2500
252b5132
RH		 2501/* A B form instruction setting the BO field. */
2502#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2503#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
2504
2505/* A BBO_MASK with the y bit of the BO field removed. This permits
2506 matching a conditional branch regardless of the setting of the y
94efba12 2507 bit. Similarly for the 'at' bits used for power4 branch hints. */
de866fcc 2508#define Y_MASK (((unsigned long) 1) << 21)
802a735e
AM		 2509#define AT1_MASK (((unsigned long) 3) << 21)
2510#define AT2_MASK (((unsigned long) 9) << 21)
2511#define BBOY_MASK (BBO_MASK &~ Y_MASK)
2512#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
252b5132
RH		 2513
2514/* A B form instruction setting the BO field and the condition bits of
2515 the BI field. */
2516#define BBOCB(op, bo, cb, aa, lk) \
2517 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
2518#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
2519
2520/* A BBOCB_MASK with the y bit of the BO field removed. */
2521#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
802a735e
AM		 2522#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
2523#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
252b5132
RH		 2524
2525/* A BBOYCB_MASK in which the BI field is fixed. */
2526#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
802a735e 2527#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
252b5132 2528
b9c361e0
JL		 2529/* A VLE C form instruction. */
2530#define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1))
2531#define C_LK_MASK C_LK(0x7fff, 1)
2532#define C(x) ((((unsigned long)(x)) & 0xffff))
2533#define C_MASK C(0xffff)
2534
23976049
EZ		 2535/* An Context form instruction. */
2536#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
fdd12ef3 2537#define CTX_MASK CTX(0x3f, 0x7)
23976049
EZ		 2538
2539/* An User Context form instruction. */
2540#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
fdd12ef3 2541#define UCTX_MASK UCTX(0x3f, 0x1f)
23976049 2542
252b5132
RH		 2543/* The main opcode mask with the RA field clear. */
2544#define DRA_MASK (OP_MASK | RA_MASK)
2545
a680de9a
PB		 2546/* A DQ form VSX instruction. */
2547#define DQX(op, xop) (OP (op) | ((xop) & 0x7))
2548#define DQX_MASK DQX (0x3f, 7)
2549
252b5132
RH		 2550/* A DS form instruction. */
2551#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
2552#define DS_MASK DSO (0x3f, 3)
2553
a680de9a
PB		 2554/* An DX form instruction. */
2555#define DX(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2556#define DX_MASK DX (0x3f, 0x1f)
1437d063
PB		 2557/* An DX form instruction with the D bits specified. */
2558#define NODX_MASK (DX_MASK | 0x1fffc1)
a680de9a 2559
23976049
EZ		 2560/* An EVSEL form instruction. */
2561#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
2562#define EVSEL_MASK EVSEL(0x3f, 0xff)
2563
b9c361e0
JL		 2564/* An IA16 form instruction. */
2565#define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2566#define IA16_MASK IA16(0x3f, 0x1f)
2567
2568/* An I16A form instruction. */
2569#define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2570#define I16A_MASK I16A(0x3f, 0x1f)
2571
2572/* An I16L form instruction. */
2573#define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2574#define I16L_MASK I16L(0x3f, 0x1f)
2575
2576/* An IM7 form instruction. */
2577#define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11)
2578#define IM7_MASK IM7(0x1f)
2579
252b5132
RH		 2580/* An M form instruction. */
2581#define M(op, rc) (OP (op) | ((rc) & 1))
2582#define M_MASK M (0x3f, 1)
2583
b9c361e0
JL		 2584/* An LI20 form instruction. */
2585#define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15)
2586#define LI20_MASK LI20(0x3f, 0x1)
2587
252b5132
RH		 2588/* An M form instruction with the ME field specified. */
2589#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
2590
2591/* An M_MASK with the MB and ME fields fixed. */
2592#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
2593
2594/* An M_MASK with the SH and ME fields fixed. */
2595#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
2596
2597/* An MD form instruction. */
2598#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
2599#define MD_MASK MD (0x3f, 0x7, 1)
2600
2601/* An MD_MASK with the MB field fixed. */
2602#define MDMB_MASK (MD_MASK | MB6_MASK)
2603
2604/* An MD_MASK with the SH field fixed. */
2605#define MDSH_MASK (MD_MASK | SH6_MASK)
2606
2607/* An MDS form instruction. */
2608#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
2609#define MDS_MASK MDS (0x3f, 0xf, 1)
2610
2611/* An MDS_MASK with the MB field fixed. */
2612#define MDSMB_MASK (MDS_MASK | MB6_MASK)
2613
2614/* An SC form instruction. */
2615#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
2616#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
2617
b9c361e0
JL		 2618/* An SCI8 form instruction. */
2619#define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11))
2620#define SCI8_MASK SCI8(0x3f, 0x1f)
2621
2622/* An SCI8 form instruction. */
2623#define SCI8BF(op, fop, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11) | (((fop) & 7) << 23))
2624#define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
2625
2626/* An SD4 form instruction. This is a 16-bit instruction. */
43e65147 2627#define SD4(op) ((((unsigned long)(op)) & 0xf) << 12)
b9c361e0
JL		 2628#define SD4_MASK SD4(0xf)
2629
2630/* An SE_IM5 form instruction. This is a 16-bit instruction. */
2631#define SE_IM5(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x1) << 9))
2632#define SE_IM5_MASK SE_IM5(0x3f, 1)
2633
2634/* An SE_R form instruction. This is a 16-bit instruction. */
2635#define SE_R(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3f) << 4))
2636#define SE_R_MASK SE_R(0x3f, 0x3f)
2637
2638/* An SE_RR form instruction. This is a 16-bit instruction. */
2639#define SE_RR(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3) << 8))
2640#define SE_RR_MASK SE_RR(0x3f, 3)
2641
2642/* A VX form instruction. */
786e2c0f
C		 2643#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2644
112290ab 2645/* The mask for an VX form instruction. */
786e2c0f
C		 2646#define VX_MASK VX(0x3f, 0x7ff)
2647
fb048c26
PB		 2648/* A VX_MASK with the VA field fixed. */
2649#define VXVA_MASK (VX_MASK | (0x1f << 16))
2650
2651/* A VX_MASK with the VB field fixed. */
2652#define VXVB_MASK (VX_MASK | (0x1f << 11))
2653
2654/* A VX_MASK with the VA and VB fields fixed. */
2655#define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))
2656
2657/* A VX_MASK with the VD and VA fields fixed. */
2658#define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))
2659
2660/* A VX_MASK with a UIMM4 field. */
2661#define VXUIMM4_MASK (VX_MASK | (0x1 << 20))
2662
2663/* A VX_MASK with a UIMM3 field. */
2664#define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
2665
2666/* A VX_MASK with a UIMM2 field. */
2667#define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
2668
c0637f3a
PB		 2669/* A VX_MASK with a PS field. */
2670#define VXPS_MASK (VX_MASK & ~(0x1 << 9))
2671
a680de9a
PB		 2672/* A VX_MASK with the VA field fixed with a PS field. */
2673#define VXVAPS_MASK ((VX_MASK | (0x1f << 16)) & ~(0x1 << 9))
2674
b9c361e0 2675/* A VA form instruction. */
2613489e 2676#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
786e2c0f 2677
112290ab 2678/* The mask for an VA form instruction. */
2613489e 2679#define VXA_MASK VXA(0x3f, 0x3f)
786e2c0f 2680
382c72e9
PB		 2681/* A VXA_MASK with a SHB field. */
2682#define VXASHB_MASK (VXA_MASK | (1 << 10))
2683
b9c361e0 2684/* A VXR form instruction. */
786e2c0f
C		 2685#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
2686
112290ab 2687/* The mask for a VXR form instruction. */
786e2c0f
C		 2688#define VXR_MASK VXR(0x3f, 0x3ff, 1)
2689
a680de9a
PB		 2690/* A VX form instruction with a VA tertiary opcode. */
2691#define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16))
2692
6fd3a02d
PB		 2693#define VXASH(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2694#define VXASH_MASK VXASH (0x3f, 0x1f)
2695
252b5132
RH		 2696/* An X form instruction. */
2697#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2698
a680de9a
PB		 2699/* A X form instruction for Quad-Precision FP Instructions. */
2700#define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16))
2701
b9c361e0
JL		 2702/* An EX form instruction. */
2703#define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2704
2705/* The mask for an EX form instruction. */
2706#define EX_MASK EX (0x3f, 0x7ff)
2707
066be9f7
PB		 2708/* An XX2 form instruction. */
2709#define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
2710
a680de9a
PB		 2711/* A XX2 form instruction with the VA bits specified. */
2712#define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16))
2713
9b4e5766
PB		 2714/* An XX3 form instruction. */
2715#define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
2716
066be9f7
PB		 2717/* An XX3 form instruction with the RC bit specified. */
2718#define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))
2719
2720/* An XX4 form instruction. */
2721#define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
9b4e5766 2722
702f0fb4
PB		 2723/* A Z form instruction. */
2724#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
2725
252b5132
RH		 2726/* An X form instruction with the RC bit specified. */
2727#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
2728
a680de9a
PB		 2729/* A X form instruction for Quad-Precision FP Instructions with RC bit. */
2730#define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1))
2731
6fd3a02d
PB		 2732/* An X form instruction with the RA bits specified as two ops. */
2733#define XMMF(op, xop, mop0, mop1) (X ((op), (xop)) | ((mop0) & 3) << 19 | ((mop1) & 7) << 16)
2734
702f0fb4
PB		 2735/* A Z form instruction with the RC bit specified. */
2736#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
2737
252b5132
RH		 2738/* The mask for an X form instruction. */
2739#define X_MASK XRC (0x3f, 0x3ff, 1)
2740
a680de9a
PB		 2741/* The mask for an X form instruction with the BF bits specified. */
2742#define XBF_MASK (X_MASK | (3 << 21))
2743
e0d602ec
BE		 2744/* An X form wait instruction with everything filled in except the WC field. */
2745#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2746
9b4e5766
PB		 2747/* The mask for an XX1 form instruction. */
2748#define XX1_MASK X (0x3f, 0x3ff)
2749
c0637f3a
PB		 2750/* An XX1_MASK with the RB field fixed. */
2751#define XX1RB_MASK (XX1_MASK | RB_MASK)
2752
066be9f7
PB		 2753/* The mask for an XX2 form instruction. */
2754#define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
2755
2756/* The mask for an XX2 form instruction with the UIM bits specified. */
2757#define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
2758
a680de9a
PB		 2759/* The mask for an XX2 form instruction with the 4 UIM bits specified. */
2760#define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20))
2761
066be9f7
PB		 2762/* The mask for an XX2 form instruction with the BF bits specified. */
2763#define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
2764
a680de9a
PB		 2765/* The mask for an XX2 form instruction with the BF and DCMX bits specified. */
2766#define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1)
2767
2768/* The mask for an XX2 form instruction with a split DCMX bits specified. */
2769#define XX2DCMXS_MASK XX2 (0x3f, 0x1ee)
2770
9b4e5766
PB		 2771/* The mask for an XX3 form instruction. */
2772#define XX3_MASK XX3 (0x3f, 0xff)
2773
066be9f7
PB		 2774/* The mask for an XX3 form instruction with the BF bits specified. */
2775#define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
2776
2777/* The mask for an XX3 form instruction with the DM or SHW bits specified. */
9b4e5766 2778#define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
066be9f7
PB		 2779#define XX3SHW_MASK XX3DM_MASK
2780
2781/* The mask for an XX4 form instruction. */
2782#define XX4_MASK XX4 (0x3f, 0x3)
2783
2784/* An X form wait instruction with everything filled in except the WC field. */
2785#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
9b4e5766 2786
6fd3a02d
PB		 2787/* The mask for an XMMF form instruction. */
2788#define XMMF_MASK (XMMF (0x3f, 0x3ff, 3, 7) | (1))
2789
702f0fb4
PB		 2790/* The mask for a Z form instruction. */
2791#define Z_MASK ZRC (0x3f, 0x1ff, 1)
0bbdef92 2792#define Z2_MASK ZRC (0x3f, 0xff, 1)
702f0fb4 2793
a680de9a 2794/* An X_MASK with the RA/VA field fixed. */
252b5132 2795#define XRA_MASK (X_MASK | RA_MASK)
a680de9a 2796#define XVA_MASK XRA_MASK
252b5132 2797
a680de9a 2798/* An XRA_MASK with the A_L/W field clear. */
ea192fa3 2799#define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
a680de9a 2800#define XRLA_MASK XWRA_MASK
ea192fa3 2801
252b5132
RH		 2802/* An X_MASK with the RB field fixed. */
2803#define XRB_MASK (X_MASK | RB_MASK)
2804
2805/* An X_MASK with the RT field fixed. */
2806#define XRT_MASK (X_MASK | RT_MASK)
2807
702f0fb4
PB		 2808/* An XRT_MASK mask with the L bits clear. */
2809#define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
2810
252b5132
RH		 2811/* An X_MASK with the RA and RB fields fixed. */
2812#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
2813
a680de9a
PB		 2814/* An XBF_MASK with the RA and RB fields fixed. */
2815#define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK)
2816
112290ab 2817/* An XRARB_MASK, but with the L bit clear. */
5ae2e65e
AM		 2818#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
2819
a680de9a
PB		 2820/* An XRARB_MASK, but with the L bits in a darn instruction clear. */
2821#define XLRAND_MASK (XRARB_MASK & ~((unsigned long) 3 << 16))
2822
252b5132
RH		 2823/* An X_MASK with the RT and RA fields fixed. */
2824#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
2825
5817ffd1
PB		 2826/* An X_MASK with the RT and RB fields fixed. */
2827#define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK)
2828
98acc1c5
AM		 2829/* An XRTRA_MASK, but with L bit clear. */
2830#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
2831
5817ffd1
PB		 2832/* An X_MASK with the RT, RA and RB fields fixed. */
2833#define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK)
2834
2835/* An XRTRARB_MASK, but with L bit clear. */
2836#define XRTLRARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 21))
2837
2838/* An XRTRARB_MASK, but with A bit clear. */
2839#define XRTARARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 25))
2840
2841/* An XRTRARB_MASK, but with BF bits clear. */
2842#define XRTBFRARB_MASK (XRTRARB_MASK & ~((unsigned long) 7 << 23))
2843
f3806e43
BE		 2844/* An X form instruction with the L bit specified. */
2845#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
252b5132 2846
e0d602ec
BE		 2847/* An X form instruction with the L bits specified. */
2848#define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2849
5817ffd1
PB		 2850/* An X form instruction with the L bit and RC bit specified. */
2851#define XRCL(op, xop, l, rc) (XRC ((op), (xop), (rc)) | ((((unsigned long)(l)) & 1) << 21))
2852
19a6653c
AM		 2853/* An X form instruction with RT fields specified */
2854#define XRT(op, xop, rt) (X ((op), (xop)) \
2855 | ((((unsigned long)(rt)) & 0x1f) << 21))
2856
2857/* An X form instruction with RT and RA fields specified */
2858#define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
2859 | ((((unsigned long)(rt)) & 0x1f) << 21) \
2860 | ((((unsigned long)(ra)) & 0x1f) << 16))
2861
252b5132
RH		 2862/* The mask for an X form comparison instruction. */
2863#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
2864
520ceea4
BE		 2865/* The mask for an X form comparison instruction with the L field
2866 fixed. */
2867#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
252b5132
RH		 2868
2869/* An X form trap instruction with the TO field specified. */
2870#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
2871#define XTO_MASK (X_MASK | TO_MASK)
2872
e0c21649
GK		 2873/* An X form tlb instruction with the SH field specified. */
2874#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
2875#define XTLB_MASK (X_MASK | SH_MASK)
2876
6ba045b1
AM		 2877/* An X form sync instruction. */
2878#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2879
2880/* An X form sync instruction with everything filled in except the LS field. */
2881#define XSYNC_MASK (0xff9fffff)
2882
aea77599
AM		 2883/* An X form sync instruction with everything filled in except the L and E fields. */
2884#define XSYNCLE_MASK (0xff90ffff)
2885
702f0fb4
PB		 2886/* An X_MASK, but with the EH bit clear. */
2887#define XEH_MASK (X_MASK & ~((unsigned long )1))
2888
f5c120c5
MG		 2889/* An X form AltiVec dss instruction. */
2890#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
2891#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
2892
252b5132
RH		 2893/* An XFL form instruction. */
2894#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
ea192fa3 2895#define XFL_MASK XFL (0x3f, 0x3ff, 1)
252b5132 2896
23976049 2897/* An X form isel instruction. */
de866fcc
AM		 2898#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2899#define XISEL_MASK XISEL(0x3f, 0x1f)
23976049 2900
252b5132
RH		 2901/* An XL form instruction with the LK field set to 0. */
2902#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2903
2904/* An XL form instruction which uses the LK field. */
2905#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
2906
2907/* The mask for an XL form instruction. */
2908#define XL_MASK XLLK (0x3f, 0x3ff, 1)
2909
c0637f3a
PB		 2910/* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */
2911#define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11))
2912
252b5132
RH		 2913/* An XL form instruction which explicitly sets the BO field. */
2914#define XLO(op, bo, xop, lk) \
2915 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2916#define XLO_MASK (XL_MASK | BO_MASK)
2917
2918/* An XL form instruction which explicitly sets the y bit of the BO
2919 field. */
2920#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
2921#define XLYLK_MASK (XL_MASK | Y_MASK)
2922
2923/* An XL form instruction which sets the BO field and the condition
2924 bits of the BI field. */
2925#define XLOCB(op, bo, cb, xop, lk) \
2926 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
2927#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
2928
2929/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
2930#define XLBB_MASK (XL_MASK | BB_MASK)
2931#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
2932#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
2933
d0618d1c
AM		 2934/* A mask for branch instructions using the BH field. */
2935#define XLBH_MASK (XL_MASK | (0x1c << 11))
2936
252b5132
RH		 2937/* An XL_MASK with the BO and BB fields fixed. */
2938#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
2939
2940/* An XL_MASK with the BO, BI and BB fields fixed. */
2941#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
2942
e01d869a
AM		 2943/* An X form mbar instruction with MO field. */
2944#define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21))
2945
252b5132
RH		 2946/* An XO form instruction. */
2947#define XO(op, xop, oe, rc) \
2948 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
2949#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
2950
2951/* An XO_MASK with the RB field fixed. */
2952#define XORB_MASK (XO_MASK | RB_MASK)
2953
c3d65c1c
BE		 2954/* An XOPS form instruction for paired singles. */
2955#define XOPS(op, xop, rc) \
2956 (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2957#define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
2958
2959
252b5132
RH		 2960/* An XS form instruction. */
2961#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
2962#define XS_MASK XS (0x3f, 0x1ff, 1)
2963
2964/* A mask for the FXM version of an XFX form instruction. */
98e69875 2965#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
252b5132
RH		 2966
2967/* An XFX form instruction with the FXM field filled in. */
98e69875
AM		 2968#define XFXM(op, xop, fxm, p4) \
2969 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
2970 | ((unsigned long)(p4) << 20))
252b5132
RH		 2971
2972/* An XFX form instruction with the SPR field filled in. */
2973#define XSPR(op, xop, spr) \
2974 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
2975#define XSPR_MASK (X_MASK | SPR_MASK)
2976
2977/* An XFX form instruction with the SPR field filled in except for the
2978 SPRBAT field. */
2979#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
2980
2981/* An XFX form instruction with the SPR field filled in except for the
2982 SPRG field. */
b84bf58a 2983#define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
252b5132
RH		 2984
2985/* An X form instruction with everything filled in except the E field. */
2986#define XE_MASK (0xffff7fff)
2987
23976049
EZ		 2988/* An X form user context instruction. */
2989#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
2990#define XUC_MASK XUC(0x3f, 0x1f)
2991
c3d65c1c
BE		 2992/* An XW form instruction. */
2993#define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
2994/* The mask for a G form instruction. rc not supported at present. */
2995#define XW_MASK XW (0x3f, 0x3f, 0)
2996
081ba1b3
AM		 2997/* An APU form instruction. */
2998#define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
2999
3000/* The mask for an APU form instruction. */
3001#define APU_MASK APU (0x3f, 0x3ff, 1)
3002#define APU_RT_MASK (APU_MASK | RT_MASK)
3003#define APU_RA_MASK (APU_MASK | RA_MASK)
3004
252b5132
RH		 3005/* The BO encodings used in extended conditional branch mnemonics. */
3006#define BODNZF (0x0)
3007#define BODNZFP (0x1)
3008#define BODZF (0x2)
3009#define BODZFP (0x3)
252b5132
RH		 3010#define BODNZT (0x8)
3011#define BODNZTP (0x9)
3012#define BODZT (0xa)
3013#define BODZTP (0xb)
802a735e
AM		 3014
3015#define BOF (0x4)
3016#define BOFP (0x5)
94efba12
AM		 3017#define BOFM4 (0x6)
3018#define BOFP4 (0x7)
252b5132
RH		 3019#define BOT (0xc)
3020#define BOTP (0xd)
94efba12
AM		 3021#define BOTM4 (0xe)
3022#define BOTP4 (0xf)
802a735e 3023
252b5132
RH		 3024#define BODNZ (0x10)
3025#define BODNZP (0x11)
3026#define BODZ (0x12)
3027#define BODZP (0x13)
94efba12
AM		 3028#define BODNZM4 (0x18)
3029#define BODNZP4 (0x19)
3030#define BODZM4 (0x1a)
3031#define BODZP4 (0x1b)
802a735e 3032
252b5132
RH		 3033#define BOU (0x14)
3034
b9c361e0
JL		 3035/* The BO16 encodings used in extended VLE conditional branch mnemonics. */
3036#define BO16F (0x0)
3037#define BO16T (0x1)
3038
3039/* The BO32 encodings used in extended VLE conditional branch mnemonics. */
3040#define BO32F (0x0)
3041#define BO32T (0x1)
3042#define BO32DNZ (0x2)
3043#define BO32DZ (0x3)
3044
252b5132
RH		 3045/* The BI condition bit encodings used in extended conditional branch
3046 mnemonics. */
3047#define CBLT (0)
3048#define CBGT (1)
3049#define CBEQ (2)
3050#define CBSO (3)
3051
3052/* The TO encodings used in extended trap mnemonics. */
3053#define TOLGT (0x1)
3054#define TOLLT (0x2)
3055#define TOEQ (0x4)
3056#define TOLGE (0x5)
3057#define TOLNL (0x5)
3058#define TOLLE (0x6)
3059#define TOLNG (0x6)
3060#define TOGT (0x8)
3061#define TOGE (0xc)
3062#define TONL (0xc)
3063#define TOLT (0x10)
3064#define TOLE (0x14)
3065#define TONG (0x14)
3066#define TONE (0x18)
3067#define TOU (0x1f)
3068\f
3069/* Smaller names for the flags so each entry in the opcodes table will
3070 fit on a single line. */
3071#undef PPC
de866fcc 3072#define PPC PPC_OPCODE_PPC
661bd698 3073#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
661bd698 3074#define POWER4 PPC_OPCODE_POWER4
1ed8e1e4 3075#define POWER5 PPC_OPCODE_POWER5
702f0fb4 3076#define POWER6 PPC_OPCODE_POWER6
066be9f7 3077#define POWER7 PPC_OPCODE_POWER7
5817ffd1 3078#define POWER8 PPC_OPCODE_POWER8
a680de9a 3079#define POWER9 PPC_OPCODE_POWER9
ede602d7 3080#define CELL PPC_OPCODE_CELL
bdc70b4a 3081#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
6b069ee7 3082#define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \
bdc70b4a 3083 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
418c1742 3084#define PPC403 PPC_OPCODE_403
081ba1b3 3085#define PPC405 PPC_OPCODE_405
7d5b217e 3086#define PPC440 PPC_OPCODE_440
c8187e15 3087#define PPC464 PPC440
9fe54b1c 3088#define PPC476 PPC_OPCODE_476
ef5a96d5
AM		 3089#define PPC750 PPC_OPCODE_750
3090#define PPC7450 PPC_OPCODE_7450
3091#define PPC860 PPC_OPCODE_860
c3d65c1c 3092#define PPCPS PPC_OPCODE_PPCPS
a404d431 3093#define PPCVEC PPC_OPCODE_ALTIVEC
9a85b496
AM		 3094#define PPCVEC2 (PPC_OPCODE_POWER8 | PPC_OPCODE_E6500)
3095#define PPCVEC3 PPC_OPCODE_POWER9
9b4e5766 3096#define PPCVSX PPC_OPCODE_VSX
9570835e
AM		 3097#define PPCVSX2 PPC_OPCODE_POWER8
3098#define PPCVSX3 PPC_OPCODE_POWER9
de866fcc
AM		 3099#define POWER PPC_OPCODE_POWER
3100#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
81a0b7e2
AM		 3101#define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
3102#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
de866fcc 3103#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
de866fcc 3104#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
661bd698 3105#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
de866fcc 3106#define MFDEC1 PPC_OPCODE_POWER
bdc70b4a 3107#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
418c1742 3108#define BOOKE PPC_OPCODE_BOOKE
14b57c7c 3109#define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS
36ae0db3 3110#define PPCE300 PPC_OPCODE_E300
14b57c7c
AM		 3111#define PPCSPE PPC_OPCODE_SPE
3112#define PPCISEL PPC_OPCODE_ISEL
3113#define PPCEFS PPC_OPCODE_EFS
de866fcc 3114#define PPCBRLK PPC_OPCODE_BRLOCK
23976049 3115#define PPCPMR PPC_OPCODE_PMR
aea77599 3116#define PPCTMR PPC_OPCODE_TMR
de866fcc 3117#define PPCCHLK PPC_OPCODE_CACHELCK
23976049 3118#define PPCRFMCI PPC_OPCODE_RFMCI
19a6653c 3119#define E500MC PPC_OPCODE_E500MC
634b50f2 3120#define PPCA2 PPC_OPCODE_A2
43e65147 3121#define TITAN PPC_OPCODE_TITAN
62adc510 3122#define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | PPC_OPCODE_476 | TITAN
e01d869a 3123#define E500 PPC_OPCODE_E500
aea77599 3124#define E6500 PPC_OPCODE_E6500
b9c361e0 3125#define PPCVLE PPC_OPCODE_VLE
ef85eab0 3126#define PPCHTM PPC_OPCODE_POWER8
dfdaec14 3127#define E200Z4 PPC_OPCODE_E200Z4
4fff86c5
PB		 3128/* The list of embedded processors that use the embedded operand ordering
3129 for the 3 operand dcbt and dcbtst instructions. */
3130#define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
14b57c7c 3131 | PPC_OPCODE_A2)
4fff86c5
PB		 3132
3133
252b5132
RH		 3134\f
3135/* The opcode table.
3136
3137 The format of the opcode table is:
3138
8ebac3aa 3139 NAME OPCODE MASK FLAGS ANTI {OPERANDS}
252b5132
RH		 3140
3141 NAME is the name of the instruction.
3142 OPCODE is the instruction opcode.
3143 MASK is the opcode mask; this is used to tell the disassembler
3144 which bits in the actual opcode must match OPCODE.
8ebac3aa
AM		 3145 FLAGS are flags indicating which processors support the instruction.
3146 ANTI indicates which processors don't support the instruction.
252b5132
RH		 3147 OPERANDS is the list of operands.
3148
3149 The disassembler reads the table in order and prints the first
3150 instruction which matches, so this table is sorted to put more
de866fcc
AM		 3151 specific instructions before more general instructions.
3152
3153 This table must be sorted by major opcode. Please try to keep it
3154 vaguely sorted within major opcode too, except of course where
3155 constrained otherwise by disassembler operation. */
252b5132
RH		 3156
3157const struct powerpc_opcode powerpc_opcodes[] = {
14b57c7c
AM		 3158{"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476|PPCVLE, {0}},
3159{"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3160{"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3161{"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3162{"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3163{"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3164{"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3165{"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3166{"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3167{"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3168{"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3169{"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3170{"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3171{"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3172{"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3173{"tdui", OPTO(2,TOU), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3174{"tdi", OP(2), OP_MASK, PPC64, PPCVLE, {TO, RA, SI}},
3175
3176{"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3177{"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3178{"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3179{"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3180{"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3181{"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3182{"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3183{"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3184{"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3185{"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3186{"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3187{"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3188{"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3189{"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3190{"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3191{"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3192{"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3193{"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3194{"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3195{"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3196{"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3197{"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3198{"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3199{"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3200{"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3201{"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3202{"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3203{"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3204{"twui", OPTO(3,TOU), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3205{"tui", OPTO(3,TOU), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3206{"twi", OP(3), OP_MASK, PPCCOM, PPCVLE, {TO, RA, SI}},
3207{"ti", OP(3), OP_MASK, PWRCOM, PPCVLE, {TO, RA, SI}},
3208
3209{"ps_cmpu0", X (4, 0), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3210{"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3211{"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
3212{"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3213{"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3214{"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3215{"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3216{"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3217{"vaddfp", VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3218{"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
3219{"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3220{"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
3221{"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3222{"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3223{"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3224{"ps_sum0", A (4, 10,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3225{"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3226{"ps_sum1", A (4, 11,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3227{"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3228{"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3229{"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3230{"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3231{"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3232{"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3233{"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3234{"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3235{"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3236{"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3237{"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3238{"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3239{"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3240{"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3241{"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
3242{"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3243{"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3244{"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3245{"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3246{"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3247{"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3248{"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3249{"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3250{"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3251{"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3252{"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3253{"vsel", VXA(4, 42), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3254{"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3255{"vperm", VXA(4, 43), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3256{"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC, 0, {VD, VA, VB, SHB}},
3257{"vpermxor", VXA(4, 45), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3258{"ps_sel", A (4, 23,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3259{"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
3260{"ps_sel.", A (4, 23,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3261{"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
3262{"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3263{"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3264{"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3265{"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3266{"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3267{"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3268{"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3269{"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3270{"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3271{"ps_msub", A (4, 28,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3272{"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3273{"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3274{"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3275{"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
3276{"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3277{"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3278{"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3279{"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3280{"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3281{"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3282{"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3283{"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3284{"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3285{"vadduhm", VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3286{"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3287{"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3288{"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3289{"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3290{"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3291{"vmulouh", VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3292{"vsubfp", VX (4, 74), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3293{"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
3294{"vmrghh", VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3295{"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
3296{"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3297{"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3298{"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3299{"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3300{"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3301{"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3302{"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3303{"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3304{"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3305{"ps_cmpu1", X (4, 64), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3306{"vadduwm", VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3307{"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3308{"vrlw", VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3309{"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3310{"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3311{"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3312{"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3313{"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3314{"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3315{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3316{"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3317{"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3318{"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3319{"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3320{"ps_cmpo1", X (4, 96), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3321{"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3322{"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3323{"vrld", VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3324{"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3325{"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3326{"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3327{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3328{"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3329{"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3330{"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3331{"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3332{"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3333{"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3334{"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3335{"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3336{"vmulosb", VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3337{"vrefp", VX (4, 266), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3338{"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3339{"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3340{"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3341{"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3342{"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3343{"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3344{"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3345{"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3346{"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3347{"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3348{"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3349{"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3350{"vmulosh", VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3351{"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3352{"vmrglh", VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3353{"vpkswus", VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3354{"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3355{"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3356{"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3357{"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3358{"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3359{"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3360{"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3361{"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3362{"vslw", VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3363{"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3364{"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3365{"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3366{"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3367{"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3368{"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3369{"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3370{"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3371{"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3372{"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3373{"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3374{"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3375{"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3376{"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3377{"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3378{"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3379{"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3380{"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3381{"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3382{"vaddubs", VX (4, 512), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3383{"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
3384{"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
3385{"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3386{"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3387{"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}},
3388{"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3389{"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}},
3390{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
3391{"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3392{"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}},
3393{"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3394{"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}},
3395{"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}},
3396{"vrfin", VX (4, 522), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3397{"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}},
3398{"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}},
3399{"vspltb", VX (4, 524), VXUIMM4_MASK, PPCVEC, 0, {VD, VB, UIMM4}},
3400{"vextractub", VX (4, 525), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3401{"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}},
3402{"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}},
3403{"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3404{"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3405{"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3406{"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3407{"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3408{"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3409{"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3410{"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
3411{"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3412{"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3413{"evnot", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
3414{"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3415{"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3416{"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3417{"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3418{"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3419{"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3420{"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3421{"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3422{"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3423{"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3424{"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3425{"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}},
3426{"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3427{"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}},
3428{"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3429{"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3430{"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3431{"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3432{"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3433{"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3434{"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3435{"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3436{"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3437{"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3438{"vadduhs", VX (4, 576), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3439{"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3440{"vminuh", VX (4, 578), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3441{"vsrh", VX (4, 580), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3442{"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3443{"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3444{"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3445{"vsplth", VX (4, 588), VXUIMM3_MASK, PPCVEC, 0, {VD, VB, UIMM3}},
3446{"vextractuh", VX (4, 589), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3447{"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3448{"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3449{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}},
3450{"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3451{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3452{"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3453{"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3454{"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3455{"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}},
3456{"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3457{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}},
3458{"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}},
3459{"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3460{"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3461{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3462{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3463{"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3464{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3465{"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}},
3466{"vextractuw", VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3467{"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3468{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3469{"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3470{"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}},
3471{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}},
3472{"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}},
3473{"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}},
3474{"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}},
3475{"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}},
3476{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}},
3477{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}},
3478{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}},
3479{"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3480{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}},
3481{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3482{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3483{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3484{"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3485{"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3486{"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3487{"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3488{"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
3489{"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3490{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
3491{"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
3492{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3493{"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3494{"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3495{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3496{"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3497{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3498{"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3499{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3500{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3501{"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3502{"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}},
3503{"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
3504{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
3505{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
3506{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
3507{"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
3508{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
3509{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
3510{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
3511{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},
3512{"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3513{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},
3514{"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3515{"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3516{"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3517{"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3518{"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3519{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, 0, {RS, RB}},
3520{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, 0, {RS, RB}},
3521{"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}},
3522{"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}},
3523{"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}},
3524{"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3525{"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3526{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, 0, {RS, RB}},
3527{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, 0, {RS, RB}},
3528{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3529{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3530{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3531{"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}},
3532{"efdcfui", VX (4, 752), VX_MASK, PPCEFS, 0, {RS, RB}},
3533{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, 0, {RS, RB}},
3534{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}},
3535{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}},
3536{"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}},
3537{"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}},
3538{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}},
3539{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}},
3540{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, 0, {RS, RB}},
3541{"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3542{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, 0, {RS, RB}},
3543{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3544{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3545{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3546{"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3547{"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3548{"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3549{"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3550{"vminsb", VX (4, 770), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3551{"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3552{"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3553{"vsrab", VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3554{"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3555{"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3556{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3557{"vmulesb", VX (4, 776), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3558{"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
3559{"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3560{"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3561{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3562{"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
3563{"vinsertb", VX (4, 781), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3564{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
3565{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3566{"vpkpx", VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3567{"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
3568{"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3569{"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3570{"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3571{"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3572{"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3573{"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3574{"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3575{"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3576{"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3577{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3578{"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3579{"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3580{"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3581{"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3582{"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3583{"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3584{"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3585{"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3586{"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3587{"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3588{"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3589{"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3590{"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3591{"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3592{"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3593{"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3594{"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3595{"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3596{"vaddshs", VX (4, 832), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3597{"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3598{"vminsh", VX (4, 834), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3599{"vsrah", VX (4, 836), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3600{"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3601{"vmulesh", VX (4, 840), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3602{"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3603{"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3604{"vspltish", VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
3605{"vinserth", VX (4, 845), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3606{"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3607{"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3608{"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3609{"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3610{"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3611{"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3612{"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3613{"vaddsws", VX (4, 896), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3614{"vminsw", VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3615{"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3616{"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3617{"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3618{"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3619{"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3620{"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
3621{"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3622{"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3623{"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3624{"vminsd", VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3625{"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3626{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3627{"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3628{"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3629{"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3630{"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3631{"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3632{"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3633{"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3634{"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3635{"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3636{"vsububm", VX (4,1024), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3637{"bcdadd.", VX (4,1025), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
3638{"vavgub", VX (4,1026), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3639{"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3640{"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3641{"vand", VX (4,1028), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3642{"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3643{"vcmpneb.", VXR(4, 7,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
62adc510
AM		 3644{"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
3645{"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 3646{"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3647{"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3648{"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3649{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3650{"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3651{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3652{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3653{"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3654{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3655{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3656{"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3657{"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3658{"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3659{"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3660{"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3661{"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3662{"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3663{"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3664{"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3665{"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3666{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3667{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3668{"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3669{"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
3670{"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3671{"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3672{"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3673{"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
62adc510
AM		 3674{"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
3675{"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 3676{"vcmpneh.", VXR(4, 71,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3677{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3678{"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3679{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3680{"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3681{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3682{"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3683{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3684{"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3685{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3686{"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3687{"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3688{"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3689{"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3690{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3691{"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3692{"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3693{"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3694{"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3695{"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3696{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3697{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3698{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3699{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3700{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3701{"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3702{"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3703{"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3704{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3705{"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3706{"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3707{"vavguw", VX (4,1154), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3708{"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3709{"vmr", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
3710{"vor", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3711{"vcmpnew.", VXR(4, 135,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3712{"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3713{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
62adc510
AM		 3714{"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
3715{"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 3716{"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3717{"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3718{"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3719{"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3720{"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3721{"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}},
3722{"bcds.", VX (4,1217), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
3723{"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}},
3724{"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}},
3725{"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}},
3726{"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}},
3727{"vxor", VX (4,1220), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3728{"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3729{"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
62adc510 3730{"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
14b57c7c 3731{"vcmpequd.", VXR(4, 199,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
62adc510 3732{"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 3733{"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3734{"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3735{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}},
3736{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}},
3737{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}},
3738{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}},
3739{"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3740{"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3741{"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3742{"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3743{"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3744{"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3745{"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3746{"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3747{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3748{"bcdtrunc.", VX (4,1281), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
3749{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3750{"vavgsb", VX (4,1282), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3751{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3752{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3753{"vnot", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
3754{"vnor", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3755{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
62adc510
AM		 3756{"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
3757{"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 3758{"vcmpnezb.", VXR(4, 263,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3759{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3760{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3761{"vcipher", VX (4,1288), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3762{"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3763{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3764{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3765{"vgbbd", VX (4,1292), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3766{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3767{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3768{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3769{"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3770{"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3771{"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3772{"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3773{"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3774{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3775{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3776{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3777{"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3778{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3779{"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3780{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3781{"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3782{"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
62adc510
AM		 3783{"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
3784{"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 3785{"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3786{"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3787{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3788{"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3789{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3790{"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3791{"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3792{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3793{"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3794{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3795{"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3796{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3797{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3798{"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3799{"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3800{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3801{"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3802{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3803{"bcdctsq.", VXVA(4,1409,0), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3804{"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3805{"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3806{"bcdctn.", VXVA(4,1409,5), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3807{"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3808{"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3809{"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3810{"vavgsw", VX (4,1410), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3811{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3812{"vnand", VX (4,1412), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3813{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3814{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
62adc510
AM		 3815{"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
3816{"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 3817{"vcmpnezw.", VXR(4, 391,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3818{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3819{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3820{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3821{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3822{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3823{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3824{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3825{"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3826{"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3827{"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3828{"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3829{"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3830{"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3831{"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3832{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3833{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3834{"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
3835{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3836{"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3837{"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
62adc510
AM		 3838{"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
3839{"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 3840{"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}},
3841{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3842{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3843{"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3844{"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3845{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3846{"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3847{"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3848{"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3849{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3850{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3851{"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3852{"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3853{"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3854{"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
3855{"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
3856{"vnegw", VXVA(4,1538,6), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3857{"vnegd", VXVA(4,1538,7), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3858{"vprtybw", VXVA(4,1538,8), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3859{"vprtybd", VXVA(4,1538,9), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3860{"vprtybq", VXVA(4,1538,10), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3861{"vextsb2w", VXVA(4,1538,16), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3862{"vextsh2w", VXVA(4,1538,17), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3863{"vextsb2d", VXVA(4,1538,24), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3864{"vextsh2d", VXVA(4,1538,25), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3865{"vextsw2d", VXVA(4,1538,26), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3866{"vctzb", VXVA(4,1538,28), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3867{"vctzh", VXVA(4,1538,29), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3868{"vctzw", VXVA(4,1538,30), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3869{"vctzd", VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3870{"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC, 0, {VD}},
3871{"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
62adc510
AM		 3872{"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
3873{"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 3874{"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3875{"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3876{"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3877{"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC, 0, {VB}},
3878{"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3879{"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
62adc510
AM		 3880{"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
3881{"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 3882{"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3883{"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3884{"vsubuws", VX (4,1664), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3885{"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
3886{"veqv", VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3887{"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
62adc510
AM		 3888{"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
3889{"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 3890{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3891{"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3892{"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3893{"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
3894{"vsrd", VX (4,1732), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3895{"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
62adc510 3896{"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
14b57c7c 3897{"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
62adc510 3898{"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 3899{"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3900{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3901{"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3902{"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3903{"vsrv", VX (4,1796), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3904{"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
62adc510
AM		 3905{"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
3906{"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 3907{"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3908{"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3909{"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3910{"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3911{"vsubshs", VX (4,1856), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3912{"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3913{"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3914{"vslv", VX (4,1860), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3915{"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3916{"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
62adc510
AM		 3917{"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
3918{"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 3919{"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3920{"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3921{"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3922{"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3923{"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3924{"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3925{"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3926{"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
62adc510
AM		 3927{"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
3928{"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 3929{"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3930{"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3931{"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3932{"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3933{"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3934{"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3935{"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3936{"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
62adc510 3937{"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
14b57c7c 3938{"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
62adc510 3939{"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
14b57c7c
AM		 3940{"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3941{"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3942{"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3943{"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3944{"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}},
3945
3946{"mulli", OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3947{"muli", OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3948
3949{"subfic", OP(8), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3950{"sfi", OP(8), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3951
3952{"dozi", OP(9), OP_MASK, M601, PPCVLE, {RT, RA, SI}},
3953
3954{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, UISIGNOPT}},
3955{"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, UISIGNOPT}},
a5721ba2 3956{"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, UISIGNOPT}},
14b57c7c
AM		 3957{"cmpli", OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}},
3958
3959{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, SI}},
3960{"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, SI}},
a5721ba2 3961{"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, SI}},
14b57c7c
AM		 3962{"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}},
3963
3964{"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3965{"ai", OP(12), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3966{"subic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
3967
3968{"addic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3969{"ai.", OP(13), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3970{"subic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
3971
3972{"li", OP(14), DRA_MASK, PPCCOM, PPCVLE, {RT, SI}},
3973{"lil", OP(14), DRA_MASK, PWRCOM, PPCVLE, {RT, SI}},
3974{"addi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SI}},
3975{"cal", OP(14), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
3976{"subi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSI}},
3977{"la", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
3978
3979{"lis", OP(15), DRA_MASK, PPCCOM, PPCVLE, {RT, SISIGNOPT}},
3980{"liu", OP(15), DRA_MASK, PWRCOM, PPCVLE, {RT, SISIGNOPT}},
3981{"addis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
3982{"cau", OP(15), OP_MASK, PWRCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
3983{"subis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSISIGNOPT}},
3984
3985{"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
3986{"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
3987{"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}},
3988{"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}},
3989{"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
3990{"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
3991{"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}},
3992{"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}},
3993{"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
3994{"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
3995{"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}},
3996{"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}},
3997{"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
3998{"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
3999{"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}},
4000{"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}},
4001{"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
4002{"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
4003{"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCVLE, {BD}},
4004{"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
4005{"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
4006{"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCVLE, {BD}},
4007{"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
4008{"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
4009{"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCVLE, {BDA}},
4010{"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
4011{"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
4012{"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCVLE, {BDA}},
4013
4014{"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4015{"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4016{"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4017{"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4018{"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4019{"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4020{"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4021{"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4022{"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4023{"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4024{"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4025{"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4026{"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4027{"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4028{"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4029{"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4030{"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4031{"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4032{"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4033{"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4034{"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4035{"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4036{"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4037{"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4038{"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4039{"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4040{"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4041{"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4042{"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4043{"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4044{"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4045{"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4046{"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4047{"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4048{"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4049{"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4050{"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4051{"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4052{"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4053{"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4054{"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4055{"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4056{"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4057{"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4058{"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4059{"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4060{"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4061{"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4062{"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4063{"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4064{"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4065{"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4066{"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4067{"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4068{"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4069{"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4070{"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4071{"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4072{"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4073{"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4074{"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4075{"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4076{"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4077{"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4078{"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4079{"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4080{"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4081{"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4082{"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4083{"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4084{"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4085{"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4086{"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4087{"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4088{"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4089{"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4090{"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4091{"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4092{"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4093{"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4094{"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4095{"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4096{"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4097{"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4098
4099{"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4100{"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4101{"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4102{"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4103{"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4104{"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4105{"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4106{"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4107{"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4108{"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4109{"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4110{"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4111{"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4112{"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4113{"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4114{"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4115{"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4116{"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4117{"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4118{"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4119{"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4120{"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4121{"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4122{"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4123{"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4124{"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4125{"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4126{"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4127{"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4128{"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4129{"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4130{"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4131{"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4132{"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4133{"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4134{"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4135{"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4136{"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4137{"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4138{"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4139{"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4140{"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4141{"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4142{"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4143{"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4144{"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4145{"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4146{"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4147{"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4148{"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4149{"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4150{"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4151{"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4152{"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4153{"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4154{"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4155{"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4156{"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4157{"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4158{"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4159
4160{"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4161{"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4162{"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4163{"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4164{"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4165{"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4166{"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4167{"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4168{"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4169{"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4170{"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4171{"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4172{"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4173{"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4174{"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4175{"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4176{"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4177{"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4178{"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4179{"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4180{"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4181{"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4182{"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4183{"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4184
4185{"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4186{"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4187{"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4188{"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4189{"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4190{"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4191{"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4192{"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4193{"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4194{"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4195{"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4196{"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4197{"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4198{"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4199{"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4200{"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4201
4202{"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4203{"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4204{"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4205{"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4206{"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4207{"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4208{"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4209{"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4210{"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4211{"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4212{"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4213{"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4214{"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4215{"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4216{"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4217{"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4218{"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4219{"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4220{"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4221{"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4222{"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4223{"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4224{"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4225{"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4226
4227{"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4228{"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4229{"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4230{"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4231{"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4232{"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4233{"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4234{"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4235{"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4236{"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4237{"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4238{"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4239{"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4240{"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4241{"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4242{"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4243
4244{"bc-", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}},
4245{"bc+", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}},
4246{"bc", B(16,0,0), B_MASK, COM, PPCVLE, {BO, BI, BD}},
4247{"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}},
4248{"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}},
4249{"bcl", B(16,0,1), B_MASK, COM, PPCVLE, {BO, BI, BD}},
4250{"bca-", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}},
4251{"bca+", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}},
4252{"bca", B(16,1,0), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
4253{"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}},
4254{"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}},
4255{"bcla", B(16,1,1), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
4256
4257{"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
dce75bf9 4258{"scv", SC(17,0,1), SC_MASK, POWER9, PPCVLE, {SVC_LEV}},
14b57c7c
AM		 4259{"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
4260{"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}},
4261{"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}},
4262{"svcla", SC(17,1,1), SC_MASK, POWER, PPCVLE, {SV}},
4263
4264{"b", B(18,0,0), B_MASK, COM, PPCVLE, {LI}},
4265{"bl", B(18,0,1), B_MASK, COM, PPCVLE, {LI}},
4266{"ba", B(18,1,0), B_MASK, COM, PPCVLE, {LIA}},
4267{"bla", B(18,1,1), B_MASK, COM, PPCVLE, {LIA}},
4268
4269{"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
4270
1437d063 4271{"lnia", DX(19,2), NODX_MASK, POWER9, PPCVLE, {RT}},
14b57c7c
AM		 4272{"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}},
4273{"subpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, NDXD}},
4274
4275{"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4276{"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4277{"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4278{"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4279{"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4280{"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4281{"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4282{"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4283{"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4284{"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4285{"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4286{"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4287{"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4288{"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}},
4289{"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4290{"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}},
4291{"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4292{"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4293{"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4294{"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4295{"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4296{"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4297{"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4298{"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4299
4300{"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4301{"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4302{"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4303{"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4304{"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4305{"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4306{"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4307{"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4308{"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4309{"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4310{"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4311{"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4312{"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4313{"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4314{"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4315{"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4316{"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4317{"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4318{"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4319{"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4320{"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4321{"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4322{"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4323{"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4324{"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4325{"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4326{"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4327{"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4328{"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4329{"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4330{"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4331{"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4332{"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4333{"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4334{"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4335{"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4336{"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4337{"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4338{"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4339{"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4340{"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4341{"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4342{"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4343{"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4344{"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4345{"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4346{"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4347{"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4348{"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4349{"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4350{"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4351{"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4352{"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4353{"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4354{"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4355{"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4356{"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4357{"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4358{"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4359{"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4360{"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4361{"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4362{"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4363{"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4364{"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4365{"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4366{"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4367{"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4368{"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4369{"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4370{"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4371{"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4372{"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4373{"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4374{"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4375{"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4376{"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4377{"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4378{"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4379{"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4380{"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4381{"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4382{"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4383{"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4384{"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4385{"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4386{"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4387{"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4388{"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4389{"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4390{"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4391{"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4392{"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4393{"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4394{"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4395{"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4396{"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4397{"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4398{"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4399{"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4400{"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4401{"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4402{"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4403{"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4404{"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4405{"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4406{"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4407{"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4408{"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4409{"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4410{"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4411{"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4412{"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4413{"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4414{"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4415{"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4416{"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4417{"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4418{"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4419{"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4420{"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4421{"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4422{"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4423{"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4424{"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4425{"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4426{"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4427{"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4428{"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4429{"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4430{"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4431{"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4432{"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4433{"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4434{"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4435{"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4436{"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4437{"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4438{"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4439{"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4440
4441{"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4442{"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4443{"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4444{"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4445{"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4446{"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4447{"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4448{"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4449{"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4450{"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4451{"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4452{"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4453{"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4454{"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4455{"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4456{"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4457{"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4458{"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4459{"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4460{"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4461{"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4462{"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4463{"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4464{"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4465{"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4466{"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4467{"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4468{"bdnztlrl-", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4469{"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4470{"bdnztlrl+", XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4471{"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4472{"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4473{"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4474{"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4475{"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4476{"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4477{"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4478{"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4479{"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4480{"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4481{"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4482{"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4483{"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4484{"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4485{"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4486{"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4487{"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4488{"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4489
4490{"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4491{"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4492{"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4493{"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4494{"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4495{"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4496{"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4497{"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4498
4499{"rfid", XL(19,18), 0xffffffff, PPC64, PPCVLE, {0}},
4500
4501{"crnot", XL(19,33), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}},
4502{"crnor", XL(19,33), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4503{"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCVLE, {0}},
4504
4505{"rfdi", XL(19,39), 0xffffffff, E500MC, PPCVLE, {0}},
4506{"rfi", XL(19,50), 0xffffffff, COM, PPCVLE, {0}},
4507{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}},
4508
dce75bf9 4509{"rfscv", XL(19,82), 0xffffffff, POWER9, PPCVLE, {0}},
14b57c7c
AM		 4510{"rfsvc", XL(19,82), 0xffffffff, POWER, PPCVLE, {0}},
4511
4512{"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCVLE, {0}},
4513
4514{"crandc", XL(19,129), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4515
4516{"rfebb", XL(19,146), XLS_MASK, POWER8, PPCVLE, {SXL}},
4517
4518{"isync", XL(19,150), 0xffffffff, PPCCOM, PPCVLE, {0}},
4519{"ics", XL(19,150), 0xffffffff, PWRCOM, PPCVLE, {0}},
4520
4521{"crclr", XL(19,193), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}},
4522{"crxor", XL(19,193), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4523
4524{"dnh", X(19,198), X_MASK, E500MC, PPCVLE, {DUI, DUIS}},
4525
4526{"crnand", XL(19,225), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4527
4528{"crand", XL(19,257), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4529
4530{"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPC476|PPCVLE, {0}},
4531
4532{"crset", XL(19,289), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}},
4533{"creqv", XL(19,289), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4534
4535{"urfid", XL(19,306), 0xffffffff, POWER9, PPCVLE, {0}},
4536{"stop", XL(19,370), 0xffffffff, POWER9, PPCVLE, {0}},
4537
4538{"doze", XL(19,402), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4539
4540{"crorc", XL(19,417), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4541
4542{"nap", XL(19,434), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4543
4544{"crmove", XL(19,449), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}},
4545{"cror", XL(19,449), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4546
4547{"sleep", XL(19,466), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4548{"rvwinkle", XL(19,498), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4549
4550{"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCVLE, {0}},
4551{"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCVLE, {0}},
4552
4553{"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4554{"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4555{"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4556{"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4557{"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4558{"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4559{"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4560{"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4561{"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4562{"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4563{"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4564{"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4565{"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4566{"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4567{"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4568{"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4569{"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4570{"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4571{"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4572{"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4573{"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4574{"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4575{"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4576{"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4577{"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4578{"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4579{"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4580{"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4581{"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4582{"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4583{"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4584{"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4585{"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4586{"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4587{"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4588{"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4589{"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4590{"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4591{"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4592{"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4593{"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4594{"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4595{"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4596{"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4597{"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4598{"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4599{"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4600{"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4601{"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4602{"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4603{"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4604{"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4605{"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4606{"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4607{"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4608{"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4609{"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4610{"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4611{"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4612{"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4613{"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4614{"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4615{"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4616{"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4617{"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4618{"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4619{"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4620{"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4621{"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4622{"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4623{"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4624{"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4625{"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4626{"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4627{"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4628{"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4629{"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4630{"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4631{"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4632{"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4633{"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4634{"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4635{"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4636{"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4637{"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4638{"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4639{"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4640{"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4641{"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4642{"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4643{"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4644{"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4645{"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4646{"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4647{"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4648{"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4649{"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4650{"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4651{"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4652{"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4653{"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4654{"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4655{"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4656{"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4657{"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4658{"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4659{"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4660{"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4661{"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4662{"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4663{"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4664{"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4665{"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4666{"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4667{"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4668{"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4669{"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4670{"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4671{"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4672{"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4673
4674{"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4675{"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4676{"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4677{"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4678{"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4679{"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4680{"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4681{"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4682{"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4683{"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4684{"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4685{"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4686{"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4687{"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4688{"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4689{"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4690{"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4691{"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4692{"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4693{"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4694
4695{"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4696{"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4697{"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4698{"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4699{"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4700{"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4701{"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4702{"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4703
4704{"bctar-", XLYLK(19,560,0,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4705{"bctarl-", XLYLK(19,560,0,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4706{"bctar+", XLYLK(19,560,1,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4707{"bctarl+", XLYLK(19,560,1,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4708{"bctar", XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}},
4709{"bctarl", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}},
4710
4711{"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4712{"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4713
4714{"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4715{"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4716
4717{"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
4718{"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},
4719{"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4720{"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4721{"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
4722{"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},
4723{"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4724{"rlinm.", M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4725
4726{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
4727{"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
4728
4729{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
4730{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4731{"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4732{"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
4733{"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4734{"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4735
4736{"nop", OP(24), 0xffffffff, PPCCOM, PPCVLE, {0}},
4737{"ori", OP(24), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4738{"oril", OP(24), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4739
4740{"oris", OP(25), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4741{"oriu", OP(25), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4742
4743{"xnop", OP(26), 0xffffffff, PPCCOM, PPCVLE, {0}},
4744{"xori", OP(26), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4745{"xoril", OP(26), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4746
4747{"xoris", OP(27), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4748{"xoriu", OP(27), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4749
4750{"andi.", OP(28), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4751{"andil.", OP(28), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4752
4753{"andis.", OP(29), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4754{"andiu.", OP(29), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4755
4756{"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}},
4757{"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}},
4758{"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4759{"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}},
4760{"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}},
4761{"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4762
4763{"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
4764{"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
4765
4766{"rldic", MD(30,2,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4767{"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4768
4769{"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4770{"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4771
4772{"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},
4773{"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
4774{"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},
4775{"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
4776
4777{"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
4778{"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
4779
4780{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
4781{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
a5721ba2 4782{"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
bdc70b4a 4783{"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
1cb0a767 4784
14b57c7c
AM		 4785{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4786{"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4787{"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4788{"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4789{"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, 0, {RA, RB}},
4790{"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, 0, {RA, RB}},
4791{"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4792{"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4793{"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, 0, {RA, RB}},
4794{"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, 0, {RA, RB}},
4795{"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4796{"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4797{"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, 0, {RA, RB}},
4798{"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, 0, {RA, RB}},
4799{"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4800{"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4801{"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4802{"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4803{"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, 0, {RA, RB}},
4804{"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, 0, {RA, RB}},
4805{"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4806{"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4807{"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4808{"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4809{"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, 0, {RA, RB}},
4810{"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, 0, {RA, RB}},
4811{"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4812{"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4813{"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, 0, {0}},
4814{"twu", XTO(31,4,TOU), XTO_MASK, PPCCOM, 0, {RA, RB}},
4815{"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}},
4816{"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}},
4817{"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}},
4818
4819{"lvsl", X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4820{"lvebx", X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4821{"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4822
4823{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4824{"sf", XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4825{"subc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
4826{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4827{"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4828{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
4829
4830{"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
4831{"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
4832
4833{"addc", XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4834{"a", XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4835{"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4836{"a.", XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4837
4838{"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4839{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4840
4841{"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
4842
4843{"isellt", X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4844
4845{"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, 0, {0}},
4846{"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, 0, {0}},
4847{"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4848{"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}},
4849
4850{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, COM, 0, {RT, FXM4}},
4851{"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, 0, {RT, FXM}},
4852
4853{"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}},
4854
4855{"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}},
4856
4857{"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, 0, {CT, RA0, RB}},
4858
4859{"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
4860{"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4861
4862{"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
4863{"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
4864{"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
4865{"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
4866
4867{"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
4868{"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
4869{"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
4870{"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
4871
4872{"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}},
4873{"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}},
4874
4875{"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}},
4876{"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}},
4877
4878{"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}},
4879{"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}},
4880
4881{"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4882
4883{"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}},
4884{"wait", X(31,30), XWC_MASK, POWER9, 0, {WC}},
4885
4886{"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4887
4888{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
4889{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
a5721ba2 4890{"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
bdc70b4a 4891{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
de866fcc 4892
14b57c7c
AM		 4893{"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4894{"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4895{"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
de866fcc 4896
ac8f0f72 4897{"mviwsplt", X(31,46), X_MASK, E6500, 0, {VD, RA, RB}},
e67ed0e8 4898
14b57c7c 4899{"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
de866fcc 4900
14b57c7c 4901{"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
de866fcc 4902
14b57c7c 4903{"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}},
066be9f7 4904
14b57c7c 4905{"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
c0637f3a 4906
14b57c7c 4907{"iseleq", X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
de866fcc 4908
14b57c7c 4909{"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, CRB}},
de866fcc 4910
14b57c7c
AM		 4911{"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4912{"sub", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RB, RA}},
4913{"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4914{"sub.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}},
de866fcc 4915
14b57c7c
AM		 4916{"mfvsrd", X(31,51), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
4917{"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
4918{"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
4919{"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}},
e0d602ec 4920
14b57c7c 4921{"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
066be9f7 4922
14b57c7c 4923{"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}},
43e65147 4924
14b57c7c 4925{"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}},
43e65147 4926
14b57c7c
AM		 4927{"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}},
4928{"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}},
de866fcc 4929
14b57c7c
AM		 4930{"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, 0, {RA, RS}},
4931{"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, 0, {RA, RS}},
de866fcc 4932
14b57c7c
AM		 4933{"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}},
4934{"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}},
de866fcc 4935
14b57c7c
AM		 4936{"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, 0, {0}},
4937{"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, 0, {0}},
4938{"wait", X(31,62), XWC_MASK, E500MC|PPCA2, 0, {WC}},
43e65147 4939
14b57c7c 4940{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
19a6653c 4941
14b57c7c
AM		 4942{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, 0, {RA, RB}},
4943{"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, 0, {RA, RB}},
4944{"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, 0, {RA, RB}},
4945{"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, 0, {RA, RB}},
4946{"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, 0, {RA, RB}},
4947{"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, 0, {RA, RB}},
4948{"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, 0, {RA, RB}},
4949{"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, 0, {RA, RB}},
4950{"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, 0, {RA, RB}},
4951{"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, 0, {RA, RB}},
4952{"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, 0, {RA, RB}},
4953{"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, 0, {RA, RB}},
4954{"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, 0, {RA, RB}},
4955{"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, 0, {RA, RB}},
4956{"tdu", XTO(31,68,TOU), XTO_MASK, PPC64, 0, {RA, RB}},
4957{"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}},
de866fcc 4958
14b57c7c
AM		 4959{"lwfcmx", APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4960{"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
4961{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
43e65147 4962
14b57c7c
AM		 4963{"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4964{"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
de866fcc 4965
62adc510
AM		 4966{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA, RS, RB}},
4967{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA, RS, RB}},
de866fcc 4968
14b57c7c 4969{"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, 0, {SR, RS}},
de866fcc 4970
14b57c7c 4971{"mfmsr", X(31,83), XRARB_MASK, COM, 0, {RT}},
43e65147 4972
14b57c7c 4973{"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}},
de866fcc 4974
c7a8dbf9 4975{"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}},
a5721ba2 4976{"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L2OPT}},
de866fcc 4977
14b57c7c 4978{"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}},
43e65147 4979
14b57c7c 4980{"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
de866fcc 4981
14b57c7c 4982{"dni", XRC(31,97,1), XRB_MASK, E6500, 0, {DUI, DCTL}},
aea77599 4983
14b57c7c
AM		 4984{"lvx", X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4985{"lqfcmx", APU(31,103,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
de866fcc 4986
14b57c7c
AM		 4987{"neg", XO(31,104,0,0), XORB_MASK, COM, 0, {RT, RA}},
4988{"neg.", XO(31,104,0,1), XORB_MASK, COM, 0, {RT, RA}},
de866fcc 4989
14b57c7c
AM		 4990{"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
4991{"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
de866fcc 4992
ac8f0f72 4993{"mvidsplt", X(31,110), X_MASK, E6500, 0, {VD, RA, RB}},
aea77599 4994
14b57c7c 4995{"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}},
de866fcc 4996
14b57c7c
AM		 4997{"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
4998{"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
4999{"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
c0637f3a 5000
14b57c7c 5001{"lharx", X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
066be9f7 5002
14b57c7c 5003{"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}},
de866fcc 5004
14b57c7c 5005{"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}},
43e65147 5006
14b57c7c 5007{"popcntb", X(31,122), XRB_MASK, POWER5, 0, {RA, RS}},
de866fcc 5008
14b57c7c
AM		 5009{"not", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RBS}},
5010{"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}},
5011{"not.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RBS}},
5012{"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}},
19a6653c 5013
14b57c7c 5014{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
43e65147 5015
fd486b63 5016{"setb", X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}},
a680de9a 5017
14b57c7c 5018{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}},
43e65147 5019
14b57c7c 5020{"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
de866fcc 5021
14b57c7c
AM		 5022{"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5023{"stbfcmx", APU(31,135,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
de866fcc 5024
14b57c7c
AM		 5025{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5026{"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5027{"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5028{"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
de866fcc 5029
14b57c7c
AM		 5030{"adde", XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5031{"ae", XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5032{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5033{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
de866fcc 5034
14b57c7c 5035{"stxsiwx", X(31,140), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
c0637f3a 5036
14b57c7c
AM		 5037{"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK, POWER8, 0, {RB}},
5038{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
de866fcc 5039
14b57c7c
AM		 5040{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, 0, {RS}},
5041{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, 0, {FXM, RS}},
5042{"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, 0, {FXM, RS}},
de866fcc 5043
14b57c7c 5044{"mtmsr", X(31,146), XRLARB_MASK, COM, 0, {RS, A_L}},
de866fcc 5045
14b57c7c 5046{"mtsle", X(31,147), XRTLRARB_MASK, POWER8, 0, {L}},
c0637f3a 5047
14b57c7c
AM		 5048{"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}},
5049{"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
e0d602ec 5050
14b57c7c 5051{"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}},
43e65147 5052
14b57c7c 5053{"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}},
43e65147 5054
14b57c7c
AM		 5055{"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
5056{"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}},
de866fcc 5057
14b57c7c
AM		 5058{"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}},
5059{"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}},
de866fcc 5060
14b57c7c
AM		 5061{"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}},
5062{"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}},
de866fcc 5063
14b57c7c 5064{"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}},
de866fcc 5065
14b57c7c 5066{"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
43e65147 5067
14b57c7c 5068{"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
43e65147 5069
14b57c7c 5070{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {E}},
43e65147 5071
14b57c7c 5072{"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
de866fcc 5073
14b57c7c
AM		 5074{"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5075{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
de866fcc 5076
14b57c7c 5077{"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
19dfcc89 5078
14b57c7c
AM		 5079{"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}},
5080{"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
de866fcc 5081
14b57c7c 5082{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, 0, {RS, A_L}},
de866fcc 5083
14b57c7c
AM		 5084{"mtvsrd", X(31,179), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
5085{"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
5086{"mtvrd", X(31,179)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5087{"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}},
e0d602ec 5088
14b57c7c 5089{"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}},
de866fcc 5090
73f07bff 5091{"stqcx.", XRC(31,182,1), X_MASK|Q_MASK, POWER8, 0, {RSQ, RA0, RB}},
14b57c7c 5092{"wchkall", X(31,182), X_MASK, PPCA2, 0, {OBF}},
e0d602ec 5093
14b57c7c
AM		 5094{"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}},
5095{"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
de866fcc 5096
14b57c7c
AM		 5097{"sliq", XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}},
5098{"sliq.", XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}},
de866fcc 5099
14b57c7c 5100{"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}},
252b5132 5101
14b57c7c 5102{"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}},
a680de9a 5103
14b57c7c 5104{"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}},
aea77599 5105
14b57c7c
AM		 5106{"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5107{"stwfcmx", APU(31,199,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
252b5132 5108
14b57c7c
AM		 5109{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5110{"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5111{"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5112{"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
252b5132 5113
14b57c7c
AM		 5114{"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5115{"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5116{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5117{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
418c1742 5118
14b57c7c 5119{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
19a6653c 5120
14b57c7c 5121{"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}},
418c1742 5122
14b57c7c
AM		 5123{"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
5124{"mtvrwa", X(31,211)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5125{"mtvsrwa", X(31,211), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
5126{"eratwe", X(31,211), X_MASK, PPCA2, 0, {RS, RA, WS}},
e0d602ec 5127
14b57c7c 5128{"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
e0d602ec 5129
14b57c7c 5130{"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}},
43e65147 5131
14b57c7c 5132{"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}},
252b5132 5133
14b57c7c
AM		 5134{"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}},
5135{"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 5136
14b57c7c
AM		 5137{"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}},
5138{"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 5139
14b57c7c 5140{"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
43e65147 5141
14b57c7c 5142{"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}},
a680de9a 5143
14b57c7c 5144{"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
7d5b217e 5145
14b57c7c
AM		 5146{"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5147{"stqfcmx", APU(31,231,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
f509565f 5148
14b57c7c
AM		 5149{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5150{"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5151{"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5152{"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
252b5132 5153
14b57c7c
AM		 5154{"mulld", XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5155{"mulld.", XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
43e65147 5156
14b57c7c
AM		 5157{"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5158{"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5159{"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5160{"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
252b5132 5161
14b57c7c
AM		 5162{"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5163{"muls", XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5164{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5165{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 5166
14b57c7c
AM		 5167{"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
5168{"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
5169{"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},
bdc70b4a 5170{"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}},
418c1742 5171
14b57c7c
AM		 5172{"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
5173{"mtvrwz", X(31,243)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5174{"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
c0637f3a 5175
14b57c7c
AM		 5176{"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
5177{"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
5178{"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
5179{"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
4fff86c5 5180
14b57c7c 5181{"stbux", X(31,247), X_MASK, COM, 0, {RS, RAS, RB}},
252b5132 5182
14b57c7c
AM		 5183{"slliq", XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}},
5184{"slliq.", XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}},
252b5132 5185
14b57c7c 5186{"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}},
066be9f7 5187
14b57c7c 5188{"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
19a6653c 5189
14b57c7c
AM		 5190{"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}},
5191{"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}},
252b5132 5192
ac8f0f72 5193{"lvexbx", X(31,261), X_MASK, E6500, 0, {VD, RA0, RB}},
aea77599 5194
14b57c7c 5195{"icbt", X(31,262), XRT_MASK, PPC403, 0, {RA, RB}},
1ed8e1e4 5196
ac8f0f72 5197{"lvepxl", X(31,263), X_MASK, E6500, 0, {VD, RA0, RB}},
aea77599 5198
14b57c7c
AM		 5199{"ldfcmx", APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5200{"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5201{"doz.", XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
252b5132 5202
14b57c7c 5203{"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}},
a680de9a 5204
14b57c7c
AM		 5205{"add", XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5206{"cax", XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5207{"add.", XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5208{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
418c1742 5209
14b57c7c 5210{"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}},
a680de9a 5211
14b57c7c
AM		 5212{"lxvx", X(31,268), XX1_MASK|1<<6, PPCVSX3, 0, {XT6, RA0, RB}},
5213{"lxvl", X(31,269), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
a680de9a 5214
14b57c7c 5215{"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, 0, {0}},
19a6653c 5216
62adc510 5217{"tlbiel", X(31,274), X_MASK|1<<20,POWER9, 0, {RB, RSO, RIC, PRS, X_R}},
a5721ba2 5218{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, LOPT}},
418c1742 5219
14b57c7c 5220{"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
1cb0a767 5221
73f07bff 5222{"lqarx", X(31,276), XEH_MASK|Q_MASK, POWER8, 0, {RTQ, RAX, RBX, EH}},
c0637f3a 5223
14b57c7c
AM		 5224{"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}},
5225{"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}},
1cb0a767 5226
14b57c7c
AM		 5227{"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
5228{"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
5229{"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
5230{"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
4fff86c5 5231
14b57c7c 5232{"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}},
1cb0a767 5233
14b57c7c 5234{"cdtbcd", X(31,282), XRB_MASK, POWER6, 0, {RA, RS}},
066be9f7 5235
14b57c7c
AM		 5236{"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}},
5237{"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}},
1cb0a767 5238
14b57c7c 5239{"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
1cb0a767 5240
62adc510 5241{"mfdcrux", X(31,291), X_MASK, PPC464|PPC476, 0, {RS, RA}},
1cb0a767 5242
ac8f0f72
AM		 5243{"lvexhx", X(31,293), X_MASK, E6500, 0, {VD, RA0, RB}},
5244{"lvepx", X(31,295), X_MASK, E6500, 0, {VD, RA0, RB}},
aea77599 5245
14b57c7c 5246{"lxvll", X(31,301), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
a680de9a 5247
14b57c7c 5248{"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}},
c0637f3a 5249
14b57c7c
AM		 5250{"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}},
5251{"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}},
a5721ba2 5252{"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, LOPT}},
14b57c7c 5253{"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}},
1cb0a767 5254
14b57c7c 5255{"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}},
a680de9a 5256
14b57c7c 5257{"ldmx", X(31,309), X_MASK, POWER9, 0, {RT, RA0, RB}},
a680de9a 5258
14b57c7c 5259{"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
1cb0a767 5260
14b57c7c 5261{"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}},
1cb0a767 5262
14b57c7c 5263{"cbcdtd", X(31,314), XRB_MASK, POWER6, 0, {RA, RS}},
066be9f7 5264
14b57c7c
AM		 5265{"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}},
5266{"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}},
1cb0a767 5267
14b57c7c 5268{"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
1cb0a767 5269
14b57c7c
AM		 5270{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, 0, {RT}},
5271{"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, 0, {RT}},
5272{"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, 0, {RT}},
5273{"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, 0, {RT}},
5274{"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, 0, {RT}},
5275{"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, 0, {RT}},
5276{"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, 0, {RT}},
5277{"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, 0, {RT}},
5278{"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, 0, {RT}},
5279{"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, 0, {RT}},
5280{"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, 0, {RT}},
5281{"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, 0, {RT}},
5282{"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, 0, {RT}},
5283{"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, 0, {RT}},
5284{"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, 0, {RT}},
5285{"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, 0, {RT}},
5286{"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, 0, {RT}},
5287{"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, 0, {RT}},
5288{"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, 0, {RT}},
5289{"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, 0, {RT}},
5290{"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, 0, {RT}},
5291{"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, 0, {RT}},
5292{"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, 0, {RT}},
5293{"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, 0, {RT}},
5294{"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, 0, {RT}},
5295{"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, 0, {RT}},
5296{"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, 0, {RT}},
5297{"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, 0, {RT}},
5298{"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, 0, {RT}},
5299{"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, 0, {RT}},
5300{"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, 0, {RT}},
5301{"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, 0, {RT}},
5302{"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, 0, {RT}},
5303{"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, 0, {RT}},
5304{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}},
5305{"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}},
1cb0a767 5306
ac8f0f72 5307{"lvexwx", X(31,325), X_MASK, E6500, 0, {VD, RA0, RB}},
aea77599 5308
14b57c7c 5309{"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}},
9fe54b1c 5310
14b57c7c
AM		 5311{"div", XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5312{"div.", XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
1cb0a767 5313
14b57c7c 5314{"lxvdsx", X(31,332), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
066be9f7 5315
14b57c7c 5316{"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}},
c03dc33b 5317{"mftmr", X(31,366), X_MASK, PPCTMR, 0, {RT, TMR}},
1cb0a767 5318
14b57c7c
AM		 5319{"slbsync", X(31,338), 0xffffffff, POWER9, 0, {0}},
5320
5321{"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, 0, {RT}},
5322{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, 0, {RT}},
5323{"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}},
5324{"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}},
5325{"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, 0, {RT}},
5326{"mflr", XSPR(31,339, 8), XSPR_MASK, COM, 0, {RT}},
5327{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, 0, {RT}},
5328{"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, 0, {RT}},
5329{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, 0, {RT}},
5330{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}},
5331{"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}},
bdc70b4a 5332{"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}},
14b57c7c
AM		 5333{"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, 0, {RT}},
5334{"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}},
5335{"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, 0, {RT}},
5336{"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, 0, {RT}},
5337{"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, 0, {RT}},
5338{"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, 0, {RT}},
5339{"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, 0, {RT}},
5340{"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, 0, {RT}},
5341{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, 0, {RT}},
5342{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, 0, {RT}},
5343{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, 0, {RT}},
5344{"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, 0, {RT}},
5345{"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, 0, {RT}},
5346{"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, 0, {RT}},
5347{"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, 0, {RT}},
5348{"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, 0, {RT}},
5349{"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, 0, {RT}},
5350{"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, 0, {RT}},
5351{"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, 0, {RT}},
5352{"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, 0, {RT}},
5353{"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, 0, {RT}},
5354{"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, 0, {RT}},
5355{"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, 0, {RT}},
5356{"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, 0, {RT}},
5357{"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, 0, {RT}},
5358{"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, 0, {RT}},
5359{"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, 0, {RT}},
5360{"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, 0, {RT}},
5361{"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, 0, {RT}},
5362{"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, 0, {RT}},
5363{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, 0, {RT, SPRG}},
5364{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5365{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5366{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5367{"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5368{"mftbu", XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
5369{"mftb", X(31,339), X_MASK, POWER4|BOOKE, 0, {RT, TBR}},
5370{"mftbl", XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
5371{"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, 0, {RT}},
5372{"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, 0, {RT}},
5373{"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, 0, {RT}},
5374{"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, 0, {RT}},
5375{"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, 0, {RT}},
5376{"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}},
5377{"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, 0, {RT}},
5378{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, 0, {RT}},
5379{"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, 0, {RT}},
5380{"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, 0, {RT}},
5381{"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, 0, {RT}},
5382{"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, 0, {RT}},
5383{"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, 0, {RT}},
5384{"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, 0, {RT}},
5385{"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, 0, {RT}},
5386{"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, 0, {RT}},
5387{"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, 0, {RT}},
5388{"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, 0, {RT}},
5389{"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, 0, {RT}},
5390{"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, 0, {RT}},
5391{"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, 0, {RT}},
5392{"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, 0, {RT}},
5393{"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, 0, {RT}},
5394{"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, 0, {RT}},
5395{"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, 0, {RT}},
5396{"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, 0, {RT}},
5397{"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, 0, {RT}},
5398{"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, 0, {RT}},
5399{"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, 0, {RT}},
5400{"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, 0, {RT}},
5401{"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, 0, {RT}},
5402{"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, 0, {RT}},
5403{"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, 0, {RT}},
5404{"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, 0, {RT}},
5405{"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, 0, {RT}},
5406{"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, 0, {RT}},
5407{"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, 0, {RT}},
5408{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, 0, {RT}},
5409{"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, 0, {RT}},
5410{"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, 0, {RT}},
5411{"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, 0, {RT}},
4b94dd2d
AM		 5412{"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE|E6500, 0, {RT}},
5413{"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE|E6500, 0, {RT}},
14b57c7c
AM		 5414{"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, 0, {RT}},
5415{"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}},
4b94dd2d
AM		 5416{"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5417{"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
14b57c7c
AM		 5418{"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5419{"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5420{"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, 0, {RT}},
5421{"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, 0, {RT}},
5422{"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, 0, {RT}},
5423{"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, 0, {RT}},
5424{"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, 0, {RT}},
5425{"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, 0, {RT}},
5426{"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, 0, {RT}},
5427{"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, 0, {RT}},
5428{"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, 0, {RT}},
5429{"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}},
5430{"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, 0, {RT}},
5431{"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, 0, {RT}},
5432{"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, 0, {RT}},
5433{"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, 0, {RT}},
5434{"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, 0, {RT}},
5435{"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, 0, {RT}},
5436{"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, 0, {RT}},
5437{"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, 0, {RT}},
5438{"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, 0, {RT}},
5439{"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, 0, {RT}},
5440{"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, 0, {RT}},
5441{"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, 0, {RT}},
5442{"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, 0, {RT}},
5443{"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, 0, {RT}},
5444{"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, 0, {RT}},
5445{"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, 0, {RT}},
5446{"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, 0, {RT}},
5447{"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, 0, {RT}},
5448{"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, 0, {RT}},
5449{"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, 0, {RT}},
5450{"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, 0, {RT}},
5451{"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, 0, {RT}},
5452{"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, 0, {RT}},
5453{"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, 0, {RT}},
5454{"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, 0, {RT}},
5455{"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, 0, {RT}},
5456{"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, 0, {RT}},
5457{"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, 0, {RT}},
5458{"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, 0, {RT}},
5459{"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, 0, {RT}},
5460{"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, 0, {RT}},
5461{"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, 0, {RT}},
5462{"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, 0, {RT}},
5463{"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, 0, {RT}},
5464{"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, 0, {RT}},
5465{"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, 0, {RT}},
5466{"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, 0, {RT}},
5467{"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, 0, {RT}},
5468{"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, 0, {RT}},
5469{"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, 0, {RT}},
5470{"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, 0, {RT}},
5471{"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, 0, {RT}},
5472{"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, 0, {RT}},
5473{"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, 0, {RT}},
5474{"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, 0, {RT}},
5475{"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, 0, {RT}},
5476{"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, 0, {RT}},
5477{"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, 0, {RT}},
5478{"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, 0, {RT}},
5479{"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, 0, {RT}},
5480{"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, 0, {RT}},
5481{"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, 0, {RT}},
5482{"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, 0, {RT}},
5483{"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, 0, {RT}},
5484{"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, 0, {RT}},
5485{"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, 0, {RT}},
5486{"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, 0, {RT}},
5487{"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, 0, {RT}},
5488{"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, 0, {RT}},
5489{"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, 0, {RT}},
5490{"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, 0, {RT}},
5491{"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, 0, {RT}},
5492{"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, 0, {RT}},
5493{"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, 0, {RT}},
5494{"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, 0, {RT}},
5495{"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, 0, {RT}},
5496{"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, 0, {RT}},
5497{"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, 0, {RT}},
5498{"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, 0, {RT}},
5499{"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, 0, {RT}},
5500{"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, 0, {RT}},
5501{"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, 0, {RT}},
5502{"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, 0, {RT}},
5503{"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, 0, {RT}},
5504{"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, 0, {RT}},
5505{"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, 0, {RS}},
5506{"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, 0, {RT}},
5507{"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, 0, {RT}},
5508{"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, 0, {RT}},
5509{"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, 0, {RT}},
5510{"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, 0, {RT}},
5511{"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, 0, {RT}},
5512{"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, 0, {RT}},
5513{"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, 0, {RT}},
5514{"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, 0, {RT}},
5515{"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, 0, {RT}},
5516{"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, 0, {RT}},
5517{"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, 0, {RT}},
5518{"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, 0, {RT}},
5519{"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, 0, {RT}},
5520{"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, 0, {RT}},
5521{"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}},
5522
5523{"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}},
5524
5525{"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
5526
5527{"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}},
5528
5529{"lvxl", X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
5530
5531{"abs", XO(31,360,0,0), XORB_MASK, M601, 0, {RT, RA}},
5532{"abs.", XO(31,360,0,1), XORB_MASK, M601, 0, {RT, RA}},
5533
5534{"divs", XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5535{"divs.", XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5536
5537{"lxvwsx", X(31,364), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5538
5539{"tlbia", X(31,370), 0xffffffff, PPC, E500|TITAN, {0}},
1cb0a767 5540
db76a700 5541{"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}},
14b57c7c 5542{"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}},
db76a700 5543{"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371|POWER4, {RT}},
1cb0a767 5544
14b57c7c 5545{"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}},
1cb0a767 5546
14b57c7c 5547{"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
1cb0a767 5548
14b57c7c 5549{"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}},
1cb0a767 5550
14b57c7c 5551{"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
066be9f7 5552
14b57c7c
AM		 5553{"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}},
5554{"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}},
1cb0a767 5555
ac8f0f72 5556{"stvexbx", X(31,389), X_MASK, E6500, 0, {VS, RA0, RB}},
aea77599 5557
14b57c7c
AM		 5558{"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5559{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
1cb0a767 5560
14b57c7c
AM		 5561{"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5562{"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5563{"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5564{"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
066be9f7 5565
14b57c7c
AM		 5566{"stxvx", X(31,396), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
5567{"stxvl", X(31,397), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
a680de9a 5568
14b57c7c 5569{"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
1cb0a767 5570
14b57c7c 5571{"slbmte", X(31,402), XRA_MASK, PPC64, 0, {RS, RB}},
1cb0a767 5572
14b57c7c 5573{"mtvsrws", X(31,403), XX1RB_MASK, PPCVSX3, 0, {XT6, RA}},
a680de9a 5574
14b57c7c 5575{"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}},
c0637f3a 5576
14b57c7c
AM		 5577{"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
5578{"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
e0d602ec 5579
14b57c7c 5580{"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}},
1cb0a767 5581
14b57c7c
AM		 5582{"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}},
5583{"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}},
1cb0a767 5584
14b57c7c 5585{"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
1cb0a767 5586
62adc510 5587{"mtdcrux", X(31,419), X_MASK, PPC464|PPC476, 0, {RA, RS}},
1cb0a767 5588
ac8f0f72 5589{"stvexhx", X(31,421), X_MASK, E6500, 0, {VS, RA0, RB}},
aea77599 5590
14b57c7c 5591{"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}},
aea77599 5592
14b57c7c
AM		 5593{"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5594{"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5595{"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5596{"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
066be9f7 5597
14b57c7c 5598{"stxvll", X(31,429), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
a680de9a 5599
14b57c7c 5600{"clrbhrb", X(31,430), 0xffffffff, POWER8, 0, {0}},
c0637f3a 5601
14b57c7c 5602{"slbie", X(31,434), XRTRA_MASK, PPC64, 0, {RB}},
1cb0a767 5603
14b57c7c 5604{"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
a680de9a 5605
14b57c7c 5606{"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
1cb0a767 5607
14b57c7c 5608{"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}},
1cb0a767 5609
14b57c7c 5610{"mdors", 0x7f9ce378, 0xffffffff, E500MC, 0, {0}},
1cb0a767 5611
14b57c7c 5612{"miso", 0x7f5ad378, 0xffffffff, E6500, 0, {0}},
aea77599 5613
9f6a6cc0 5614/* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for
14b57c7c
AM		 5615 "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */
5616{"yield", 0x7f7bdb78, 0xffffffff, POWER7, 0, {0}},
5617{"mdoio", 0x7fbdeb78, 0xffffffff, POWER7, 0, {0}},
5618{"mdoom", 0x7fdef378, 0xffffffff, POWER7, 0, {0}},
5619{"mr", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RBS}},
5620{"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}},
5621{"mr.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RBS}},
5622{"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}},
5623
5624{"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, 0, {RS}},
5625{"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, 0, {RS}},
5626{"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, 0, {RS}},
5627{"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, 0, {RS}},
5628{"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, 0, {RS}},
5629{"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, 0, {RS}},
5630{"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, 0, {RS}},
5631{"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, 0, {RS}},
5632{"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, 0, {RS}},
5633{"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, 0, {RS}},
5634{"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, 0, {RS}},
5635{"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, 0, {RS}},
5636{"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, 0, {RS}},
5637{"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, 0, {RS}},
5638{"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, 0, {RS}},
5639{"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, 0, {RS}},
5640{"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, 0, {RS}},
5641{"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, 0, {RS}},
5642{"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, 0, {RS}},
5643{"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, 0, {RS}},
5644{"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, 0, {RS}},
5645{"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, 0, {RS}},
5646{"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, 0, {RS}},
5647{"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, 0, {RS}},
5648{"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, 0, {RS}},
5649{"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, 0, {RS}},
5650{"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, 0, {RS}},
5651{"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, 0, {RS}},
5652{"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, 0, {RS}},
5653{"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, 0, {RS}},
5654{"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, 0, {RS}},
5655{"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, 0, {RS}},
5656{"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, 0, {RS}},
5657{"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, 0, {RS}},
5658{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}},
5659{"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, 0, {SPR, RS}},
5660
ac8f0f72 5661{"stvexwx", X(31,453), X_MASK, E6500, 0, {VS, RA0, RB}},
14b57c7c 5662
62adc510 5663{"dccci", X(31,454), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
14b57c7c
AM		 5664{"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, 0, {CT}},
5665
5666{"divdu", XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5667{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5668
5669{"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5670{"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5671
5672{"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}},
c03dc33b 5673{"mttmr", X(31,494), X_MASK, PPCTMR, 0, {TMR, RS}},
14b57c7c
AM		 5674
5675{"slbieg", X(31,466), XRA_MASK, POWER9, 0, {RS, RB}},
5676
5677{"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, 0, {RS}},
5678{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, 0, {RS}},
5679{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, 0, {RS}},
5680{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, 0, {RS}},
5681{"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, 0, {RS}},
5682{"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, 0, {RS}},
5683{"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}},
5684{"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}},
5685{"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, TITAN, {RS}},
5686{"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, TITAN, {RS}},
5687{"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, 0, {RS}},
5688{"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, 0, {RS}},
5689{"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN, {RS}},
5690{"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, 0, {RS}},
5691{"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, 0, {RS}},
5692{"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, 0, {RS}},
5693{"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, 0, {RS}},
5694{"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, 0, {RS}},
5695{"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, 0, {RS}},
5696{"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, 0, {RS}},
5697{"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, 0, {RS}},
5698{"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, 0, {RS}},
5699{"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, 0, {RS}},
5700{"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, 0, {RS}},
5701{"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, 0, {RS}},
5702{"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, 0, {RS}},
5703{"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, 0, {RS}},
5704{"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, 0, {RS}},
5705{"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, 0, {RS}},
5706{"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, 0, {RS}},
5707{"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, 0, {RS}},
5708{"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, 0, {RS}},
5709{"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, 0, {RS}},
5710{"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, 0, {RS}},
5711{"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, 0, {RS}},
5712{"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, 0, {RS}},
5713{"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, 0, {RS}},
5714{"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, 0, {RS}},
5715{"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, 0, {RS}},
5716{"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, 0, {RS}},
5717{"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, 0, {RS}},
5718{"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, 0, {RS}},
5719{"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC, 0, {SPRG, RS}},
5720{"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, 0, {RS}},
5721{"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, 0, {RS}},
5722{"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, 0, {RS}},
5723{"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, 0, {RS}},
5724{"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5725{"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5726{"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5727{"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5728{"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, 0, {RS}},
5729{"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}},
5730{"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, 0, {RS}},
5731{"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, 0, {RS}},
5732{"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, 0, {RS}},
5733{"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, 0, {RS}},
5734{"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, 0, {RS}},
5735{"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, 0, {RS}},
5736{"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, 0, {RS}},
5737{"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, 0, {RS}},
5738{"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, 0, {RS}},
5739{"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, 0, {RS}},
5740{"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, 0, {RS}},
5741{"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, 0, {RS}},
5742{"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, 0, {RS}},
5743{"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, 0, {RS}},
5744{"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, 0, {RS}},
5745{"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, 0, {RS}},
5746{"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, 0, {RS}},
5747{"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, 0, {RS}},
5748{"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, 0, {RS}},
5749{"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, 0, {RS}},
5750{"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, 0, {RS}},
5751{"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, 0, {RS}},
5752{"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, 0, {RS}},
5753{"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, 0, {RS}},
5754{"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, 0, {RS}},
5755{"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, 0, {RS}},
5756{"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, 0, {RS}},
5757{"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, 0, {RS}},
5758{"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, 0, {RS}},
5759{"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, 0, {RS}},
5760{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, 0, {RS}},
5761{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, 0, {RS}},
5762{"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, 0, {RS}},
5763{"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, 0, {RS}},
5764{"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, 0, {RS}},
4b94dd2d
AM		 5765{"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE|E6500, 0, {RS}},
5766{"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE|E6500, 0, {RS}},
14b57c7c
AM		 5767{"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, 0, {RS}},
5768{"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, 0, {RS}},
4b94dd2d
AM		 5769{"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5770{"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
14b57c7c
AM		 5771{"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5772{"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5773{"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}},
5774{"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}},
5775{"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}},
5776{"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, 0, {RS}},
5777{"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, 0, {RS}},
5778{"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, 0, {RS}},
5779{"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, 0, {RS}},
5780{"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, 0, {RS}},
5781{"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, 0, {RS}},
5782{"mtppr", XSPR(31,467,896), XSPR_MASK, POWER7, 0, {RS}},
5783{"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER7, 0, {RS}},
5784{"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, 0, {RS}},
5785{"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, 0, {RS}},
5786{"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, 0, {RS}},
5787{"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, 0, {RS}},
5788{"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, 0, {RS}},
5789{"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, 0, {RS}},
5790{"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, 0, {RS}},
5791{"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, 0, {RS}},
5792{"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, 0, {RS}},
5793{"mtrmmucr", XSPR(31,467,946), XSPR_MASK, TITAN, 0, {RS}},
5794{"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, 0, {RS}},
5795{"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, 0, {RS}},
5796{"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, 0, {RS}},
5797{"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, 0, {RS}},
5798{"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, 0, {RS}},
5799{"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, 0, {RS}},
5800{"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, 0, {RS}},
5801{"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, 0, {RS}},
5802{"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, 0, {RS}},
5803{"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, 0, {RS}},
5804{"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, 0, {RS}},
5805{"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, 0, {RS}},
5806{"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, 0, {RS}},
5807{"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, 0, {RS}},
5808{"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, 0, {RS}},
5809{"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, 0, {RS}},
5810{"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, 0, {RS}},
5811{"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, 0, {RS}},
5812{"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, 0, {RS}},
5813{"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, 0, {RS}},
5814{"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, 0, {RS}},
5815{"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, 0, {RS}},
5816{"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, 0, {RS}},
5817{"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, 0, {RS}},
5818{"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, 0, {RS}},
5819{"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, 0, {RS}},
5820{"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, 0, {RS}},
5821{"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, 0, {RS}},
5822{"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, 0, {RS}},
5823{"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, 0, {RS}},
5824{"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, 0, {RS}},
5825{"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, 0, {RS}},
5826{"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, 0, {RS}},
5827{"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, 0, {RS}},
5828{"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, 0, {RS}},
5829{"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, 0, {RS}},
5830{"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, 0, {RS}},
5831{"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, 0, {RS}},
5832{"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, 0, {RS}},
5833{"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, 0, {RS}},
5834{"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, 0, {RS}},
5835{"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, 0, {RS}},
5836{"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, 0, {RS}},
5837{"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, 0, {RS}},
5838{"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, 0, {RS}},
5839{"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, 0, {RS}},
5840{"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, 0, {RS}},
5841{"mtspr", X(31,467), X_MASK, COM, 0, {SPR, RS}},
5842
5843{"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}},
5844
5845{"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}},
5846{"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}},
5847
5848{"dsn", X(31,483), XRT_MASK, E500MC, 0, {RA, RB}},
5849
62adc510 5850{"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2, {RT, RA0, RB}},
14b57c7c
AM		 5851
5852{"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5853
5854{"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5855
5856{"nabs", XO(31,488,0,0), XORB_MASK, M601, 0, {RT, RA}},
5857{"nabs.", XO(31,488,0,1), XORB_MASK, M601, 0, {RT, RA}},
5858
5859{"divd", XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5860{"divd.", XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5861
5862{"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5863{"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5864
5865{"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
5866
5867{"slbia", X(31,498), 0xff1fffff, POWER6, 0, {IH}},
4bc0608a 5868{"slbia", X(31,498), 0xffffffff, PPC64, POWER6, {0}},
1cb0a767 5869
14b57c7c 5870{"cli", X(31,502), XRB_MASK, POWER, 0, {RT, RA}},
1cb0a767 5871
14b57c7c 5872{"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
066be9f7 5873
14b57c7c 5874{"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}},
1cb0a767 5875
14b57c7c 5876{"mcrxr", X(31,512), XBFRARB_MASK, COM, POWER7, {BF}},
252b5132 5877
dfdaec14 5878{"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}},
a8cc8a54 5879{"lbdx", X(31,515), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}},
19a6653c 5880
14b57c7c 5881{"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}},
252b5132 5882
14b57c7c
AM		 5883{"lvlx", X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}},
5884{"lbfcmux", APU(31,519,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
252b5132 5885
14b57c7c
AM		 5886{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5887{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5888{"subco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
5889{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5890{"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5891{"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
43e65147 5892
14b57c7c
AM		 5893{"addco", XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5894{"ao", XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5895{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5896{"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 5897
14b57c7c 5898{"lxsspx", X(31,524), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
c0637f3a 5899
14b57c7c 5900{"clcs", X(31,531), XRB_MASK, M601, 0, {RT, RA}},
418c1742 5901
14b57c7c 5902{"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}},
418c1742 5903
14b57c7c
AM		 5904{"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}},
5905{"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 5906
14b57c7c
AM		 5907{"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
5908{"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 5909
14b57c7c 5910{"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
702f0fb4 5911
14b57c7c
AM		 5912{"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
5913{"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
5914{"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
5915{"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
252b5132 5916
14b57c7c
AM		 5917{"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}},
5918{"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}},
23976049 5919
14b57c7c
AM		 5920{"cnttzw", XRC(31,538,0), XRB_MASK, POWER9, 0, {RA, RS}},
5921{"cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, 0, {RA, RS}},
a680de9a 5922
14b57c7c
AM		 5923{"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}},
5924{"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}},
f509565f 5925
14b57c7c
AM		 5926{"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}},
5927{"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 5928
dfdaec14 5929{"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}},
a8cc8a54 5930{"lhdx", X(31,547), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}},
19a6653c 5931
ac8f0f72 5932{"lvtrx", X(31,549), X_MASK, E6500, 0, {VD, RA0, RB}},
aea77599 5933
14b57c7c 5934{"bbelr", X(31,550), X_MASK, PPCBRLK, 0, {0}},
418c1742 5935
14b57c7c
AM		 5936{"lvrx", X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}},
5937{"lhfcmux", APU(31,551,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
252b5132 5938
14b57c7c
AM		 5939{"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5940{"subo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RB, RA}},
5941{"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5942{"subo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RB, RA}},
252b5132 5943
14b57c7c 5944{"tlbsync", X(31,566), 0xffffffff, PPC, 0, {0}},
252b5132 5945
14b57c7c 5946{"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
252b5132 5947
14b57c7c
AM		 5948{"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, 0, {RA, RS}},
5949{"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, 0, {RA, RS}},
a680de9a 5950
14b57c7c 5951{"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}},
a680de9a 5952
dfdaec14 5953{"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}},
a8cc8a54 5954{"lwdx", X(31,579), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}},
19a6653c 5955
ac8f0f72 5956{"lvtlx", X(31,581), X_MASK, E6500, 0, {VD, RA0, RB}},
aea77599 5957
14b57c7c 5958{"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}},
a680de9a 5959
14b57c7c 5960{"lwfcmux", APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
081ba1b3 5961
14b57c7c 5962{"lxsdx", X(31,588), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
066be9f7 5963
14b57c7c 5964{"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}},
252b5132 5965
14b57c7c
AM		 5966{"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, NBI}},
5967{"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}},
252b5132 5968
dc302c00 5969{"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}},
e01d869a 5970{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
14b57c7c 5971{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, 0, {0}},
fd486b63
PB		 5972{"sync", X(31,598), XSYNCLE_MASK, E6500, 0, {LS, ESYNC}},
5973{"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}},
14b57c7c
AM		 5974{"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, 0, {0}},
5975{"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}},
5976{"lwsync", X(31,598), 0xffffffff, E500, 0, {0}},
5977{"dcs", X(31,598), 0xffffffff, PWRCOM, 0, {0}},
418c1742 5978
14b57c7c 5979{"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
23976049 5980
066be9f7 5981{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}},
14b57c7c 5982{"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}},
252b5132 5983
14b57c7c 5984{"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}},
19a6653c 5985
ac8f0f72 5986{"lvswx", X(31,613), X_MASK, E6500, 0, {VD, RA0, RB}},
aea77599 5987
14b57c7c 5988{"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}},
a680de9a 5989
14b57c7c 5990{"lqfcmux", APU(31,615,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
081ba1b3 5991
14b57c7c
AM		 5992{"nego", XO(31,104,1,0), XORB_MASK, COM, 0, {RT, RA}},
5993{"nego.", XO(31,104,1,1), XORB_MASK, COM, 0, {RT, RA}},
252b5132 5994
14b57c7c
AM		 5995{"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
5996{"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
252b5132 5997
14b57c7c 5998{"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}},
252b5132 5999
14b57c7c 6000{"dclst", X(31,630), XRB_MASK, M601, 0, {RS, RA}},
252b5132 6001
14b57c7c 6002{"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
252b5132 6003
dfdaec14 6004{"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}},
a8cc8a54 6005{"stbdx", X(31,643), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}},
19a6653c 6006
14b57c7c
AM		 6007{"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}},
6008{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
23976049 6009
14b57c7c 6010{"stxsspx", X(31,652), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
c0637f3a 6011
14b57c7c 6012{"tbegin.", XRC(31,654,1), XRTLRARB_MASK, PPCHTM, 0, {HTM_R}},
5817ffd1 6013
14b57c7c
AM		 6014{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6015{"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6016{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6017{"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 6018
14b57c7c
AM		 6019{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6020{"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6021{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6022{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 6023
14b57c7c 6024{"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}},
418c1742 6025
14b57c7c 6026{"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}},
252b5132 6027
14b57c7c
AM		 6028{"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}},
6029{"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
418c1742 6030
14b57c7c
AM		 6031{"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
6032{"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
252b5132 6033
14b57c7c 6034{"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
ede602d7 6035
14b57c7c
AM		 6036{"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}},
6037{"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 6038
14b57c7c
AM		 6039{"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}},
6040{"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 6041
dfdaec14 6042{"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}},
a8cc8a54 6043{"sthdx", X(31,675), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}},
19a6653c 6044
ac8f0f72 6045{"stvfrx", X(31,677), X_MASK, E6500, 0, {VS, RA0, RB}},
aea77599 6046
14b57c7c
AM		 6047{"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}},
6048{"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
252b5132 6049
14b57c7c
AM		 6050{"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, 0, {0}},
6051{"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, 0, {HTM_A}},
5817ffd1 6052
14b57c7c 6053{"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
066be9f7 6054
14b57c7c 6055{"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
252b5132 6056
14b57c7c
AM		 6057{"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}},
6058{"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}},
252b5132 6059
dfdaec14 6060{"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}},
a8cc8a54 6061{"stwdx", X(31,707), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}},
19a6653c 6062
ac8f0f72 6063{"stvflx", X(31,709), X_MASK, E6500, 0, {VS, RA0, RB}},
aea77599 6064
14b57c7c 6065{"stwat", X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}},
a680de9a 6066
14b57c7c 6067{"stwfcmux", APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
081ba1b3 6068
14b57c7c 6069{"stxsdx", X(31,716), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
066be9f7 6070
14b57c7c 6071{"tcheck", X(31,718), XRTBFRARB_MASK, PPCHTM, 0, {BF}},
5817ffd1 6072
14b57c7c
AM		 6073{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
6074{"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
6075{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
6076{"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
418c1742 6077
14b57c7c
AM		 6078{"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
6079{"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
6080{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
6081{"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
fdd12ef3 6082
14b57c7c
AM		 6083{"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}},
6084{"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}},
252b5132 6085
14b57c7c 6086{"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
066be9f7 6087
14b57c7c 6088{"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
252b5132 6089
14b57c7c
AM		 6090{"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}},
6091{"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}},
418c1742 6092
14b57c7c
AM		 6093{"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}},
6094{"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 6095
066be9f7 6096{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}},
14b57c7c 6097{"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}},
252b5132 6098
14b57c7c 6099{"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}},
19a6653c 6100
ac8f0f72 6101{"stvswx", X(31,741), X_MASK, E6500, 0, {VS, RA0, RB}},
aea77599 6102
14b57c7c 6103{"stdat", X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}},
a680de9a 6104
14b57c7c 6105{"stqfcmux", APU(31,743,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
081ba1b3 6106
14b57c7c
AM		 6107{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
6108{"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
6109{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
6110{"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
252b5132 6111
14b57c7c
AM		 6112{"mulldo", XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6113{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
252b5132 6114
14b57c7c
AM		 6115{"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
6116{"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
6117{"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
6118{"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
418c1742 6119
14b57c7c
AM		 6120{"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6121{"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6122{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6123{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
702f0fb4 6124
14b57c7c
AM		 6125{"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM, 0, {0}},
6126{"tresume.", XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, 0, {0}},
6127{"tsr.", XRC(31,750,1), XRTLRARB_MASK,PPCHTM, 0, {L}},
5817ffd1 6128
14b57c7c 6129{"darn", X(31,755), XLRAND_MASK, POWER9, 0, {RT, LRAND}},
a680de9a 6130
14b57c7c
AM		 6131{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
6132{"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, 0, {RA0, RB}},
252b5132 6133
14b57c7c 6134{"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
252b5132 6135
14b57c7c
AM		 6136{"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}},
6137{"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}},
252b5132 6138
ac8f0f72 6139{"lvsm", X(31,773), X_MASK, E6500, 0, {VD, RA0, RB}},
a680de9a 6140
fd486b63 6141{"copy", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}},
a680de9a 6142
ac8f0f72 6143{"stvepxl", X(31,775), X_MASK, E6500, 0, {VS, RA0, RB}},
14b57c7c
AM		 6144{"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}},
6145{"ldfcmux", APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
ede602d7 6146
14b57c7c
AM		 6147{"dozo", XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6148{"dozo.", XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
252b5132 6149
14b57c7c
AM		 6150{"addo", XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6151{"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6152{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6153{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 6154
14b57c7c
AM		 6155{"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}},
6156{"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}},
a680de9a 6157
14b57c7c
AM		 6158{"lxvw4x", X(31,780), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
6159{"lxsibzx", X(31,781), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
066be9f7 6160
14b57c7c 6161{"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
5817ffd1 6162
14b57c7c 6163{"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
252b5132 6164
14b57c7c 6165{"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}},
252b5132 6166
14b57c7c 6167{"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}},
252b5132 6168
73f07bff 6169{"lfdpx", X(31,791), X_MASK|Q_MASK, POWER6, POWER7, {FRTp, RA0, RB}},
14b57c7c 6170{"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}},
418c1742 6171
14b57c7c
AM		 6172{"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6173{"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
6174{"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6175{"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
fdd12ef3 6176
14b57c7c
AM		 6177{"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}},
6178{"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}},
252b5132 6179
14b57c7c 6180{"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}},
19a6653c 6181
ac8f0f72
AM		 6182{"lvtrxl", X(31,805), X_MASK, E6500, 0, {VD, RA0, RB}},
6183{"stvepx", X(31,807), X_MASK, E6500, 0, {VS, RA0, RB}},
14b57c7c 6184{"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}},
252b5132 6185
14b57c7c
AM		 6186{"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6187{"lxsihzx", X(31,813), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
a680de9a 6188
14b57c7c 6189{"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
5817ffd1 6190
14b57c7c 6191{"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}},
252b5132 6192
14b57c7c 6193{"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}},
e0d602ec 6194
14b57c7c 6195{"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}},
252b5132 6196
14b57c7c 6197{"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, 0, {STRM}},
252b5132 6198
14b57c7c 6199{"lfqux", X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}},
fdd12ef3 6200
14b57c7c
AM		 6201{"srawi", XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}},
6202{"srai", XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}},
6203{"srawi.", XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}},
6204{"srai.", XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}},
702f0fb4 6205
14b57c7c
AM		 6206{"sradi", XS(31,413,0), XS_MASK, PPC64, 0, {RA, RS, SH6}},
6207{"sradi.", XS(31,413,1), XS_MASK, PPC64, 0, {RA, RS, SH6}},
e0c21649 6208
ac8f0f72 6209{"lvtlxl", X(31,837), X_MASK, E6500, 0, {VD, RA0, RB}},
aea77599 6210
fd486b63 6211{"cpabort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}},
a680de9a 6212
14b57c7c
AM		 6213{"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6214{"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
252b5132 6215
14b57c7c 6216{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
a680de9a 6217{"lxvx", X(31,844), XX1_MASK, POWER8, POWER9|PPCVSX3, {XT6, RA0, RB}},
9b4e5766 6218
14b57c7c 6219{"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
5817ffd1 6220
14b57c7c 6221{"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}},
e0d602ec 6222
fd486b63 6223{"slbiag", X(31,850), XRARB_MASK, POWER9, 0, {RS}},
14b57c7c 6224{"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
a680de9a 6225{"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}},
252b5132 6226
14b57c7c 6227{"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}},
418c1742 6228
9fe54b1c 6229{"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}},
14b57c7c
AM		 6230{"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, 0, {MO}},
6231{"eieio", XMBAR(31,854,1),0xffffffff, E500, 0, {0}},
6232{"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, 0, {0}},
418c1742 6233
14b57c7c 6234{"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}},
418c1742 6235
ac8f0f72 6236{"lvswxl", X(31,869), X_MASK, E6500, 0, {VD, RA0, RB}},
aea77599 6237
14b57c7c
AM		 6238{"abso", XO(31,360,1,0), XORB_MASK, M601, 0, {RT, RA}},
6239{"abso.", XO(31,360,1,1), XORB_MASK, M601, 0, {RT, RA}},
702f0fb4 6240
14b57c7c
AM		 6241{"divso", XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6242{"divso.", XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
252b5132 6243
14b57c7c 6244{"lxvb16x", X(31,876), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
a680de9a 6245
14b57c7c 6246{"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
5817ffd1 6247
14b57c7c 6248{"rmieg", X(31,882), XRTRA_MASK, POWER9, 0, {RB}},
a680de9a 6249
14b57c7c 6250{"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}},
252b5132 6251
14b57c7c 6252{"msgsync", X(31,886), 0xffffffff, POWER9, 0, {0}},
a680de9a 6253
14b57c7c 6254{"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}},
066be9f7 6255
14b57c7c
AM		 6256{"extswsli", XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}},
6257{"extswsli.", XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}},
a680de9a 6258
fd486b63 6259{"paste.", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}},
a680de9a 6260
14b57c7c
AM		 6261{"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}},
6262{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
252b5132 6263
14b57c7c
AM		 6264{"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6265{"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6266{"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6267{"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
066be9f7 6268
14b57c7c
AM		 6269{"stxvw4x", X(31,908), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
6270{"stxsibx", X(31,909), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
066be9f7 6271
14b57c7c 6272{"tabort.", XRC(31,910,1), XRTRB_MASK, PPCHTM, 0, {RA}},
5817ffd1 6273
14b57c7c
AM		 6274{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
6275{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
252b5132 6276
14b57c7c 6277{"slbmfee", X(31,915), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
a680de9a 6278{"slbmfee", X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}},
702f0fb4 6279
14b57c7c 6280{"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}},
f5c120c5 6281
14b57c7c 6282{"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}},
252b5132 6283
73f07bff 6284{"stfdpx", X(31,919), X_MASK|Q_MASK, POWER6, POWER7, {FRSp, RA0, RB}},
14b57c7c 6285{"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}},
6ba045b1 6286
14b57c7c
AM		 6287{"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}},
6288{"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}},
702f0fb4 6289
14b57c7c
AM		 6290{"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}},
6291{"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 6292
14b57c7c
AM		 6293{"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
6294{"exts", XRC(31,922,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
6295{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
6296{"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
702f0fb4 6297
14b57c7c 6298{"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}},
19a6653c 6299
ac8f0f72 6300{"stvfrxl", X(31,933), X_MASK, E6500, 0, {VS, RA0, RB}},
aea77599 6301
14b57c7c 6302{"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}},
a5721ba2
AM		 6303{"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L2}},
6304{"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}},
85d4ac0b 6305
14b57c7c 6306{"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}},
6ba045b1 6307
14b57c7c
AM		 6308{"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6309{"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6310{"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6311{"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
066be9f7 6312
14b57c7c
AM		 6313{"stxvh8x", X(31,940), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6314{"stxsihx", X(31,941), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
a680de9a 6315
14b57c7c 6316{"treclaim.", XRC(31,942,1), XRTRB_MASK, PPCHTM, 0, {RA}},
5817ffd1 6317
e0d602ec
BE		 6318{"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
6319{"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
14b57c7c 6320{"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
702f0fb4 6321
14b57c7c 6322{"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}},
252b5132 6323
14b57c7c
AM		 6324{"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}},
6325{"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}},
51b5d4a8 6326
14b57c7c 6327{"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}},
252b5132 6328
14b57c7c
AM		 6329{"sraiq", XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}},
6330{"sraiq.", XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}},
252b5132 6331
14b57c7c
AM		 6332{"extsb", XRC(31,954,0), XRB_MASK, PPC, 0, {RA, RS}},
6333{"extsb.", XRC(31,954,1), XRB_MASK, PPC, 0, {RA, RS}},
252b5132 6334
ac8f0f72 6335{"stvflxl", X(31,965), X_MASK, E6500, 0, {VS, RA0, RB}},
aea77599 6336
62adc510 6337{"iccci", X(31,966), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
14b57c7c 6338{"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, 0, {CT}},
43e65147 6339
14b57c7c
AM		 6340{"divduo", XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6341{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
43e65147 6342
14b57c7c
AM		 6343{"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6344{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
252b5132 6345
14b57c7c 6346{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
a680de9a 6347{"stxvx", X(31,972), XX1_MASK, POWER8, POWER9|PPCVSX3, {XS6, RA0, RB}},
9b4e5766 6348
9fe54b1c 6349{"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
14b57c7c
AM		 6350{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, 0, {RT, RA}},
6351{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, 0, {RT, RA}},
6352{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
418c1742 6353
14b57c7c 6354{"slbfee.", XRC(31,979,1), XRA_MASK, POWER6, 0, {RT, RB}},
c4e676f1 6355
14b57c7c 6356{"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}},
252b5132 6357
14b57c7c 6358{"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}},
252b5132 6359
14b57c7c 6360{"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}},
702f0fb4 6361
14b57c7c
AM		 6362{"extsw", XRC(31,986,0), XRB_MASK, PPC64, 0, {RA, RS}},
6363{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, 0, {RA, RS}},
252b5132 6364
14b57c7c 6365{"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
19a6653c 6366
ac8f0f72 6367{"stvswxl", X(31,997), X_MASK, E6500, 0, {VS, RA0, RB}},
aea77599 6368
14b57c7c 6369{"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}},
252b5132 6370
14b57c7c
AM		 6371{"nabso", XO(31,488,1,0), XORB_MASK, M601, 0, {RT, RA}},
6372{"nabso.", XO(31,488,1,1), XORB_MASK, M601, 0, {RT, RA}},
252b5132 6373
14b57c7c
AM		 6374{"divdo", XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6375{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
43e65147 6376
14b57c7c
AM		 6377{"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6378{"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
418c1742 6379
14b57c7c 6380{"stxvb16x", X(31,1004), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
a680de9a 6381
14b57c7c 6382{"trechkpt.", XRC(31,1006,1), XRTRARB_MASK,PPCHTM, 0, {0}},
702f0fb4 6383
14b57c7c 6384{"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}},
252b5132 6385
14b57c7c 6386{"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}},
418c1742 6387
14b57c7c
AM		 6388{"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
6389{"dclz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
786e2c0f 6390
14b57c7c 6391{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
ede602d7 6392
14b57c7c 6393{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}},
252b5132 6394
14b57c7c
AM		 6395{"cctpl", 0x7c210b78, 0xffffffff, CELL, 0, {0}},
6396{"cctpm", 0x7c421378, 0xffffffff, CELL, 0, {0}},
6397{"cctph", 0x7c631b78, 0xffffffff, CELL, 0, {0}},
252b5132 6398
14b57c7c
AM		 6399{"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
6400{"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
6401{"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, 0, {0}},
252b5132 6402
14b57c7c
AM		 6403{"db8cyc", 0x7f9ce378, 0xffffffff, CELL, 0, {0}},
6404{"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, 0, {0}},
6405{"db12cyc", 0x7fdef378, 0xffffffff, CELL, 0, {0}},
6406{"db16cyc", 0x7ffffb78, 0xffffffff, CELL, 0, {0}},
252b5132 6407
14b57c7c
AM		 6408{"lwz", OP(32), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
6409{"l", OP(32), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
252b5132 6410
14b57c7c
AM		 6411{"lwzu", OP(33), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAL}},
6412{"lu", OP(33), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
252b5132 6413
14b57c7c 6414{"lbz", OP(34), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
252b5132 6415
14b57c7c 6416{"lbzu", OP(35), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
252b5132 6417
14b57c7c
AM		 6418{"stw", OP(36), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},
6419{"st", OP(36), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
252b5132 6420
14b57c7c
AM		 6421{"stwu", OP(37), OP_MASK, PPCCOM, PPCVLE, {RS, D, RAS}},
6422{"stu", OP(37), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
252b5132 6423
14b57c7c 6424{"stb", OP(38), OP_MASK, COM, PPCVLE, {RS, D, RA0}},
252b5132 6425
14b57c7c 6426{"stbu", OP(39), OP_MASK, COM, PPCVLE, {RS, D, RAS}},
252b5132 6427
14b57c7c 6428{"lhz", OP(40), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
252b5132 6429
14b57c7c 6430{"lhzu", OP(41), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
252b5132 6431
14b57c7c 6432{"lha", OP(42), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
252b5132 6433
14b57c7c 6434{"lhau", OP(43), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
252b5132 6435
14b57c7c 6436{"sth", OP(44), OP_MASK, COM, PPCVLE, {RS, D, RA0}},
252b5132 6437
14b57c7c 6438{"sthu", OP(45), OP_MASK, COM, PPCVLE, {RS, D, RAS}},
252b5132 6439
14b57c7c
AM		 6440{"lmw", OP(46), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAM}},
6441{"lm", OP(46), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
252b5132 6442
14b57c7c
AM		 6443{"stmw", OP(47), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},
6444{"stm", OP(47), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
252b5132 6445
14b57c7c 6446{"lfs", OP(48), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},
252b5132 6447
14b57c7c 6448{"lfsu", OP(49), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}},
252b5132 6449
14b57c7c 6450{"lfd", OP(50), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},
252b5132 6451
14b57c7c 6452{"lfdu", OP(51), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}},
252b5132 6453
14b57c7c 6454{"stfs", OP(52), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
adadcc0c 6455
14b57c7c 6456{"stfsu", OP(53), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
252b5132 6457
14b57c7c 6458{"stfd", OP(54), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
c3d65c1c 6459
14b57c7c 6460{"stfdu", OP(55), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
252b5132 6461
73f07bff 6462{"lq", OP(56), OP_MASK|Q_MASK, POWER4, PPC476|PPCVLE, {RTQ, DQ, RAQ}},
14b57c7c
AM		 6463{"psq_l", OP(56), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
6464{"lfq", OP(56), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},
418c1742 6465
14b57c7c
AM		 6466{"lxsd", DSO(57,2), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}},
6467{"lxssp", DSO(57,3), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}},
73f07bff 6468{"lfdp", OP(57), OP_MASK|Q_MASK, POWER6, POWER7|PPCVLE, {FRTp, DS, RA0}},
14b57c7c
AM		 6469{"psq_lu", OP(57), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
6470{"lfqu", OP(57), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},
802a735e 6471
14b57c7c
AM		 6472{"ld", DSO(58,0), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
6473{"ldu", DSO(58,1), DS_MASK, PPC64, PPCVLE, {RT, DS, RAL}},
6474{"lwa", DSO(58,2), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
702f0fb4 6475
14b57c7c
AM		 6476{"dadd", XRC(59,2,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6477{"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
252b5132 6478
14b57c7c
AM		 6479{"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
6480{"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
252b5132 6481
14b57c7c
AM		 6482{"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6483{"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
252b5132 6484
14b57c7c
AM		 6485{"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6486{"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
252b5132 6487
14b57c7c
AM		 6488{"fadds", A(59,21,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6489{"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
252b5132 6490
14b57c7c
AM		 6491{"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}},
6492{"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}},
252b5132 6493
14b57c7c
AM		 6494{"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6495{"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6496{"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6497{"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
1ed8e1e4 6498
14b57c7c
AM		 6499{"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6500{"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
252b5132 6501
14b57c7c
AM		 6502{"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6503{"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6504{"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6505{"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
252b5132 6506
14b57c7c
AM		 6507{"fmsubs", A(59,28,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6508{"fmsubs.", A(59,28,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
252b5132 6509
14b57c7c
AM		 6510{"fmadds", A(59,29,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6511{"fmadds.", A(59,29,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
252b5132 6512
14b57c7c
AM		 6513{"fnmsubs", A(59,30,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6514{"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
702f0fb4 6515
14b57c7c
AM		 6516{"fnmadds", A(59,31,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6517{"fnmadds.", A(59,31,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
702f0fb4 6518
14b57c7c
AM		 6519{"dmul", XRC(59,34,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6520{"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
702f0fb4 6521
14b57c7c
AM		 6522{"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
6523{"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
702f0fb4 6524
14b57c7c
AM		 6525{"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6526{"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
702f0fb4 6527
14b57c7c
AM		 6528{"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
6529{"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
702f0fb4 6530
14b57c7c
AM		 6531{"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6532{"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
702f0fb4 6533
14b57c7c
AM		 6534{"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6535{"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
702f0fb4 6536
14b57c7c 6537{"dcmpo", X(59,130), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
702f0fb4 6538
14b57c7c
AM		 6539{"dtstex", X(59,162), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6540{"dtstdc", Z(59,194), Z_MASK, POWER6, PPCVLE, {BF, FRA, DCM}},
6541{"dtstdg", Z(59,226), Z_MASK, POWER6, PPCVLE, {BF, FRA, DGM}},
6542
6543{"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6544{"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6545
6546{"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6547{"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6548
6549{"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6550{"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6551
6552{"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
6553{"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
6554
6555{"dxex", XRC(59,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6556{"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6557
6558{"dsub", XRC(59,514,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6559{"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6560
6561{"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6562{"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6563
6564{"dcmpu", X(59,642), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6565
6566{"dtstsf", X(59,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6567{"dtstsfi", X(59,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRB}},
6568
6569{"drsp", XRC(59,770,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6570{"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6571
6572{"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6573{"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6574
6575{"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
6576{"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
6577
6578{"fcfids", XRC(59,846,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6579{"fcfids.", XRC(59,846,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6580
6581{"diex", XRC(59,866,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6582{"diex.", XRC(59,866,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6583
6584{"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6585{"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6586
6587{"xsaddsp", XX3(60,0), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6588{"xsmaddasp", XX3(60,1), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6589{"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, SHW}},
6590{"xscmpeqdp", XX3(60,3), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6591{"xsrsqrtesp", XX2(60,10), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6592{"xssqrtsp", XX2(60,11), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6593{"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, XC6}},
6594{"xssubsp", XX3(60,8), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6595{"xsmaddmsp", XX3(60,9), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6596{"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S, DMEX}},
6597{"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6598{"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6599{"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6600{"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, DM}},
6601{"xscmpgtdp", XX3(60,11), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6602{"xsresp", XX2(60,26), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6603{"xsmulsp", XX3(60,16), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6604{"xsmsubasp", XX3(60,17), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6605{"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6606{"xscmpgedp", XX3(60,19), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6607{"xsdivsp", XX3(60,24), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6608{"xsmsubmsp", XX3(60,25), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6609{"xxperm", XX3(60,26), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6610{"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6611{"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6612{"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6613{"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6614{"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6615{"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6616{"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6617{"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6618{"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6619{"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6620{"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6621{"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6622{"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6623{"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6624{"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6625{"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6626{"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6627{"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6628{"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6629{"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6630{"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6631{"xxpermr", XX3(60,58), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6632{"xscmpexpdp", XX3(60,59), XX3BF_MASK, PPCVSX3, PPCVLE, {BF, XA6, XB6}},
6633{"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6634{"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6635{"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6636{"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6637{"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6638{"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6639{"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6640{"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6641{"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6642{"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6643{"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6644{"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6645{"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6646{"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6647{"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6648{"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6649{"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6650{"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6651{"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6652{"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCVLE, {XT6, XB6, UIM}},
6653{"xxextractuw", XX2(60,165), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}},
6654{"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6655{"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6656{"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6657{"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6658{"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6659{"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6660{"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6661{"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6662{"xxspltib", X(60,360), XX1_MASK|3<<19, PPCVSX3, PPCVLE, {XT6, IMM8}},
6663{"xxinsertw", XX2(60,181), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}},
6664{"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6665{"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6666{"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6667{"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6668{"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6669{"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6670{"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6671{"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6672{"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6673{"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6674{"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6675{"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6676{"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6677{"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6678{"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6679{"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6680{"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6681{"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6682{"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6683{"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6684{"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6685{"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6686{"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6687{"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6688{"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6689{"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6690{"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6691{"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6692{"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6693{"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6694{"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6695{"xsmaxcdp", XX3(60,128), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6696{"xsnmaddasp", XX3(60,129), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6697{"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6698{"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6699{"xscvdpspn", XX2(60,267), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6700{"xsmincdp", XX3(60,136), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6701{"xsnmaddmsp", XX3(60,137), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6702{"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6703{"xsrsp", XX2(60,281), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6704{"xsmaxjdp", XX3(60,144), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6705{"xsnmsubasp", XX3(60,145), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6706{"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6707{"xscvuxdsp", XX2(60,296), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6708{"xststdcsp", XX2(60,298), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}},
6709{"xsminjdp", XX3(60,152), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6710{"xsnmsubmsp", XX3(60,153), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6711{"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6712{"xscvsxdsp", XX2(60,312), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6713{"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6714{"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6715{"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6716{"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6717{"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6718{"xscvspdpn", XX2(60,331), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6719{"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6720{"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6721{"xxlorc", XX3(60,170), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6722{"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6723{"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6724{"xsxexpdp", XX2VA(60,347,0),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
6725{"xsxsigdp", XX2VA(60,347,1),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
6726{"xscvhpdp", XX2VA(60,347,16),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6727{"xscvdphp", XX2VA(60,347,17),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6728{"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6729{"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6730{"xxlnand", XX3(60,178), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6731{"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6732{"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6733{"xststdcdp", XX2(60,362), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}},
6734{"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6735{"xxleqv", XX3(60,186), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6736{"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6737{"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6738{"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6739{"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6740{"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6741{"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6742{"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6743{"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6744{"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6745{"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6746{"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6747{"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6748{"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6749{"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6750{"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6751{"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}},
6752{"xviexpsp", XX3(60,216), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6753{"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6754{"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6755{"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6756{"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6757{"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6758{"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6759{"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6760{"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCVLE, {XT6, RA, RB}},
6761{"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6762{"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6763{"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6764{"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6765{"xvxexpdp", XX2VA(60,475,0),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6766{"xvxsigdp", XX2VA(60,475,1),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6767{"xxbrh", XX2VA(60,475,7),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6768{"xvxexpsp", XX2VA(60,475,8),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6769{"xvxsigsp", XX2VA(60,475,9),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6770{"xxbrw", XX2VA(60,475,15),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6771{"xxbrd", XX2VA(60,475,23),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6772{"xvcvhpsp", XX2VA(60,475,24),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6773{"xvcvsphp", XX2VA(60,475,25),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6774{"xxbrq", XX2VA(60,475,31),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6775{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6776{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6777{"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6778{"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6779{"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6780{"xvtstdcdp", XX2(60,490), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}},
6781{"xviexpdp", XX3(60,248), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6782{"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6783{"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6784{"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6785
6786{"psq_st", OP(60), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
6787{"stfq", OP(60), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
6788
6789{"lxv", DQX(61,1), DQX_MASK, PPCVSX3, PPCVLE, {XTQ6, DQ, RA0}},
6790{"stxv", DQX(61,5), DQX_MASK, PPCVSX3, PPCVLE, {XSQ6, DQ, RA0}},
6791{"stxsd", DSO(61,2), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},
6792{"stxssp", DSO(61,3), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},
73f07bff 6793{"stfdp", OP(61), OP_MASK|Q_MASK, POWER6, POWER7|PPCVLE, {FRSp, DS, RA0}},
14b57c7c
AM		 6794{"psq_stu", OP(61), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
6795{"stfqu", OP(61), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
6796
6797{"std", DSO(62,0), DS_MASK, PPC64, PPCVLE, {RS, DS, RA0}},
6798{"stdu", DSO(62,1), DS_MASK, PPC64, PPCVLE, {RS, DS, RAS}},
73f07bff 6799{"stq", DSO(62,2), DS_MASK|Q_MASK, POWER4, PPC476|PPCVLE, {RSQ, DS, RA0}},
14b57c7c
AM		 6800
6801{"fcmpu", X(63,0), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}},
6802
73f07bff
AM		 6803{"daddq", XRC(63,2,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6804{"daddq.", XRC(63,2,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
14b57c7c 6805
73f07bff
AM		 6806{"dquaq", ZRC(63,3,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}},
6807{"dquaq.", ZRC(63,3,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}},
14b57c7c
AM		 6808
6809{"xsaddqp", XRC(63,4,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6810{"xsaddqpo", XRC(63,4,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6811
6812{"xsrqpi", ZRC(63,5,0), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
6813{"xsrqpix", ZRC(63,5,1), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
6814
6815{"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
6816{"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
6817
6818{"frsp", XRC(63,12,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6819{"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6820
6821{"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6822{"fcir", XRC(63,14,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6823{"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6824{"fcir.", XRC(63,14,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6825
6826{"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6827{"fcirz", XRC(63,15,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6828{"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6829{"fcirz.", XRC(63,15,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6830
6831{"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6832{"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6833{"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6834{"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6835
6836{"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6837{"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6838{"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6839{"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6840
6841{"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6842{"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6843{"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6844{"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6845
6846{"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}},
6847{"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}},
6848
6849{"fsel", A(63,23,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6850{"fsel.", A(63,23,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6851
6852{"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6853{"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6854{"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6855{"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
1ed8e1e4 6856
14b57c7c
AM		 6857{"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6858{"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}},
6859{"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6860{"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}},
252b5132 6861
14b57c7c
AM		 6862{"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6863{"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6864{"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6865{"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
252b5132 6866
14b57c7c
AM		 6867{"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6868{"fms", A(63,28,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6869{"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6870{"fms.", A(63,28,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
252b5132 6871
14b57c7c
AM		 6872{"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6873{"fma", A(63,29,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6874{"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6875{"fma.", A(63,29,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
252b5132 6876
14b57c7c
AM		 6877{"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6878{"fnms", A(63,30,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6879{"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6880{"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
252b5132 6881
14b57c7c
AM		 6882{"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6883{"fnma", A(63,31,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6884{"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6885{"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
252b5132 6886
14b57c7c 6887{"fcmpo", X(63,32), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}},
252b5132 6888
73f07bff
AM		 6889{"dmulq", XRC(63,34,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6890{"dmulq.", XRC(63,34,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
702f0fb4 6891
73f07bff
AM		 6892{"drrndq", ZRC(63,35,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}},
6893{"drrndq.", ZRC(63,35,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}},
702f0fb4 6894
14b57c7c
AM		 6895{"xsmulqp", XRC(63,36,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6896{"xsmulqpo", XRC(63,36,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 6897
14b57c7c 6898{"xsrqpxp", Z(63,37), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
a680de9a 6899
14b57c7c
AM		 6900{"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCVLE, {BT}},
6901{"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCVLE, {BT}},
252b5132 6902
14b57c7c
AM		 6903{"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6904{"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
252b5132 6905
14b57c7c 6906{"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
252b5132 6907
73f07bff
AM		 6908{"dscliq", ZRC(63,66,0), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6909{"dscliq.", ZRC(63,66,1), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
702f0fb4 6910
73f07bff
AM		 6911{"dquaiq", ZRC(63,67,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
6912{"dquaiq.", ZRC(63,67,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
702f0fb4 6913
14b57c7c
AM		 6914{"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCVLE, {BT}},
6915{"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCVLE, {BT}},
252b5132 6916
14b57c7c
AM		 6917{"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6918{"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
252b5132 6919
73f07bff
AM		 6920{"dscriq", ZRC(63,98,0), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6921{"dscriq.", ZRC(63,98,1), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
702f0fb4 6922
73f07bff
AM		 6923{"drintxq", ZRC(63,99,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6924{"drintxq.", ZRC(63,99,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
702f0fb4 6925
14b57c7c 6926{"xscpsgnqp", X(63,100), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 6927
14b57c7c 6928{"ftdiv", X(63,128), XBF_MASK, POWER7, PPCVLE, {BF, FRA, FRB}},
066be9f7 6929
14b57c7c 6930{"dcmpoq", X(63,130), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
702f0fb4 6931
14b57c7c 6932{"xscmpoqp", X(63,132), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
a680de9a 6933
14b57c7c
AM		 6934{"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}},
6935{"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}},
6936{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}},
6937{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}},
252b5132 6938
14b57c7c
AM		 6939{"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6940{"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
252b5132 6941
14b57c7c
AM		 6942{"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6943{"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6944{"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6945{"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
066be9f7 6946
14b57c7c 6947{"ftsqrt", X(63,160), XBF_MASK|FRA_MASK, POWER7, PPCVLE, {BF, FRB}},
066be9f7 6948
14b57c7c 6949{"dtstexq", X(63,162), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
a680de9a 6950
14b57c7c 6951{"xscmpexpqp", X(63,164), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
a680de9a 6952
14b57c7c
AM		 6953{"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DCM}},
6954{"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DGM}},
702f0fb4 6955
73f07bff
AM		 6956{"drintnq", ZRC(63,227,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6957{"drintnq.", ZRC(63,227,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
702f0fb4 6958
73f07bff
AM		 6959{"dctqpq", XRC(63,258,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
6960{"dctqpq.", XRC(63,258,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
702f0fb4 6961
14b57c7c
AM		 6962{"fabs", XRC(63,264,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6963{"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
252b5132 6964
14b57c7c
AM		 6965{"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6966{"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
702f0fb4 6967
73f07bff
AM		 6968{"ddedpdq", XRC(63,322,0), X_MASK|Q_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
6969{"ddedpdq.", XRC(63,322,1), X_MASK|Q_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
702f0fb4 6970
14b57c7c
AM		 6971{"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6972{"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
702f0fb4 6973
14b57c7c
AM		 6974{"xsmaddqp", XRC(63,388,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6975{"xsmaddqpo", XRC(63,388,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 6976
14b57c7c
AM		 6977{"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6978{"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
a680de9a 6979
14b57c7c
AM		 6980{"xsmsubqp", XRC(63,420,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6981{"xsmsubqpo", XRC(63,420,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 6982
14b57c7c
AM		 6983{"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6984{"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
a680de9a 6985
14b57c7c
AM		 6986{"xsnmaddqp", XRC(63,452,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6987{"xsnmaddqpo", XRC(63,452,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 6988
14b57c7c
AM		 6989{"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6990{"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
a680de9a 6991
14b57c7c
AM		 6992{"xsnmsubqp", XRC(63,484,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6993{"xsnmsubqpo", XRC(63,484,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 6994
14b57c7c
AM		 6995{"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6996{"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
ce7a772b 6997
73f07bff
AM		 6998{"dsubq", XRC(63,514,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6999{"dsubq.", XRC(63,514,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
702f0fb4 7000
14b57c7c
AM		 7001{"xssubqp", XRC(63,516,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7002{"xssubqpo", XRC(63,516,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 7003
73f07bff
AM		 7004{"ddivq", XRC(63,546,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
7005{"ddivq.", XRC(63,546,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
702f0fb4 7006
14b57c7c
AM		 7007{"xsdivqp", XRC(63,548,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7008{"xsdivqpo", XRC(63,548,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 7009
14b57c7c
AM		 7010{"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}},
7011{"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}},
252b5132 7012
6fd3a02d
PB		 7013{"mffsce", XMMF(63,583,0,1), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}},
7014{"mffscdrn", XMMF(63,583,2,4), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}},
7015{"mffscdrni", XMMF(63,583,2,5), XMMF_MASK|(3<<14), POWER9, PPCVLE, {FRT, DRM}},
7016{"mffscrn", XMMF(63,583,2,6), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}},
7017{"mffscrni", XMMF(63,583,2,7), XMMF_MASK|(7<<13), POWER9, PPCVLE, {FRT, RM}},
7018{"mffsl", XMMF(63,583,3,0), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}},
7019
14b57c7c 7020{"dcmpuq", X(63,642), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
702f0fb4 7021
14b57c7c 7022{"xscmpuqp", X(63,644), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
a680de9a 7023
14b57c7c
AM		 7024{"dtstsfq", X(63,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRBp}},
7025{"dtstsfiq", X(63,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRBp}},
a680de9a 7026
14b57c7c 7027{"xststdcqp", X(63,708), X_MASK, PPCVSX3, PPCVLE, {BF, VB, DCMX}},
702f0fb4 7028
14b57c7c
AM		 7029{"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}},
7030{"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
7031{"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}},
7032{"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
252b5132 7033
73f07bff
AM		 7034{"drdpq", XRC(63,770,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
7035{"drdpq.", XRC(63,770,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
702f0fb4 7036
73f07bff
AM		 7037{"dcffixq", XRC(63,802,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
7038{"dcffixq.", XRC(63,802,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
702f0fb4 7039
14b57c7c
AM		 7040{"xsabsqp", XVA(63,804,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7041{"xsxexpqp", XVA(63,804,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7042{"xsnabsqp", XVA(63,804,8), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7043{"xsnegqp", XVA(63,804,16), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7044{"xsxsigqp", XVA(63,804,18), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7045{"xssqrtqp", XVARC(63,804,27,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7046{"xssqrtqpo", XVARC(63,804,27,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
a680de9a 7047
14b57c7c
AM		 7048{"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7049{"fctid", XRC(63,814,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
7050{"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7051{"fctid.", XRC(63,814,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
252b5132 7052
14b57c7c
AM		 7053{"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7054{"fctidz", XRC(63,815,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
7055{"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7056{"fctidz.", XRC(63,815,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
252b5132 7057
73f07bff
AM		 7058{"denbcdq", XRC(63,834,0), X_MASK|Q_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
7059{"denbcdq.", XRC(63,834,1), X_MASK|Q_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
702f0fb4 7060
14b57c7c
AM		 7061{"xscvqpuwz", XVA(63,836,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7062{"xscvudqp", XVA(63,836,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7063{"xscvqpswz", XVA(63,836,9), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7064{"xscvsdqp", XVA(63,836,10), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7065{"xscvqpudz", XVA(63,836,17), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7066{"xscvqpdp", XVARC(63,836,20,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7067{"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7068{"xscvdpqp", XVA(63,836,22), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7069{"xscvqpsdz", XVA(63,836,25), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
a680de9a 7070
14b57c7c 7071{"fmrgow", X(63,838), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
c0637f3a 7072
14b57c7c
AM		 7073{"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7074{"fcfid", XRC(63,846,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
7075{"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7076{"fcfid.", XRC(63,846,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
252b5132 7077
73f07bff
AM		 7078{"diexq", XRC(63,866,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
7079{"diexq.", XRC(63,866,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
702f0fb4 7080
14b57c7c 7081{"xsiexpqp", X(63,868), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 7082
14b57c7c
AM		 7083{"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
7084{"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
066be9f7 7085
14b57c7c
AM		 7086{"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
7087{"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
066be9f7 7088
14b57c7c 7089{"fmrgew", X(63,966), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
c0637f3a 7090
14b57c7c
AM		 7091{"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
7092{"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
252b5132
RH		 7093};
7094
7095const int powerpc_num_opcodes =
7096 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
7097\f
b9c361e0
JL		 7098/* The VLE opcode table.
7099
7100 The format of this opcode table is the same as the main opcode table. */
7101
7102const struct powerpc_opcode vle_opcodes[] = {
14b57c7c
AM		 7103{"se_illegal", C(0), C_MASK, PPCVLE, 0, {}},
7104{"se_isync", C(1), C_MASK, PPCVLE, 0, {}},
7105{"se_sc", C(2), C_MASK, PPCVLE, 0, {}},
7106{"se_blr", C_LK(2,0), C_LK_MASK, PPCVLE, 0, {}},
7107{"se_blrl", C_LK(2,1), C_LK_MASK, PPCVLE, 0, {}},
7108{"se_bctr", C_LK(3,0), C_LK_MASK, PPCVLE, 0, {}},
7109{"se_bctrl", C_LK(3,1), C_LK_MASK, PPCVLE, 0, {}},
7110{"se_rfi", C(8), C_MASK, PPCVLE, 0, {}},
7111{"se_rfci", C(9), C_MASK, PPCVLE, 0, {}},
7112{"se_rfdi", C(10), C_MASK, PPCVLE, 0, {}},
7113{"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}},
a8cc8a54 7114{"se_rfgi", C(12), C_MASK, PPCVLE, 0, {}},
14b57c7c
AM		 7115{"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, 0, {RX}},
7116{"se_neg", SE_R(0,3), SE_R_MASK, PPCVLE, 0, {RX}},
7117{"se_mflr", SE_R(0,8), SE_R_MASK, PPCVLE, 0, {RX}},
7118{"se_mtlr", SE_R(0,9), SE_R_MASK, PPCVLE, 0, {RX}},
7119{"se_mfctr", SE_R(0,10), SE_R_MASK, PPCVLE, 0, {RX}},
7120{"se_mtctr", SE_R(0,11), SE_R_MASK, PPCVLE, 0, {RX}},
7121{"se_extzb", SE_R(0,12), SE_R_MASK, PPCVLE, 0, {RX}},
7122{"se_extsb", SE_R(0,13), SE_R_MASK, PPCVLE, 0, {RX}},
7123{"se_extzh", SE_R(0,14), SE_R_MASK, PPCVLE, 0, {RX}},
7124{"se_extsh", SE_R(0,15), SE_R_MASK, PPCVLE, 0, {RX}},
7125{"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7126{"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, 0, {ARX, RY}},
7127{"se_mfar", SE_RR(0,3), SE_RR_MASK, PPCVLE, 0, {RX, ARY}},
7128{"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7129{"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7130{"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7131{"se_subf", SE_RR(1,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7132{"se_cmp", SE_RR(3,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7133{"se_cmpl", SE_RR(3,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7134{"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7135{"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7136
7137{"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
dfdaec14 7138{"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
14b57c7c 7139{"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
dfdaec14 7140{"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
14b57c7c
AM		 7141{"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7142{"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7143{"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7144{"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7145{"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7146{"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7147{"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7148{"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7149{"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7150{"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7151{"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7152{"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7153{"e_nop", SCI8(6,26), 0xffffffff, PPCVLE, 0, {0}},
7154{"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7155{"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7156{"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7157{"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7158{"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7159{"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7160{"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7161{"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7162{"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7163{"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7164{"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7165{"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7166{"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
dfdaec14
AJ		 7167{"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7168{"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7169{"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7170{"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7171{"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7172{"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7173{"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7174{"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7175{"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7176{"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
14b57c7c
AM		 7177{"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}},
7178{"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7179{"e_sub16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}},
7180
7181{"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7182{"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7183{"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7184{"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7185{"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7186{"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7187{"se_andi", SE_IM5(11,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7188
7189{"e_lbz", OP(12), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7190{"e_stb", OP(13), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7191{"e_lha", OP(14), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7192
7193{"se_srw", SE_RR(16,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7194{"se_sraw", SE_RR(16,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7195{"se_slw", SE_RR(16,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7196{"se_nop", SE_RR(17,0), 0xffff, PPCVLE, 0, {0}},
7197{"se_or", SE_RR(17,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7198{"se_andc", SE_RR(17,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7199{"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7200{"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7201{"se_li", IM7(9), IM7_MASK, PPCVLE, 0, {RX, UI7}},
7202
7203{"e_lwz", OP(20), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7204{"e_stw", OP(21), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7205{"e_lhz", OP(22), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7206{"e_sth", OP(23), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7207
7208{"se_bclri", SE_IM5(24,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7209{"se_bgeni", SE_IM5(24,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7210{"se_bseti", SE_IM5(25,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7211{"se_btsti", SE_IM5(25,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7212{"se_srwi", SE_IM5(26,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7213{"se_srawi", SE_IM5(26,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7214{"se_slwi", SE_IM5(27,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7215
7216{"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7217{"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7218{"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7219{"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7220{"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7221{"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
7222{"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
7223{"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
14b57c7c
AM		 7224{"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7225{"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
14b57c7c
AM		 7226{"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
7227{"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7228{"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
7229{"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7230{"e_li", LI20(28,0), LI20_MASK, PPCVLE, 0, {RT, IMM20}},
7231{"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}},
7232{"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RT, SH, MBE, ME}},
7233{"e_b", BD24(30,0,0), BD24_MASK, PPCVLE, 0, {B24}},
7234{"e_bl", BD24(30,0,1), BD24_MASK, PPCVLE, 0, {B24}},
7235{"e_bdnz", EBD15(30,8,BO32DNZ,0), EBD15_MASK, PPCVLE, 0, {B15}},
7236{"e_bdnzl", EBD15(30,8,BO32DNZ,1), EBD15_MASK, PPCVLE, 0, {B15}},
7237{"e_bdz", EBD15(30,8,BO32DZ,0), EBD15_MASK, PPCVLE, 0, {B15}},
7238{"e_bdzl", EBD15(30,8,BO32DZ,1), EBD15_MASK, PPCVLE, 0, {B15}},
7239{"e_bge", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7240{"e_bgel", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7241{"e_bnl", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7242{"e_bnll", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7243{"e_blt", EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7244{"e_bltl", EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7245{"e_bgt", EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7246{"e_bgtl", EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7247{"e_ble", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7248{"e_blel", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7249{"e_bng", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7250{"e_bngl", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7251{"e_bne", EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7252{"e_bnel", EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7253{"e_beq", EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7254{"e_beql", EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7255{"e_bso", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7256{"e_bsol", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7257{"e_bun", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7258{"e_bunl", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7259{"e_bns", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7260{"e_bnsl", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7261{"e_bnu", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7262{"e_bnul", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7263{"e_bc", BD15(30,8,0), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
7264{"e_bcl", BD15(30,8,1), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
7265
7266{"e_bf", EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7267{"e_bfl", EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7268{"e_bt", EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7269{"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7270
7271{"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
a8cc8a54 7272{"e_sc", X(31,36), XRTRA_MASK, PPCVLE, 0, {ELEV}},
14b57c7c
AM		 7273{"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
7274{"e_crandc", XL(31,129), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7275{"e_crnand", XL(31,225), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7276{"e_crnot", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BBA}},
7277{"e_crnor", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7278{"e_crclr", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}},
7279{"e_crxor", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7280{"e_mcrf", XL(31,16), XL_MASK, PPCVLE, 0, {CRD, CR}},
7281{"e_slwi", EX(31,112), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7282{"e_slwi.", EX(31,113), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7283
7284{"e_crand", XL(31,257), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7285
7286{"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
7287{"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
7288
7289{"e_crset", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}},
7290{"e_creqv", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7291
7292{"e_rlwi", EX(31,624), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7293{"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7294
7295{"e_crorc", XL(31,417), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7296
7297{"e_crmove", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BBA}},
7298{"e_cror", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7299
7300{"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, 0, {RS}},
7301
7302{"e_srwi", EX(31,1136), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7303{"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7304
7305{"se_lbz", SD4(8), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
7306
7307{"se_stb", SD4(9), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
7308
7309{"se_lhz", SD4(10), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
7310
7311{"se_sth", SD4(11), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
7312
7313{"se_lwz", SD4(12), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
7314
7315{"se_stw", SD4(13), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
7316
7317{"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7318{"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7319{"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7320{"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7321{"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7322{"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7323{"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7324{"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}},
7325{"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7326{"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7327{"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7328{"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7329{"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7330{"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}},
7331{"se_bc", BD8IO(28), BD8IO_MASK, PPCVLE, 0, {BO16, BI16, B8}},
7332{"se_b", BD8(58,0,0), BD8_MASK, PPCVLE, 0, {B8}},
7333{"se_bl", BD8(58,0,1), BD8_MASK, PPCVLE, 0, {B8}},
b9c361e0
JL		 7334};
7335
7336const int vle_num_opcodes =
7337 sizeof (vle_opcodes) / sizeof (vle_opcodes[0]);
7338\f
252b5132
RH		 7339/* The macro table. This is only used by the assembler. */
7340
7341/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
7342 when x=0; 32-x when x is between 1 and 31; are negative if x is
7343 negative; and are 32 or more otherwise. This is what you want
7344 when, for instance, you are emulating a right shift by a
7345 rotate-left-and-mask, because the underlying instructions support
7346 shifts of size 0 but not shifts of size 32. By comparison, when
7347 extracting x bits from some word you want to use just 32-x, because
7348 the underlying instructions don't support extracting 0 bits but do
7349 support extracting the whole word (32 bits in this case). */
7350
7351const struct powerpc_macro powerpc_macros[] = {
de866fcc
AM		 7352{"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"},
7353{"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"},
bdc7fcfe
AM		 7354{"extrdi", 4, PPC64, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
7355{"extrdi.", 4, PPC64, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
de866fcc
AM		 7356{"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"},
7357{"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"},
7358{"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
7359{"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
7360{"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"},
7361{"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"},
7362{"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
7363{"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
7364{"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"},
7365{"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"},
7366{"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"},
14b57c7c 7367{"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"},
de866fcc
AM		 7368
7369{"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
7370{"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
7371{"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7372{"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7373{"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7374{"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7375{"insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
7376{"insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
7377{"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7378{"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7379{"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"},
7380{"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
7381{"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"},
7382{"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"},
7383{"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7384{"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7385{"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7386{"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7387{"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"},
7388{"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
7389{"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
7390{"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
a4ebc835
AM		 7391
7392{"e_extlwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"},
7393{"e_extrwi", 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7394{"e_inslwi", 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7395{"e_insrwi", 4, PPCVLE, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
7396{"e_rotlwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31"},
7397{"e_rotrwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7398{"e_slwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31-(%2)"},
7399{"e_srwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7400{"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"},
7401{"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"},
7402{"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
252b5132
RH		 7403};
7404
7405const int powerpc_num_macros =
7406 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
GDB Binutils - Deliverables
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