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Fix PR18360 - internal error when using "interrupt -a"
[deliverable/binutils-gdb.git] / opcodes / ppc-opc.c
CommitLineData
252b5132 1/* ppc-opc.c -- PowerPC opcode list
2571583a 2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
252b5132
RH		 3 Written by Ian Lance Taylor, Cygnus Support
4
9b201bb5 5 This file is part of the GNU opcodes library.
252b5132 6
9b201bb5
NC		 7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
252b5132 11
9b201bb5
NC		 12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
252b5132 16
112290ab 17 You should have received a copy of the GNU General Public License
9b201bb5
NC		 18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
252b5132 21
0d8dfecf 22#include "sysdep.h"
df7b86aa 23#include <stdio.h>
252b5132
RH		 24#include "opcode/ppc.h"
25#include "opintl.h"
26
27/* This file holds the PowerPC opcode table. The opcode table
28 includes almost all of the extended instruction mnemonics. This
29 permits the disassembler to use them, and simplifies the assembler
30 logic, at the cost of increasing the table size. The table is
31 strictly constant data, so the compiler should be able to put it in
32 the .text section.
33
34 This file also holds the operand table. All knowledge about
35 inserting operands into instructions and vice-versa is kept in this
36 file. */
37\f
38/* Local insertion and extraction functions. */
39
b9c361e0
JL		 40static unsigned long insert_arx (unsigned long, long, ppc_cpu_t, const char **);
41static long extract_arx (unsigned long, ppc_cpu_t, int *);
42static unsigned long insert_ary (unsigned long, long, ppc_cpu_t, const char **);
43static long extract_ary (unsigned long, ppc_cpu_t, int *);
fa452fa6
PB		 44static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **);
45static long extract_bat (unsigned long, ppc_cpu_t, int *);
46static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **);
47static long extract_bba (unsigned long, ppc_cpu_t, int *);
48static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **);
49static long extract_bdm (unsigned long, ppc_cpu_t, int *);
50static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **);
51static long extract_bdp (unsigned long, ppc_cpu_t, int *);
52static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **);
53static long extract_bo (unsigned long, ppc_cpu_t, int *);
54static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **);
55static long extract_boe (unsigned long, ppc_cpu_t, int *);
7b934113 56static unsigned long insert_esync (unsigned long, long, ppc_cpu_t, const char **);
73f07bff 57static long extract_esync (unsigned long, ppc_cpu_t, int *);
a680de9a
PB		 58static unsigned long insert_dcmxs (unsigned long, long, ppc_cpu_t, const char **);
59static long extract_dcmxs (unsigned long, ppc_cpu_t, int *);
60static unsigned long insert_dxd (unsigned long, long, ppc_cpu_t, const char **);
61static long extract_dxd (unsigned long, ppc_cpu_t, int *);
62static unsigned long insert_dxdn (unsigned long, long, ppc_cpu_t, const char **);
63static long extract_dxdn (unsigned long, ppc_cpu_t, int *);
fa452fa6
PB		 64static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
65static long extract_fxm (unsigned long, ppc_cpu_t, int *);
b9c361e0
JL		 66static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **);
67static long extract_li20 (unsigned long, ppc_cpu_t, int *);
aea77599 68static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **);
73f07bff 69static long extract_ls (unsigned long, ppc_cpu_t, int *);
fa452fa6
PB		 70static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **);
71static long extract_mbe (unsigned long, ppc_cpu_t, int *);
72static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **);
73static long extract_mb6 (unsigned long, ppc_cpu_t, int *);
74static long extract_nb (unsigned long, ppc_cpu_t, int *);
989993d8 75static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t, const char **);
fa452fa6
PB		 76static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **);
77static long extract_nsi (unsigned long, ppc_cpu_t, int *);
b9c361e0
JL		 78static unsigned long insert_oimm (unsigned long, long, ppc_cpu_t, const char **);
79static long extract_oimm (unsigned long, ppc_cpu_t, int *);
fa452fa6 80static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **);
73f07bff 81static long extract_ral (unsigned long, ppc_cpu_t, int *);
fa452fa6 82static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **);
73f07bff 83static long extract_ram (unsigned long, ppc_cpu_t, int *);
fa452fa6 84static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **);
73f07bff 85static long extract_raq (unsigned long, ppc_cpu_t, int *);
fa452fa6 86static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **);
73f07bff 87static long extract_ras (unsigned long, ppc_cpu_t, int *);
fa452fa6
PB		 88static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **);
89static long extract_rbs (unsigned long, ppc_cpu_t, int *);
989993d8 90static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t, const char **);
73f07bff 91static long extract_rbx (unsigned long, ppc_cpu_t, int *);
b9c361e0
JL		 92static unsigned long insert_rx (unsigned long, long, ppc_cpu_t, const char **);
93static long extract_rx (unsigned long, ppc_cpu_t, int *);
94static unsigned long insert_ry (unsigned long, long, ppc_cpu_t, const char **);
95static long extract_ry (unsigned long, ppc_cpu_t, int *);
fa452fa6
PB		 96static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **);
97static long extract_sh6 (unsigned long, ppc_cpu_t, int *);
b9c361e0
JL		 98static unsigned long insert_sci8 (unsigned long, long, ppc_cpu_t, const char **);
99static long extract_sci8 (unsigned long, ppc_cpu_t, int *);
100static unsigned long insert_sci8n (unsigned long, long, ppc_cpu_t, const char **);
101static long extract_sci8n (unsigned long, ppc_cpu_t, int *);
102static unsigned long insert_sd4h (unsigned long, long, ppc_cpu_t, const char **);
103static long extract_sd4h (unsigned long, ppc_cpu_t, int *);
104static unsigned long insert_sd4w (unsigned long, long, ppc_cpu_t, const char **);
105static long extract_sd4w (unsigned long, ppc_cpu_t, int *);
fa452fa6
PB		 106static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **);
107static long extract_spr (unsigned long, ppc_cpu_t, int *);
108static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **);
109static long extract_sprg (unsigned long, ppc_cpu_t, int *);
110static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **);
111static long extract_tbr (unsigned long, ppc_cpu_t, int *);
9b4e5766
PB		 112static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **);
113static long extract_xt6 (unsigned long, ppc_cpu_t, int *);
a680de9a
PB		 114static unsigned long insert_xtq6 (unsigned long, long, ppc_cpu_t, const char **);
115static long extract_xtq6 (unsigned long, ppc_cpu_t, int *);
9b4e5766
PB		 116static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **);
117static long extract_xa6 (unsigned long, ppc_cpu_t, int *);
118static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **);
119static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
120static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
121static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
066be9f7
PB		 122static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **);
123static long extract_xc6 (unsigned long, ppc_cpu_t, int *);
124static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **);
125static long extract_dm (unsigned long, ppc_cpu_t, int *);
b9c361e0
JL		 126static unsigned long insert_vlesi (unsigned long, long, ppc_cpu_t, const char **);
127static long extract_vlesi (unsigned long, ppc_cpu_t, int *);
128static unsigned long insert_vlensi (unsigned long, long, ppc_cpu_t, const char **);
129static long extract_vlensi (unsigned long, ppc_cpu_t, int *);
130static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t, const char **);
131static long extract_vleui (unsigned long, ppc_cpu_t, int *);
132static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t, const char **);
133static long extract_vleil (unsigned long, ppc_cpu_t, int *);
252b5132
RH		 134\f
135/* The operands table.
136
717bbdf1 137 The fields are bitm, shift, insert, extract, flags.
252b5132
RH		 138
139 We used to put parens around the various additions, like the one
140 for BA just below. However, that caused trouble with feeble
141 compilers with a limit on depth of a parenthesized expression, like
142 (reportedly) the compiler in Microsoft Developer Studio 5. So we
143 omit the parens, since the macros are never used in a context where
144 the addition will be ambiguous. */
145
146const struct powerpc_operand powerpc_operands[] =
147{
148 /* The zero index is used to indicate the end of the list of
149 operands. */
150#define UNUSED 0
bbac1f2a 151 { 0, 0, NULL, NULL, 0 },
252b5132
RH		 152
153 /* The BA field in an XL form instruction. */
154#define BA UNUSED + 1
717bbdf1
AM		 155 /* The BI field in a B form or XL form instruction. */
156#define BI BA
157#define BI_MASK (0x1f << 16)
b9c361e0 158 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
252b5132
RH		 159
160 /* The BA field in an XL form instruction when it must be the same
161 as the BT field in the same instruction. */
162#define BAT BA + 1
b84bf58a 163 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
252b5132
RH		 164
165 /* The BB field in an XL form instruction. */
166#define BB BAT + 1
167#define BB_MASK (0x1f << 11)
b9c361e0 168 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT },
252b5132
RH		 169
170 /* The BB field in an XL form instruction when it must be the same
171 as the BA field in the same instruction. */
172#define BBA BB + 1
c7a5aa9c
PB		 173 /* The VB field in a VX form instruction when it must be the same
174 as the VA field in the same instruction. */
175#define VBA BBA
b84bf58a 176 { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
252b5132
RH		 177
178 /* The BD field in a B form instruction. The lower two bits are
179 forced to zero. */
180#define BD BBA + 1
b84bf58a 181 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 182
183 /* The BD field in a B form instruction when absolute addressing is
184 used. */
185#define BDA BD + 1
b84bf58a 186 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 187
188 /* The BD field in a B form instruction when the - modifier is used.
189 This sets the y bit of the BO field appropriately. */
190#define BDM BDA + 1
b84bf58a 191 { 0xfffc, 0, insert_bdm, extract_bdm,
e43de63c 192 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 193
194 /* The BD field in a B form instruction when the - modifier is used
195 and absolute address is used. */
196#define BDMA BDM + 1
b84bf58a 197 { 0xfffc, 0, insert_bdm, extract_bdm,
e43de63c 198 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 199
200 /* The BD field in a B form instruction when the + modifier is used.
201 This sets the y bit of the BO field appropriately. */
202#define BDP BDMA + 1
b84bf58a 203 { 0xfffc, 0, insert_bdp, extract_bdp,
e43de63c 204 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 205
206 /* The BD field in a B form instruction when the + modifier is used
207 and absolute addressing is used. */
208#define BDPA BDP + 1
b84bf58a 209 { 0xfffc, 0, insert_bdp, extract_bdp,
e43de63c 210 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 211
212 /* The BF field in an X or XL form instruction. */
213#define BF BDPA + 1
717bbdf1
AM		 214 /* The CRFD field in an X form instruction. */
215#define CRFD BF
b9c361e0
JL		 216 /* The CRD field in an XL form instruction. */
217#define CRD BF
218 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG },
252b5132 219
ea192fa3
PB		 220 /* The BF field in an X or XL form instruction. */
221#define BFF BF + 1
222 { 0x7, 23, NULL, NULL, 0 },
223
252b5132
RH		 224 /* An optional BF field. This is used for comparison instructions,
225 in which an omitted BF field is taken as zero. */
ea192fa3 226#define OBF BFF + 1
b9c361e0 227 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
252b5132
RH		 228
229 /* The BFA field in an X or XL form instruction. */
230#define BFA OBF + 1
b9c361e0 231 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG },
252b5132 232
252b5132
RH		 233 /* The BO field in a B form instruction. Certain values are
234 illegal. */
717bbdf1 235#define BO BFA + 1
252b5132 236#define BO_MASK (0x1f << 21)
b84bf58a 237 { 0x1f, 21, insert_bo, extract_bo, 0 },
252b5132
RH		 238
239 /* The BO field in a B form instruction when the + or - modifier is
240 used. This is like the BO field, but it must be even. */
241#define BOE BO + 1
b84bf58a 242 { 0x1e, 21, insert_boe, extract_boe, 0 },
252b5132 243
6fd3a02d
PB		 244 /* The RM field in an X form instruction. */
245#define RM BOE + 1
246 { 0x3, 11, NULL, NULL, 0 },
247
248#define BH RM + 1
b84bf58a 249 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
d0618d1c 250
252b5132 251 /* The BT field in an X or XL form instruction. */
d0618d1c 252#define BT BH + 1
b9c361e0
JL		 253 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT },
254
255 /* The BI16 field in a BD8 form instruction. */
256#define BI16 BT + 1
257 { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT },
258
259 /* The BI32 field in a BD15 form instruction. */
260#define BI32 BI16 + 1
261 { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
262
263 /* The BO32 field in a BD15 form instruction. */
264#define BO32 BI32 + 1
265 { 0x3, 20, NULL, NULL, 0 },
266
267 /* The B8 field in a BD8 form instruction. */
268#define B8 BO32 + 1
269 { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
270
271 /* The B15 field in a BD15 form instruction. The lowest bit is
272 forced to zero. */
273#define B15 B8 + 1
274 { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
275
276 /* The B24 field in a BD24 form instruction. The lowest bit is
277 forced to zero. */
278#define B24 B15 + 1
279 { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 280
281 /* The condition register number portion of the BI field in a B form
282 or XL form instruction. This is used for the extended
283 conditional branch mnemonics, which set the lower two bits of the
284 BI field. This field is optional. */
b9c361e0
JL		 285#define CR B24 + 1
286 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
252b5132 287
23976049
EZ		 288 /* The CRB field in an X form instruction. */
289#define CRB CR + 1
717bbdf1
AM		 290 /* The MB field in an M form instruction. */
291#define MB CRB
292#define MB_MASK (0x1f << 6)
b84bf58a 293 { 0x1f, 6, NULL, NULL, 0 },
23976049 294
b9c361e0
JL		 295 /* The CRD32 field in an XL form instruction. */
296#define CRD32 CRB + 1
297 { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG },
298
23976049 299 /* The CRFS field in an X form instruction. */
b9c361e0
JL		 300#define CRFS CRD32 + 1
301 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG },
302
303#define CRS CRFS + 1
304 { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
23976049 305
418c1742 306 /* The CT field in an X form instruction. */
b9c361e0 307#define CT CRS + 1
717bbdf1
AM		 308 /* The MO field in an mbar instruction. */
309#define MO CT
b84bf58a 310 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
418c1742 311
252b5132
RH		 312 /* The D field in a D form instruction. This is a displacement off
313 a register, and implies that the next operand is a register in
314 parentheses. */
418c1742 315#define D CT + 1
b84bf58a 316 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
252b5132 317
b9c361e0
JL		 318 /* The D8 field in a D form instruction. This is a displacement off
319 a register, and implies that the next operand is a register in
320 parentheses. */
321#define D8 D + 1
322 { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
323
a680de9a
PB		 324 /* The DCMX field in an X form instruction. */
325#define DCMX D8 + 1
326 { 0x7f, 16, NULL, NULL, 0 },
327
328 /* The split DCMX field in an X form instruction. */
329#define DCMXS DCMX + 1
330 { 0x7f, PPC_OPSHIFT_INV, insert_dcmxs, extract_dcmxs, 0 },
331
adadcc0c
AM		 332 /* The DQ field in a DQ form instruction. This is like D, but the
333 lower four bits are forced to zero. */
a680de9a 334#define DQ DCMXS + 1
b84bf58a
AM		 335 { 0xfff0, 0, NULL, NULL,
336 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
adadcc0c 337
252b5132
RH		 338 /* The DS field in a DS form instruction. This is like D, but the
339 lower two bits are forced to zero. */
adadcc0c 340#define DS DQ + 1
b84bf58a
AM		 341 { 0xfffc, 0, NULL, NULL,
342 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
252b5132 343
c0637f3a
PB		 344 /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits
345 unsigned imediate */
19a6653c 346#define DUIS DS + 1
c0637f3a 347#define BHRBE DUIS
19a6653c
AM		 348 { 0x3ff, 11, NULL, NULL, 0 },
349
a680de9a
PB		 350 /* The split D field in a DX form instruction. */
351#define DXD DUIS + 1
352 { 0xffff, PPC_OPSHIFT_INV, insert_dxd, extract_dxd,
353 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
354
355 /* The split ND field in a DX form instruction.
356 This is the same as the DX field, only negated. */
357#define NDXD DXD + 1
358 { 0xffff, PPC_OPSHIFT_INV, insert_dxdn, extract_dxdn,
359 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
360
252b5132 361 /* The E field in a wrteei instruction. */
c3d65c1c 362 /* And the W bit in the pair singles instructions. */
c0637f3a 363 /* And the ST field in a VX form instruction. */
a680de9a 364#define E NDXD + 1
c3d65c1c 365#define PSW E
c0637f3a 366#define ST E
b84bf58a 367 { 0x1, 15, NULL, NULL, 0 },
252b5132
RH		 368
369 /* The FL1 field in a POWER SC form instruction. */
370#define FL1 E + 1
717bbdf1
AM		 371 /* The U field in an X form instruction. */
372#define U FL1
b84bf58a 373 { 0xf, 12, NULL, NULL, 0 },
252b5132
RH		 374
375 /* The FL2 field in a POWER SC form instruction. */
376#define FL2 FL1 + 1
b84bf58a 377 { 0x7, 2, NULL, NULL, 0 },
252b5132
RH		 378
379 /* The FLM field in an XFL form instruction. */
380#define FLM FL2 + 1
b84bf58a 381 { 0xff, 17, NULL, NULL, 0 },
252b5132
RH		 382
383 /* The FRA field in an X or A form instruction. */
384#define FRA FLM + 1
385#define FRA_MASK (0x1f << 16)
b84bf58a 386 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
252b5132 387
989993d8
JB		 388 /* The FRAp field of DFP instructions. */
389#define FRAp FRA + 1
390 { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR },
391
252b5132 392 /* The FRB field in an X or A form instruction. */
989993d8 393#define FRB FRAp + 1
252b5132 394#define FRB_MASK (0x1f << 11)
b84bf58a 395 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
252b5132 396
989993d8
JB		 397 /* The FRBp field of DFP instructions. */
398#define FRBp FRB + 1
399 { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR },
400
252b5132 401 /* The FRC field in an A form instruction. */
989993d8 402#define FRC FRBp + 1
252b5132 403#define FRC_MASK (0x1f << 6)
b84bf58a 404 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 405
406 /* The FRS field in an X form instruction or the FRT field in a D, X
407 or A form instruction. */
408#define FRS FRC + 1
409#define FRT FRS
b84bf58a 410 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
252b5132 411
989993d8
JB		 412 /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
413 instructions. */
414#define FRSp FRS + 1
415#define FRTp FRSp
416 { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR },
417
252b5132 418 /* The FXM field in an XFX instruction. */
989993d8 419#define FXM FRSp + 1
b84bf58a 420 { 0xff, 12, insert_fxm, extract_fxm, 0 },
c168870a
AM		 421
422 /* Power4 version for mfcr. */
423#define FXM4 FXM + 1
e43de63c
AM		 424 { 0xff, 12, insert_fxm, extract_fxm,
425 PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
11a0cf2e
PB		 426 /* If the FXM4 operand is ommitted, use the sentinel value -1. */
427 { -1, -1, NULL, NULL, 0},
252b5132 428
b9c361e0 429 /* The IMM20 field in an LI instruction. */
11a0cf2e 430#define IMM20 FXM4 + 2
b9c361e0
JL		 431 { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED},
432
252b5132 433 /* The L field in a D or X form instruction. */
b9c361e0 434#define L IMM20 + 1
a5721ba2
AM		 435 { 0x1, 21, NULL, NULL, 0 },
436
437 /* The optional L field in tlbie and tlbiel instructions. */
438#define LOPT L + 1
5817ffd1 439 /* The R field in a HTM X form instruction. */
a5721ba2 440#define HTM_R LOPT
b84bf58a 441 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
252b5132 442
a5721ba2
AM		 443 /* The optional (for 32-bit) L field in cmp[l][i] instructions. */
444#define L32OPT LOPT + 1
445 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL32 },
a680de9a 446
a5721ba2
AM		 447 /* The L field in dcbf instruction. */
448#define L2OPT L32OPT + 1
449 { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
a680de9a 450
dce75bf9 451 /* The LEV field in a POWER SVC / POWER9 SCV form instruction. */
a5721ba2 452#define SVC_LEV L2OPT + 1
b84bf58a 453 { 0x7f, 5, NULL, NULL, 0 },
252b5132 454
1ed8e1e4
AM		 455 /* The LEV field in an SC form instruction. */
456#define LEV SVC_LEV + 1
b84bf58a 457 { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
1ed8e1e4 458
252b5132
RH		 459 /* The LI field in an I form instruction. The lower two bits are
460 forced to zero. */
461#define LI LEV + 1
b84bf58a 462 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 463
464 /* The LI field in an I form instruction when used as an absolute
465 address. */
466#define LIA LI + 1
b84bf58a 467 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132 468
066be9f7 469 /* The LS or WC field in an X (sync or wait) form instruction. */
6ba045b1 470#define LS LIA + 1
066be9f7 471#define WC LS
73f07bff 472 { 0x3, 21, insert_ls, extract_ls, PPC_OPERAND_OPTIONAL },
6ba045b1 473
252b5132 474 /* The ME field in an M form instruction. */
717bbdf1 475#define ME LS + 1
252b5132 476#define ME_MASK (0x1f << 1)
b84bf58a 477 { 0x1f, 1, NULL, NULL, 0 },
252b5132
RH		 478
479 /* The MB and ME fields in an M form instruction expressed a single
480 operand which is a bitmask indicating which bits to select. This
481 is a two operand form using PPC_OPERAND_NEXT. See the
482 description in opcode/ppc.h for what this means. */
483#define MBE ME + 1
b84bf58a 484 { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
eb42fac1 485 { -1, 0, insert_mbe, extract_mbe, 0 },
252b5132
RH		 486
487 /* The MB or ME field in an MD or MDS form instruction. The high
488 bit is wrapped to the low end. */
489#define MB6 MBE + 2
490#define ME6 MB6
491#define MB6_MASK (0x3f << 5)
b84bf58a 492 { 0x3f, 5, insert_mb6, extract_mb6, 0 },
252b5132
RH		 493
494 /* The NB field in an X form instruction. The value 32 is stored as
495 0. */
717bbdf1 496#define NB MB6 + 1
b84bf58a 497 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
252b5132 498
989993d8
JB		 499 /* The NBI field in an lswi instruction, which has special value
500 restrictions. The value 32 is stored as 0. */
501#define NBI NB + 1
502 { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 },
503
252b5132
RH		 504 /* The NSI field in a D form instruction. This is the same as the
505 SI field, only negated. */
989993d8 506#define NSI NBI + 1
b84bf58a 507 { 0xffff, 0, insert_nsi, extract_nsi,
e43de63c
AM		 508 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
509
510 /* The NSI field in a D form instruction when we accept a wide range
511 of positive values. */
512#define NSISIGNOPT NSI + 1
514e58b7 513 { 0xffff, 0, insert_nsi, extract_nsi,
e43de63c 514 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
252b5132 515
adadcc0c 516 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
e43de63c 517#define RA NSISIGNOPT + 1
252b5132 518#define RA_MASK (0x1f << 16)
b84bf58a 519 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
252b5132 520
fdd12ef3
AM		 521 /* As above, but 0 in the RA field means zero, not r0. */
522#define RA0 RA + 1
b84bf58a 523 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
fdd12ef3 524
989993d8 525 /* The RA field in the DQ form lq or an lswx instruction, which have special
adadcc0c 526 value restrictions. */
fdd12ef3 527#define RAQ RA0 + 1
989993d8 528#define RAX RAQ
73f07bff 529 { 0x1f, 16, insert_raq, extract_raq, PPC_OPERAND_GPR_0 },
adadcc0c 530
252b5132
RH		 531 /* The RA field in a D or X form instruction which is an updating
532 load, which means that the RA field may not be zero and may not
533 equal the RT field. */
adadcc0c 534#define RAL RAQ + 1
73f07bff 535 { 0x1f, 16, insert_ral, extract_ral, PPC_OPERAND_GPR_0 },
252b5132
RH		 536
537 /* The RA field in an lmw instruction, which has special value
538 restrictions. */
539#define RAM RAL + 1
73f07bff 540 { 0x1f, 16, insert_ram, extract_ram, PPC_OPERAND_GPR_0 },
252b5132
RH		 541
542 /* The RA field in a D or X form instruction which is an updating
543 store or an updating floating point load, which means that the RA
544 field may not be zero. */
545#define RAS RAM + 1
73f07bff 546 { 0x1f, 16, insert_ras, extract_ras, PPC_OPERAND_GPR_0 },
252b5132 547
cee62821
PB		 548 /* The RA field of the tlbwe, dccci and iccci instructions,
549 which are optional. */
fdd12ef3 550#define RAOPT RAS + 1
b84bf58a 551 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
1f6c9eb0 552
252b5132 553 /* The RB field in an X, XO, M, or MDS form instruction. */
fdd12ef3 554#define RB RAOPT + 1
252b5132 555#define RB_MASK (0x1f << 11)
b84bf58a 556 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
252b5132
RH		 557
558 /* The RB field in an X form instruction when it must be the same as
559 the RS field in the instruction. This is used for extended
560 mnemonics like mr. */
561#define RBS RB + 1
b84bf58a 562 { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
252b5132 563
989993d8
JB		 564 /* The RB field in an lswx instruction, which has special value
565 restrictions. */
566#define RBX RBS + 1
73f07bff 567 { 0x1f, 11, insert_rbx, extract_rbx, PPC_OPERAND_GPR },
989993d8 568
cee62821 569 /* The RB field of the dccci and iccci instructions, which are optional. */
989993d8 570#define RBOPT RBX + 1
cee62821
PB		 571 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
572
a680de9a
PB		 573 /* The RC register field in an maddld, maddhd or maddhdu instruction. */
574#define RC RBOPT + 1
575 { 0x1f, 6, NULL, NULL, PPC_OPERAND_GPR },
576
252b5132
RH		 577 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
578 instruction or the RT field in a D, DS, X, XFX or XO form
579 instruction. */
a680de9a 580#define RS RC + 1
252b5132
RH		 581#define RT RS
582#define RT_MASK (0x1f << 21)
b9c361e0 583#define RD RS
b84bf58a 584 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
252b5132 585
588925d0
PB		 586 /* The RS and RT fields of the DS form stq and DQ form lq instructions,
587 which have special value restrictions. */
adadcc0c 588#define RSQ RS + 1
717bbdf1 589#define RTQ RSQ
73f07bff 590#define Q_MASK (1 << 21)
588925d0 591 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR },
adadcc0c 592
1f6c9eb0 593 /* The RS field of the tlbwe instruction, which is optional. */
717bbdf1 594#define RSO RSQ + 1
eed0d89a 595#define RTO RSO
b84bf58a 596 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
1f6c9eb0 597
b9c361e0
JL		 598 /* The RX field of the SE_RR form instruction. */
599#define RX RSO + 1
600 { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR },
601
602 /* The ARX field of the SE_RR form instruction. */
603#define ARX RX + 1
604 { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR },
605
606 /* The RY field of the SE_RR form instruction. */
607#define RY ARX + 1
608#define RZ RY
609 { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR },
610
611 /* The ARY field of the SE_RR form instruction. */
612#define ARY RY + 1
613 { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR },
614
615 /* The SCLSCI8 field in a D form instruction. */
616#define SCLSCI8 ARY + 1
617 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 },
618
619 /* The SCLSCI8N field in a D form instruction. This is the same as the
620 SCLSCI8 field, only negated. */
621#define SCLSCI8N SCLSCI8 + 1
622 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n,
e43de63c 623 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
b9c361e0
JL		 624
625 /* The SD field of the SD4 form instruction. */
626#define SE_SD SCLSCI8N + 1
627 { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS },
628
629 /* The SD field of the SD4 form instruction, for halfword. */
630#define SE_SDH SE_SD + 1
631 { 0x1e, PPC_OPSHIFT_INV, insert_sd4h, extract_sd4h, PPC_OPERAND_PARENS },
632
633 /* The SD field of the SD4 form instruction, for word. */
634#define SE_SDW SE_SDH + 1
635 { 0x3c, PPC_OPSHIFT_INV, insert_sd4w, extract_sd4w, PPC_OPERAND_PARENS },
636
252b5132 637 /* The SH field in an X or M form instruction. */
b9c361e0 638#define SH SE_SDW + 1
252b5132 639#define SH_MASK (0x1f << 11)
717bbdf1
AM		 640 /* The other UIMM field in a EVX form instruction. */
641#define EVUIMM SH
a680de9a
PB		 642 /* The FC field in an atomic X form instruction. */
643#define FC SH
b84bf58a 644 { 0x1f, 11, NULL, NULL, 0 },
252b5132 645
5817ffd1
PB		 646 /* The SI field in a HTM X form instruction. */
647#define HTM_SI SH + 1
648 { 0x1f, 11, NULL, NULL, PPC_OPERAND_SIGNED },
649
252b5132 650 /* The SH field in an MD form instruction. This is split. */
5817ffd1 651#define SH6 HTM_SI + 1
252b5132 652#define SH6_MASK ((0x1f << 11) | (1 << 1))
b9c361e0 653 { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 },
252b5132 654
1f6c9eb0
ZW		 655 /* The SH field of the tlbwe instruction, which is optional. */
656#define SHO SH6 + 1
b84bf58a 657 { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
1f6c9eb0 658
252b5132 659 /* The SI field in a D form instruction. */
1f6c9eb0 660#define SI SHO + 1
b84bf58a 661 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
252b5132
RH		 662
663 /* The SI field in a D form instruction when we accept a wide range
664 of positive values. */
665#define SISIGNOPT SI + 1
b84bf58a 666 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
252b5132 667
b9c361e0
JL		 668 /* The SI8 field in a D form instruction. */
669#define SI8 SISIGNOPT + 1
670 { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
671
252b5132
RH		 672 /* The SPR field in an XFX form instruction. This is flipped--the
673 lower 5 bits are stored in the upper 5 and vice- versa. */
b9c361e0 674#define SPR SI8 + 1
914749f6 675#define PMR SPR
aea77599 676#define TMR SPR
252b5132 677#define SPR_MASK (0x3ff << 11)
7e0de605 678 { 0x3ff, 11, insert_spr, extract_spr, PPC_OPERAND_SPR },
252b5132
RH		 679
680 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
681#define SPRBAT SPR + 1
682#define SPRBAT_MASK (0x3 << 17)
b84bf58a 683 { 0x3, 17, NULL, NULL, 0 },
252b5132
RH		 684
685 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
686#define SPRG SPRBAT + 1
7e0de605 687 { 0x1f, 16, insert_sprg, extract_sprg, PPC_OPERAND_SPR },
252b5132
RH		 688
689 /* The SR field in an X form instruction. */
690#define SR SPRG + 1
fb048c26
PB		 691 /* The 4-bit UIMM field in a VX form instruction. */
692#define UIMM4 SR
b84bf58a 693 { 0xf, 16, NULL, NULL, 0 },
252b5132 694
f5c120c5
MG		 695 /* The STRM field in an X AltiVec form instruction. */
696#define STRM SR + 1
19a6653c
AM		 697 /* The T field in a tlbilx form instruction. */
698#define T STRM
a5721ba2
AM		 699 /* The L field in wclr instructions. */
700#define L2 STRM
b84bf58a 701 { 0x3, 21, NULL, NULL, 0 },
f5c120c5 702
aea77599
AM		 703 /* The ESYNC field in an X (sync) form instruction. */
704#define ESYNC STRM + 1
73f07bff 705 { 0xf, 16, insert_esync, extract_esync, PPC_OPERAND_OPTIONAL },
aea77599 706
252b5132 707 /* The SV field in a POWER SC form instruction. */
aea77599 708#define SV ESYNC + 1
b84bf58a 709 { 0x3fff, 2, NULL, NULL, 0 },
252b5132
RH		 710
711 /* The TBR field in an XFX form instruction. This is like the SPR
712 field, but it is optional. */
713#define TBR SV + 1
e43de63c 714 { 0x3ff, 11, insert_tbr, extract_tbr,
7e0de605 715 PPC_OPERAND_SPR | PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
11a0cf2e
PB		 716 /* If the TBR operand is ommitted, use the value 268. */
717 { -1, 268, NULL, NULL, 0},
252b5132
RH		 718
719 /* The TO field in a D or X form instruction. */
11a0cf2e 720#define TO TBR + 2
19a6653c 721#define DUI TO
252b5132 722#define TO_MASK (0x1f << 21)
b84bf58a 723 { 0x1f, 21, NULL, NULL, 0 },
252b5132 724
252b5132 725 /* The UI field in a D form instruction. */
717bbdf1 726#define UI TO + 1
b84bf58a 727 { 0xffff, 0, NULL, NULL, 0 },
786e2c0f 728
a47622ac
AM		 729#define UISIGNOPT UI + 1
730 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNOPT },
731
b9c361e0 732 /* The IMM field in an SE_IM5 instruction. */
a47622ac 733#define UI5 UISIGNOPT + 1
b9c361e0
JL		 734 { 0x1f, 4, NULL, NULL, 0 },
735
736 /* The OIMM field in an SE_OIM5 instruction. */
737#define OIMM5 UI5 + 1
738 { 0x1f, PPC_OPSHIFT_INV, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 },
739
740 /* The UI7 field in an SE_LI instruction. */
741#define UI7 OIMM5 + 1
742 { 0x7f, 4, NULL, NULL, 0 },
743
112290ab 744 /* The VA field in a VA, VX or VXR form instruction. */
b9c361e0 745#define VA UI7 + 1
b84bf58a 746 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 747
112290ab 748 /* The VB field in a VA, VX or VXR form instruction. */
786e2c0f 749#define VB VA + 1
b84bf58a 750 { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 751
112290ab 752 /* The VC field in a VA form instruction. */
786e2c0f 753#define VC VB + 1
b84bf58a 754 { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 755
112290ab 756 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
786e2c0f
C		 757#define VD VC + 1
758#define VS VD
b84bf58a 759 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 760
8dbcd839 761 /* The SIMM field in a VX form instruction, and TE in Z form. */
786e2c0f 762#define SIMM VD + 1
8dbcd839 763#define TE SIMM
b84bf58a 764 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
786e2c0f 765
8dbcd839 766 /* The UIMM field in a VX form instruction. */
786e2c0f 767#define UIMM SIMM + 1
aea77599 768#define DCTL UIMM
b84bf58a 769 { 0x1f, 16, NULL, NULL, 0 },
786e2c0f 770
fb048c26
PB		 771 /* The 3-bit UIMM field in a VX form instruction. */
772#define UIMM3 UIMM + 1
773 { 0x7, 16, NULL, NULL, 0 },
774
a680de9a
PB		 775 /* The 6-bit UIM field in a X form instruction. */
776#define UIM6 UIMM3 + 1
777 { 0x3f, 16, NULL, NULL, 0 },
778
c0637f3a 779 /* The SIX field in a VX form instruction. */
a680de9a 780#define SIX UIM6 + 1
c0637f3a
PB		 781 { 0xf, 11, NULL, NULL, 0 },
782
783 /* The PS field in a VX form instruction. */
784#define PS SIX + 1
785 { 0x1, 9, NULL, NULL, 0 },
786
112290ab 787 /* The SHB field in a VA form instruction. */
c0637f3a 788#define SHB PS + 1
b84bf58a 789 { 0xf, 6, NULL, NULL, 0 },
ff3a6ee3 790
112290ab 791 /* The other UIMM field in a half word EVX form instruction. */
717bbdf1 792#define EVUIMM_2 SHB + 1
b84bf58a 793 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
23976049 794
112290ab 795 /* The other UIMM field in a word EVX form instruction. */
23976049 796#define EVUIMM_4 EVUIMM_2 + 1
b84bf58a 797 { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
23976049 798
112290ab 799 /* The other UIMM field in a double EVX form instruction. */
23976049 800#define EVUIMM_8 EVUIMM_4 + 1
b84bf58a 801 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
23976049 802
6fd3a02d 803 /* The WS or DRM field in an X form instruction. */
23976049 804#define WS EVUIMM_8 + 1
6fd3a02d 805#define DRM WS
b84bf58a 806 { 0x7, 11, NULL, NULL, 0 },
ff3a6ee3 807
c3d65c1c
BE		 808 /* PowerPC paired singles extensions. */
809 /* W bit in the pair singles instructions for x type instructions. */
810#define PSWM WS + 1
b9c361e0
JL		 811 /* The BO16 field in a BD8 form instruction. */
812#define BO16 PSWM
c3d65c1c
BE		 813 { 0x1, 10, 0, 0, 0 },
814
815 /* IDX bits for quantization in the pair singles instructions. */
816#define PSQ PSWM + 1
7e0de605 817 { 0x7, 12, 0, 0, PPC_OPERAND_GQR },
c3d65c1c
BE		 818
819 /* IDX bits for quantization in the pair singles x-type instructions. */
820#define PSQM PSQ + 1
7e0de605 821 { 0x7, 7, 0, 0, PPC_OPERAND_GQR },
c3d65c1c
BE		 822
823 /* Smaller D field for quantization in the pair singles instructions. */
824#define PSD PSQM + 1
825 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
826
a680de9a 827 /* The L field in an mtmsrd or A form instruction or R or W in an X form. */
c3d65c1c 828#define A_L PSD + 1
ea192fa3 829#define W A_L
a680de9a 830#define X_R A_L
b84bf58a 831 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
5ae2e65e 832
19dfcc89 833 /* The RMC or CY field in a Z23 form instruction. */
99a2c561 834#define RMC A_L + 1
19dfcc89 835#define CY RMC
b84bf58a 836 { 0x3, 9, NULL, NULL, 0 },
702f0fb4
PB		 837
838#define R RMC + 1
b84bf58a 839 { 0x1, 16, NULL, NULL, 0 },
702f0fb4 840
a680de9a
PB		 841#define RIC R + 1
842 { 0x3, 18, NULL, NULL, PPC_OPERAND_OPTIONAL },
843
844#define PRS RIC + 1
845 { 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL },
846
847#define SP PRS + 1
b84bf58a 848 { 0x3, 19, NULL, NULL, 0 },
702f0fb4
PB		 849
850#define S SP + 1
b84bf58a 851 { 0x1, 20, NULL, NULL, 0 },
702f0fb4 852
c0637f3a
PB		 853 /* The S field in a XL form instruction. */
854#define SXL S + 1
11a0cf2e
PB		 855 { 0x1, 11, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
856 /* If the SXL operand is ommitted, use the value 1. */
857 { -1, 1, NULL, NULL, 0},
c0637f3a 858
702f0fb4 859 /* SH field starting at bit position 16. */
11a0cf2e 860#define SH16 SXL + 2
0bbdef92
AM		 861 /* The DCM and DGM fields in a Z form instruction. */
862#define DCM SH16
863#define DGM DCM
b84bf58a 864 { 0x3f, 10, NULL, NULL, 0 },
702f0fb4 865
702f0fb4 866 /* The EH field in larx instruction. */
717bbdf1 867#define EH SH16 + 1
b84bf58a 868 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
ea192fa3
PB		 869
870 /* The L field in an mtfsf or XFL form instruction. */
5817ffd1 871 /* The A field in a HTM X form instruction. */
ea192fa3 872#define XFL_L EH + 1
5817ffd1 873#define HTM_A XFL_L
ea192fa3 874 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
081ba1b3
AM		 875
876 /* Xilinx APU related masks and macros */
877#define FCRT XFL_L + 1
878#define FCRT_MASK (0x1f << 21)
879 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
880
43e65147 881 /* Xilinx FSL related masks and macros */
081ba1b3
AM		 882#define FSL FCRT + 1
883#define FSL_MASK (0x1f << 11)
43e65147 884 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
081ba1b3 885
43e65147 886 /* Xilinx UDI related masks and macros */
081ba1b3
AM		 887#define URT FSL + 1
888 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
889
890#define URA URT + 1
891 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
892
893#define URB URA + 1
894 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
895
896#define URC URB + 1
897 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
898
b9c361e0
JL		 899 /* The VLESIMM field in a D form instruction. */
900#define VLESIMM URC + 1
901 { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi,
e43de63c 902 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
b9c361e0
JL		 903
904 /* The VLENSIMM field in a D form instruction. */
905#define VLENSIMM VLESIMM + 1
906 { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi,
e43de63c 907 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
b9c361e0
JL		 908
909 /* The VLEUIMM field in a D form instruction. */
910#define VLEUIMM VLENSIMM + 1
911 { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 },
912
913 /* The VLEUIMML field in a D form instruction. */
914#define VLEUIMML VLEUIMM + 1
915 { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 },
916
9b4e5766 917 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
b9c361e0 918#define XS6 VLEUIMML + 1
9b4e5766 919#define XT6 XS6
b9c361e0 920 { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
9b4e5766 921
a680de9a
PB		 922 /* The XT and XS fields in an DQ form VSX instruction. This is split. */
923#define XSQ6 XT6 + 1
924#define XTQ6 XSQ6
925 { 0x3f, PPC_OPSHIFT_INV, insert_xtq6, extract_xtq6, PPC_OPERAND_VSR },
926
9b4e5766 927 /* The XA field in an XX3 form instruction. This is split. */
a680de9a 928#define XA6 XTQ6 + 1
b9c361e0 929 { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
9b4e5766 930
066be9f7 931 /* The XB field in an XX2 or XX3 form instruction. This is split. */
9b4e5766 932#define XB6 XA6 + 1
b9c361e0 933 { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
9b4e5766
PB		 934
935 /* The XB field in an XX3 form instruction when it must be the same as
936 the XA field in the instruction. This is used in extended mnemonics
937 like xvmovdp. This is split. */
938#define XB6S XB6 + 1
b9c361e0 939 { 0x3f, PPC_OPSHIFT_INV, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
9b4e5766 940
066be9f7
PB		 941 /* The XC field in an XX4 form instruction. This is split. */
942#define XC6 XB6S + 1
b9c361e0 943 { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
066be9f7
PB		 944
945 /* The DM or SHW field in an XX3 form instruction. */
946#define DM XC6 + 1
947#define SHW DM
9b4e5766 948 { 0x3, 8, NULL, NULL, 0 },
066be9f7
PB		 949
950 /* The DM field in an extended mnemonic XX3 form instruction. */
951#define DMEX DM + 1
952 { 0x3, 8, insert_dm, extract_dm, 0 },
953
954 /* The UIM field in an XX2 form instruction. */
955#define UIM DMEX + 1
fb048c26
PB		 956 /* The 2-bit UIMM field in a VX form instruction. */
957#define UIMM2 UIM
a680de9a
PB		 958 /* The 2-bit L field in a darn instruction. */
959#define LRAND UIM
066be9f7 960 { 0x3, 16, NULL, NULL, 0 },
e0d602ec
BE		 961
962#define ERAT_T UIM + 1
963 { 0x7, 21, NULL, NULL, 0 },
4bc0608a
PB		 964
965#define IH ERAT_T + 1
966 { 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
a680de9a
PB		 967
968 /* The 8-bit IMM8 field in a XX1 form instruction. */
969#define IMM8 IH + 1
1178da44 970 { 0xff, 11, NULL, NULL, PPC_OPERAND_SIGNOPT },
252b5132
RH		 971};
972
b84bf58a
AM		 973const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
974 / sizeof (powerpc_operands[0]));
975
252b5132
RH		 976/* The functions used to insert and extract complicated operands. */
977
b9c361e0
JL		 978/* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
979
980static unsigned long
981insert_arx (unsigned long insn,
982 long value,
983 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
984 const char **errmsg ATTRIBUTE_UNUSED)
985{
986 if (value >= 8 && value < 24)
987 return insn | ((value - 8) & 0xf);
988 else
989 {
990 *errmsg = _("invalid register");
991 return 0;
992 }
993}
994
995static long
996extract_arx (unsigned long insn,
997 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
998 int *invalid ATTRIBUTE_UNUSED)
43e65147 999{
b9c361e0
JL		 1000 return (insn & 0xf) + 8;
1001}
1002
1003static unsigned long
1004insert_ary (unsigned long insn,
1005 long value,
1006 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1007 const char **errmsg ATTRIBUTE_UNUSED)
1008{
1009 if (value >= 8 && value < 24)
1010 return insn | (((value - 8) & 0xf) << 4);
1011 else
1012 {
1013 *errmsg = _("invalid register");
1014 return 0;
1015 }
1016}
1017
1018static long
1019extract_ary (unsigned long insn,
1020 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1021 int *invalid ATTRIBUTE_UNUSED)
1022{
1023 return ((insn >> 4) & 0xf) + 8;
1024}
1025
1026static unsigned long
1027insert_rx (unsigned long insn,
1028 long value,
1029 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1030 const char **errmsg)
1031{
1032 if (value >= 0 && value < 8)
1033 return insn | value;
1034 else if (value >= 24 && value <= 31)
1035 return insn | (value - 16);
1036 else
1037 {
1038 *errmsg = _("invalid register");
1039 return 0;
1040 }
1041}
1042
1043static long
1044extract_rx (unsigned long insn,
1045 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1046 int *invalid ATTRIBUTE_UNUSED)
1047{
1048 int value = insn & 0xf;
1049 if (value >= 0 && value < 8)
1050 return value;
1051 else
1052 return value + 16;
1053}
1054
1055static unsigned long
1056insert_ry (unsigned long insn,
1057 long value,
1058 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1059 const char **errmsg)
1060{
1061 if (value >= 0 && value < 8)
1062 return insn | (value << 4);
1063 else if (value >= 24 && value <= 31)
1064 return insn | ((value - 16) << 4);
1065 else
1066 {
1067 *errmsg = _("invalid register");
1068 return 0;
1069 }
1070}
1071
1072static long
1073extract_ry (unsigned long insn,
1074 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1075 int *invalid ATTRIBUTE_UNUSED)
1076{
1077 int value = (insn >> 4) & 0xf;
1078 if (value >= 0 && value < 8)
1079 return value;
1080 else
1081 return value + 16;
1082}
1083
252b5132
RH		 1084/* The BA field in an XL form instruction when it must be the same as
1085 the BT field in the same instruction. This operand is marked FAKE.
1086 The insertion function just copies the BT field into the BA field,
1087 and the extraction function just checks that the fields are the
1088 same. */
1089
252b5132 1090static unsigned long
2fbfdc41
AM		 1091insert_bat (unsigned long insn,
1092 long value ATTRIBUTE_UNUSED,
fa452fa6 1093 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1094 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1095{
1096 return insn | (((insn >> 21) & 0x1f) << 16);
1097}
1098
1099static long
2fbfdc41 1100extract_bat (unsigned long insn,
fa452fa6 1101 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1102 int *invalid)
252b5132 1103{
8427c424 1104 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
252b5132
RH		 1105 *invalid = 1;
1106 return 0;
1107}
1108
1109/* The BB field in an XL form instruction when it must be the same as
1110 the BA field in the same instruction. This operand is marked FAKE.
1111 The insertion function just copies the BA field into the BB field,
1112 and the extraction function just checks that the fields are the
1113 same. */
1114
252b5132 1115static unsigned long
2fbfdc41
AM		 1116insert_bba (unsigned long insn,
1117 long value ATTRIBUTE_UNUSED,
fa452fa6 1118 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1119 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1120{
1121 return insn | (((insn >> 16) & 0x1f) << 11);
1122}
1123
1124static long
2fbfdc41 1125extract_bba (unsigned long insn,
fa452fa6 1126 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1127 int *invalid)
252b5132 1128{
8427c424 1129 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
252b5132
RH		 1130 *invalid = 1;
1131 return 0;
1132}
1133
252b5132
RH		 1134/* The BD field in a B form instruction when the - modifier is used.
1135 This modifier means that the branch is not expected to be taken.
94efba12
AM		 1136 For chips built to versions of the architecture prior to version 2
1137 (ie. not Power4 compatible), we set the y bit of the BO field to 1
1138 if the offset is negative. When extracting, we require that the y
1139 bit be 1 and that the offset be positive, since if the y bit is 0
1140 we just want to print the normal form of the instruction.
1141 Power4 compatible targets use two bits, "a", and "t", instead of
1142 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
1143 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
1144 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
ba4e851b
AM		 1145 for branch on CTR. We only handle the taken/not-taken hint here.
1146 Note that we don't relax the conditions tested here when
1147 disassembling with -Many because insns using extract_bdm and
1148 extract_bdp always occur in pairs. One or the other will always
1149 be valid. */
252b5132 1150
8ebac3aa
AM		 1151#define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
1152
252b5132 1153static unsigned long
2fbfdc41
AM		 1154insert_bdm (unsigned long insn,
1155 long value,
fa452fa6 1156 ppc_cpu_t dialect,
2fbfdc41 1157 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 1158{
8ebac3aa 1159 if ((dialect & ISA_V2) == 0)
802a735e
AM		 1160 {
1161 if ((value & 0x8000) != 0)
1162 insn |= 1 << 21;
1163 }
1164 else
1165 {
1166 if ((insn & (0x14 << 21)) == (0x04 << 21))
1167 insn |= 0x02 << 21;
1168 else if ((insn & (0x14 << 21)) == (0x10 << 21))
1169 insn |= 0x08 << 21;
1170 }
252b5132
RH		 1171 return insn | (value & 0xfffc);
1172}
1173
1174static long
2fbfdc41 1175extract_bdm (unsigned long insn,
fa452fa6 1176 ppc_cpu_t dialect,
2fbfdc41 1177 int *invalid)
252b5132 1178{
8ebac3aa 1179 if ((dialect & ISA_V2) == 0)
802a735e 1180 {
8427c424
AM		 1181 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
1182 *invalid = 1;
802a735e 1183 }
8427c424
AM		 1184 else
1185 {
1186 if ((insn & (0x17 << 21)) != (0x06 << 21)
1187 && (insn & (0x1d << 21)) != (0x18 << 21))
1188 *invalid = 1;
1189 }
1190
802a735e 1191 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 1192}
1193
1194/* The BD field in a B form instruction when the + modifier is used.
1195 This is like BDM, above, except that the branch is expected to be
1196 taken. */
1197
252b5132 1198static unsigned long
2fbfdc41
AM		 1199insert_bdp (unsigned long insn,
1200 long value,
fa452fa6 1201 ppc_cpu_t dialect,
2fbfdc41 1202 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 1203{
8ebac3aa 1204 if ((dialect & ISA_V2) == 0)
802a735e
AM		 1205 {
1206 if ((value & 0x8000) == 0)
1207 insn |= 1 << 21;
1208 }
1209 else
1210 {
1211 if ((insn & (0x14 << 21)) == (0x04 << 21))
1212 insn |= 0x03 << 21;
1213 else if ((insn & (0x14 << 21)) == (0x10 << 21))
1214 insn |= 0x09 << 21;
1215 }
252b5132
RH		 1216 return insn | (value & 0xfffc);
1217}
1218
1219static long
2fbfdc41 1220extract_bdp (unsigned long insn,
fa452fa6 1221 ppc_cpu_t dialect,
2fbfdc41 1222 int *invalid)
252b5132 1223{
8ebac3aa 1224 if ((dialect & ISA_V2) == 0)
802a735e 1225 {
8427c424
AM		 1226 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
1227 *invalid = 1;
1228 }
1229 else
1230 {
1231 if ((insn & (0x17 << 21)) != (0x07 << 21)
1232 && (insn & (0x1d << 21)) != (0x19 << 21))
1233 *invalid = 1;
802a735e 1234 }
8427c424 1235
802a735e 1236 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 1237}
1238
8ebac3aa
AM		 1239static inline int
1240valid_bo_pre_v2 (long value)
252b5132 1241{
8ebac3aa
AM		 1242 /* Certain encodings have bits that are required to be zero.
1243 These are (z must be zero, y may be anything):
43e65147
L		 1244 0000y
1245 0001y
8ebac3aa 1246 001zy
43e65147
L		 1247 0100y
1248 0101y
8ebac3aa
AM		 1249 011zy
1250 1z00y
1251 1z01y
1252 1z1zz
1253 */
1254 if ((value & 0x14) == 0)
1255 return 1;
1256 else if ((value & 0x14) == 0x4)
1257 return (value & 0x2) == 0;
1258 else if ((value & 0x14) == 0x10)
1259 return (value & 0x8) == 0;
1260 else
1261 return value == 0x14;
1262}
ba4e851b 1263
8ebac3aa
AM		 1264static inline int
1265valid_bo_post_v2 (long value)
1266{
ba4e851b
AM		 1267 /* Certain encodings have bits that are required to be zero.
1268 These are (z must be zero, a & t may be anything):
1269 0000z
1270 0001z
8ebac3aa 1271 001at
ba4e851b
AM		 1272 0100z
1273 0101z
ba4e851b
AM		 1274 011at
1275 1a00t
1276 1a01t
1277 1z1zz
1278 */
1279 if ((value & 0x14) == 0)
1280 return (value & 0x1) == 0;
1281 else if ((value & 0x14) == 0x14)
1282 return value == 0x14;
802a735e 1283 else
ba4e851b 1284 return 1;
252b5132
RH		 1285}
1286
8ebac3aa
AM		 1287/* Check for legal values of a BO field. */
1288
1289static int
1290valid_bo (long value, ppc_cpu_t dialect, int extract)
1291{
1292 int valid_y = valid_bo_pre_v2 (value);
1293 int valid_at = valid_bo_post_v2 (value);
1294
1295 /* When disassembling with -Many, accept either encoding on the
1296 second pass through opcodes. */
1297 if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY)
1298 return valid_y || valid_at;
1299 if ((dialect & ISA_V2) == 0)
1300 return valid_y;
1301 else
1302 return valid_at;
1303}
1304
252b5132
RH		 1305/* The BO field in a B form instruction. Warn about attempts to set
1306 the field to an illegal value. */
1307
1308static unsigned long
2fbfdc41
AM		 1309insert_bo (unsigned long insn,
1310 long value,
fa452fa6 1311 ppc_cpu_t dialect,
2fbfdc41 1312 const char **errmsg)
252b5132 1313{
ba4e851b 1314 if (!valid_bo (value, dialect, 0))
252b5132 1315 *errmsg = _("invalid conditional option");
989993d8
JB		 1316 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1317 *errmsg = _("invalid counter access");
252b5132
RH		 1318 return insn | ((value & 0x1f) << 21);
1319}
1320
1321static long
2fbfdc41 1322extract_bo (unsigned long insn,
fa452fa6 1323 ppc_cpu_t dialect,
2fbfdc41 1324 int *invalid)
252b5132
RH		 1325{
1326 long value;
1327
1328 value = (insn >> 21) & 0x1f;
ba4e851b 1329 if (!valid_bo (value, dialect, 1))
252b5132
RH		 1330 *invalid = 1;
1331 return value;
1332}
1333
1334/* The BO field in a B form instruction when the + or - modifier is
1335 used. This is like the BO field, but it must be even. When
1336 extracting it, we force it to be even. */
1337
1338static unsigned long
2fbfdc41
AM		 1339insert_boe (unsigned long insn,
1340 long value,
fa452fa6 1341 ppc_cpu_t dialect,
2fbfdc41 1342 const char **errmsg)
252b5132 1343{
ba4e851b 1344 if (!valid_bo (value, dialect, 0))
8427c424 1345 *errmsg = _("invalid conditional option");
989993d8
JB		 1346 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1347 *errmsg = _("invalid counter access");
8427c424
AM		 1348 else if ((value & 1) != 0)
1349 *errmsg = _("attempt to set y bit when using + or - modifier");
1350
252b5132
RH		 1351 return insn | ((value & 0x1f) << 21);
1352}
1353
1354static long
2fbfdc41 1355extract_boe (unsigned long insn,
fa452fa6 1356 ppc_cpu_t dialect,
2fbfdc41 1357 int *invalid)
252b5132
RH		 1358{
1359 long value;
1360
1361 value = (insn >> 21) & 0x1f;
ba4e851b 1362 if (!valid_bo (value, dialect, 1))
252b5132
RH		 1363 *invalid = 1;
1364 return value & 0x1e;
1365}
1366
a680de9a
PB		 1367/* The DCMX field in a X form instruction when the field is split
1368 into separate DC, DM and DX fields. */
1369
1370static unsigned long
1371insert_dcmxs (unsigned long insn,
1372 long value,
1373 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1374 const char **errmsg ATTRIBUTE_UNUSED)
1375{
1376 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3) | (value & 0x40);
1377}
1378
1379static long
1380extract_dcmxs (unsigned long insn,
1381 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1382 int *invalid ATTRIBUTE_UNUSED)
1383{
1384 return (insn & 0x40) | ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
1385}
1386
1387/* The D field in a DX form instruction when the field is split
1388 into separate D0, D1 and D2 fields. */
1389
1390static unsigned long
1391insert_dxd (unsigned long insn,
1392 long value,
1393 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1394 const char **errmsg ATTRIBUTE_UNUSED)
1395{
1396 return insn | (value & 0xffc1) | ((value & 0x3e) << 15);
1397}
1398
1399static long
1400extract_dxd (unsigned long insn,
1401 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1402 int *invalid ATTRIBUTE_UNUSED)
1403{
1404 unsigned long dxd = (insn & 0xffc1) | ((insn >> 15) & 0x3e);
1405 return (dxd ^ 0x8000) - 0x8000;
1406}
1407
1408static unsigned long
1409insert_dxdn (unsigned long insn,
1410 long value,
1411 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1412 const char **errmsg ATTRIBUTE_UNUSED)
1413{
1414 return insert_dxd (insn, -value, dialect, errmsg);
1415}
1416
1417static long
1418extract_dxdn (unsigned long insn,
1419 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1420 int *invalid ATTRIBUTE_UNUSED)
1421{
1422 return -extract_dxd (insn, dialect, invalid);
1423}
1424
2fbfdc41
AM		 1425/* FXM mask in mfcr and mtcrf instructions. */
1426
1427static unsigned long
1428insert_fxm (unsigned long insn,
1429 long value,
fa452fa6 1430 ppc_cpu_t dialect,
2fbfdc41 1431 const char **errmsg)
c168870a 1432{
98e69875
AM		 1433 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1434 one bit of the mask field is set. */
1435 if ((insn & (1 << 20)) != 0)
1436 {
1437 if (value == 0 || (value & -value) != value)
1438 {
1439 *errmsg = _("invalid mask field");
1440 value = 0;
1441 }
1442 }
1443
c168870a 1444 /* If only one bit of the FXM field is set, we can use the new form
661bd698 1445 of the instruction, which is faster. Unlike the Power4 branch hint
a30e9cc4
AM		 1446 encoding, this is not backward compatible. Do not generate the
1447 new form unless -mpower4 has been given, or -many and the two
1448 operand form of mfcr was used. */
11a0cf2e
PB		 1449 else if (value > 0
1450 && (value & -value) == value
a30e9cc4
AM		 1451 && ((dialect & PPC_OPCODE_POWER4) != 0
1452 || ((dialect & PPC_OPCODE_ANY) != 0
1453 && (insn & (0x3ff << 1)) == 19 << 1)))
c168870a
AM		 1454 insn |= 1 << 20;
1455
1456 /* Any other value on mfcr is an error. */
1457 else if ((insn & (0x3ff << 1)) == 19 << 1)
1458 {
11a0cf2e
PB		 1459 /* A value of -1 means we used the one operand form of
1460 mfcr which is valid. */
1461 if (value != -1)
b817670b 1462 *errmsg = _("invalid mfcr mask");
c168870a
AM		 1463 value = 0;
1464 }
1465
1466 return insn | ((value & 0xff) << 12);
1467}
1468
2fbfdc41
AM		 1469static long
1470extract_fxm (unsigned long insn,
fa452fa6 1471 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1472 int *invalid)
c168870a
AM		 1473{
1474 long mask = (insn >> 12) & 0xff;
1475
1476 /* Is this a Power4 insn? */
1477 if ((insn & (1 << 20)) != 0)
1478 {
98e69875
AM		 1479 /* Exactly one bit of MASK should be set. */
1480 if (mask == 0 || (mask & -mask) != mask)
8427c424 1481 *invalid = 1;
c168870a
AM		 1482 }
1483
1484 /* Check that non-power4 form of mfcr has a zero MASK. */
1485 else if ((insn & (0x3ff << 1)) == 19 << 1)
1486 {
8427c424 1487 if (mask != 0)
c168870a 1488 *invalid = 1;
11a0cf2e
PB		 1489 else
1490 mask = -1;
c168870a
AM		 1491 }
1492
1493 return mask;
1494}
1495
b9c361e0
JL		 1496static unsigned long
1497insert_li20 (unsigned long insn,
1498 long value,
1499 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1500 const char **errmsg ATTRIBUTE_UNUSED)
1501{
1502 return insn | ((value & 0xf0000) >> 5) | ((value & 0x0f800) << 5) | (value & 0x7ff);
1503}
1504
1505static long
1506extract_li20 (unsigned long insn,
1507 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1508 int *invalid ATTRIBUTE_UNUSED)
1509{
1510 long ext = ((insn & 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000;
1511
1512 return ext
1513 | (((insn >> 11) & 0xf) << 16)
1514 | (((insn >> 17) & 0xf) << 12)
1515 | (((insn >> 16) & 0x1) << 11)
1516 | (insn & 0x7ff);
1517}
1518
7b934113
PB		 1519/* The 2-bit L field in a SYNC or WC field in a WAIT instruction.
1520 For SYNC, some L values are reserved:
1521 * Value 3 is reserved on newer server cpus.
1522 * Values 2 and 3 are reserved on all other cpus. */
aea77599
AM		 1523
1524static unsigned long
1525insert_ls (unsigned long insn,
1526 long value,
7b934113
PB		 1527 ppc_cpu_t dialect,
1528 const char **errmsg)
1529{
1530 /* For SYNC, some L values are illegal. */
1531 if (((insn >> 1) & 0x3ff) == 598)
1532 {
1533 long max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1;
1534 if (value > max_lvalue)
1535 {
1536 *errmsg = _("illegal L operand value");
1537 return insn;
1538 }
1539 }
1540
1541 return insn | ((value & 0x3) << 21);
1542}
1543
73f07bff
AM		 1544static long
1545extract_ls (unsigned long insn,
1546 ppc_cpu_t dialect,
1547 int *invalid)
1548{
1549 unsigned long lvalue = (insn >> 21) & 3;
1550
1551 if (((insn >> 1) & 0x3ff) == 598)
1552 {
1553 unsigned long max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1;
1554 if (lvalue > max_lvalue)
1555 *invalid = 1;
1556 }
1557 return lvalue;
1558}
1559
7b934113
PB		 1560/* The 4-bit E field in a sync instruction that accepts 2 operands.
1561 If ESYNC is non-zero, then the L field must be either 0 or 1 and
1562 the complement of ESYNC-bit2. */
1563
1564static unsigned long
1565insert_esync (unsigned long insn,
1566 long value,
a680de9a 1567 ppc_cpu_t dialect,
7b934113 1568 const char **errmsg)
aea77599 1569{
a680de9a 1570 unsigned long ls = (insn >> 21) & 0x03;
aea77599 1571
aea77599
AM		 1572 if (value == 0)
1573 {
a680de9a
PB		 1574 if (((dialect & PPC_OPCODE_E6500) != 0 && ls > 1)
1575 || ((dialect & PPC_OPCODE_POWER9) != 0 && ls > 2))
1576 *errmsg = _("illegal L operand value");
aea77599
AM		 1577 return insn;
1578 }
7b934113
PB		 1579
1580 if ((ls & ~0x1)
1581 || (((value >> 1) & 0x1) ^ ls) == 0)
1582 *errmsg = _("incompatible L operand value");
1583
1584 return insn | ((value & 0xf) << 16);
aea77599
AM		 1585}
1586
73f07bff
AM		 1587static long
1588extract_esync (unsigned long insn,
1589 ppc_cpu_t dialect,
1590 int *invalid)
1591{
1592 unsigned long ls = (insn >> 21) & 0x3;
1593 unsigned long lvalue = (insn >> 16) & 0xf;
1594
1595 if (lvalue == 0)
1596 {
1597 if (((dialect & PPC_OPCODE_E6500) != 0 && ls > 1)
1598 || ((dialect & PPC_OPCODE_POWER9) != 0 && ls > 2))
1599 *invalid = 1;
1600 }
1601 else if ((ls & ~0x1)
1602 || (((lvalue >> 1) & 0x1) ^ ls) == 0)
1603 *invalid = 1;
1604
1605 return lvalue;
1606}
1607
252b5132
RH		 1608/* The MB and ME fields in an M form instruction expressed as a single
1609 operand which is itself a bitmask. The extraction function always
1610 marks it as invalid, since we never want to recognize an
1611 instruction which uses a field of this type. */
1612
1613static unsigned long
2fbfdc41
AM		 1614insert_mbe (unsigned long insn,
1615 long value,
fa452fa6 1616 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1617 const char **errmsg)
252b5132
RH		 1618{
1619 unsigned long uval, mask;
1620 int mb, me, mx, count, last;
1621
1622 uval = value;
1623
1624 if (uval == 0)
1625 {
8427c424 1626 *errmsg = _("illegal bitmask");
252b5132
RH		 1627 return insn;
1628 }
1629
1630 mb = 0;
1631 me = 32;
1632 if ((uval & 1) != 0)
1633 last = 1;
1634 else
1635 last = 0;
1636 count = 0;
1637
1638 /* mb: location of last 0->1 transition */
1639 /* me: location of last 1->0 transition */
1640 /* count: # transitions */
1641
0deb7ac5 1642 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
252b5132
RH		 1643 {
1644 if ((uval & mask) && !last)
1645 {
1646 ++count;
1647 mb = mx;
1648 last = 1;
1649 }
1650 else if (!(uval & mask) && last)
1651 {
1652 ++count;
1653 me = mx;
1654 last = 0;
1655 }
1656 }
1657 if (me == 0)
1658 me = 32;
1659
1660 if (count != 2 && (count != 0 || ! last))
8427c424 1661 *errmsg = _("illegal bitmask");
252b5132
RH		 1662
1663 return insn | (mb << 6) | ((me - 1) << 1);
1664}
1665
1666static long
2fbfdc41 1667extract_mbe (unsigned long insn,
fa452fa6 1668 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1669 int *invalid)
252b5132
RH		 1670{
1671 long ret;
1672 int mb, me;
1673 int i;
1674
8427c424 1675 *invalid = 1;
252b5132
RH		 1676
1677 mb = (insn >> 6) & 0x1f;
1678 me = (insn >> 1) & 0x1f;
1679 if (mb < me + 1)
1680 {
1681 ret = 0;
1682 for (i = mb; i <= me; i++)
0deb7ac5 1683 ret |= 1L << (31 - i);
252b5132
RH		 1684 }
1685 else if (mb == me + 1)
8427c424 1686 ret = ~0;
252b5132
RH		 1687 else /* (mb > me + 1) */
1688 {
2fbfdc41 1689 ret = ~0;
252b5132 1690 for (i = me + 1; i < mb; i++)
0deb7ac5 1691 ret &= ~(1L << (31 - i));
252b5132
RH		 1692 }
1693 return ret;
1694}
1695
1696/* The MB or ME field in an MD or MDS form instruction. The high bit
1697 is wrapped to the low end. */
1698
252b5132 1699static unsigned long
2fbfdc41
AM		 1700insert_mb6 (unsigned long insn,
1701 long value,
fa452fa6 1702 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1703 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1704{
1705 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1706}
1707
252b5132 1708static long
2fbfdc41 1709extract_mb6 (unsigned long insn,
fa452fa6 1710 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1711 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1712{
1713 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1714}
1715
1716/* The NB field in an X form instruction. The value 32 is stored as
1717 0. */
1718
252b5132 1719static long
2fbfdc41 1720extract_nb (unsigned long insn,
fa452fa6 1721 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1722 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1723{
1724 long ret;
1725
1726 ret = (insn >> 11) & 0x1f;
1727 if (ret == 0)
1728 ret = 32;
1729 return ret;
1730}
1731
989993d8
JB		 1732/* The NB field in an lswi instruction, which has special value
1733 restrictions. The value 32 is stored as 0. */
1734
1735static unsigned long
1736insert_nbi (unsigned long insn,
1737 long value,
1738 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1739 const char **errmsg ATTRIBUTE_UNUSED)
1740{
1741 long rtvalue = (insn & RT_MASK) >> 21;
1742 long ravalue = (insn & RA_MASK) >> 16;
1743
1744 if (value == 0)
1745 value = 32;
1746 if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32
1747 : ravalue))
1748 *errmsg = _("address register in load range");
1749 return insn | ((value & 0x1f) << 11);
1750}
1751
252b5132
RH		 1752/* The NSI field in a D form instruction. This is the same as the SI
1753 field, only negated. The extraction function always marks it as
1754 invalid, since we never want to recognize an instruction which uses
1755 a field of this type. */
1756
252b5132 1757static unsigned long
2fbfdc41
AM		 1758insert_nsi (unsigned long insn,
1759 long value,
fa452fa6 1760 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1761 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 1762{
2fbfdc41 1763 return insn | (-value & 0xffff);
252b5132
RH		 1764}
1765
1766static long
2fbfdc41 1767extract_nsi (unsigned long insn,
fa452fa6 1768 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1769 int *invalid)
252b5132 1770{
8427c424 1771 *invalid = 1;
2fbfdc41 1772 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
252b5132
RH		 1773}
1774
1775/* The RA field in a D or X form instruction which is an updating
1776 load, which means that the RA field may not be zero and may not
1777 equal the RT field. */
1778
1779static unsigned long
2fbfdc41
AM		 1780insert_ral (unsigned long insn,
1781 long value,
fa452fa6 1782 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1783 const char **errmsg)
252b5132
RH		 1784{
1785 if (value == 0
1786 || (unsigned long) value == ((insn >> 21) & 0x1f))
1787 *errmsg = "invalid register operand when updating";
1788 return insn | ((value & 0x1f) << 16);
1789}
1790
73f07bff
AM		 1791static long
1792extract_ral (unsigned long insn,
1793 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1794 int *invalid)
1795{
1796 long rtvalue = (insn >> 21) & 0x1f;
1797 long ravalue = (insn >> 16) & 0x1f;
1798
1799 if (rtvalue == ravalue || ravalue == 0)
1800 *invalid = 1;
1801 return ravalue;
1802}
1803
252b5132
RH		 1804/* The RA field in an lmw instruction, which has special value
1805 restrictions. */
1806
1807static unsigned long
2fbfdc41
AM		 1808insert_ram (unsigned long insn,
1809 long value,
fa452fa6 1810 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1811 const char **errmsg)
252b5132
RH		 1812{
1813 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1814 *errmsg = _("index register in load range");
1815 return insn | ((value & 0x1f) << 16);
1816}
1817
73f07bff
AM		 1818static long
1819extract_ram (unsigned long insn,
1820 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1821 int *invalid)
1822{
1823 unsigned long rtvalue = (insn >> 21) & 0x1f;
1824 unsigned long ravalue = (insn >> 16) & 0x1f;
1825
1826 if (ravalue >= rtvalue)
1827 *invalid = 1;
1828 return ravalue;
1829}
1830
989993d8 1831/* The RA field in the DQ form lq or an lswx instruction, which have special
8427c424 1832 value restrictions. */
adadcc0c 1833
adadcc0c 1834static unsigned long
2fbfdc41
AM		 1835insert_raq (unsigned long insn,
1836 long value,
fa452fa6 1837 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1838 const char **errmsg)
adadcc0c
AM		 1839{
1840 long rtvalue = (insn & RT_MASK) >> 21;
1841
8427c424 1842 if (value == rtvalue)
adadcc0c
AM		 1843 *errmsg = _("source and target register operands must be different");
1844 return insn | ((value & 0x1f) << 16);
1845}
1846
73f07bff
AM		 1847static long
1848extract_raq (unsigned long insn,
1849 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1850 int *invalid)
1851{
1852 unsigned long rtvalue = (insn >> 21) & 0x1f;
1853 unsigned long ravalue = (insn >> 16) & 0x1f;
1854
1855 if (ravalue == rtvalue)
1856 *invalid = 1;
1857 return ravalue;
1858}
1859
252b5132
RH		 1860/* The RA field in a D or X form instruction which is an updating
1861 store or an updating floating point load, which means that the RA
1862 field may not be zero. */
1863
1864static unsigned long
2fbfdc41
AM		 1865insert_ras (unsigned long insn,
1866 long value,
fa452fa6 1867 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1868 const char **errmsg)
252b5132
RH		 1869{
1870 if (value == 0)
1871 *errmsg = _("invalid register operand when updating");
1872 return insn | ((value & 0x1f) << 16);
1873}
1874
73f07bff
AM		 1875static long
1876extract_ras (unsigned long insn,
1877 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1878 int *invalid)
1879{
1880 unsigned long ravalue = (insn >> 16) & 0x1f;
1881
1882 if (ravalue == 0)
1883 *invalid = 1;
1884 return ravalue;
1885}
1886
252b5132
RH		 1887/* The RB field in an X form instruction when it must be the same as
1888 the RS field in the instruction. This is used for extended
1889 mnemonics like mr. This operand is marked FAKE. The insertion
1890 function just copies the BT field into the BA field, and the
1891 extraction function just checks that the fields are the same. */
1892
252b5132 1893static unsigned long
2fbfdc41
AM		 1894insert_rbs (unsigned long insn,
1895 long value ATTRIBUTE_UNUSED,
fa452fa6 1896 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1897 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1898{
1899 return insn | (((insn >> 21) & 0x1f) << 11);
1900}
1901
1902static long
2fbfdc41 1903extract_rbs (unsigned long insn,
fa452fa6 1904 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 1905 int *invalid)
252b5132 1906{
8427c424 1907 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
252b5132
RH		 1908 *invalid = 1;
1909 return 0;
1910}
1911
989993d8
JB		 1912/* The RB field in an lswx instruction, which has special value
1913 restrictions. */
1914
1915static unsigned long
1916insert_rbx (unsigned long insn,
1917 long value,
1918 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1919 const char **errmsg)
1920{
1921 long rtvalue = (insn & RT_MASK) >> 21;
1922
1923 if (value == rtvalue)
1924 *errmsg = _("source and target register operands must be different");
1925 return insn | ((value & 0x1f) << 11);
1926}
1927
73f07bff
AM		 1928static long
1929extract_rbx (unsigned long insn,
1930 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1931 int *invalid)
1932{
1933 unsigned long rtvalue = (insn >> 21) & 0x1f;
1934 unsigned long rbvalue = (insn >> 11) & 0x1f;
1935
1936 if (rbvalue == rtvalue)
1937 *invalid = 1;
1938 return rbvalue;
1939}
1940
b9c361e0
JL		 1941/* The SCI8 field is made up of SCL and {U,N}I8 fields. */
1942static unsigned long
1943insert_sci8 (unsigned long insn,
1944 long value,
1945 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1946 const char **errmsg)
1947{
943d398f
AM		 1948 unsigned int fill_scale = 0;
1949 unsigned long ui8 = value;
b9c361e0 1950
943d398f
AM		 1951 if ((ui8 & 0xffffff00) == 0)
1952 ;
1953 else if ((ui8 & 0xffffff00) == 0xffffff00)
1954 fill_scale = 0x400;
1955 else if ((ui8 & 0xffff00ff) == 0)
b9c361e0 1956 {
943d398f
AM		 1957 fill_scale = 1 << 8;
1958 ui8 >>= 8;
b9c361e0 1959 }
943d398f 1960 else if ((ui8 & 0xffff00ff) == 0xffff00ff)
b9c361e0 1961 {
943d398f
AM		 1962 fill_scale = 0x400 | (1 << 8);
1963 ui8 >>= 8;
b9c361e0 1964 }
943d398f 1965 else if ((ui8 & 0xff00ffff) == 0)
b9c361e0 1966 {
943d398f
AM		 1967 fill_scale = 2 << 8;
1968 ui8 >>= 16;
b9c361e0 1969 }
943d398f 1970 else if ((ui8 & 0xff00ffff) == 0xff00ffff)
b9c361e0 1971 {
943d398f
AM		 1972 fill_scale = 0x400 | (2 << 8);
1973 ui8 >>= 16;
b9c361e0 1974 }
943d398f 1975 else if ((ui8 & 0x00ffffff) == 0)
b9c361e0 1976 {
943d398f
AM		 1977 fill_scale = 3 << 8;
1978 ui8 >>= 24;
b9c361e0 1979 }
943d398f 1980 else if ((ui8 & 0x00ffffff) == 0x00ffffff)
b9c361e0 1981 {
943d398f
AM		 1982 fill_scale = 0x400 | (3 << 8);
1983 ui8 >>= 24;
b9c361e0 1984 }
943d398f 1985 else
b9c361e0 1986 {
943d398f
AM		 1987 *errmsg = _("illegal immediate value");
1988 ui8 = 0;
b9c361e0 1989 }
b9c361e0 1990
943d398f 1991 return insn | fill_scale | (ui8 & 0xff);
b9c361e0
JL		 1992}
1993
1994static long
1995extract_sci8 (unsigned long insn,
1996 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1997 int *invalid ATTRIBUTE_UNUSED)
1998{
943d398f
AM		 1999 int fill = insn & 0x400;
2000 int scale_factor = (insn & 0x300) >> 5;
2001 long value = (insn & 0xff) << scale_factor;
2002
2003 if (fill != 0)
2004 value |= ~((long) 0xff << scale_factor);
2005 return value;
b9c361e0
JL		 2006}
2007
2008static unsigned long
2009insert_sci8n (unsigned long insn,
2010 long value,
943d398f 2011 ppc_cpu_t dialect,
b9c361e0
JL		 2012 const char **errmsg)
2013{
943d398f 2014 return insert_sci8 (insn, -value, dialect, errmsg);
b9c361e0
JL		 2015}
2016
2017static long
2018extract_sci8n (unsigned long insn,
943d398f
AM		 2019 ppc_cpu_t dialect,
2020 int *invalid)
b9c361e0 2021{
943d398f 2022 return -extract_sci8 (insn, dialect, invalid);
b9c361e0
JL		 2023}
2024
2025static unsigned long
2026insert_sd4h (unsigned long insn,
2027 long value,
2028 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2029 const char **errmsg ATTRIBUTE_UNUSED)
2030{
2031 return insn | ((value & 0x1e) << 7);
2032}
2033
2034static long
2035extract_sd4h (unsigned long insn,
2036 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2037 int *invalid ATTRIBUTE_UNUSED)
2038{
2039 return ((insn >> 8) & 0xf) << 1;
2040}
2041
2042static unsigned long
2043insert_sd4w (unsigned long insn,
2044 long value,
2045 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2046 const char **errmsg ATTRIBUTE_UNUSED)
2047{
2048 return insn | ((value & 0x3c) << 6);
2049}
2050
2051static long
2052extract_sd4w (unsigned long insn,
2053 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2054 int *invalid ATTRIBUTE_UNUSED)
2055{
2056 return ((insn >> 8) & 0xf) << 2;
2057}
2058
2059static unsigned long
2060insert_oimm (unsigned long insn,
2061 long value,
2062 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2063 const char **errmsg ATTRIBUTE_UNUSED)
2064{
2065 return insn | (((value - 1) & 0x1f) << 4);
2066}
2067
2068static long
2069extract_oimm (unsigned long insn,
2070 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2071 int *invalid ATTRIBUTE_UNUSED)
2072{
2073 return ((insn >> 4) & 0x1f) + 1;
2074}
2075
252b5132
RH		 2076/* The SH field in an MD form instruction. This is split. */
2077
252b5132 2078static unsigned long
2fbfdc41
AM		 2079insert_sh6 (unsigned long insn,
2080 long value,
fa452fa6 2081 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 2082 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 2083{
6fd3a02d
PB		 2084 /* SH6 operand in the rldixor instructions. */
2085 if (PPC_OP (insn) == 4)
2086 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 5);
2087 else
2088 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
252b5132
RH		 2089}
2090
252b5132 2091static long
2fbfdc41 2092extract_sh6 (unsigned long insn,
fa452fa6 2093 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 2094 int *invalid ATTRIBUTE_UNUSED)
252b5132 2095{
6fd3a02d
PB		 2096 /* SH6 operand in the rldixor instructions. */
2097 if (PPC_OP (insn) == 4)
2098 return ((insn >> 6) & 0x1f) | ((insn << 5) & 0x20);
2099 else
2100 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
252b5132
RH		 2101}
2102
2103/* The SPR field in an XFX form instruction. This is flipped--the
2104 lower 5 bits are stored in the upper 5 and vice- versa. */
2105
2106static unsigned long
2fbfdc41
AM		 2107insert_spr (unsigned long insn,
2108 long value,
fa452fa6 2109 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 2110 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 2111{
2112 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
2113}
2114
2115static long
2fbfdc41 2116extract_spr (unsigned long insn,
fa452fa6 2117 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2fbfdc41 2118 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 2119{
2120 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
2121}
2122
da99ee72 2123/* Some dialects have 8 SPRG registers instead of the standard 4. */
14b57c7c 2124#define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405)
da99ee72
AM		 2125
2126static unsigned long
2127insert_sprg (unsigned long insn,
2128 long value,
fa452fa6 2129 ppc_cpu_t dialect,
da99ee72
AM		 2130 const char **errmsg)
2131{
da99ee72 2132 if (value > 7
98c76446 2133 || (value > 3 && (dialect & ALLOW8_SPRG) == 0))
da99ee72
AM		 2134 *errmsg = _("invalid sprg number");
2135
2136 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
2137 user mode. Anything else must use spr 272..279. */
2138 if (value <= 3 || (insn & 0x100) != 0)
2139 value |= 0x10;
2140
2141 return insn | ((value & 0x17) << 16);
2142}
2143
2144static long
2145extract_sprg (unsigned long insn,
fa452fa6 2146 ppc_cpu_t dialect,
da99ee72
AM		 2147 int *invalid)
2148{
2149 unsigned long val = (insn >> 16) & 0x1f;
2150
2151 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
98c76446
AM		 2152 If not BOOKE, 405 or VLE, then both use only 272..275. */
2153 if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0)
e1c93c69
AM		 2154 || (val - 0x10 > 7 && (insn & 0x100) != 0)
2155 || val <= 3
2156 || (val & 8) != 0)
da99ee72
AM		 2157 *invalid = 1;
2158 return val & 7;
2159}
2160
252b5132 2161/* The TBR field in an XFX instruction. This is just like SPR, but it
11a0cf2e 2162 is optional. */
252b5132 2163
252b5132 2164static unsigned long
2fbfdc41
AM		 2165insert_tbr (unsigned long insn,
2166 long value,
fa452fa6 2167 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
8514e4db 2168 const char **errmsg)
252b5132 2169{
8514e4db
AM		 2170 if (value != 268 && value != 269)
2171 *errmsg = _("invalid tbr number");
252b5132
RH		 2172 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
2173}
2174
2175static long
2fbfdc41 2176extract_tbr (unsigned long insn,
fa452fa6 2177 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
8514e4db 2178 int *invalid)
252b5132
RH		 2179{
2180 long ret;
2181
2182 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
8514e4db
AM		 2183 if (ret != 268 && ret != 269)
2184 *invalid = 1;
252b5132
RH		 2185 return ret;
2186}
9b4e5766
PB		 2187
2188/* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
2189
2190static unsigned long
2191insert_xt6 (unsigned long insn,
2192 long value,
2193 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2194 const char **errmsg ATTRIBUTE_UNUSED)
2195{
2196 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5);
2197}
2198
2199static long
2200extract_xt6 (unsigned long insn,
2201 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2202 int *invalid ATTRIBUTE_UNUSED)
2203{
2204 return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
2205}
2206
a680de9a
PB		 2207/* The XT and XS fields in an DQ form VSX instruction. This is split. */
2208static unsigned long
2209insert_xtq6 (unsigned long insn,
2210 long value,
2211 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2212 const char **errmsg ATTRIBUTE_UNUSED)
2213{
2214 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 2);
2215}
2216
2217static long
2218extract_xtq6 (unsigned long insn,
2219 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2220 int *invalid ATTRIBUTE_UNUSED)
2221{
2222 return ((insn << 2) & 0x20) | ((insn >> 21) & 0x1f);
2223}
2224
9b4e5766
PB		 2225/* The XA field in an XX3 form instruction. This is split. */
2226
2227static unsigned long
2228insert_xa6 (unsigned long insn,
2229 long value,
2230 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2231 const char **errmsg ATTRIBUTE_UNUSED)
2232{
2233 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3);
2234}
2235
2236static long
2237extract_xa6 (unsigned long insn,
2238 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2239 int *invalid ATTRIBUTE_UNUSED)
2240{
2241 return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
2242}
2243
2244/* The XB field in an XX3 form instruction. This is split. */
2245
2246static unsigned long
2247insert_xb6 (unsigned long insn,
2248 long value,
2249 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2250 const char **errmsg ATTRIBUTE_UNUSED)
2251{
2252 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
2253}
2254
2255static long
2256extract_xb6 (unsigned long insn,
2257 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2258 int *invalid ATTRIBUTE_UNUSED)
2259{
2260 return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f);
2261}
2262
2263/* The XB field in an XX3 form instruction when it must be the same as
2264 the XA field in the instruction. This is used for extended
2265 mnemonics like xvmovdp. This operand is marked FAKE. The insertion
2266 function just copies the XA field into the XB field, and the
2267 extraction function just checks that the fields are the same. */
2268
2269static unsigned long
2270insert_xb6s (unsigned long insn,
2271 long value ATTRIBUTE_UNUSED,
2272 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2273 const char **errmsg ATTRIBUTE_UNUSED)
2274{
2275 return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1);
2276}
2277
2278static long
2279extract_xb6s (unsigned long insn,
2280 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2281 int *invalid)
2282{
2283 if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
2284 || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1)))
2285 *invalid = 1;
2286 return 0;
2287}
066be9f7
PB		 2288
2289/* The XC field in an XX4 form instruction. This is split. */
2290
2291static unsigned long
2292insert_xc6 (unsigned long insn,
2293 long value,
2294 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2295 const char **errmsg ATTRIBUTE_UNUSED)
2296{
2297 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2);
2298}
2299
2300static long
2301extract_xc6 (unsigned long insn,
2302 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2303 int *invalid ATTRIBUTE_UNUSED)
2304{
2305 return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f);
2306}
2307
2308static unsigned long
2309insert_dm (unsigned long insn,
2310 long value,
2311 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2312 const char **errmsg)
2313{
2314 if (value != 0 && value != 1)
2315 *errmsg = _("invalid constant");
2316 return insn | (((value) ? 3 : 0) << 8);
2317}
2318
2319static long
2320extract_dm (unsigned long insn,
2321 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2322 int *invalid)
2323{
2324 long value;
2325
2326 value = (insn >> 8) & 3;
2327 if (value != 0 && value != 3)
2328 *invalid = 1;
2329 return (value) ? 1 : 0;
2330}
7b934113 2331
b9c361e0
JL		 2332/* The VLESIMM field in an I16A form instruction. This is split. */
2333
2334static unsigned long
2335insert_vlesi (unsigned long insn,
2336 long value,
2337 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2338 const char **errmsg ATTRIBUTE_UNUSED)
2339{
2340 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2341}
2342
2343static long
2344extract_vlesi (unsigned long insn,
2345 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2346 int *invalid ATTRIBUTE_UNUSED)
2347{
b9c361e0 2348 long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
9f0682fe 2349 value = (value ^ 0x8000) - 0x8000;
b9c361e0
JL		 2350 return value;
2351}
2352
2353static unsigned long
2354insert_vlensi (unsigned long insn,
2355 long value,
2356 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2357 const char **errmsg ATTRIBUTE_UNUSED)
2358{
2359 value = -value;
2360 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2361}
2362static long
2363extract_vlensi (unsigned long insn,
2364 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2365 int *invalid ATTRIBUTE_UNUSED)
2366{
2367 long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
9f0682fe
AM		 2368 value = (value ^ 0x8000) - 0x8000;
2369 /* Don't use for disassembly. */
b9c361e0
JL		 2370 *invalid = 1;
2371 return -value;
2372}
2373
2374/* The VLEUIMM field in an I16A form instruction. This is split. */
2375
2376static unsigned long
2377insert_vleui (unsigned long insn,
2378 long value,
2379 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2380 const char **errmsg ATTRIBUTE_UNUSED)
2381{
2382 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2383}
2384
2385static long
2386extract_vleui (unsigned long insn,
2387 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2388 int *invalid ATTRIBUTE_UNUSED)
2389{
2390 return ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2391}
2392
2393/* The VLEUIMML field in an I16L form instruction. This is split. */
2394
2395static unsigned long
2396insert_vleil (unsigned long insn,
2397 long value,
2398 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2399 const char **errmsg ATTRIBUTE_UNUSED)
2400{
2401 return insn | ((value & 0xf800) << 5) | (value & 0x7ff);
2402}
2403
2404static long
2405extract_vleil (unsigned long insn,
2406 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2407 int *invalid ATTRIBUTE_UNUSED)
2408{
2409 return ((insn >> 5) & 0xf800) | (insn & 0x7ff);
2410}
2411
252b5132
RH		 2412\f
2413/* Macros used to form opcodes. */
2414
2415/* The main opcode. */
2416#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
2417#define OP_MASK OP (0x3f)
2418
2419/* The main opcode combined with a trap code in the TO field of a D
2420 form instruction. Used for extended mnemonics for the trap
2421 instructions. */
2422#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
2423#define OPTO_MASK (OP_MASK | TO_MASK)
2424
2425/* The main opcode combined with a comparison size bit in the L field
2426 of a D form or X form instruction. Used for extended mnemonics for
2427 the comparison instructions. */
2428#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
2429#define OPL_MASK OPL (0x3f,1)
2430
b9c361e0
JL		 2431/* The main opcode combined with an update code in D form instruction.
2432 Used for extended mnemonics for VLE memory instructions. */
2433#define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8))
2434#define OPVUP_MASK OPVUP (0x3f, 0xff)
2435
dfdaec14
AJ		 2436/* The main opcode combined with an update code and the RT fields specified in
2437 D form instruction. Used for VLE volatile context save/restore
2438 instructions. */
2439#define OPVUPRT(x,vup,rt) (OPVUP (x, vup) | ((((unsigned long)(rt)) & 0x1f) << 21))
2440#define OPVUPRT_MASK OPVUPRT (0x3f, 0xff, 0x1f)
2441
252b5132
RH		 2442/* An A form instruction. */
2443#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
2444#define A_MASK A (0x3f, 0x1f, 1)
2445
2446/* An A_MASK with the FRB field fixed. */
2447#define AFRB_MASK (A_MASK | FRB_MASK)
2448
2449/* An A_MASK with the FRC field fixed. */
2450#define AFRC_MASK (A_MASK | FRC_MASK)
2451
2452/* An A_MASK with the FRA and FRC fields fixed. */
2453#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
2454
702f0fb4
PB		 2455/* An AFRAFRC_MASK, but with L bit clear. */
2456#define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
2457
252b5132
RH		 2458/* A B form instruction. */
2459#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
2460#define B_MASK B (0x3f, 1, 1)
2461
b9c361e0
JL		 2462/* A BD8 form instruction. This is a 16-bit instruction. */
2463#define BD8(op, aa, lk) (((((unsigned long)(op)) & 0x3f) << 10) | (((aa) & 1) << 9) | (((lk) & 1) << 8))
2464#define BD8_MASK BD8 (0x3f, 1, 1)
2465
2466/* Another BD8 form instruction. This is a 16-bit instruction. */
2467#define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11)
2468#define BD8IO_MASK BD8IO (0x1f)
2469
2470/* A BD8 form instruction for simplified mnemonics. */
2471#define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
2472/* A mask that excludes BO32 and BI32. */
2473#define EBD8IO1_MASK 0xf800
2474/* A mask that includes BO32 and excludes BI32. */
2475#define EBD8IO2_MASK 0xfc00
2476/* A mask that include BO32 AND BI32. */
2477#define EBD8IO3_MASK 0xff00
2478
2479/* A BD15 form instruction. */
2480#define BD15(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 0xf) << 22) | ((lk) & 1))
2481#define BD15_MASK BD15 (0x3f, 0xf, 1)
2482
2483/* A BD15 form instruction for extended conditional branch mnemonics. */
2484#define EBD15(op, aa, bo, lk) (((op) & 0x3f) << 26) | (((aa) & 0xf) << 22) | (((bo) & 0x3) << 20) | ((lk) & 1)
2485#define EBD15_MASK 0xfff00001
2486
2487/* A BD15 form instruction for extended conditional branch mnemonics with BI. */
2488#define EBD15BI(op, aa, bo, bi, lk) (((op) & 0x3f) << 26) \
2489 | (((aa) & 0xf) << 22) \
2490 | (((bo) & 0x3) << 20) \
2491 | (((bi) & 0x3) << 16) \
2492 | ((lk) & 1)
2493#define EBD15BI_MASK 0xfff30001
2494
2495/* A BD24 form instruction. */
2496#define BD24(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 25) | ((lk) & 1))
2497#define BD24_MASK BD24 (0x3f, 1, 1)
2498
252b5132
RH		 2499/* A B form instruction setting the BO field. */
2500#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2501#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
2502
2503/* A BBO_MASK with the y bit of the BO field removed. This permits
2504 matching a conditional branch regardless of the setting of the y
94efba12 2505 bit. Similarly for the 'at' bits used for power4 branch hints. */
de866fcc 2506#define Y_MASK (((unsigned long) 1) << 21)
802a735e
AM		 2507#define AT1_MASK (((unsigned long) 3) << 21)
2508#define AT2_MASK (((unsigned long) 9) << 21)
2509#define BBOY_MASK (BBO_MASK &~ Y_MASK)
2510#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
252b5132
RH		 2511
2512/* A B form instruction setting the BO field and the condition bits of
2513 the BI field. */
2514#define BBOCB(op, bo, cb, aa, lk) \
2515 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
2516#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
2517
2518/* A BBOCB_MASK with the y bit of the BO field removed. */
2519#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
802a735e
AM		 2520#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
2521#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
252b5132
RH		 2522
2523/* A BBOYCB_MASK in which the BI field is fixed. */
2524#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
802a735e 2525#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
252b5132 2526
b9c361e0
JL		 2527/* A VLE C form instruction. */
2528#define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1))
2529#define C_LK_MASK C_LK(0x7fff, 1)
2530#define C(x) ((((unsigned long)(x)) & 0xffff))
2531#define C_MASK C(0xffff)
2532
23976049
EZ		 2533/* An Context form instruction. */
2534#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
fdd12ef3 2535#define CTX_MASK CTX(0x3f, 0x7)
23976049
EZ		 2536
2537/* An User Context form instruction. */
2538#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
fdd12ef3 2539#define UCTX_MASK UCTX(0x3f, 0x1f)
23976049 2540
252b5132
RH		 2541/* The main opcode mask with the RA field clear. */
2542#define DRA_MASK (OP_MASK | RA_MASK)
2543
a680de9a
PB		 2544/* A DQ form VSX instruction. */
2545#define DQX(op, xop) (OP (op) | ((xop) & 0x7))
2546#define DQX_MASK DQX (0x3f, 7)
2547
252b5132
RH		 2548/* A DS form instruction. */
2549#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
2550#define DS_MASK DSO (0x3f, 3)
2551
a680de9a
PB		 2552/* An DX form instruction. */
2553#define DX(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2554#define DX_MASK DX (0x3f, 0x1f)
2555
23976049
EZ		 2556/* An EVSEL form instruction. */
2557#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
2558#define EVSEL_MASK EVSEL(0x3f, 0xff)
2559
b9c361e0
JL		 2560/* An IA16 form instruction. */
2561#define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2562#define IA16_MASK IA16(0x3f, 0x1f)
2563
2564/* An I16A form instruction. */
2565#define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2566#define I16A_MASK I16A(0x3f, 0x1f)
2567
2568/* An I16L form instruction. */
2569#define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2570#define I16L_MASK I16L(0x3f, 0x1f)
2571
2572/* An IM7 form instruction. */
2573#define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11)
2574#define IM7_MASK IM7(0x1f)
2575
252b5132
RH		 2576/* An M form instruction. */
2577#define M(op, rc) (OP (op) | ((rc) & 1))
2578#define M_MASK M (0x3f, 1)
2579
b9c361e0
JL		 2580/* An LI20 form instruction. */
2581#define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15)
2582#define LI20_MASK LI20(0x3f, 0x1)
2583
252b5132
RH		 2584/* An M form instruction with the ME field specified. */
2585#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
2586
2587/* An M_MASK with the MB and ME fields fixed. */
2588#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
2589
2590/* An M_MASK with the SH and ME fields fixed. */
2591#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
2592
2593/* An MD form instruction. */
2594#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
2595#define MD_MASK MD (0x3f, 0x7, 1)
2596
2597/* An MD_MASK with the MB field fixed. */
2598#define MDMB_MASK (MD_MASK | MB6_MASK)
2599
2600/* An MD_MASK with the SH field fixed. */
2601#define MDSH_MASK (MD_MASK | SH6_MASK)
2602
2603/* An MDS form instruction. */
2604#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
2605#define MDS_MASK MDS (0x3f, 0xf, 1)
2606
2607/* An MDS_MASK with the MB field fixed. */
2608#define MDSMB_MASK (MDS_MASK | MB6_MASK)
2609
2610/* An SC form instruction. */
2611#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
2612#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
2613
b9c361e0
JL		 2614/* An SCI8 form instruction. */
2615#define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11))
2616#define SCI8_MASK SCI8(0x3f, 0x1f)
2617
2618/* An SCI8 form instruction. */
2619#define SCI8BF(op, fop, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11) | (((fop) & 7) << 23))
2620#define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
2621
2622/* An SD4 form instruction. This is a 16-bit instruction. */
43e65147 2623#define SD4(op) ((((unsigned long)(op)) & 0xf) << 12)
b9c361e0
JL		 2624#define SD4_MASK SD4(0xf)
2625
2626/* An SE_IM5 form instruction. This is a 16-bit instruction. */
2627#define SE_IM5(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x1) << 9))
2628#define SE_IM5_MASK SE_IM5(0x3f, 1)
2629
2630/* An SE_R form instruction. This is a 16-bit instruction. */
2631#define SE_R(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3f) << 4))
2632#define SE_R_MASK SE_R(0x3f, 0x3f)
2633
2634/* An SE_RR form instruction. This is a 16-bit instruction. */
2635#define SE_RR(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3) << 8))
2636#define SE_RR_MASK SE_RR(0x3f, 3)
2637
2638/* A VX form instruction. */
786e2c0f
C		 2639#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2640
112290ab 2641/* The mask for an VX form instruction. */
786e2c0f
C		 2642#define VX_MASK VX(0x3f, 0x7ff)
2643
fb048c26
PB		 2644/* A VX_MASK with the VA field fixed. */
2645#define VXVA_MASK (VX_MASK | (0x1f << 16))
2646
2647/* A VX_MASK with the VB field fixed. */
2648#define VXVB_MASK (VX_MASK | (0x1f << 11))
2649
2650/* A VX_MASK with the VA and VB fields fixed. */
2651#define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))
2652
2653/* A VX_MASK with the VD and VA fields fixed. */
2654#define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))
2655
2656/* A VX_MASK with a UIMM4 field. */
2657#define VXUIMM4_MASK (VX_MASK | (0x1 << 20))
2658
2659/* A VX_MASK with a UIMM3 field. */
2660#define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
2661
2662/* A VX_MASK with a UIMM2 field. */
2663#define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
2664
c0637f3a
PB		 2665/* A VX_MASK with a PS field. */
2666#define VXPS_MASK (VX_MASK & ~(0x1 << 9))
2667
a680de9a
PB		 2668/* A VX_MASK with the VA field fixed with a PS field. */
2669#define VXVAPS_MASK ((VX_MASK | (0x1f << 16)) & ~(0x1 << 9))
2670
b9c361e0 2671/* A VA form instruction. */
2613489e 2672#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
786e2c0f 2673
112290ab 2674/* The mask for an VA form instruction. */
2613489e 2675#define VXA_MASK VXA(0x3f, 0x3f)
786e2c0f 2676
382c72e9
PB		 2677/* A VXA_MASK with a SHB field. */
2678#define VXASHB_MASK (VXA_MASK | (1 << 10))
2679
b9c361e0 2680/* A VXR form instruction. */
786e2c0f
C		 2681#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
2682
112290ab 2683/* The mask for a VXR form instruction. */
786e2c0f
C		 2684#define VXR_MASK VXR(0x3f, 0x3ff, 1)
2685
a680de9a
PB		 2686/* A VX form instruction with a VA tertiary opcode. */
2687#define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16))
2688
6fd3a02d
PB		 2689#define VXASH(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2690#define VXASH_MASK VXASH (0x3f, 0x1f)
2691
252b5132
RH		 2692/* An X form instruction. */
2693#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2694
a680de9a
PB		 2695/* A X form instruction for Quad-Precision FP Instructions. */
2696#define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16))
2697
b9c361e0
JL		 2698/* An EX form instruction. */
2699#define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2700
2701/* The mask for an EX form instruction. */
2702#define EX_MASK EX (0x3f, 0x7ff)
2703
066be9f7
PB		 2704/* An XX2 form instruction. */
2705#define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
2706
a680de9a
PB		 2707/* A XX2 form instruction with the VA bits specified. */
2708#define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16))
2709
9b4e5766
PB		 2710/* An XX3 form instruction. */
2711#define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
2712
066be9f7
PB		 2713/* An XX3 form instruction with the RC bit specified. */
2714#define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))
2715
2716/* An XX4 form instruction. */
2717#define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
9b4e5766 2718
702f0fb4
PB		 2719/* A Z form instruction. */
2720#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
2721
252b5132
RH		 2722/* An X form instruction with the RC bit specified. */
2723#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
2724
a680de9a
PB		 2725/* A X form instruction for Quad-Precision FP Instructions with RC bit. */
2726#define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1))
2727
6fd3a02d
PB		 2728/* An X form instruction with the RA bits specified as two ops. */
2729#define XMMF(op, xop, mop0, mop1) (X ((op), (xop)) | ((mop0) & 3) << 19 | ((mop1) & 7) << 16)
2730
702f0fb4
PB		 2731/* A Z form instruction with the RC bit specified. */
2732#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
2733
252b5132
RH		 2734/* The mask for an X form instruction. */
2735#define X_MASK XRC (0x3f, 0x3ff, 1)
2736
a680de9a
PB		 2737/* The mask for an X form instruction with the BF bits specified. */
2738#define XBF_MASK (X_MASK | (3 << 21))
2739
e0d602ec
BE		 2740/* An X form wait instruction with everything filled in except the WC field. */
2741#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2742
9b4e5766
PB		 2743/* The mask for an XX1 form instruction. */
2744#define XX1_MASK X (0x3f, 0x3ff)
2745
c0637f3a
PB		 2746/* An XX1_MASK with the RB field fixed. */
2747#define XX1RB_MASK (XX1_MASK | RB_MASK)
2748
066be9f7
PB		 2749/* The mask for an XX2 form instruction. */
2750#define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
2751
2752/* The mask for an XX2 form instruction with the UIM bits specified. */
2753#define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
2754
a680de9a
PB		 2755/* The mask for an XX2 form instruction with the 4 UIM bits specified. */
2756#define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20))
2757
066be9f7
PB		 2758/* The mask for an XX2 form instruction with the BF bits specified. */
2759#define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
2760
a680de9a
PB		 2761/* The mask for an XX2 form instruction with the BF and DCMX bits specified. */
2762#define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1)
2763
2764/* The mask for an XX2 form instruction with a split DCMX bits specified. */
2765#define XX2DCMXS_MASK XX2 (0x3f, 0x1ee)
2766
9b4e5766
PB		 2767/* The mask for an XX3 form instruction. */
2768#define XX3_MASK XX3 (0x3f, 0xff)
2769
066be9f7
PB		 2770/* The mask for an XX3 form instruction with the BF bits specified. */
2771#define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
2772
2773/* The mask for an XX3 form instruction with the DM or SHW bits specified. */
9b4e5766 2774#define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
066be9f7
PB		 2775#define XX3SHW_MASK XX3DM_MASK
2776
2777/* The mask for an XX4 form instruction. */
2778#define XX4_MASK XX4 (0x3f, 0x3)
2779
2780/* An X form wait instruction with everything filled in except the WC field. */
2781#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
9b4e5766 2782
6fd3a02d
PB		 2783/* The mask for an XMMF form instruction. */
2784#define XMMF_MASK (XMMF (0x3f, 0x3ff, 3, 7) | (1))
2785
702f0fb4
PB		 2786/* The mask for a Z form instruction. */
2787#define Z_MASK ZRC (0x3f, 0x1ff, 1)
0bbdef92 2788#define Z2_MASK ZRC (0x3f, 0xff, 1)
702f0fb4 2789
a680de9a 2790/* An X_MASK with the RA/VA field fixed. */
252b5132 2791#define XRA_MASK (X_MASK | RA_MASK)
a680de9a 2792#define XVA_MASK XRA_MASK
252b5132 2793
a680de9a 2794/* An XRA_MASK with the A_L/W field clear. */
ea192fa3 2795#define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
a680de9a 2796#define XRLA_MASK XWRA_MASK
ea192fa3 2797
252b5132
RH		 2798/* An X_MASK with the RB field fixed. */
2799#define XRB_MASK (X_MASK | RB_MASK)
2800
2801/* An X_MASK with the RT field fixed. */
2802#define XRT_MASK (X_MASK | RT_MASK)
2803
702f0fb4
PB		 2804/* An XRT_MASK mask with the L bits clear. */
2805#define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
2806
252b5132
RH		 2807/* An X_MASK with the RA and RB fields fixed. */
2808#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
2809
a680de9a
PB		 2810/* An XBF_MASK with the RA and RB fields fixed. */
2811#define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK)
2812
112290ab 2813/* An XRARB_MASK, but with the L bit clear. */
5ae2e65e
AM		 2814#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
2815
a680de9a
PB		 2816/* An XRARB_MASK, but with the L bits in a darn instruction clear. */
2817#define XLRAND_MASK (XRARB_MASK & ~((unsigned long) 3 << 16))
2818
252b5132
RH		 2819/* An X_MASK with the RT and RA fields fixed. */
2820#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
2821
5817ffd1
PB		 2822/* An X_MASK with the RT and RB fields fixed. */
2823#define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK)
2824
98acc1c5
AM		 2825/* An XRTRA_MASK, but with L bit clear. */
2826#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
2827
5817ffd1
PB		 2828/* An X_MASK with the RT, RA and RB fields fixed. */
2829#define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK)
2830
2831/* An XRTRARB_MASK, but with L bit clear. */
2832#define XRTLRARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 21))
2833
2834/* An XRTRARB_MASK, but with A bit clear. */
2835#define XRTARARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 25))
2836
2837/* An XRTRARB_MASK, but with BF bits clear. */
2838#define XRTBFRARB_MASK (XRTRARB_MASK & ~((unsigned long) 7 << 23))
2839
f3806e43
BE		 2840/* An X form instruction with the L bit specified. */
2841#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
252b5132 2842
e0d602ec
BE		 2843/* An X form instruction with the L bits specified. */
2844#define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2845
5817ffd1
PB		 2846/* An X form instruction with the L bit and RC bit specified. */
2847#define XRCL(op, xop, l, rc) (XRC ((op), (xop), (rc)) | ((((unsigned long)(l)) & 1) << 21))
2848
19a6653c
AM		 2849/* An X form instruction with RT fields specified */
2850#define XRT(op, xop, rt) (X ((op), (xop)) \
2851 | ((((unsigned long)(rt)) & 0x1f) << 21))
2852
2853/* An X form instruction with RT and RA fields specified */
2854#define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
2855 | ((((unsigned long)(rt)) & 0x1f) << 21) \
2856 | ((((unsigned long)(ra)) & 0x1f) << 16))
2857
252b5132
RH		 2858/* The mask for an X form comparison instruction. */
2859#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
2860
520ceea4
BE		 2861/* The mask for an X form comparison instruction with the L field
2862 fixed. */
2863#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
252b5132
RH		 2864
2865/* An X form trap instruction with the TO field specified. */
2866#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
2867#define XTO_MASK (X_MASK | TO_MASK)
2868
e0c21649
GK		 2869/* An X form tlb instruction with the SH field specified. */
2870#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
2871#define XTLB_MASK (X_MASK | SH_MASK)
2872
6ba045b1
AM		 2873/* An X form sync instruction. */
2874#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2875
2876/* An X form sync instruction with everything filled in except the LS field. */
2877#define XSYNC_MASK (0xff9fffff)
2878
aea77599
AM		 2879/* An X form sync instruction with everything filled in except the L and E fields. */
2880#define XSYNCLE_MASK (0xff90ffff)
2881
702f0fb4
PB		 2882/* An X_MASK, but with the EH bit clear. */
2883#define XEH_MASK (X_MASK & ~((unsigned long )1))
2884
f5c120c5
MG		 2885/* An X form AltiVec dss instruction. */
2886#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
2887#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
2888
252b5132
RH		 2889/* An XFL form instruction. */
2890#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
ea192fa3 2891#define XFL_MASK XFL (0x3f, 0x3ff, 1)
252b5132 2892
23976049 2893/* An X form isel instruction. */
de866fcc
AM		 2894#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2895#define XISEL_MASK XISEL(0x3f, 0x1f)
23976049 2896
252b5132
RH		 2897/* An XL form instruction with the LK field set to 0. */
2898#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2899
2900/* An XL form instruction which uses the LK field. */
2901#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
2902
2903/* The mask for an XL form instruction. */
2904#define XL_MASK XLLK (0x3f, 0x3ff, 1)
2905
c0637f3a
PB		 2906/* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */
2907#define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11))
2908
252b5132
RH		 2909/* An XL form instruction which explicitly sets the BO field. */
2910#define XLO(op, bo, xop, lk) \
2911 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2912#define XLO_MASK (XL_MASK | BO_MASK)
2913
2914/* An XL form instruction which explicitly sets the y bit of the BO
2915 field. */
2916#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
2917#define XLYLK_MASK (XL_MASK | Y_MASK)
2918
2919/* An XL form instruction which sets the BO field and the condition
2920 bits of the BI field. */
2921#define XLOCB(op, bo, cb, xop, lk) \
2922 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
2923#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
2924
2925/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
2926#define XLBB_MASK (XL_MASK | BB_MASK)
2927#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
2928#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
2929
d0618d1c
AM		 2930/* A mask for branch instructions using the BH field. */
2931#define XLBH_MASK (XL_MASK | (0x1c << 11))
2932
252b5132
RH		 2933/* An XL_MASK with the BO and BB fields fixed. */
2934#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
2935
2936/* An XL_MASK with the BO, BI and BB fields fixed. */
2937#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
2938
e01d869a
AM		 2939/* An X form mbar instruction with MO field. */
2940#define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21))
2941
252b5132
RH		 2942/* An XO form instruction. */
2943#define XO(op, xop, oe, rc) \
2944 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
2945#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
2946
2947/* An XO_MASK with the RB field fixed. */
2948#define XORB_MASK (XO_MASK | RB_MASK)
2949
c3d65c1c
BE		 2950/* An XOPS form instruction for paired singles. */
2951#define XOPS(op, xop, rc) \
2952 (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2953#define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
2954
2955
252b5132
RH		 2956/* An XS form instruction. */
2957#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
2958#define XS_MASK XS (0x3f, 0x1ff, 1)
2959
2960/* A mask for the FXM version of an XFX form instruction. */
98e69875 2961#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
252b5132
RH		 2962
2963/* An XFX form instruction with the FXM field filled in. */
98e69875
AM		 2964#define XFXM(op, xop, fxm, p4) \
2965 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
2966 | ((unsigned long)(p4) << 20))
252b5132
RH		 2967
2968/* An XFX form instruction with the SPR field filled in. */
2969#define XSPR(op, xop, spr) \
2970 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
2971#define XSPR_MASK (X_MASK | SPR_MASK)
2972
2973/* An XFX form instruction with the SPR field filled in except for the
2974 SPRBAT field. */
2975#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
2976
2977/* An XFX form instruction with the SPR field filled in except for the
2978 SPRG field. */
b84bf58a 2979#define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
252b5132
RH		 2980
2981/* An X form instruction with everything filled in except the E field. */
2982#define XE_MASK (0xffff7fff)
2983
23976049
EZ		 2984/* An X form user context instruction. */
2985#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
2986#define XUC_MASK XUC(0x3f, 0x1f)
2987
c3d65c1c
BE		 2988/* An XW form instruction. */
2989#define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
2990/* The mask for a G form instruction. rc not supported at present. */
2991#define XW_MASK XW (0x3f, 0x3f, 0)
2992
081ba1b3
AM		 2993/* An APU form instruction. */
2994#define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
2995
2996/* The mask for an APU form instruction. */
2997#define APU_MASK APU (0x3f, 0x3ff, 1)
2998#define APU_RT_MASK (APU_MASK | RT_MASK)
2999#define APU_RA_MASK (APU_MASK | RA_MASK)
3000
252b5132
RH		 3001/* The BO encodings used in extended conditional branch mnemonics. */
3002#define BODNZF (0x0)
3003#define BODNZFP (0x1)
3004#define BODZF (0x2)
3005#define BODZFP (0x3)
252b5132
RH		 3006#define BODNZT (0x8)
3007#define BODNZTP (0x9)
3008#define BODZT (0xa)
3009#define BODZTP (0xb)
802a735e
AM		 3010
3011#define BOF (0x4)
3012#define BOFP (0x5)
94efba12
AM		 3013#define BOFM4 (0x6)
3014#define BOFP4 (0x7)
252b5132
RH		 3015#define BOT (0xc)
3016#define BOTP (0xd)
94efba12
AM		 3017#define BOTM4 (0xe)
3018#define BOTP4 (0xf)
802a735e 3019
252b5132
RH		 3020#define BODNZ (0x10)
3021#define BODNZP (0x11)
3022#define BODZ (0x12)
3023#define BODZP (0x13)
94efba12
AM		 3024#define BODNZM4 (0x18)
3025#define BODNZP4 (0x19)
3026#define BODZM4 (0x1a)
3027#define BODZP4 (0x1b)
802a735e 3028
252b5132
RH		 3029#define BOU (0x14)
3030
b9c361e0
JL		 3031/* The BO16 encodings used in extended VLE conditional branch mnemonics. */
3032#define BO16F (0x0)
3033#define BO16T (0x1)
3034
3035/* The BO32 encodings used in extended VLE conditional branch mnemonics. */
3036#define BO32F (0x0)
3037#define BO32T (0x1)
3038#define BO32DNZ (0x2)
3039#define BO32DZ (0x3)
3040
252b5132
RH		 3041/* The BI condition bit encodings used in extended conditional branch
3042 mnemonics. */
3043#define CBLT (0)
3044#define CBGT (1)
3045#define CBEQ (2)
3046#define CBSO (3)
3047
3048/* The TO encodings used in extended trap mnemonics. */
3049#define TOLGT (0x1)
3050#define TOLLT (0x2)
3051#define TOEQ (0x4)
3052#define TOLGE (0x5)
3053#define TOLNL (0x5)
3054#define TOLLE (0x6)
3055#define TOLNG (0x6)
3056#define TOGT (0x8)
3057#define TOGE (0xc)
3058#define TONL (0xc)
3059#define TOLT (0x10)
3060#define TOLE (0x14)
3061#define TONG (0x14)
3062#define TONE (0x18)
3063#define TOU (0x1f)
3064\f
3065/* Smaller names for the flags so each entry in the opcodes table will
3066 fit on a single line. */
3067#undef PPC
de866fcc 3068#define PPC PPC_OPCODE_PPC
661bd698 3069#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
661bd698 3070#define POWER4 PPC_OPCODE_POWER4
1ed8e1e4 3071#define POWER5 PPC_OPCODE_POWER5
702f0fb4 3072#define POWER6 PPC_OPCODE_POWER6
066be9f7 3073#define POWER7 PPC_OPCODE_POWER7
5817ffd1 3074#define POWER8 PPC_OPCODE_POWER8
a680de9a 3075#define POWER9 PPC_OPCODE_POWER9
ede602d7 3076#define CELL PPC_OPCODE_CELL
bdc70b4a 3077#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
6b069ee7 3078#define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \
bdc70b4a 3079 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
418c1742 3080#define PPC403 PPC_OPCODE_403
081ba1b3 3081#define PPC405 PPC_OPCODE_405
7d5b217e 3082#define PPC440 PPC_OPCODE_440
c8187e15 3083#define PPC464 PPC440
9fe54b1c 3084#define PPC476 PPC_OPCODE_476
ef5a96d5
AM		 3085#define PPC750 PPC_OPCODE_750
3086#define PPC7450 PPC_OPCODE_7450
3087#define PPC860 PPC_OPCODE_860
c3d65c1c 3088#define PPCPS PPC_OPCODE_PPCPS
a404d431 3089#define PPCVEC PPC_OPCODE_ALTIVEC
aea77599 3090#define PPCVEC2 PPC_OPCODE_ALTIVEC2
a680de9a 3091#define PPCVEC3 PPC_OPCODE_ALTIVEC2
9b4e5766 3092#define PPCVSX PPC_OPCODE_VSX
c0637f3a 3093#define PPCVSX2 PPC_OPCODE_VSX
a680de9a 3094#define PPCVSX3 PPC_OPCODE_VSX3
de866fcc
AM		 3095#define POWER PPC_OPCODE_POWER
3096#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
81a0b7e2
AM		 3097#define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
3098#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
de866fcc 3099#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
de866fcc 3100#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
661bd698 3101#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
de866fcc 3102#define MFDEC1 PPC_OPCODE_POWER
bdc70b4a 3103#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
418c1742 3104#define BOOKE PPC_OPCODE_BOOKE
14b57c7c 3105#define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS
36ae0db3 3106#define PPCE300 PPC_OPCODE_E300
14b57c7c
AM		 3107#define PPCSPE PPC_OPCODE_SPE
3108#define PPCISEL PPC_OPCODE_ISEL
3109#define PPCEFS PPC_OPCODE_EFS
de866fcc 3110#define PPCBRLK PPC_OPCODE_BRLOCK
23976049 3111#define PPCPMR PPC_OPCODE_PMR
aea77599 3112#define PPCTMR PPC_OPCODE_TMR
de866fcc 3113#define PPCCHLK PPC_OPCODE_CACHELCK
23976049 3114#define PPCRFMCI PPC_OPCODE_RFMCI
19a6653c 3115#define E500MC PPC_OPCODE_E500MC
634b50f2 3116#define PPCA2 PPC_OPCODE_A2
43e65147 3117#define TITAN PPC_OPCODE_TITAN
14b57c7c 3118#define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN
e01d869a 3119#define E500 PPC_OPCODE_E500
aea77599 3120#define E6500 PPC_OPCODE_E6500
b9c361e0 3121#define PPCVLE PPC_OPCODE_VLE
5817ffd1 3122#define PPCHTM PPC_OPCODE_HTM
dfdaec14 3123#define E200Z4 PPC_OPCODE_E200Z4
4fff86c5
PB		 3124/* The list of embedded processors that use the embedded operand ordering
3125 for the 3 operand dcbt and dcbtst instructions. */
3126#define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
14b57c7c 3127 | PPC_OPCODE_A2)
4fff86c5
PB		 3128
3129
252b5132
RH		 3130\f
3131/* The opcode table.
3132
3133 The format of the opcode table is:
3134
8ebac3aa 3135 NAME OPCODE MASK FLAGS ANTI {OPERANDS}
252b5132
RH		 3136
3137 NAME is the name of the instruction.
3138 OPCODE is the instruction opcode.
3139 MASK is the opcode mask; this is used to tell the disassembler
3140 which bits in the actual opcode must match OPCODE.
8ebac3aa
AM		 3141 FLAGS are flags indicating which processors support the instruction.
3142 ANTI indicates which processors don't support the instruction.
252b5132
RH		 3143 OPERANDS is the list of operands.
3144
3145 The disassembler reads the table in order and prints the first
3146 instruction which matches, so this table is sorted to put more
de866fcc
AM		 3147 specific instructions before more general instructions.
3148
3149 This table must be sorted by major opcode. Please try to keep it
3150 vaguely sorted within major opcode too, except of course where
3151 constrained otherwise by disassembler operation. */
252b5132
RH		 3152
3153const struct powerpc_opcode powerpc_opcodes[] = {
14b57c7c
AM		 3154{"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476|PPCVLE, {0}},
3155{"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3156{"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3157{"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3158{"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3159{"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3160{"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3161{"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3162{"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3163{"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3164{"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3165{"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3166{"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3167{"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3168{"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3169{"tdui", OPTO(2,TOU), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3170{"tdi", OP(2), OP_MASK, PPC64, PPCVLE, {TO, RA, SI}},
3171
3172{"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3173{"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3174{"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3175{"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3176{"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3177{"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3178{"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3179{"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3180{"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3181{"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3182{"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3183{"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3184{"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3185{"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3186{"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3187{"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3188{"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3189{"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3190{"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3191{"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3192{"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3193{"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3194{"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3195{"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3196{"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3197{"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3198{"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3199{"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3200{"twui", OPTO(3,TOU), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3201{"tui", OPTO(3,TOU), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3202{"twi", OP(3), OP_MASK, PPCCOM, PPCVLE, {TO, RA, SI}},
3203{"ti", OP(3), OP_MASK, PWRCOM, PPCVLE, {TO, RA, SI}},
3204
3205{"ps_cmpu0", X (4, 0), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3206{"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3207{"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
3208{"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3209{"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3210{"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3211{"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3212{"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3213{"vaddfp", VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3214{"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
3215{"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3216{"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
3217{"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3218{"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3219{"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3220{"ps_sum0", A (4, 10,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3221{"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3222{"ps_sum1", A (4, 11,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3223{"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3224{"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3225{"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3226{"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3227{"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3228{"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3229{"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3230{"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3231{"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3232{"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3233{"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3234{"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3235{"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3236{"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3237{"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
3238{"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3239{"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3240{"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3241{"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3242{"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3243{"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3244{"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3245{"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3246{"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3247{"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3248{"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3249{"vsel", VXA(4, 42), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3250{"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3251{"vperm", VXA(4, 43), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3252{"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC, 0, {VD, VA, VB, SHB}},
3253{"vpermxor", VXA(4, 45), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3254{"ps_sel", A (4, 23,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3255{"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
3256{"ps_sel.", A (4, 23,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3257{"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
3258{"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3259{"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3260{"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3261{"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3262{"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3263{"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3264{"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3265{"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3266{"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3267{"ps_msub", A (4, 28,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3268{"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3269{"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3270{"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3271{"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
3272{"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3273{"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3274{"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3275{"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3276{"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3277{"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3278{"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3279{"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3280{"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3281{"vadduhm", VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3282{"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3283{"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3284{"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3285{"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3286{"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3287{"vmulouh", VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3288{"vsubfp", VX (4, 74), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3289{"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
3290{"vmrghh", VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3291{"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
3292{"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3293{"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3294{"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3295{"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3296{"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3297{"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3298{"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3299{"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3300{"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3301{"ps_cmpu1", X (4, 64), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3302{"vadduwm", VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3303{"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3304{"vrlw", VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3305{"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3306{"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3307{"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3308{"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3309{"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3310{"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3311{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3312{"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3313{"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3314{"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3315{"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3316{"ps_cmpo1", X (4, 96), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3317{"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3318{"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3319{"vrld", VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3320{"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3321{"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3322{"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3323{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3324{"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3325{"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3326{"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3327{"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3328{"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3329{"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3330{"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3331{"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3332{"vmulosb", VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3333{"vrefp", VX (4, 266), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3334{"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3335{"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3336{"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3337{"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3338{"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3339{"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3340{"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3341{"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3342{"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3343{"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3344{"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3345{"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3346{"vmulosh", VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3347{"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3348{"vmrglh", VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3349{"vpkswus", VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3350{"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3351{"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3352{"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3353{"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3354{"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3355{"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3356{"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3357{"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3358{"vslw", VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3359{"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3360{"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3361{"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3362{"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3363{"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3364{"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3365{"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3366{"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3367{"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3368{"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3369{"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3370{"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3371{"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3372{"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3373{"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3374{"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3375{"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3376{"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3377{"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3378{"vaddubs", VX (4, 512), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3379{"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
3380{"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
3381{"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3382{"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3383{"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}},
3384{"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3385{"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}},
3386{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
3387{"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3388{"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}},
3389{"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3390{"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}},
3391{"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}},
3392{"vrfin", VX (4, 522), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3393{"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}},
3394{"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}},
3395{"vspltb", VX (4, 524), VXUIMM4_MASK, PPCVEC, 0, {VD, VB, UIMM4}},
3396{"vextractub", VX (4, 525), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3397{"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}},
3398{"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}},
3399{"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3400{"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3401{"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3402{"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3403{"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3404{"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3405{"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3406{"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
3407{"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3408{"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3409{"evnot", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
3410{"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3411{"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3412{"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3413{"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3414{"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3415{"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3416{"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3417{"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3418{"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3419{"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3420{"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3421{"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}},
3422{"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3423{"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}},
3424{"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3425{"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3426{"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3427{"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3428{"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3429{"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3430{"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3431{"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3432{"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3433{"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3434{"vadduhs", VX (4, 576), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3435{"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3436{"vminuh", VX (4, 578), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3437{"vsrh", VX (4, 580), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3438{"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3439{"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3440{"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3441{"vsplth", VX (4, 588), VXUIMM3_MASK, PPCVEC, 0, {VD, VB, UIMM3}},
3442{"vextractuh", VX (4, 589), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3443{"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3444{"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3445{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}},
3446{"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3447{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3448{"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3449{"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3450{"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3451{"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}},
3452{"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3453{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}},
3454{"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}},
3455{"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3456{"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3457{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3458{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3459{"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3460{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3461{"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}},
3462{"vextractuw", VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3463{"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3464{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3465{"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3466{"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}},
3467{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}},
3468{"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}},
3469{"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}},
3470{"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}},
3471{"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}},
3472{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}},
3473{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}},
3474{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}},
3475{"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3476{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}},
3477{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3478{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3479{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3480{"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3481{"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3482{"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3483{"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3484{"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
3485{"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3486{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
3487{"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
3488{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3489{"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3490{"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3491{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3492{"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3493{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3494{"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3495{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3496{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3497{"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3498{"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}},
3499{"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
3500{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
3501{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
3502{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
3503{"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
3504{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
3505{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
3506{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
3507{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},
3508{"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3509{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},
3510{"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3511{"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3512{"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3513{"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3514{"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3515{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, 0, {RS, RB}},
3516{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, 0, {RS, RB}},
3517{"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}},
3518{"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}},
3519{"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}},
3520{"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3521{"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3522{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, 0, {RS, RB}},
3523{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, 0, {RS, RB}},
3524{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3525{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3526{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3527{"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}},
3528{"efdcfui", VX (4, 752), VX_MASK, PPCEFS, 0, {RS, RB}},
3529{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, 0, {RS, RB}},
3530{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}},
3531{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}},
3532{"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}},
3533{"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}},
3534{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}},
3535{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}},
3536{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, 0, {RS, RB}},
3537{"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3538{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, 0, {RS, RB}},
3539{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3540{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3541{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3542{"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3543{"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3544{"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3545{"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3546{"vminsb", VX (4, 770), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3547{"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3548{"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3549{"vsrab", VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3550{"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3551{"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3552{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3553{"vmulesb", VX (4, 776), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3554{"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
3555{"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3556{"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3557{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3558{"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
3559{"vinsertb", VX (4, 781), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3560{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
3561{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3562{"vpkpx", VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3563{"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
3564{"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3565{"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3566{"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3567{"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3568{"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3569{"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3570{"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3571{"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3572{"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3573{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3574{"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3575{"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3576{"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3577{"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3578{"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3579{"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3580{"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3581{"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3582{"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3583{"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3584{"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3585{"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3586{"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3587{"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3588{"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3589{"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3590{"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3591{"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3592{"vaddshs", VX (4, 832), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3593{"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3594{"vminsh", VX (4, 834), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3595{"vsrah", VX (4, 836), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3596{"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3597{"vmulesh", VX (4, 840), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3598{"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3599{"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3600{"vspltish", VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
3601{"vinserth", VX (4, 845), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3602{"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3603{"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3604{"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3605{"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3606{"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3607{"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3608{"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3609{"vaddsws", VX (4, 896), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3610{"vminsw", VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3611{"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3612{"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3613{"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3614{"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3615{"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3616{"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
3617{"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3618{"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3619{"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3620{"vminsd", VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3621{"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3622{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3623{"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3624{"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3625{"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3626{"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3627{"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3628{"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3629{"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3630{"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3631{"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3632{"vsububm", VX (4,1024), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3633{"bcdadd.", VX (4,1025), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
3634{"vavgub", VX (4,1026), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3635{"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3636{"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3637{"vand", VX (4,1028), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3638{"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3639{"vcmpneb.", VXR(4, 7,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3640{"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3641{"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3642{"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3643{"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3644{"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3645{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3646{"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3647{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3648{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3649{"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3650{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3651{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3652{"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3653{"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3654{"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3655{"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3656{"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3657{"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3658{"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3659{"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3660{"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3661{"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3662{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3663{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3664{"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3665{"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
3666{"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3667{"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3668{"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3669{"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3670{"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3671{"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3672{"vcmpneh.", VXR(4, 71,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3673{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3674{"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3675{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3676{"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3677{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3678{"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3679{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3680{"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3681{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3682{"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3683{"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3684{"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3685{"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3686{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3687{"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3688{"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3689{"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3690{"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3691{"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3692{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3693{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3694{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3695{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3696{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3697{"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3698{"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3699{"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3700{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3701{"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3702{"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3703{"vavguw", VX (4,1154), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3704{"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3705{"vmr", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
3706{"vor", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3707{"vcmpnew.", VXR(4, 135,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3708{"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3709{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3710{"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3711{"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3712{"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3713{"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3714{"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3715{"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3716{"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3717{"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}},
3718{"bcds.", VX (4,1217), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
3719{"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}},
3720{"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}},
3721{"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}},
3722{"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}},
3723{"vxor", VX (4,1220), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3724{"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3725{"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3726{"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3727{"vcmpequd.", VXR(4, 199,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3728{"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3729{"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3730{"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3731{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}},
3732{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}},
3733{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}},
3734{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}},
3735{"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3736{"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3737{"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3738{"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3739{"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3740{"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3741{"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3742{"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3743{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3744{"bcdtrunc.", VX (4,1281), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
3745{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3746{"vavgsb", VX (4,1282), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3747{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3748{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3749{"vnot", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
3750{"vnor", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3751{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3752{"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3753{"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3754{"vcmpnezb.", VXR(4, 263,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3755{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3756{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3757{"vcipher", VX (4,1288), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3758{"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3759{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3760{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3761{"vgbbd", VX (4,1292), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3762{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3763{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3764{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3765{"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3766{"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3767{"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3768{"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3769{"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3770{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3771{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3772{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3773{"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3774{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3775{"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3776{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3777{"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3778{"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3779{"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3780{"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3781{"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3782{"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3783{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3784{"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3785{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3786{"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3787{"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3788{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3789{"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3790{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3791{"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3792{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3793{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3794{"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3795{"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3796{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3797{"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3798{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3799{"bcdctsq.", VXVA(4,1409,0), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3800{"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3801{"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3802{"bcdctn.", VXVA(4,1409,5), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3803{"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3804{"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3805{"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3806{"vavgsw", VX (4,1410), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3807{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3808{"vnand", VX (4,1412), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3809{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3810{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3811{"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3812{"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3813{"vcmpnezw.", VXR(4, 391,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3814{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3815{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3816{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3817{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3818{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3819{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3820{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3821{"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3822{"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3823{"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3824{"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3825{"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3826{"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3827{"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3828{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3829{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3830{"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
3831{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3832{"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3833{"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3834{"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3835{"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3836{"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}},
3837{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3838{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3839{"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3840{"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3841{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3842{"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3843{"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3844{"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3845{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3846{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3847{"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3848{"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3849{"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3850{"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
3851{"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
3852{"vnegw", VXVA(4,1538,6), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3853{"vnegd", VXVA(4,1538,7), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3854{"vprtybw", VXVA(4,1538,8), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3855{"vprtybd", VXVA(4,1538,9), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3856{"vprtybq", VXVA(4,1538,10), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3857{"vextsb2w", VXVA(4,1538,16), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3858{"vextsh2w", VXVA(4,1538,17), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3859{"vextsb2d", VXVA(4,1538,24), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3860{"vextsh2d", VXVA(4,1538,25), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3861{"vextsw2d", VXVA(4,1538,26), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3862{"vctzb", VXVA(4,1538,28), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3863{"vctzh", VXVA(4,1538,29), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3864{"vctzw", VXVA(4,1538,30), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3865{"vctzd", VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3866{"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC, 0, {VD}},
3867{"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
9fe54b1c
PB		 3868{"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3869{"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
14b57c7c
AM		 3870{"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3871{"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3872{"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3873{"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC, 0, {VB}},
3874{"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3875{"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
9fe54b1c
PB		 3876{"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3877{"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
14b57c7c
AM		 3878{"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3879{"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3880{"vsubuws", VX (4,1664), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3881{"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
3882{"veqv", VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3883{"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
9fe54b1c
PB		 3884{"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3885{"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
14b57c7c
AM		 3886{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3887{"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3888{"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3889{"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
3890{"vsrd", VX (4,1732), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3891{"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
9fe54b1c 3892{"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
14b57c7c 3893{"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
9fe54b1c 3894{"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
14b57c7c
AM		 3895{"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3896{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3897{"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3898{"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3899{"vsrv", VX (4,1796), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3900{"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
9fe54b1c
PB		 3901{"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3902{"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
14b57c7c
AM		 3903{"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3904{"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3905{"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3906{"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3907{"vsubshs", VX (4,1856), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3908{"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3909{"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3910{"vslv", VX (4,1860), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3911{"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3912{"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
9fe54b1c
PB		 3913{"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3914{"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
14b57c7c
AM		 3915{"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3916{"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3917{"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3918{"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3919{"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3920{"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3921{"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3922{"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
9fe54b1c
PB		 3923{"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3924{"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
14b57c7c
AM		 3925{"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3926{"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3927{"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3928{"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3929{"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3930{"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3931{"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3932{"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
9fe54b1c 3933{"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
14b57c7c 3934{"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
9fe54b1c 3935{"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
14b57c7c
AM		 3936{"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3937{"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3938{"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3939{"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3940{"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}},
3941
3942{"mulli", OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3943{"muli", OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3944
3945{"subfic", OP(8), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3946{"sfi", OP(8), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3947
3948{"dozi", OP(9), OP_MASK, M601, PPCVLE, {RT, RA, SI}},
3949
3950{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, UISIGNOPT}},
3951{"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, UISIGNOPT}},
a5721ba2 3952{"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, UISIGNOPT}},
14b57c7c
AM		 3953{"cmpli", OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}},
3954
3955{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, SI}},
3956{"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, SI}},
a5721ba2 3957{"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, SI}},
14b57c7c
AM		 3958{"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}},
3959
3960{"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3961{"ai", OP(12), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3962{"subic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
3963
3964{"addic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3965{"ai.", OP(13), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3966{"subic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
3967
3968{"li", OP(14), DRA_MASK, PPCCOM, PPCVLE, {RT, SI}},
3969{"lil", OP(14), DRA_MASK, PWRCOM, PPCVLE, {RT, SI}},
3970{"addi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SI}},
3971{"cal", OP(14), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
3972{"subi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSI}},
3973{"la", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
3974
3975{"lis", OP(15), DRA_MASK, PPCCOM, PPCVLE, {RT, SISIGNOPT}},
3976{"liu", OP(15), DRA_MASK, PWRCOM, PPCVLE, {RT, SISIGNOPT}},
3977{"addis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
3978{"cau", OP(15), OP_MASK, PWRCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
3979{"subis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSISIGNOPT}},
3980
3981{"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
3982{"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
3983{"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}},
3984{"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}},
3985{"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
3986{"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
3987{"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}},
3988{"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}},
3989{"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
3990{"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
3991{"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}},
3992{"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}},
3993{"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
3994{"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
3995{"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}},
3996{"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}},
3997{"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
3998{"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
3999{"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCVLE, {BD}},
4000{"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
4001{"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
4002{"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCVLE, {BD}},
4003{"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
4004{"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
4005{"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCVLE, {BDA}},
4006{"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
4007{"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
4008{"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCVLE, {BDA}},
4009
4010{"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4011{"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4012{"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4013{"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4014{"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4015{"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4016{"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4017{"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4018{"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4019{"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4020{"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4021{"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4022{"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4023{"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4024{"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4025{"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4026{"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4027{"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4028{"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4029{"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4030{"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4031{"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4032{"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4033{"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4034{"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4035{"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4036{"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4037{"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4038{"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4039{"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4040{"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4041{"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4042{"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4043{"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4044{"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4045{"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4046{"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4047{"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4048{"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4049{"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4050{"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4051{"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4052{"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4053{"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4054{"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4055{"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4056{"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4057{"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4058{"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4059{"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4060{"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4061{"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4062{"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4063{"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4064{"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4065{"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4066{"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4067{"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4068{"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4069{"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4070{"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4071{"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4072{"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4073{"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4074{"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4075{"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4076{"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4077{"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4078{"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4079{"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4080{"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4081{"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4082{"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4083{"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4084{"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4085{"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4086{"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4087{"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4088{"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4089{"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4090{"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4091{"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4092{"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4093{"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4094
4095{"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4096{"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4097{"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4098{"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4099{"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4100{"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4101{"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4102{"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4103{"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4104{"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4105{"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4106{"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4107{"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4108{"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4109{"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4110{"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4111{"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4112{"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4113{"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4114{"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4115{"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4116{"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4117{"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4118{"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4119{"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4120{"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4121{"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4122{"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4123{"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4124{"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4125{"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4126{"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4127{"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4128{"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4129{"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4130{"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4131{"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4132{"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4133{"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4134{"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4135{"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4136{"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4137{"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4138{"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4139{"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4140{"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4141{"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4142{"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4143{"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4144{"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4145{"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4146{"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4147{"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4148{"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4149{"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4150{"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4151{"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4152{"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4153{"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4154{"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4155
4156{"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4157{"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4158{"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4159{"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4160{"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4161{"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4162{"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4163{"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4164{"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4165{"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4166{"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4167{"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4168{"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4169{"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4170{"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4171{"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4172{"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4173{"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4174{"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4175{"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4176{"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4177{"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4178{"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4179{"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4180
4181{"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4182{"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4183{"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4184{"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4185{"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4186{"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4187{"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4188{"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4189{"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4190{"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4191{"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4192{"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4193{"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4194{"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4195{"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4196{"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4197
4198{"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4199{"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4200{"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4201{"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4202{"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4203{"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4204{"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4205{"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4206{"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4207{"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4208{"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4209{"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4210{"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4211{"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4212{"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4213{"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4214{"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4215{"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4216{"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4217{"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4218{"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4219{"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4220{"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4221{"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4222
4223{"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4224{"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4225{"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4226{"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4227{"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4228{"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4229{"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4230{"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4231{"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4232{"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4233{"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4234{"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4235{"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4236{"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4237{"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4238{"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4239
4240{"bc-", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}},
4241{"bc+", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}},
4242{"bc", B(16,0,0), B_MASK, COM, PPCVLE, {BO, BI, BD}},
4243{"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}},
4244{"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}},
4245{"bcl", B(16,0,1), B_MASK, COM, PPCVLE, {BO, BI, BD}},
4246{"bca-", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}},
4247{"bca+", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}},
4248{"bca", B(16,1,0), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
4249{"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}},
4250{"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}},
4251{"bcla", B(16,1,1), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
4252
4253{"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
dce75bf9 4254{"scv", SC(17,0,1), SC_MASK, POWER9, PPCVLE, {SVC_LEV}},
14b57c7c
AM		 4255{"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
4256{"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}},
4257{"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}},
4258{"svcla", SC(17,1,1), SC_MASK, POWER, PPCVLE, {SV}},
4259
4260{"b", B(18,0,0), B_MASK, COM, PPCVLE, {LI}},
4261{"bl", B(18,0,1), B_MASK, COM, PPCVLE, {LI}},
4262{"ba", B(18,1,0), B_MASK, COM, PPCVLE, {LIA}},
4263{"bla", B(18,1,1), B_MASK, COM, PPCVLE, {LIA}},
4264
4265{"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
4266
4267{"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}},
4268{"subpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, NDXD}},
4269
4270{"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4271{"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4272{"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4273{"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4274{"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4275{"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4276{"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4277{"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4278{"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4279{"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4280{"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4281{"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4282{"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4283{"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}},
4284{"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4285{"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}},
4286{"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4287{"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4288{"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4289{"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4290{"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4291{"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4292{"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4293{"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4294
4295{"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4296{"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4297{"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4298{"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4299{"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4300{"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4301{"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4302{"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4303{"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4304{"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4305{"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4306{"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4307{"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4308{"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4309{"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4310{"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4311{"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4312{"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4313{"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4314{"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4315{"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4316{"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4317{"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4318{"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4319{"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4320{"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4321{"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4322{"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4323{"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4324{"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4325{"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4326{"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4327{"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4328{"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4329{"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4330{"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4331{"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4332{"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4333{"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4334{"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4335{"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4336{"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4337{"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4338{"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4339{"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4340{"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4341{"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4342{"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4343{"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4344{"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4345{"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4346{"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4347{"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4348{"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4349{"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4350{"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4351{"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4352{"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4353{"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4354{"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4355{"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4356{"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4357{"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4358{"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4359{"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4360{"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4361{"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4362{"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4363{"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4364{"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4365{"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4366{"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4367{"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4368{"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4369{"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4370{"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4371{"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4372{"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4373{"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4374{"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4375{"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4376{"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4377{"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4378{"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4379{"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4380{"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4381{"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4382{"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4383{"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4384{"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4385{"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4386{"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4387{"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4388{"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4389{"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4390{"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4391{"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4392{"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4393{"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4394{"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4395{"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4396{"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4397{"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4398{"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4399{"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4400{"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4401{"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4402{"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4403{"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4404{"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4405{"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4406{"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4407{"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4408{"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4409{"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4410{"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4411{"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4412{"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4413{"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4414{"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4415{"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4416{"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4417{"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4418{"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4419{"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4420{"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4421{"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4422{"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4423{"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4424{"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4425{"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4426{"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4427{"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4428{"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4429{"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4430{"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4431{"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4432{"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4433{"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4434{"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4435
4436{"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4437{"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4438{"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4439{"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4440{"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4441{"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4442{"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4443{"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4444{"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4445{"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4446{"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4447{"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4448{"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4449{"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4450{"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4451{"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4452{"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4453{"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4454{"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4455{"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4456{"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4457{"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4458{"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4459{"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4460{"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4461{"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4462{"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4463{"bdnztlrl-", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4464{"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4465{"bdnztlrl+", XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4466{"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4467{"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4468{"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4469{"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4470{"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4471{"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4472{"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4473{"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4474{"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4475{"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4476{"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4477{"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4478{"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4479{"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4480{"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4481{"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4482{"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4483{"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4484
4485{"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4486{"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4487{"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4488{"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4489{"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4490{"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4491{"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4492{"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4493
4494{"rfid", XL(19,18), 0xffffffff, PPC64, PPCVLE, {0}},
4495
4496{"crnot", XL(19,33), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}},
4497{"crnor", XL(19,33), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4498{"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCVLE, {0}},
4499
4500{"rfdi", XL(19,39), 0xffffffff, E500MC, PPCVLE, {0}},
4501{"rfi", XL(19,50), 0xffffffff, COM, PPCVLE, {0}},
4502{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}},
4503
dce75bf9 4504{"rfscv", XL(19,82), 0xffffffff, POWER9, PPCVLE, {0}},
14b57c7c
AM		 4505{"rfsvc", XL(19,82), 0xffffffff, POWER, PPCVLE, {0}},
4506
4507{"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCVLE, {0}},
4508
4509{"crandc", XL(19,129), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4510
4511{"rfebb", XL(19,146), XLS_MASK, POWER8, PPCVLE, {SXL}},
4512
4513{"isync", XL(19,150), 0xffffffff, PPCCOM, PPCVLE, {0}},
4514{"ics", XL(19,150), 0xffffffff, PWRCOM, PPCVLE, {0}},
4515
4516{"crclr", XL(19,193), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}},
4517{"crxor", XL(19,193), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4518
4519{"dnh", X(19,198), X_MASK, E500MC, PPCVLE, {DUI, DUIS}},
4520
4521{"crnand", XL(19,225), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4522
4523{"crand", XL(19,257), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4524
4525{"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPC476|PPCVLE, {0}},
4526
4527{"crset", XL(19,289), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}},
4528{"creqv", XL(19,289), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4529
4530{"urfid", XL(19,306), 0xffffffff, POWER9, PPCVLE, {0}},
4531{"stop", XL(19,370), 0xffffffff, POWER9, PPCVLE, {0}},
4532
4533{"doze", XL(19,402), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4534
4535{"crorc", XL(19,417), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4536
4537{"nap", XL(19,434), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4538
4539{"crmove", XL(19,449), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}},
4540{"cror", XL(19,449), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4541
4542{"sleep", XL(19,466), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4543{"rvwinkle", XL(19,498), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4544
4545{"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCVLE, {0}},
4546{"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCVLE, {0}},
4547
4548{"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4549{"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4550{"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4551{"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4552{"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4553{"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4554{"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4555{"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4556{"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4557{"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4558{"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4559{"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4560{"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4561{"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4562{"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4563{"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4564{"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4565{"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4566{"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4567{"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4568{"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4569{"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4570{"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4571{"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4572{"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4573{"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4574{"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4575{"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4576{"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4577{"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4578{"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4579{"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4580{"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4581{"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4582{"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4583{"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4584{"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4585{"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4586{"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4587{"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4588{"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4589{"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4590{"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4591{"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4592{"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4593{"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4594{"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4595{"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4596{"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4597{"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4598{"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4599{"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4600{"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4601{"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4602{"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4603{"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4604{"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4605{"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4606{"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4607{"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4608{"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4609{"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4610{"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4611{"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4612{"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4613{"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4614{"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4615{"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4616{"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4617{"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4618{"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4619{"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4620{"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4621{"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4622{"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4623{"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4624{"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4625{"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4626{"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4627{"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4628{"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4629{"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4630{"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4631{"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4632{"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4633{"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4634{"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4635{"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4636{"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4637{"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4638{"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4639{"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4640{"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4641{"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4642{"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4643{"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4644{"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4645{"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4646{"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4647{"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4648{"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4649{"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4650{"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4651{"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4652{"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4653{"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4654{"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4655{"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4656{"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4657{"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4658{"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4659{"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4660{"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4661{"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4662{"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4663{"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4664{"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4665{"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4666{"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4667{"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4668
4669{"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4670{"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4671{"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4672{"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4673{"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4674{"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4675{"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4676{"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4677{"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4678{"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4679{"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4680{"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4681{"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4682{"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4683{"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4684{"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4685{"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4686{"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4687{"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4688{"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4689
4690{"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4691{"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4692{"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4693{"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4694{"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4695{"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4696{"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4697{"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4698
4699{"bctar-", XLYLK(19,560,0,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4700{"bctarl-", XLYLK(19,560,0,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4701{"bctar+", XLYLK(19,560,1,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4702{"bctarl+", XLYLK(19,560,1,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4703{"bctar", XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}},
4704{"bctarl", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}},
4705
4706{"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4707{"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4708
4709{"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4710{"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4711
4712{"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
4713{"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},
4714{"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4715{"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4716{"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
4717{"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},
4718{"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4719{"rlinm.", M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4720
4721{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
4722{"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
4723
4724{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
4725{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4726{"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4727{"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
4728{"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4729{"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4730
4731{"nop", OP(24), 0xffffffff, PPCCOM, PPCVLE, {0}},
4732{"ori", OP(24), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4733{"oril", OP(24), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4734
4735{"oris", OP(25), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4736{"oriu", OP(25), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4737
4738{"xnop", OP(26), 0xffffffff, PPCCOM, PPCVLE, {0}},
4739{"xori", OP(26), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4740{"xoril", OP(26), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4741
4742{"xoris", OP(27), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4743{"xoriu", OP(27), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4744
4745{"andi.", OP(28), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4746{"andil.", OP(28), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4747
4748{"andis.", OP(29), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4749{"andiu.", OP(29), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4750
4751{"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}},
4752{"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}},
4753{"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4754{"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}},
4755{"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}},
4756{"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4757
4758{"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
4759{"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
4760
4761{"rldic", MD(30,2,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4762{"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4763
4764{"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4765{"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4766
4767{"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},
4768{"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
4769{"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},
4770{"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
4771
4772{"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
4773{"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
4774
4775{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
4776{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
a5721ba2 4777{"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
bdc70b4a 4778{"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
1cb0a767 4779
14b57c7c
AM		 4780{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4781{"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4782{"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4783{"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4784{"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, 0, {RA, RB}},
4785{"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, 0, {RA, RB}},
4786{"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4787{"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4788{"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, 0, {RA, RB}},
4789{"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, 0, {RA, RB}},
4790{"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4791{"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4792{"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, 0, {RA, RB}},
4793{"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, 0, {RA, RB}},
4794{"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4795{"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4796{"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4797{"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4798{"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, 0, {RA, RB}},
4799{"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, 0, {RA, RB}},
4800{"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4801{"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4802{"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4803{"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4804{"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, 0, {RA, RB}},
4805{"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, 0, {RA, RB}},
4806{"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4807{"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4808{"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, 0, {0}},
4809{"twu", XTO(31,4,TOU), XTO_MASK, PPCCOM, 0, {RA, RB}},
4810{"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}},
4811{"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}},
4812{"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}},
4813
4814{"lvsl", X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4815{"lvebx", X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4816{"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4817
4818{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4819{"sf", XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4820{"subc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
4821{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4822{"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4823{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
4824
4825{"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
4826{"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
4827
4828{"addc", XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4829{"a", XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4830{"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4831{"a.", XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4832
4833{"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4834{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4835
4836{"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
4837
4838{"isellt", X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4839
4840{"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, 0, {0}},
4841{"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, 0, {0}},
4842{"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4843{"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}},
4844
4845{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, COM, 0, {RT, FXM4}},
4846{"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, 0, {RT, FXM}},
4847
4848{"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}},
4849
4850{"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}},
4851
4852{"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, 0, {CT, RA0, RB}},
4853
4854{"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
4855{"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4856
4857{"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
4858{"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
4859{"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
4860{"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
4861
4862{"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
4863{"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
4864{"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
4865{"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
4866
4867{"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}},
4868{"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}},
4869
4870{"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}},
4871{"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}},
4872
4873{"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}},
4874{"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}},
4875
4876{"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4877
4878{"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}},
4879{"wait", X(31,30), XWC_MASK, POWER9, 0, {WC}},
4880
4881{"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4882
4883{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
4884{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
a5721ba2 4885{"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
bdc70b4a 4886{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
de866fcc 4887
14b57c7c
AM		 4888{"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4889{"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4890{"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
de866fcc 4891
14b57c7c 4892{"mviwsplt", X(31,46), X_MASK, PPCVEC2, 0, {VD, RA, RB}},
e67ed0e8 4893
14b57c7c 4894{"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
de866fcc 4895
14b57c7c 4896{"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
de866fcc 4897
14b57c7c 4898{"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}},
066be9f7 4899
14b57c7c 4900{"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
c0637f3a 4901
14b57c7c 4902{"iseleq", X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
de866fcc 4903
14b57c7c 4904{"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, CRB}},
de866fcc 4905
14b57c7c
AM		 4906{"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4907{"sub", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RB, RA}},
4908{"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4909{"sub.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}},
de866fcc 4910
14b57c7c
AM		 4911{"mfvsrd", X(31,51), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
4912{"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
4913{"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
4914{"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}},
e0d602ec 4915
14b57c7c 4916{"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
066be9f7 4917
14b57c7c 4918{"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}},
43e65147 4919
14b57c7c 4920{"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}},
43e65147 4921
14b57c7c
AM		 4922{"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}},
4923{"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}},
de866fcc 4924
14b57c7c
AM		 4925{"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, 0, {RA, RS}},
4926{"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, 0, {RA, RS}},
de866fcc 4927
14b57c7c
AM		 4928{"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}},
4929{"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}},
de866fcc 4930
14b57c7c
AM		 4931{"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, 0, {0}},
4932{"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, 0, {0}},
4933{"wait", X(31,62), XWC_MASK, E500MC|PPCA2, 0, {WC}},
43e65147 4934
14b57c7c 4935{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
19a6653c 4936
14b57c7c
AM		 4937{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, 0, {RA, RB}},
4938{"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, 0, {RA, RB}},
4939{"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, 0, {RA, RB}},
4940{"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, 0, {RA, RB}},
4941{"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, 0, {RA, RB}},
4942{"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, 0, {RA, RB}},
4943{"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, 0, {RA, RB}},
4944{"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, 0, {RA, RB}},
4945{"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, 0, {RA, RB}},
4946{"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, 0, {RA, RB}},
4947{"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, 0, {RA, RB}},
4948{"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, 0, {RA, RB}},
4949{"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, 0, {RA, RB}},
4950{"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, 0, {RA, RB}},
4951{"tdu", XTO(31,68,TOU), XTO_MASK, PPC64, 0, {RA, RB}},
4952{"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}},
de866fcc 4953
14b57c7c
AM		 4954{"lwfcmx", APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4955{"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
4956{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
43e65147 4957
14b57c7c
AM		 4958{"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4959{"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
de866fcc 4960
14b57c7c
AM		 4961{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}},
4962{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}},
de866fcc 4963
14b57c7c 4964{"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, 0, {SR, RS}},
de866fcc 4965
14b57c7c 4966{"mfmsr", X(31,83), XRARB_MASK, COM, 0, {RT}},
43e65147 4967
14b57c7c 4968{"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}},
de866fcc 4969
c7a8dbf9 4970{"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}},
a5721ba2 4971{"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L2OPT}},
de866fcc 4972
14b57c7c 4973{"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}},
43e65147 4974
14b57c7c 4975{"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
de866fcc 4976
14b57c7c 4977{"dni", XRC(31,97,1), XRB_MASK, E6500, 0, {DUI, DCTL}},
aea77599 4978
14b57c7c
AM		 4979{"lvx", X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4980{"lqfcmx", APU(31,103,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
de866fcc 4981
14b57c7c
AM		 4982{"neg", XO(31,104,0,0), XORB_MASK, COM, 0, {RT, RA}},
4983{"neg.", XO(31,104,0,1), XORB_MASK, COM, 0, {RT, RA}},
de866fcc 4984
14b57c7c
AM		 4985{"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
4986{"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
de866fcc 4987
14b57c7c 4988{"mvidsplt", X(31,110), X_MASK, PPCVEC2, 0, {VD, RA, RB}},
aea77599 4989
14b57c7c 4990{"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}},
de866fcc 4991
14b57c7c
AM		 4992{"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
4993{"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
4994{"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
c0637f3a 4995
14b57c7c 4996{"lharx", X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
066be9f7 4997
14b57c7c 4998{"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}},
de866fcc 4999
14b57c7c 5000{"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}},
43e65147 5001
14b57c7c 5002{"popcntb", X(31,122), XRB_MASK, POWER5, 0, {RA, RS}},
de866fcc 5003
14b57c7c
AM		 5004{"not", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RBS}},
5005{"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}},
5006{"not.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RBS}},
5007{"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}},
19a6653c 5008
14b57c7c 5009{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
43e65147 5010
fd486b63 5011{"setb", X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}},
a680de9a 5012
14b57c7c 5013{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}},
43e65147 5014
14b57c7c 5015{"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
de866fcc 5016
14b57c7c
AM		 5017{"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5018{"stbfcmx", APU(31,135,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
de866fcc 5019
14b57c7c
AM		 5020{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5021{"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5022{"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5023{"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
de866fcc 5024
14b57c7c
AM		 5025{"adde", XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5026{"ae", XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5027{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5028{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
de866fcc 5029
14b57c7c 5030{"stxsiwx", X(31,140), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
c0637f3a 5031
14b57c7c
AM		 5032{"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK, POWER8, 0, {RB}},
5033{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
de866fcc 5034
14b57c7c
AM		 5035{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, 0, {RS}},
5036{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, 0, {FXM, RS}},
5037{"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, 0, {FXM, RS}},
de866fcc 5038
14b57c7c 5039{"mtmsr", X(31,146), XRLARB_MASK, COM, 0, {RS, A_L}},
de866fcc 5040
14b57c7c 5041{"mtsle", X(31,147), XRTLRARB_MASK, POWER8, 0, {L}},
c0637f3a 5042
14b57c7c
AM		 5043{"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}},
5044{"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
e0d602ec 5045
14b57c7c 5046{"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}},
43e65147 5047
14b57c7c 5048{"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}},
43e65147 5049
14b57c7c
AM		 5050{"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
5051{"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}},
de866fcc 5052
14b57c7c
AM		 5053{"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}},
5054{"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}},
de866fcc 5055
14b57c7c
AM		 5056{"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}},
5057{"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}},
de866fcc 5058
14b57c7c 5059{"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}},
de866fcc 5060
14b57c7c 5061{"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
43e65147 5062
14b57c7c 5063{"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
43e65147 5064
14b57c7c 5065{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {E}},
43e65147 5066
14b57c7c 5067{"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
de866fcc 5068
14b57c7c
AM		 5069{"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5070{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
de866fcc 5071
14b57c7c 5072{"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
19dfcc89 5073
14b57c7c
AM		 5074{"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}},
5075{"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
de866fcc 5076
14b57c7c 5077{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, 0, {RS, A_L}},
de866fcc 5078
14b57c7c
AM		 5079{"mtvsrd", X(31,179), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
5080{"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
5081{"mtvrd", X(31,179)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5082{"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}},
e0d602ec 5083
14b57c7c 5084{"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}},
de866fcc 5085
73f07bff 5086{"stqcx.", XRC(31,182,1), X_MASK|Q_MASK, POWER8, 0, {RSQ, RA0, RB}},
14b57c7c 5087{"wchkall", X(31,182), X_MASK, PPCA2, 0, {OBF}},
e0d602ec 5088
14b57c7c
AM		 5089{"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}},
5090{"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
de866fcc 5091
14b57c7c
AM		 5092{"sliq", XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}},
5093{"sliq.", XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}},
de866fcc 5094
14b57c7c 5095{"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}},
252b5132 5096
14b57c7c 5097{"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}},
a680de9a 5098
14b57c7c 5099{"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}},
aea77599 5100
14b57c7c
AM		 5101{"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5102{"stwfcmx", APU(31,199,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
252b5132 5103
14b57c7c
AM		 5104{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5105{"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5106{"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5107{"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
252b5132 5108
14b57c7c
AM		 5109{"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5110{"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5111{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5112{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
418c1742 5113
14b57c7c 5114{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
19a6653c 5115
14b57c7c 5116{"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}},
418c1742 5117
14b57c7c
AM		 5118{"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
5119{"mtvrwa", X(31,211)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5120{"mtvsrwa", X(31,211), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
5121{"eratwe", X(31,211), X_MASK, PPCA2, 0, {RS, RA, WS}},
e0d602ec 5122
14b57c7c 5123{"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
e0d602ec 5124
14b57c7c 5125{"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}},
43e65147 5126
14b57c7c 5127{"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}},
252b5132 5128
14b57c7c
AM		 5129{"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}},
5130{"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 5131
14b57c7c
AM		 5132{"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}},
5133{"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 5134
14b57c7c 5135{"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
43e65147 5136
14b57c7c 5137{"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}},
a680de9a 5138
14b57c7c 5139{"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
7d5b217e 5140
14b57c7c
AM		 5141{"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5142{"stqfcmx", APU(31,231,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
f509565f 5143
14b57c7c
AM		 5144{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5145{"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5146{"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5147{"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
252b5132 5148
14b57c7c
AM		 5149{"mulld", XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5150{"mulld.", XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
43e65147 5151
14b57c7c
AM		 5152{"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5153{"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5154{"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5155{"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
252b5132 5156
14b57c7c
AM		 5157{"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5158{"muls", XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5159{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5160{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 5161
14b57c7c
AM		 5162{"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
5163{"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
5164{"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},
bdc70b4a 5165{"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}},
418c1742 5166
14b57c7c
AM		 5167{"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
5168{"mtvrwz", X(31,243)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5169{"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
c0637f3a 5170
14b57c7c
AM		 5171{"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
5172{"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
5173{"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
5174{"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
4fff86c5 5175
14b57c7c 5176{"stbux", X(31,247), X_MASK, COM, 0, {RS, RAS, RB}},
252b5132 5177
14b57c7c
AM		 5178{"slliq", XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}},
5179{"slliq.", XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}},
252b5132 5180
14b57c7c 5181{"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}},
066be9f7 5182
14b57c7c 5183{"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
19a6653c 5184
14b57c7c
AM		 5185{"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}},
5186{"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}},
252b5132 5187
14b57c7c 5188{"lvexbx", X(31,261), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
aea77599 5189
14b57c7c 5190{"icbt", X(31,262), XRT_MASK, PPC403, 0, {RA, RB}},
1ed8e1e4 5191
14b57c7c 5192{"lvepxl", X(31,263), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
aea77599 5193
14b57c7c
AM		 5194{"ldfcmx", APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5195{"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5196{"doz.", XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
252b5132 5197
14b57c7c 5198{"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}},
a680de9a 5199
14b57c7c
AM		 5200{"add", XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5201{"cax", XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5202{"add.", XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5203{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
418c1742 5204
14b57c7c 5205{"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}},
a680de9a 5206
14b57c7c
AM		 5207{"lxvx", X(31,268), XX1_MASK|1<<6, PPCVSX3, 0, {XT6, RA0, RB}},
5208{"lxvl", X(31,269), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
a680de9a 5209
14b57c7c 5210{"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, 0, {0}},
19a6653c 5211
14b57c7c 5212{"tlbiel", X(31,274), X_MASK|1<<20,POWER9, PPC476, {RB, RSO, RIC, PRS, X_R}},
a5721ba2 5213{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, LOPT}},
418c1742 5214
14b57c7c 5215{"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
1cb0a767 5216
73f07bff 5217{"lqarx", X(31,276), XEH_MASK|Q_MASK, POWER8, 0, {RTQ, RAX, RBX, EH}},
c0637f3a 5218
14b57c7c
AM		 5219{"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}},
5220{"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}},
1cb0a767 5221
14b57c7c
AM		 5222{"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
5223{"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
5224{"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
5225{"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
4fff86c5 5226
14b57c7c 5227{"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}},
1cb0a767 5228
14b57c7c 5229{"cdtbcd", X(31,282), XRB_MASK, POWER6, 0, {RA, RS}},
066be9f7 5230
14b57c7c
AM		 5231{"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}},
5232{"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}},
1cb0a767 5233
14b57c7c 5234{"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
1cb0a767 5235
14b57c7c 5236{"mfdcrux", X(31,291), X_MASK, PPC464, 0, {RS, RA}},
1cb0a767 5237
14b57c7c
AM		 5238{"lvexhx", X(31,293), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5239{"lvepx", X(31,295), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
aea77599 5240
14b57c7c 5241{"lxvll", X(31,301), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
a680de9a 5242
14b57c7c 5243{"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}},
c0637f3a 5244
14b57c7c
AM		 5245{"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}},
5246{"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}},
a5721ba2 5247{"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, LOPT}},
14b57c7c 5248{"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}},
1cb0a767 5249
14b57c7c 5250{"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}},
a680de9a 5251
14b57c7c 5252{"ldmx", X(31,309), X_MASK, POWER9, 0, {RT, RA0, RB}},
a680de9a 5253
14b57c7c 5254{"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
1cb0a767 5255
14b57c7c 5256{"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}},
1cb0a767 5257
14b57c7c 5258{"cbcdtd", X(31,314), XRB_MASK, POWER6, 0, {RA, RS}},
066be9f7 5259
14b57c7c
AM		 5260{"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}},
5261{"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}},
1cb0a767 5262
14b57c7c 5263{"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
1cb0a767 5264
14b57c7c
AM		 5265{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, 0, {RT}},
5266{"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, 0, {RT}},
5267{"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, 0, {RT}},
5268{"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, 0, {RT}},
5269{"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, 0, {RT}},
5270{"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, 0, {RT}},
5271{"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, 0, {RT}},
5272{"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, 0, {RT}},
5273{"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, 0, {RT}},
5274{"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, 0, {RT}},
5275{"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, 0, {RT}},
5276{"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, 0, {RT}},
5277{"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, 0, {RT}},
5278{"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, 0, {RT}},
5279{"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, 0, {RT}},
5280{"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, 0, {RT}},
5281{"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, 0, {RT}},
5282{"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, 0, {RT}},
5283{"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, 0, {RT}},
5284{"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, 0, {RT}},
5285{"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, 0, {RT}},
5286{"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, 0, {RT}},
5287{"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, 0, {RT}},
5288{"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, 0, {RT}},
5289{"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, 0, {RT}},
5290{"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, 0, {RT}},
5291{"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, 0, {RT}},
5292{"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, 0, {RT}},
5293{"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, 0, {RT}},
5294{"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, 0, {RT}},
5295{"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, 0, {RT}},
5296{"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, 0, {RT}},
5297{"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, 0, {RT}},
5298{"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, 0, {RT}},
5299{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}},
5300{"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}},
1cb0a767 5301
14b57c7c 5302{"lvexwx", X(31,325), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
aea77599 5303
14b57c7c 5304{"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}},
9fe54b1c 5305
14b57c7c
AM		 5306{"div", XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5307{"div.", XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
1cb0a767 5308
14b57c7c 5309{"lxvdsx", X(31,332), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
066be9f7 5310
14b57c7c
AM		 5311{"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}},
5312{"mftmr", X(31,366), X_MASK, PPCTMR|E6500, 0, {RT, TMR}},
1cb0a767 5313
14b57c7c
AM		 5314{"slbsync", X(31,338), 0xffffffff, POWER9, 0, {0}},
5315
5316{"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, 0, {RT}},
5317{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, 0, {RT}},
5318{"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}},
5319{"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}},
5320{"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, 0, {RT}},
5321{"mflr", XSPR(31,339, 8), XSPR_MASK, COM, 0, {RT}},
5322{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, 0, {RT}},
5323{"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, 0, {RT}},
5324{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, 0, {RT}},
5325{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}},
5326{"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}},
bdc70b4a 5327{"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}},
14b57c7c
AM		 5328{"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, 0, {RT}},
5329{"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}},
5330{"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, 0, {RT}},
5331{"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, 0, {RT}},
5332{"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, 0, {RT}},
5333{"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, 0, {RT}},
5334{"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, 0, {RT}},
5335{"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, 0, {RT}},
5336{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, 0, {RT}},
5337{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, 0, {RT}},
5338{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, 0, {RT}},
5339{"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, 0, {RT}},
5340{"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, 0, {RT}},
5341{"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, 0, {RT}},
5342{"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, 0, {RT}},
5343{"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, 0, {RT}},
5344{"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, 0, {RT}},
5345{"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, 0, {RT}},
5346{"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, 0, {RT}},
5347{"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, 0, {RT}},
5348{"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, 0, {RT}},
5349{"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, 0, {RT}},
5350{"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, 0, {RT}},
5351{"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, 0, {RT}},
5352{"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, 0, {RT}},
5353{"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, 0, {RT}},
5354{"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, 0, {RT}},
5355{"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, 0, {RT}},
5356{"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, 0, {RT}},
5357{"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, 0, {RT}},
5358{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, 0, {RT, SPRG}},
5359{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5360{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5361{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5362{"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5363{"mftbu", XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
5364{"mftb", X(31,339), X_MASK, POWER4|BOOKE, 0, {RT, TBR}},
5365{"mftbl", XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
5366{"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, 0, {RT}},
5367{"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, 0, {RT}},
5368{"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, 0, {RT}},
5369{"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, 0, {RT}},
5370{"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, 0, {RT}},
5371{"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}},
5372{"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, 0, {RT}},
5373{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, 0, {RT}},
5374{"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, 0, {RT}},
5375{"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, 0, {RT}},
5376{"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, 0, {RT}},
5377{"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, 0, {RT}},
5378{"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, 0, {RT}},
5379{"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, 0, {RT}},
5380{"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, 0, {RT}},
5381{"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, 0, {RT}},
5382{"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, 0, {RT}},
5383{"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, 0, {RT}},
5384{"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, 0, {RT}},
5385{"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, 0, {RT}},
5386{"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, 0, {RT}},
5387{"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, 0, {RT}},
5388{"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, 0, {RT}},
5389{"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, 0, {RT}},
5390{"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, 0, {RT}},
5391{"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, 0, {RT}},
5392{"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, 0, {RT}},
5393{"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, 0, {RT}},
5394{"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, 0, {RT}},
5395{"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, 0, {RT}},
5396{"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, 0, {RT}},
5397{"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, 0, {RT}},
5398{"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, 0, {RT}},
5399{"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, 0, {RT}},
5400{"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, 0, {RT}},
5401{"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, 0, {RT}},
5402{"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, 0, {RT}},
5403{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, 0, {RT}},
5404{"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, 0, {RT}},
5405{"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, 0, {RT}},
5406{"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, 0, {RT}},
5407{"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, 0, {RT}},
5408{"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5409{"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, 0, {RT}},
5410{"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5411{"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, 0, {RT}},
5412{"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}},
5413{"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5414{"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5415{"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, 0, {RT}},
5416{"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, 0, {RT}},
5417{"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, 0, {RT}},
5418{"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, 0, {RT}},
5419{"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, 0, {RT}},
5420{"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, 0, {RT}},
5421{"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, 0, {RT}},
5422{"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, 0, {RT}},
5423{"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, 0, {RT}},
5424{"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}},
5425{"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, 0, {RT}},
5426{"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, 0, {RT}},
5427{"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, 0, {RT}},
5428{"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, 0, {RT}},
5429{"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, 0, {RT}},
5430{"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, 0, {RT}},
5431{"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, 0, {RT}},
5432{"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, 0, {RT}},
5433{"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, 0, {RT}},
5434{"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, 0, {RT}},
5435{"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, 0, {RT}},
5436{"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, 0, {RT}},
5437{"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, 0, {RT}},
5438{"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, 0, {RT}},
5439{"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, 0, {RT}},
5440{"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, 0, {RT}},
5441{"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, 0, {RT}},
5442{"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, 0, {RT}},
5443{"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, 0, {RT}},
5444{"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, 0, {RT}},
5445{"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, 0, {RT}},
5446{"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, 0, {RT}},
5447{"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, 0, {RT}},
5448{"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, 0, {RT}},
5449{"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, 0, {RT}},
5450{"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, 0, {RT}},
5451{"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, 0, {RT}},
5452{"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, 0, {RT}},
5453{"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, 0, {RT}},
5454{"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, 0, {RT}},
5455{"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, 0, {RT}},
5456{"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, 0, {RT}},
5457{"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, 0, {RT}},
5458{"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, 0, {RT}},
5459{"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, 0, {RT}},
5460{"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, 0, {RT}},
5461{"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, 0, {RT}},
5462{"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, 0, {RT}},
5463{"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, 0, {RT}},
5464{"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, 0, {RT}},
5465{"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, 0, {RT}},
5466{"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, 0, {RT}},
5467{"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, 0, {RT}},
5468{"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, 0, {RT}},
5469{"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, 0, {RT}},
5470{"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, 0, {RT}},
5471{"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, 0, {RT}},
5472{"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, 0, {RT}},
5473{"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, 0, {RT}},
5474{"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, 0, {RT}},
5475{"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, 0, {RT}},
5476{"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, 0, {RT}},
5477{"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, 0, {RT}},
5478{"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, 0, {RT}},
5479{"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, 0, {RT}},
5480{"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, 0, {RT}},
5481{"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, 0, {RT}},
5482{"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, 0, {RT}},
5483{"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, 0, {RT}},
5484{"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, 0, {RT}},
5485{"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, 0, {RT}},
5486{"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, 0, {RT}},
5487{"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, 0, {RT}},
5488{"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, 0, {RT}},
5489{"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, 0, {RT}},
5490{"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, 0, {RT}},
5491{"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, 0, {RT}},
5492{"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, 0, {RT}},
5493{"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, 0, {RT}},
5494{"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, 0, {RT}},
5495{"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, 0, {RT}},
5496{"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, 0, {RT}},
5497{"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, 0, {RT}},
5498{"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, 0, {RT}},
5499{"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, 0, {RT}},
5500{"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, 0, {RS}},
5501{"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, 0, {RT}},
5502{"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, 0, {RT}},
5503{"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, 0, {RT}},
5504{"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, 0, {RT}},
5505{"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, 0, {RT}},
5506{"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, 0, {RT}},
5507{"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, 0, {RT}},
5508{"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, 0, {RT}},
5509{"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, 0, {RT}},
5510{"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, 0, {RT}},
5511{"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, 0, {RT}},
5512{"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, 0, {RT}},
5513{"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, 0, {RT}},
5514{"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, 0, {RT}},
5515{"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, 0, {RT}},
5516{"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}},
5517
5518{"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}},
5519
5520{"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
5521
5522{"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}},
5523
5524{"lvxl", X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
5525
5526{"abs", XO(31,360,0,0), XORB_MASK, M601, 0, {RT, RA}},
5527{"abs.", XO(31,360,0,1), XORB_MASK, M601, 0, {RT, RA}},
5528
5529{"divs", XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5530{"divs.", XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5531
5532{"lxvwsx", X(31,364), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5533
5534{"tlbia", X(31,370), 0xffffffff, PPC, E500|TITAN, {0}},
1cb0a767 5535
db76a700 5536{"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}},
14b57c7c 5537{"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}},
db76a700 5538{"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371|POWER4, {RT}},
1cb0a767 5539
14b57c7c 5540{"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}},
1cb0a767 5541
14b57c7c 5542{"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
1cb0a767 5543
14b57c7c 5544{"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}},
1cb0a767 5545
14b57c7c 5546{"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
066be9f7 5547
14b57c7c
AM		 5548{"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}},
5549{"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}},
1cb0a767 5550
14b57c7c 5551{"stvexbx", X(31,389), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
aea77599 5552
14b57c7c
AM		 5553{"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5554{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
1cb0a767 5555
14b57c7c
AM		 5556{"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5557{"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5558{"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5559{"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
066be9f7 5560
14b57c7c
AM		 5561{"stxvx", X(31,396), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
5562{"stxvl", X(31,397), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
a680de9a 5563
14b57c7c 5564{"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
1cb0a767 5565
14b57c7c 5566{"slbmte", X(31,402), XRA_MASK, PPC64, 0, {RS, RB}},
1cb0a767 5567
14b57c7c 5568{"mtvsrws", X(31,403), XX1RB_MASK, PPCVSX3, 0, {XT6, RA}},
a680de9a 5569
14b57c7c 5570{"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}},
c0637f3a 5571
14b57c7c
AM		 5572{"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
5573{"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
e0d602ec 5574
14b57c7c 5575{"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}},
1cb0a767 5576
14b57c7c
AM		 5577{"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}},
5578{"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}},
1cb0a767 5579
14b57c7c 5580{"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
1cb0a767 5581
14b57c7c 5582{"mtdcrux", X(31,419), X_MASK, PPC464, 0, {RA, RS}},
1cb0a767 5583
14b57c7c 5584{"stvexhx", X(31,421), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
aea77599 5585
14b57c7c 5586{"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}},
aea77599 5587
14b57c7c
AM		 5588{"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5589{"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5590{"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5591{"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
066be9f7 5592
14b57c7c 5593{"stxvll", X(31,429), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
a680de9a 5594
14b57c7c 5595{"clrbhrb", X(31,430), 0xffffffff, POWER8, 0, {0}},
c0637f3a 5596
14b57c7c 5597{"slbie", X(31,434), XRTRA_MASK, PPC64, 0, {RB}},
1cb0a767 5598
14b57c7c 5599{"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
a680de9a 5600
14b57c7c 5601{"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
1cb0a767 5602
14b57c7c 5603{"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}},
1cb0a767 5604
14b57c7c 5605{"mdors", 0x7f9ce378, 0xffffffff, E500MC, 0, {0}},
1cb0a767 5606
14b57c7c 5607{"miso", 0x7f5ad378, 0xffffffff, E6500, 0, {0}},
aea77599 5608
9f6a6cc0 5609/* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for
14b57c7c
AM		 5610 "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */
5611{"yield", 0x7f7bdb78, 0xffffffff, POWER7, 0, {0}},
5612{"mdoio", 0x7fbdeb78, 0xffffffff, POWER7, 0, {0}},
5613{"mdoom", 0x7fdef378, 0xffffffff, POWER7, 0, {0}},
5614{"mr", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RBS}},
5615{"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}},
5616{"mr.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RBS}},
5617{"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}},
5618
5619{"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, 0, {RS}},
5620{"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, 0, {RS}},
5621{"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, 0, {RS}},
5622{"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, 0, {RS}},
5623{"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, 0, {RS}},
5624{"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, 0, {RS}},
5625{"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, 0, {RS}},
5626{"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, 0, {RS}},
5627{"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, 0, {RS}},
5628{"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, 0, {RS}},
5629{"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, 0, {RS}},
5630{"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, 0, {RS}},
5631{"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, 0, {RS}},
5632{"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, 0, {RS}},
5633{"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, 0, {RS}},
5634{"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, 0, {RS}},
5635{"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, 0, {RS}},
5636{"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, 0, {RS}},
5637{"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, 0, {RS}},
5638{"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, 0, {RS}},
5639{"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, 0, {RS}},
5640{"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, 0, {RS}},
5641{"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, 0, {RS}},
5642{"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, 0, {RS}},
5643{"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, 0, {RS}},
5644{"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, 0, {RS}},
5645{"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, 0, {RS}},
5646{"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, 0, {RS}},
5647{"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, 0, {RS}},
5648{"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, 0, {RS}},
5649{"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, 0, {RS}},
5650{"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, 0, {RS}},
5651{"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, 0, {RS}},
5652{"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, 0, {RS}},
5653{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}},
5654{"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, 0, {SPR, RS}},
5655
5656{"stvexwx", X(31,453), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5657
5658{"dccci", X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
5659{"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, 0, {CT}},
5660
5661{"divdu", XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5662{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5663
5664{"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5665{"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5666
5667{"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}},
5668{"mttmr", X(31,494), X_MASK, PPCTMR|E6500, 0, {TMR, RS}},
5669
5670{"slbieg", X(31,466), XRA_MASK, POWER9, 0, {RS, RB}},
5671
5672{"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, 0, {RS}},
5673{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, 0, {RS}},
5674{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, 0, {RS}},
5675{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, 0, {RS}},
5676{"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, 0, {RS}},
5677{"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, 0, {RS}},
5678{"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}},
5679{"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}},
5680{"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, TITAN, {RS}},
5681{"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, TITAN, {RS}},
5682{"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, 0, {RS}},
5683{"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, 0, {RS}},
5684{"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN, {RS}},
5685{"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, 0, {RS}},
5686{"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, 0, {RS}},
5687{"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, 0, {RS}},
5688{"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, 0, {RS}},
5689{"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, 0, {RS}},
5690{"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, 0, {RS}},
5691{"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, 0, {RS}},
5692{"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, 0, {RS}},
5693{"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, 0, {RS}},
5694{"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, 0, {RS}},
5695{"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, 0, {RS}},
5696{"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, 0, {RS}},
5697{"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, 0, {RS}},
5698{"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, 0, {RS}},
5699{"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, 0, {RS}},
5700{"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, 0, {RS}},
5701{"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, 0, {RS}},
5702{"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, 0, {RS}},
5703{"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, 0, {RS}},
5704{"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, 0, {RS}},
5705{"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, 0, {RS}},
5706{"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, 0, {RS}},
5707{"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, 0, {RS}},
5708{"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, 0, {RS}},
5709{"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, 0, {RS}},
5710{"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, 0, {RS}},
5711{"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, 0, {RS}},
5712{"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, 0, {RS}},
5713{"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, 0, {RS}},
5714{"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC, 0, {SPRG, RS}},
5715{"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, 0, {RS}},
5716{"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, 0, {RS}},
5717{"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, 0, {RS}},
5718{"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, 0, {RS}},
5719{"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5720{"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5721{"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5722{"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5723{"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, 0, {RS}},
5724{"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}},
5725{"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, 0, {RS}},
5726{"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, 0, {RS}},
5727{"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, 0, {RS}},
5728{"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, 0, {RS}},
5729{"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, 0, {RS}},
5730{"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, 0, {RS}},
5731{"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, 0, {RS}},
5732{"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, 0, {RS}},
5733{"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, 0, {RS}},
5734{"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, 0, {RS}},
5735{"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, 0, {RS}},
5736{"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, 0, {RS}},
5737{"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, 0, {RS}},
5738{"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, 0, {RS}},
5739{"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, 0, {RS}},
5740{"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, 0, {RS}},
5741{"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, 0, {RS}},
5742{"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, 0, {RS}},
5743{"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, 0, {RS}},
5744{"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, 0, {RS}},
5745{"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, 0, {RS}},
5746{"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, 0, {RS}},
5747{"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, 0, {RS}},
5748{"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, 0, {RS}},
5749{"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, 0, {RS}},
5750{"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, 0, {RS}},
5751{"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, 0, {RS}},
5752{"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, 0, {RS}},
5753{"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, 0, {RS}},
5754{"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, 0, {RS}},
5755{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, 0, {RS}},
5756{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, 0, {RS}},
5757{"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, 0, {RS}},
5758{"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, 0, {RS}},
5759{"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, 0, {RS}},
5760{"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, 0, {RS}},
5761{"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5762{"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, 0, {RS}},
5763{"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5764{"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, 0, {RS}},
5765{"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, 0, {RS}},
5766{"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5767{"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5768{"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}},
5769{"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}},
5770{"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}},
5771{"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, 0, {RS}},
5772{"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, 0, {RS}},
5773{"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, 0, {RS}},
5774{"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, 0, {RS}},
5775{"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, 0, {RS}},
5776{"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, 0, {RS}},
5777{"mtppr", XSPR(31,467,896), XSPR_MASK, POWER7, 0, {RS}},
5778{"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER7, 0, {RS}},
5779{"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, 0, {RS}},
5780{"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, 0, {RS}},
5781{"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, 0, {RS}},
5782{"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, 0, {RS}},
5783{"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, 0, {RS}},
5784{"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, 0, {RS}},
5785{"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, 0, {RS}},
5786{"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, 0, {RS}},
5787{"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, 0, {RS}},
5788{"mtrmmucr", XSPR(31,467,946), XSPR_MASK, TITAN, 0, {RS}},
5789{"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, 0, {RS}},
5790{"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, 0, {RS}},
5791{"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, 0, {RS}},
5792{"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, 0, {RS}},
5793{"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, 0, {RS}},
5794{"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, 0, {RS}},
5795{"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, 0, {RS}},
5796{"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, 0, {RS}},
5797{"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, 0, {RS}},
5798{"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, 0, {RS}},
5799{"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, 0, {RS}},
5800{"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, 0, {RS}},
5801{"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, 0, {RS}},
5802{"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, 0, {RS}},
5803{"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, 0, {RS}},
5804{"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, 0, {RS}},
5805{"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, 0, {RS}},
5806{"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, 0, {RS}},
5807{"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, 0, {RS}},
5808{"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, 0, {RS}},
5809{"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, 0, {RS}},
5810{"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, 0, {RS}},
5811{"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, 0, {RS}},
5812{"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, 0, {RS}},
5813{"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, 0, {RS}},
5814{"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, 0, {RS}},
5815{"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, 0, {RS}},
5816{"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, 0, {RS}},
5817{"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, 0, {RS}},
5818{"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, 0, {RS}},
5819{"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, 0, {RS}},
5820{"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, 0, {RS}},
5821{"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, 0, {RS}},
5822{"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, 0, {RS}},
5823{"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, 0, {RS}},
5824{"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, 0, {RS}},
5825{"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, 0, {RS}},
5826{"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, 0, {RS}},
5827{"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, 0, {RS}},
5828{"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, 0, {RS}},
5829{"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, 0, {RS}},
5830{"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, 0, {RS}},
5831{"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, 0, {RS}},
5832{"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, 0, {RS}},
5833{"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, 0, {RS}},
5834{"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, 0, {RS}},
5835{"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, 0, {RS}},
5836{"mtspr", X(31,467), X_MASK, COM, 0, {SPR, RS}},
5837
5838{"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}},
5839
5840{"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}},
5841{"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}},
5842
5843{"dsn", X(31,483), XRT_MASK, E500MC, 0, {RA, RB}},
5844
5845{"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2|PPC476, {RT, RA0, RB}},
5846
5847{"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5848
5849{"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5850
5851{"nabs", XO(31,488,0,0), XORB_MASK, M601, 0, {RT, RA}},
5852{"nabs.", XO(31,488,0,1), XORB_MASK, M601, 0, {RT, RA}},
5853
5854{"divd", XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5855{"divd.", XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5856
5857{"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5858{"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5859
5860{"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
5861
5862{"slbia", X(31,498), 0xff1fffff, POWER6, 0, {IH}},
4bc0608a 5863{"slbia", X(31,498), 0xffffffff, PPC64, POWER6, {0}},
1cb0a767 5864
14b57c7c 5865{"cli", X(31,502), XRB_MASK, POWER, 0, {RT, RA}},
1cb0a767 5866
14b57c7c 5867{"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
066be9f7 5868
14b57c7c 5869{"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}},
1cb0a767 5870
14b57c7c 5871{"mcrxr", X(31,512), XBFRARB_MASK, COM, POWER7, {BF}},
252b5132 5872
dfdaec14 5873{"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}},
14b57c7c 5874{"lbdx", X(31,515), X_MASK, E500MC, 0, {RT, RA, RB}},
19a6653c 5875
14b57c7c 5876{"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}},
252b5132 5877
14b57c7c
AM		 5878{"lvlx", X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}},
5879{"lbfcmux", APU(31,519,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
252b5132 5880
14b57c7c
AM		 5881{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5882{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5883{"subco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
5884{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5885{"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5886{"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
43e65147 5887
14b57c7c
AM		 5888{"addco", XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5889{"ao", XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5890{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5891{"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 5892
14b57c7c 5893{"lxsspx", X(31,524), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
c0637f3a 5894
14b57c7c 5895{"clcs", X(31,531), XRB_MASK, M601, 0, {RT, RA}},
418c1742 5896
14b57c7c 5897{"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}},
418c1742 5898
14b57c7c
AM		 5899{"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}},
5900{"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 5901
14b57c7c
AM		 5902{"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
5903{"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 5904
14b57c7c 5905{"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
702f0fb4 5906
14b57c7c
AM		 5907{"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
5908{"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
5909{"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
5910{"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
252b5132 5911
14b57c7c
AM		 5912{"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}},
5913{"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}},
23976049 5914
14b57c7c
AM		 5915{"cnttzw", XRC(31,538,0), XRB_MASK, POWER9, 0, {RA, RS}},
5916{"cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, 0, {RA, RS}},
a680de9a 5917
14b57c7c
AM		 5918{"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}},
5919{"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}},
f509565f 5920
14b57c7c
AM		 5921{"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}},
5922{"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 5923
dfdaec14 5924{"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}},
14b57c7c 5925{"lhdx", X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}},
19a6653c 5926
14b57c7c 5927{"lvtrx", X(31,549), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
aea77599 5928
14b57c7c 5929{"bbelr", X(31,550), X_MASK, PPCBRLK, 0, {0}},
418c1742 5930
14b57c7c
AM		 5931{"lvrx", X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}},
5932{"lhfcmux", APU(31,551,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
252b5132 5933
14b57c7c
AM		 5934{"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5935{"subo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RB, RA}},
5936{"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5937{"subo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RB, RA}},
252b5132 5938
14b57c7c 5939{"tlbsync", X(31,566), 0xffffffff, PPC, 0, {0}},
252b5132 5940
14b57c7c 5941{"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
252b5132 5942
14b57c7c
AM		 5943{"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, 0, {RA, RS}},
5944{"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, 0, {RA, RS}},
a680de9a 5945
14b57c7c 5946{"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}},
a680de9a 5947
dfdaec14 5948{"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}},
14b57c7c 5949{"lwdx", X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}},
19a6653c 5950
14b57c7c 5951{"lvtlx", X(31,581), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
aea77599 5952
14b57c7c 5953{"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}},
a680de9a 5954
14b57c7c 5955{"lwfcmux", APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
081ba1b3 5956
14b57c7c 5957{"lxsdx", X(31,588), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
066be9f7 5958
14b57c7c 5959{"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}},
252b5132 5960
14b57c7c
AM		 5961{"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, NBI}},
5962{"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}},
252b5132 5963
dc302c00 5964{"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}},
e01d869a 5965{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
14b57c7c 5966{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, 0, {0}},
fd486b63
PB		 5967{"sync", X(31,598), XSYNCLE_MASK, E6500, 0, {LS, ESYNC}},
5968{"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}},
14b57c7c
AM		 5969{"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, 0, {0}},
5970{"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}},
5971{"lwsync", X(31,598), 0xffffffff, E500, 0, {0}},
5972{"dcs", X(31,598), 0xffffffff, PWRCOM, 0, {0}},
418c1742 5973
14b57c7c 5974{"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
23976049 5975
066be9f7 5976{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}},
14b57c7c 5977{"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}},
252b5132 5978
14b57c7c 5979{"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}},
19a6653c 5980
14b57c7c 5981{"lvswx", X(31,613), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
aea77599 5982
14b57c7c 5983{"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}},
a680de9a 5984
14b57c7c 5985{"lqfcmux", APU(31,615,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
081ba1b3 5986
14b57c7c
AM		 5987{"nego", XO(31,104,1,0), XORB_MASK, COM, 0, {RT, RA}},
5988{"nego.", XO(31,104,1,1), XORB_MASK, COM, 0, {RT, RA}},
252b5132 5989
14b57c7c
AM		 5990{"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
5991{"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
252b5132 5992
14b57c7c 5993{"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}},
252b5132 5994
14b57c7c 5995{"dclst", X(31,630), XRB_MASK, M601, 0, {RS, RA}},
252b5132 5996
14b57c7c 5997{"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
252b5132 5998
dfdaec14 5999{"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}},
14b57c7c 6000{"stbdx", X(31,643), X_MASK, E500MC, 0, {RS, RA, RB}},
19a6653c 6001
14b57c7c
AM		 6002{"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}},
6003{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
23976049 6004
14b57c7c 6005{"stxsspx", X(31,652), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
c0637f3a 6006
14b57c7c 6007{"tbegin.", XRC(31,654,1), XRTLRARB_MASK, PPCHTM, 0, {HTM_R}},
5817ffd1 6008
14b57c7c
AM		 6009{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6010{"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6011{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6012{"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 6013
14b57c7c
AM		 6014{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6015{"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6016{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6017{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 6018
14b57c7c 6019{"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}},
418c1742 6020
14b57c7c 6021{"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}},
252b5132 6022
14b57c7c
AM		 6023{"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}},
6024{"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
418c1742 6025
14b57c7c
AM		 6026{"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
6027{"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
252b5132 6028
14b57c7c 6029{"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
ede602d7 6030
14b57c7c
AM		 6031{"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}},
6032{"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 6033
14b57c7c
AM		 6034{"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}},
6035{"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 6036
dfdaec14 6037{"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}},
14b57c7c 6038{"sthdx", X(31,675), X_MASK, E500MC, 0, {RS, RA, RB}},
19a6653c 6039
14b57c7c 6040{"stvfrx", X(31,677), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
aea77599 6041
14b57c7c
AM		 6042{"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}},
6043{"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
252b5132 6044
14b57c7c
AM		 6045{"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, 0, {0}},
6046{"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, 0, {HTM_A}},
5817ffd1 6047
14b57c7c 6048{"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
066be9f7 6049
14b57c7c 6050{"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
252b5132 6051
14b57c7c
AM		 6052{"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}},
6053{"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}},
252b5132 6054
dfdaec14 6055{"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}},
14b57c7c 6056{"stwdx", X(31,707), X_MASK, E500MC, 0, {RS, RA, RB}},
19a6653c 6057
14b57c7c 6058{"stvflx", X(31,709), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
aea77599 6059
14b57c7c 6060{"stwat", X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}},
a680de9a 6061
14b57c7c 6062{"stwfcmux", APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
081ba1b3 6063
14b57c7c 6064{"stxsdx", X(31,716), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
066be9f7 6065
14b57c7c 6066{"tcheck", X(31,718), XRTBFRARB_MASK, PPCHTM, 0, {BF}},
5817ffd1 6067
14b57c7c
AM		 6068{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
6069{"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
6070{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
6071{"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
418c1742 6072
14b57c7c
AM		 6073{"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
6074{"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
6075{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
6076{"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
fdd12ef3 6077
14b57c7c
AM		 6078{"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}},
6079{"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}},
252b5132 6080
14b57c7c 6081{"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
066be9f7 6082
14b57c7c 6083{"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
252b5132 6084
14b57c7c
AM		 6085{"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}},
6086{"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}},
418c1742 6087
14b57c7c
AM		 6088{"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}},
6089{"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 6090
066be9f7 6091{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}},
14b57c7c 6092{"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}},
252b5132 6093
14b57c7c 6094{"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}},
19a6653c 6095
14b57c7c 6096{"stvswx", X(31,741), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
aea77599 6097
14b57c7c 6098{"stdat", X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}},
a680de9a 6099
14b57c7c 6100{"stqfcmux", APU(31,743,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
081ba1b3 6101
14b57c7c
AM		 6102{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
6103{"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
6104{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
6105{"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
252b5132 6106
14b57c7c
AM		 6107{"mulldo", XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6108{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
252b5132 6109
14b57c7c
AM		 6110{"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
6111{"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
6112{"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
6113{"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
418c1742 6114
14b57c7c
AM		 6115{"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6116{"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6117{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6118{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
702f0fb4 6119
14b57c7c
AM		 6120{"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM, 0, {0}},
6121{"tresume.", XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, 0, {0}},
6122{"tsr.", XRC(31,750,1), XRTLRARB_MASK,PPCHTM, 0, {L}},
5817ffd1 6123
14b57c7c 6124{"darn", X(31,755), XLRAND_MASK, POWER9, 0, {RT, LRAND}},
a680de9a 6125
14b57c7c
AM		 6126{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
6127{"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, 0, {RA0, RB}},
252b5132 6128
14b57c7c 6129{"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
252b5132 6130
14b57c7c
AM		 6131{"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}},
6132{"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}},
252b5132 6133
14b57c7c 6134{"lvsm", X(31,773), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
a680de9a 6135
fd486b63 6136{"copy", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}},
a680de9a 6137
14b57c7c
AM		 6138{"stvepxl", X(31,775), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6139{"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}},
6140{"ldfcmux", APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
ede602d7 6141
14b57c7c
AM		 6142{"dozo", XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6143{"dozo.", XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
252b5132 6144
14b57c7c
AM		 6145{"addo", XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6146{"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6147{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6148{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
252b5132 6149
14b57c7c
AM		 6150{"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}},
6151{"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}},
a680de9a 6152
14b57c7c
AM		 6153{"lxvw4x", X(31,780), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
6154{"lxsibzx", X(31,781), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
066be9f7 6155
14b57c7c 6156{"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
5817ffd1 6157
14b57c7c 6158{"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
252b5132 6159
14b57c7c 6160{"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}},
252b5132 6161
14b57c7c 6162{"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}},
252b5132 6163
73f07bff 6164{"lfdpx", X(31,791), X_MASK|Q_MASK, POWER6, POWER7, {FRTp, RA0, RB}},
14b57c7c 6165{"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}},
418c1742 6166
14b57c7c
AM		 6167{"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6168{"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
6169{"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6170{"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
fdd12ef3 6171
14b57c7c
AM		 6172{"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}},
6173{"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}},
252b5132 6174
14b57c7c 6175{"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}},
19a6653c 6176
14b57c7c
AM		 6177{"lvtrxl", X(31,805), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
6178{"stvepx", X(31,807), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6179{"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}},
252b5132 6180
14b57c7c
AM		 6181{"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6182{"lxsihzx", X(31,813), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
a680de9a 6183
14b57c7c 6184{"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
5817ffd1 6185
14b57c7c 6186{"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}},
252b5132 6187
14b57c7c 6188{"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}},
e0d602ec 6189
14b57c7c 6190{"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}},
252b5132 6191
14b57c7c 6192{"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, 0, {STRM}},
252b5132 6193
14b57c7c 6194{"lfqux", X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}},
fdd12ef3 6195
14b57c7c
AM		 6196{"srawi", XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}},
6197{"srai", XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}},
6198{"srawi.", XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}},
6199{"srai.", XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}},
702f0fb4 6200
14b57c7c
AM		 6201{"sradi", XS(31,413,0), XS_MASK, PPC64, 0, {RA, RS, SH6}},
6202{"sradi.", XS(31,413,1), XS_MASK, PPC64, 0, {RA, RS, SH6}},
e0c21649 6203
14b57c7c 6204{"lvtlxl", X(31,837), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
aea77599 6205
fd486b63 6206{"cpabort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}},
a680de9a 6207
14b57c7c
AM		 6208{"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6209{"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
252b5132 6210
14b57c7c 6211{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
a680de9a 6212{"lxvx", X(31,844), XX1_MASK, POWER8, POWER9|PPCVSX3, {XT6, RA0, RB}},
9b4e5766 6213
14b57c7c 6214{"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
5817ffd1 6215
14b57c7c 6216{"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}},
e0d602ec 6217
fd486b63 6218{"slbiag", X(31,850), XRARB_MASK, POWER9, 0, {RS}},
14b57c7c 6219{"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
a680de9a 6220{"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}},
252b5132 6221
14b57c7c 6222{"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}},
418c1742 6223
9fe54b1c 6224{"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}},
14b57c7c
AM		 6225{"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, 0, {MO}},
6226{"eieio", XMBAR(31,854,1),0xffffffff, E500, 0, {0}},
6227{"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, 0, {0}},
418c1742 6228
14b57c7c 6229{"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}},
418c1742 6230
14b57c7c 6231{"lvswxl", X(31,869), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
aea77599 6232
14b57c7c
AM		 6233{"abso", XO(31,360,1,0), XORB_MASK, M601, 0, {RT, RA}},
6234{"abso.", XO(31,360,1,1), XORB_MASK, M601, 0, {RT, RA}},
702f0fb4 6235
14b57c7c
AM		 6236{"divso", XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6237{"divso.", XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
252b5132 6238
14b57c7c 6239{"lxvb16x", X(31,876), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
a680de9a 6240
14b57c7c 6241{"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
5817ffd1 6242
14b57c7c 6243{"rmieg", X(31,882), XRTRA_MASK, POWER9, 0, {RB}},
a680de9a 6244
14b57c7c 6245{"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}},
252b5132 6246
14b57c7c 6247{"msgsync", X(31,886), 0xffffffff, POWER9, 0, {0}},
a680de9a 6248
14b57c7c 6249{"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}},
066be9f7 6250
14b57c7c
AM		 6251{"extswsli", XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}},
6252{"extswsli.", XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}},
a680de9a 6253
fd486b63 6254{"paste.", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}},
a680de9a 6255
14b57c7c
AM		 6256{"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}},
6257{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
252b5132 6258
14b57c7c
AM		 6259{"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6260{"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6261{"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6262{"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
066be9f7 6263
14b57c7c
AM		 6264{"stxvw4x", X(31,908), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
6265{"stxsibx", X(31,909), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
066be9f7 6266
14b57c7c 6267{"tabort.", XRC(31,910,1), XRTRB_MASK, PPCHTM, 0, {RA}},
5817ffd1 6268
14b57c7c
AM		 6269{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
6270{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
252b5132 6271
14b57c7c 6272{"slbmfee", X(31,915), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
a680de9a 6273{"slbmfee", X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}},
702f0fb4 6274
14b57c7c 6275{"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}},
f5c120c5 6276
14b57c7c 6277{"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}},
252b5132 6278
73f07bff 6279{"stfdpx", X(31,919), X_MASK|Q_MASK, POWER6, POWER7, {FRSp, RA0, RB}},
14b57c7c 6280{"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}},
6ba045b1 6281
14b57c7c
AM		 6282{"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}},
6283{"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}},
702f0fb4 6284
14b57c7c
AM		 6285{"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}},
6286{"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}},
252b5132 6287
14b57c7c
AM		 6288{"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
6289{"exts", XRC(31,922,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
6290{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
6291{"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
702f0fb4 6292
14b57c7c 6293{"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}},
19a6653c 6294
14b57c7c 6295{"stvfrxl", X(31,933), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
aea77599 6296
14b57c7c 6297{"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}},
a5721ba2
AM		 6298{"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L2}},
6299{"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}},
85d4ac0b 6300
14b57c7c 6301{"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}},
6ba045b1 6302
14b57c7c
AM		 6303{"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6304{"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6305{"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6306{"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
066be9f7 6307
14b57c7c
AM		 6308{"stxvh8x", X(31,940), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6309{"stxsihx", X(31,941), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
a680de9a 6310
14b57c7c 6311{"treclaim.", XRC(31,942,1), XRTRB_MASK, PPCHTM, 0, {RA}},
5817ffd1 6312
e0d602ec
BE		 6313{"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
6314{"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
14b57c7c 6315{"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
702f0fb4 6316
14b57c7c 6317{"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}},
252b5132 6318
14b57c7c
AM		 6319{"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}},
6320{"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}},
51b5d4a8 6321
14b57c7c 6322{"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}},
252b5132 6323
14b57c7c
AM		 6324{"sraiq", XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}},
6325{"sraiq.", XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}},
252b5132 6326
14b57c7c
AM		 6327{"extsb", XRC(31,954,0), XRB_MASK, PPC, 0, {RA, RS}},
6328{"extsb.", XRC(31,954,1), XRB_MASK, PPC, 0, {RA, RS}},
252b5132 6329
14b57c7c 6330{"stvflxl", X(31,965), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
aea77599 6331
14b57c7c
AM		 6332{"iccci", X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
6333{"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, 0, {CT}},
43e65147 6334
14b57c7c
AM		 6335{"divduo", XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6336{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
43e65147 6337
14b57c7c
AM		 6338{"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6339{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
252b5132 6340
14b57c7c 6341{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
a680de9a 6342{"stxvx", X(31,972), XX1_MASK, POWER8, POWER9|PPCVSX3, {XS6, RA0, RB}},
9b4e5766 6343
9fe54b1c 6344{"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
14b57c7c
AM		 6345{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, 0, {RT, RA}},
6346{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, 0, {RT, RA}},
6347{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
418c1742 6348
14b57c7c 6349{"slbfee.", XRC(31,979,1), XRA_MASK, POWER6, 0, {RT, RB}},
c4e676f1 6350
14b57c7c 6351{"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}},
252b5132 6352
14b57c7c 6353{"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}},
252b5132 6354
14b57c7c 6355{"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}},
702f0fb4 6356
14b57c7c
AM		 6357{"extsw", XRC(31,986,0), XRB_MASK, PPC64, 0, {RA, RS}},
6358{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, 0, {RA, RS}},
252b5132 6359
14b57c7c 6360{"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
19a6653c 6361
14b57c7c 6362{"stvswxl", X(31,997), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
aea77599 6363
14b57c7c 6364{"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}},
252b5132 6365
14b57c7c
AM		 6366{"nabso", XO(31,488,1,0), XORB_MASK, M601, 0, {RT, RA}},
6367{"nabso.", XO(31,488,1,1), XORB_MASK, M601, 0, {RT, RA}},
252b5132 6368
14b57c7c
AM		 6369{"divdo", XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6370{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
43e65147 6371
14b57c7c
AM		 6372{"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6373{"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
418c1742 6374
14b57c7c 6375{"stxvb16x", X(31,1004), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
a680de9a 6376
14b57c7c 6377{"trechkpt.", XRC(31,1006,1), XRTRARB_MASK,PPCHTM, 0, {0}},
702f0fb4 6378
14b57c7c 6379{"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}},
252b5132 6380
14b57c7c 6381{"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}},
418c1742 6382
14b57c7c
AM		 6383{"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
6384{"dclz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
786e2c0f 6385
14b57c7c 6386{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
ede602d7 6387
14b57c7c 6388{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}},
252b5132 6389
14b57c7c
AM		 6390{"cctpl", 0x7c210b78, 0xffffffff, CELL, 0, {0}},
6391{"cctpm", 0x7c421378, 0xffffffff, CELL, 0, {0}},
6392{"cctph", 0x7c631b78, 0xffffffff, CELL, 0, {0}},
252b5132 6393
14b57c7c
AM		 6394{"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
6395{"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
6396{"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, 0, {0}},
252b5132 6397
14b57c7c
AM		 6398{"db8cyc", 0x7f9ce378, 0xffffffff, CELL, 0, {0}},
6399{"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, 0, {0}},
6400{"db12cyc", 0x7fdef378, 0xffffffff, CELL, 0, {0}},
6401{"db16cyc", 0x7ffffb78, 0xffffffff, CELL, 0, {0}},
252b5132 6402
14b57c7c
AM		 6403{"lwz", OP(32), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
6404{"l", OP(32), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
252b5132 6405
14b57c7c
AM		 6406{"lwzu", OP(33), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAL}},
6407{"lu", OP(33), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
252b5132 6408
14b57c7c 6409{"lbz", OP(34), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
252b5132 6410
14b57c7c 6411{"lbzu", OP(35), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
252b5132 6412
14b57c7c
AM		 6413{"stw", OP(36), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},
6414{"st", OP(36), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
252b5132 6415
14b57c7c
AM		 6416{"stwu", OP(37), OP_MASK, PPCCOM, PPCVLE, {RS, D, RAS}},
6417{"stu", OP(37), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
252b5132 6418
14b57c7c 6419{"stb", OP(38), OP_MASK, COM, PPCVLE, {RS, D, RA0}},
252b5132 6420
14b57c7c 6421{"stbu", OP(39), OP_MASK, COM, PPCVLE, {RS, D, RAS}},
252b5132 6422
14b57c7c 6423{"lhz", OP(40), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
252b5132 6424
14b57c7c 6425{"lhzu", OP(41), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
252b5132 6426
14b57c7c 6427{"lha", OP(42), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
252b5132 6428
14b57c7c 6429{"lhau", OP(43), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
252b5132 6430
14b57c7c 6431{"sth", OP(44), OP_MASK, COM, PPCVLE, {RS, D, RA0}},
252b5132 6432
14b57c7c 6433{"sthu", OP(45), OP_MASK, COM, PPCVLE, {RS, D, RAS}},
252b5132 6434
14b57c7c
AM		 6435{"lmw", OP(46), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAM}},
6436{"lm", OP(46), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
252b5132 6437
14b57c7c
AM		 6438{"stmw", OP(47), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},
6439{"stm", OP(47), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
252b5132 6440
14b57c7c 6441{"lfs", OP(48), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},
252b5132 6442
14b57c7c 6443{"lfsu", OP(49), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}},
252b5132 6444
14b57c7c 6445{"lfd", OP(50), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},
252b5132 6446
14b57c7c 6447{"lfdu", OP(51), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}},
252b5132 6448
14b57c7c 6449{"stfs", OP(52), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
adadcc0c 6450
14b57c7c 6451{"stfsu", OP(53), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
252b5132 6452
14b57c7c 6453{"stfd", OP(54), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
c3d65c1c 6454
14b57c7c 6455{"stfdu", OP(55), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
252b5132 6456
73f07bff 6457{"lq", OP(56), OP_MASK|Q_MASK, POWER4, PPC476|PPCVLE, {RTQ, DQ, RAQ}},
14b57c7c
AM		 6458{"psq_l", OP(56), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
6459{"lfq", OP(56), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},
418c1742 6460
14b57c7c
AM		 6461{"lxsd", DSO(57,2), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}},
6462{"lxssp", DSO(57,3), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}},
73f07bff 6463{"lfdp", OP(57), OP_MASK|Q_MASK, POWER6, POWER7|PPCVLE, {FRTp, DS, RA0}},
14b57c7c
AM		 6464{"psq_lu", OP(57), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
6465{"lfqu", OP(57), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},
802a735e 6466
14b57c7c
AM		 6467{"ld", DSO(58,0), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
6468{"ldu", DSO(58,1), DS_MASK, PPC64, PPCVLE, {RT, DS, RAL}},
6469{"lwa", DSO(58,2), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
702f0fb4 6470
14b57c7c
AM		 6471{"dadd", XRC(59,2,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6472{"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
252b5132 6473
14b57c7c
AM		 6474{"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
6475{"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
252b5132 6476
14b57c7c
AM		 6477{"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6478{"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
252b5132 6479
14b57c7c
AM		 6480{"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6481{"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
252b5132 6482
14b57c7c
AM		 6483{"fadds", A(59,21,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6484{"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
252b5132 6485
14b57c7c
AM		 6486{"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}},
6487{"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}},
252b5132 6488
14b57c7c
AM		 6489{"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6490{"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6491{"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6492{"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
1ed8e1e4 6493
14b57c7c
AM		 6494{"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6495{"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
252b5132 6496
14b57c7c
AM		 6497{"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6498{"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6499{"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6500{"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
252b5132 6501
14b57c7c
AM		 6502{"fmsubs", A(59,28,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6503{"fmsubs.", A(59,28,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
252b5132 6504
14b57c7c
AM		 6505{"fmadds", A(59,29,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6506{"fmadds.", A(59,29,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
252b5132 6507
14b57c7c
AM		 6508{"fnmsubs", A(59,30,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6509{"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
702f0fb4 6510
14b57c7c
AM		 6511{"fnmadds", A(59,31,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6512{"fnmadds.", A(59,31,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
702f0fb4 6513
14b57c7c
AM		 6514{"dmul", XRC(59,34,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6515{"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
702f0fb4 6516
14b57c7c
AM		 6517{"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
6518{"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
702f0fb4 6519
14b57c7c
AM		 6520{"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6521{"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
702f0fb4 6522
14b57c7c
AM		 6523{"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
6524{"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
702f0fb4 6525
14b57c7c
AM		 6526{"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6527{"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
702f0fb4 6528
14b57c7c
AM		 6529{"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6530{"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
702f0fb4 6531
14b57c7c 6532{"dcmpo", X(59,130), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
702f0fb4 6533
14b57c7c
AM		 6534{"dtstex", X(59,162), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6535{"dtstdc", Z(59,194), Z_MASK, POWER6, PPCVLE, {BF, FRA, DCM}},
6536{"dtstdg", Z(59,226), Z_MASK, POWER6, PPCVLE, {BF, FRA, DGM}},
6537
6538{"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6539{"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6540
6541{"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6542{"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6543
6544{"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6545{"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6546
6547{"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
6548{"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
6549
6550{"dxex", XRC(59,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6551{"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6552
6553{"dsub", XRC(59,514,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6554{"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6555
6556{"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6557{"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6558
6559{"dcmpu", X(59,642), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6560
6561{"dtstsf", X(59,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6562{"dtstsfi", X(59,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRB}},
6563
6564{"drsp", XRC(59,770,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6565{"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6566
6567{"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6568{"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6569
6570{"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
6571{"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
6572
6573{"fcfids", XRC(59,846,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6574{"fcfids.", XRC(59,846,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6575
6576{"diex", XRC(59,866,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6577{"diex.", XRC(59,866,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6578
6579{"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6580{"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6581
6582{"xsaddsp", XX3(60,0), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6583{"xsmaddasp", XX3(60,1), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6584{"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, SHW}},
6585{"xscmpeqdp", XX3(60,3), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6586{"xsrsqrtesp", XX2(60,10), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6587{"xssqrtsp", XX2(60,11), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6588{"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, XC6}},
6589{"xssubsp", XX3(60,8), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6590{"xsmaddmsp", XX3(60,9), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6591{"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S, DMEX}},
6592{"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6593{"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6594{"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6595{"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, DM}},
6596{"xscmpgtdp", XX3(60,11), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6597{"xsresp", XX2(60,26), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6598{"xsmulsp", XX3(60,16), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6599{"xsmsubasp", XX3(60,17), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6600{"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6601{"xscmpgedp", XX3(60,19), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6602{"xsdivsp", XX3(60,24), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6603{"xsmsubmsp", XX3(60,25), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6604{"xxperm", XX3(60,26), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6605{"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6606{"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6607{"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6608{"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6609{"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6610{"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6611{"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6612{"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6613{"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6614{"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6615{"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6616{"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6617{"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6618{"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6619{"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6620{"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6621{"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6622{"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6623{"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6624{"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6625{"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6626{"xxpermr", XX3(60,58), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6627{"xscmpexpdp", XX3(60,59), XX3BF_MASK, PPCVSX3, PPCVLE, {BF, XA6, XB6}},
6628{"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6629{"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6630{"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6631{"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6632{"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6633{"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6634{"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6635{"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6636{"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6637{"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6638{"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6639{"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6640{"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6641{"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6642{"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6643{"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6644{"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6645{"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6646{"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6647{"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCVLE, {XT6, XB6, UIM}},
6648{"xxextractuw", XX2(60,165), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}},
6649{"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6650{"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6651{"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6652{"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6653{"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6654{"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6655{"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6656{"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6657{"xxspltib", X(60,360), XX1_MASK|3<<19, PPCVSX3, PPCVLE, {XT6, IMM8}},
6658{"xxinsertw", XX2(60,181), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}},
6659{"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6660{"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6661{"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6662{"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6663{"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6664{"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6665{"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6666{"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6667{"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6668{"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6669{"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6670{"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6671{"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6672{"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6673{"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6674{"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6675{"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6676{"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6677{"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6678{"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6679{"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6680{"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6681{"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6682{"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6683{"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6684{"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6685{"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6686{"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6687{"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6688{"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6689{"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6690{"xsmaxcdp", XX3(60,128), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6691{"xsnmaddasp", XX3(60,129), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6692{"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6693{"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6694{"xscvdpspn", XX2(60,267), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6695{"xsmincdp", XX3(60,136), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6696{"xsnmaddmsp", XX3(60,137), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6697{"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6698{"xsrsp", XX2(60,281), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6699{"xsmaxjdp", XX3(60,144), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6700{"xsnmsubasp", XX3(60,145), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6701{"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6702{"xscvuxdsp", XX2(60,296), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6703{"xststdcsp", XX2(60,298), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}},
6704{"xsminjdp", XX3(60,152), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6705{"xsnmsubmsp", XX3(60,153), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6706{"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6707{"xscvsxdsp", XX2(60,312), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6708{"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6709{"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6710{"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6711{"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6712{"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6713{"xscvspdpn", XX2(60,331), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6714{"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6715{"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6716{"xxlorc", XX3(60,170), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6717{"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6718{"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6719{"xsxexpdp", XX2VA(60,347,0),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
6720{"xsxsigdp", XX2VA(60,347,1),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
6721{"xscvhpdp", XX2VA(60,347,16),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6722{"xscvdphp", XX2VA(60,347,17),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6723{"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6724{"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6725{"xxlnand", XX3(60,178), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6726{"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6727{"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6728{"xststdcdp", XX2(60,362), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}},
6729{"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6730{"xxleqv", XX3(60,186), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6731{"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6732{"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6733{"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6734{"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6735{"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6736{"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6737{"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6738{"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6739{"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6740{"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6741{"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6742{"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6743{"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6744{"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6745{"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6746{"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}},
6747{"xviexpsp", XX3(60,216), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6748{"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6749{"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6750{"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6751{"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6752{"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6753{"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6754{"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6755{"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCVLE, {XT6, RA, RB}},
6756{"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6757{"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6758{"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6759{"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6760{"xvxexpdp", XX2VA(60,475,0),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6761{"xvxsigdp", XX2VA(60,475,1),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6762{"xxbrh", XX2VA(60,475,7),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6763{"xvxexpsp", XX2VA(60,475,8),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6764{"xvxsigsp", XX2VA(60,475,9),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6765{"xxbrw", XX2VA(60,475,15),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6766{"xxbrd", XX2VA(60,475,23),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6767{"xvcvhpsp", XX2VA(60,475,24),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6768{"xvcvsphp", XX2VA(60,475,25),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6769{"xxbrq", XX2VA(60,475,31),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6770{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6771{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6772{"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6773{"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6774{"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6775{"xvtstdcdp", XX2(60,490), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}},
6776{"xviexpdp", XX3(60,248), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6777{"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6778{"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6779{"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6780
6781{"psq_st", OP(60), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
6782{"stfq", OP(60), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
6783
6784{"lxv", DQX(61,1), DQX_MASK, PPCVSX3, PPCVLE, {XTQ6, DQ, RA0}},
6785{"stxv", DQX(61,5), DQX_MASK, PPCVSX3, PPCVLE, {XSQ6, DQ, RA0}},
6786{"stxsd", DSO(61,2), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},
6787{"stxssp", DSO(61,3), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},
73f07bff 6788{"stfdp", OP(61), OP_MASK|Q_MASK, POWER6, POWER7|PPCVLE, {FRSp, DS, RA0}},
14b57c7c
AM		 6789{"psq_stu", OP(61), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
6790{"stfqu", OP(61), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
6791
6792{"std", DSO(62,0), DS_MASK, PPC64, PPCVLE, {RS, DS, RA0}},
6793{"stdu", DSO(62,1), DS_MASK, PPC64, PPCVLE, {RS, DS, RAS}},
73f07bff 6794{"stq", DSO(62,2), DS_MASK|Q_MASK, POWER4, PPC476|PPCVLE, {RSQ, DS, RA0}},
14b57c7c
AM		 6795
6796{"fcmpu", X(63,0), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}},
6797
73f07bff
AM		 6798{"daddq", XRC(63,2,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6799{"daddq.", XRC(63,2,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
14b57c7c 6800
73f07bff
AM		 6801{"dquaq", ZRC(63,3,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}},
6802{"dquaq.", ZRC(63,3,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}},
14b57c7c
AM		 6803
6804{"xsaddqp", XRC(63,4,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6805{"xsaddqpo", XRC(63,4,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6806
6807{"xsrqpi", ZRC(63,5,0), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
6808{"xsrqpix", ZRC(63,5,1), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
6809
6810{"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
6811{"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
6812
6813{"frsp", XRC(63,12,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6814{"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6815
6816{"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6817{"fcir", XRC(63,14,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6818{"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6819{"fcir.", XRC(63,14,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6820
6821{"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6822{"fcirz", XRC(63,15,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6823{"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6824{"fcirz.", XRC(63,15,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6825
6826{"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6827{"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6828{"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6829{"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6830
6831{"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6832{"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6833{"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6834{"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6835
6836{"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6837{"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6838{"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6839{"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6840
6841{"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}},
6842{"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}},
6843
6844{"fsel", A(63,23,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6845{"fsel.", A(63,23,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6846
6847{"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6848{"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6849{"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6850{"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
1ed8e1e4 6851
14b57c7c
AM		 6852{"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6853{"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}},
6854{"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6855{"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}},
252b5132 6856
14b57c7c
AM		 6857{"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6858{"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6859{"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6860{"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
252b5132 6861
14b57c7c
AM		 6862{"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6863{"fms", A(63,28,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6864{"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6865{"fms.", A(63,28,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
252b5132 6866
14b57c7c
AM		 6867{"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6868{"fma", A(63,29,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6869{"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6870{"fma.", A(63,29,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
252b5132 6871
14b57c7c
AM		 6872{"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6873{"fnms", A(63,30,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6874{"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6875{"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
252b5132 6876
14b57c7c
AM		 6877{"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6878{"fnma", A(63,31,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6879{"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6880{"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
252b5132 6881
14b57c7c 6882{"fcmpo", X(63,32), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}},
252b5132 6883
73f07bff
AM		 6884{"dmulq", XRC(63,34,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6885{"dmulq.", XRC(63,34,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
702f0fb4 6886
73f07bff
AM		 6887{"drrndq", ZRC(63,35,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}},
6888{"drrndq.", ZRC(63,35,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}},
702f0fb4 6889
14b57c7c
AM		 6890{"xsmulqp", XRC(63,36,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6891{"xsmulqpo", XRC(63,36,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 6892
14b57c7c 6893{"xsrqpxp", Z(63,37), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
a680de9a 6894
14b57c7c
AM		 6895{"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCVLE, {BT}},
6896{"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCVLE, {BT}},
252b5132 6897
14b57c7c
AM		 6898{"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6899{"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
252b5132 6900
14b57c7c 6901{"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
252b5132 6902
73f07bff
AM		 6903{"dscliq", ZRC(63,66,0), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6904{"dscliq.", ZRC(63,66,1), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
702f0fb4 6905
73f07bff
AM		 6906{"dquaiq", ZRC(63,67,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
6907{"dquaiq.", ZRC(63,67,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
702f0fb4 6908
14b57c7c
AM		 6909{"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCVLE, {BT}},
6910{"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCVLE, {BT}},
252b5132 6911
14b57c7c
AM		 6912{"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6913{"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
252b5132 6914
73f07bff
AM		 6915{"dscriq", ZRC(63,98,0), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6916{"dscriq.", ZRC(63,98,1), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
702f0fb4 6917
73f07bff
AM		 6918{"drintxq", ZRC(63,99,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6919{"drintxq.", ZRC(63,99,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
702f0fb4 6920
14b57c7c 6921{"xscpsgnqp", X(63,100), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 6922
14b57c7c 6923{"ftdiv", X(63,128), XBF_MASK, POWER7, PPCVLE, {BF, FRA, FRB}},
066be9f7 6924
14b57c7c 6925{"dcmpoq", X(63,130), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
702f0fb4 6926
14b57c7c 6927{"xscmpoqp", X(63,132), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
a680de9a 6928
14b57c7c
AM		 6929{"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}},
6930{"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}},
6931{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}},
6932{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}},
252b5132 6933
14b57c7c
AM		 6934{"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6935{"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
252b5132 6936
14b57c7c
AM		 6937{"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6938{"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6939{"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6940{"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
066be9f7 6941
14b57c7c 6942{"ftsqrt", X(63,160), XBF_MASK|FRA_MASK, POWER7, PPCVLE, {BF, FRB}},
066be9f7 6943
14b57c7c 6944{"dtstexq", X(63,162), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
a680de9a 6945
14b57c7c 6946{"xscmpexpqp", X(63,164), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
a680de9a 6947
14b57c7c
AM		 6948{"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DCM}},
6949{"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DGM}},
702f0fb4 6950
73f07bff
AM		 6951{"drintnq", ZRC(63,227,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6952{"drintnq.", ZRC(63,227,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
702f0fb4 6953
73f07bff
AM		 6954{"dctqpq", XRC(63,258,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
6955{"dctqpq.", XRC(63,258,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
702f0fb4 6956
14b57c7c
AM		 6957{"fabs", XRC(63,264,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6958{"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
252b5132 6959
14b57c7c
AM		 6960{"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6961{"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
702f0fb4 6962
73f07bff
AM		 6963{"ddedpdq", XRC(63,322,0), X_MASK|Q_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
6964{"ddedpdq.", XRC(63,322,1), X_MASK|Q_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
702f0fb4 6965
14b57c7c
AM		 6966{"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6967{"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
702f0fb4 6968
14b57c7c
AM		 6969{"xsmaddqp", XRC(63,388,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6970{"xsmaddqpo", XRC(63,388,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 6971
14b57c7c
AM		 6972{"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6973{"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
a680de9a 6974
14b57c7c
AM		 6975{"xsmsubqp", XRC(63,420,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6976{"xsmsubqpo", XRC(63,420,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 6977
14b57c7c
AM		 6978{"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6979{"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
a680de9a 6980
14b57c7c
AM		 6981{"xsnmaddqp", XRC(63,452,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6982{"xsnmaddqpo", XRC(63,452,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 6983
14b57c7c
AM		 6984{"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6985{"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
a680de9a 6986
14b57c7c
AM		 6987{"xsnmsubqp", XRC(63,484,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6988{"xsnmsubqpo", XRC(63,484,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 6989
14b57c7c
AM		 6990{"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6991{"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
ce7a772b 6992
73f07bff
AM		 6993{"dsubq", XRC(63,514,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6994{"dsubq.", XRC(63,514,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
702f0fb4 6995
14b57c7c
AM		 6996{"xssubqp", XRC(63,516,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6997{"xssubqpo", XRC(63,516,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 6998
73f07bff
AM		 6999{"ddivq", XRC(63,546,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
7000{"ddivq.", XRC(63,546,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
702f0fb4 7001
14b57c7c
AM		 7002{"xsdivqp", XRC(63,548,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
7003{"xsdivqpo", XRC(63,548,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 7004
14b57c7c
AM		 7005{"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}},
7006{"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}},
252b5132 7007
6fd3a02d
PB		 7008{"mffsce", XMMF(63,583,0,1), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}},
7009{"mffscdrn", XMMF(63,583,2,4), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}},
7010{"mffscdrni", XMMF(63,583,2,5), XMMF_MASK|(3<<14), POWER9, PPCVLE, {FRT, DRM}},
7011{"mffscrn", XMMF(63,583,2,6), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}},
7012{"mffscrni", XMMF(63,583,2,7), XMMF_MASK|(7<<13), POWER9, PPCVLE, {FRT, RM}},
7013{"mffsl", XMMF(63,583,3,0), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}},
7014
14b57c7c 7015{"dcmpuq", X(63,642), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
702f0fb4 7016
14b57c7c 7017{"xscmpuqp", X(63,644), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
a680de9a 7018
14b57c7c
AM		 7019{"dtstsfq", X(63,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRBp}},
7020{"dtstsfiq", X(63,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRBp}},
a680de9a 7021
14b57c7c 7022{"xststdcqp", X(63,708), X_MASK, PPCVSX3, PPCVLE, {BF, VB, DCMX}},
702f0fb4 7023
14b57c7c
AM		 7024{"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}},
7025{"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
7026{"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}},
7027{"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
252b5132 7028
73f07bff
AM		 7029{"drdpq", XRC(63,770,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
7030{"drdpq.", XRC(63,770,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
702f0fb4 7031
73f07bff
AM		 7032{"dcffixq", XRC(63,802,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
7033{"dcffixq.", XRC(63,802,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
702f0fb4 7034
14b57c7c
AM		 7035{"xsabsqp", XVA(63,804,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7036{"xsxexpqp", XVA(63,804,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7037{"xsnabsqp", XVA(63,804,8), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7038{"xsnegqp", XVA(63,804,16), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7039{"xsxsigqp", XVA(63,804,18), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7040{"xssqrtqp", XVARC(63,804,27,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7041{"xssqrtqpo", XVARC(63,804,27,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
a680de9a 7042
14b57c7c
AM		 7043{"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7044{"fctid", XRC(63,814,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
7045{"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7046{"fctid.", XRC(63,814,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
252b5132 7047
14b57c7c
AM		 7048{"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7049{"fctidz", XRC(63,815,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
7050{"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7051{"fctidz.", XRC(63,815,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
252b5132 7052
73f07bff
AM		 7053{"denbcdq", XRC(63,834,0), X_MASK|Q_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
7054{"denbcdq.", XRC(63,834,1), X_MASK|Q_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
702f0fb4 7055
14b57c7c
AM		 7056{"xscvqpuwz", XVA(63,836,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7057{"xscvudqp", XVA(63,836,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7058{"xscvqpswz", XVA(63,836,9), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7059{"xscvsdqp", XVA(63,836,10), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7060{"xscvqpudz", XVA(63,836,17), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7061{"xscvqpdp", XVARC(63,836,20,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7062{"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7063{"xscvdpqp", XVA(63,836,22), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
7064{"xscvqpsdz", XVA(63,836,25), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
a680de9a 7065
14b57c7c 7066{"fmrgow", X(63,838), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
c0637f3a 7067
14b57c7c
AM		 7068{"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7069{"fcfid", XRC(63,846,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
7070{"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
7071{"fcfid.", XRC(63,846,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
252b5132 7072
73f07bff
AM		 7073{"diexq", XRC(63,866,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
7074{"diexq.", XRC(63,866,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
702f0fb4 7075
14b57c7c 7076{"xsiexpqp", X(63,868), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
a680de9a 7077
14b57c7c
AM		 7078{"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
7079{"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
066be9f7 7080
14b57c7c
AM		 7081{"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
7082{"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
066be9f7 7083
14b57c7c 7084{"fmrgew", X(63,966), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
c0637f3a 7085
14b57c7c
AM		 7086{"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
7087{"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
252b5132
RH		 7088};
7089
7090const int powerpc_num_opcodes =
7091 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
7092\f
b9c361e0
JL		 7093/* The VLE opcode table.
7094
7095 The format of this opcode table is the same as the main opcode table. */
7096
7097const struct powerpc_opcode vle_opcodes[] = {
14b57c7c
AM		 7098{"se_illegal", C(0), C_MASK, PPCVLE, 0, {}},
7099{"se_isync", C(1), C_MASK, PPCVLE, 0, {}},
7100{"se_sc", C(2), C_MASK, PPCVLE, 0, {}},
7101{"se_blr", C_LK(2,0), C_LK_MASK, PPCVLE, 0, {}},
7102{"se_blrl", C_LK(2,1), C_LK_MASK, PPCVLE, 0, {}},
7103{"se_bctr", C_LK(3,0), C_LK_MASK, PPCVLE, 0, {}},
7104{"se_bctrl", C_LK(3,1), C_LK_MASK, PPCVLE, 0, {}},
7105{"se_rfi", C(8), C_MASK, PPCVLE, 0, {}},
7106{"se_rfci", C(9), C_MASK, PPCVLE, 0, {}},
7107{"se_rfdi", C(10), C_MASK, PPCVLE, 0, {}},
7108{"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}},
7109{"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, 0, {RX}},
7110{"se_neg", SE_R(0,3), SE_R_MASK, PPCVLE, 0, {RX}},
7111{"se_mflr", SE_R(0,8), SE_R_MASK, PPCVLE, 0, {RX}},
7112{"se_mtlr", SE_R(0,9), SE_R_MASK, PPCVLE, 0, {RX}},
7113{"se_mfctr", SE_R(0,10), SE_R_MASK, PPCVLE, 0, {RX}},
7114{"se_mtctr", SE_R(0,11), SE_R_MASK, PPCVLE, 0, {RX}},
7115{"se_extzb", SE_R(0,12), SE_R_MASK, PPCVLE, 0, {RX}},
7116{"se_extsb", SE_R(0,13), SE_R_MASK, PPCVLE, 0, {RX}},
7117{"se_extzh", SE_R(0,14), SE_R_MASK, PPCVLE, 0, {RX}},
7118{"se_extsh", SE_R(0,15), SE_R_MASK, PPCVLE, 0, {RX}},
7119{"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7120{"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, 0, {ARX, RY}},
7121{"se_mfar", SE_RR(0,3), SE_RR_MASK, PPCVLE, 0, {RX, ARY}},
7122{"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7123{"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7124{"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7125{"se_subf", SE_RR(1,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7126{"se_cmp", SE_RR(3,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7127{"se_cmpl", SE_RR(3,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7128{"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7129{"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7130
7131{"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
dfdaec14 7132{"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
14b57c7c 7133{"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
dfdaec14 7134{"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
14b57c7c
AM		 7135{"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7136{"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7137{"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7138{"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7139{"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7140{"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7141{"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7142{"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7143{"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7144{"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7145{"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7146{"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7147{"e_nop", SCI8(6,26), 0xffffffff, PPCVLE, 0, {0}},
7148{"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7149{"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7150{"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7151{"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7152{"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7153{"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7154{"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7155{"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7156{"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7157{"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7158{"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7159{"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7160{"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
dfdaec14
AJ		 7161{"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7162{"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7163{"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7164{"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7165{"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7166{"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7167{"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7168{"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7169{"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7170{"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
14b57c7c
AM		 7171{"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}},
7172{"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7173{"e_sub16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}},
7174
7175{"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7176{"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7177{"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7178{"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7179{"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7180{"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7181{"se_andi", SE_IM5(11,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7182
7183{"e_lbz", OP(12), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7184{"e_stb", OP(13), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7185{"e_lha", OP(14), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7186
7187{"se_srw", SE_RR(16,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7188{"se_sraw", SE_RR(16,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7189{"se_slw", SE_RR(16,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7190{"se_nop", SE_RR(17,0), 0xffff, PPCVLE, 0, {0}},
7191{"se_or", SE_RR(17,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7192{"se_andc", SE_RR(17,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7193{"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7194{"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7195{"se_li", IM7(9), IM7_MASK, PPCVLE, 0, {RX, UI7}},
7196
7197{"e_lwz", OP(20), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7198{"e_stw", OP(21), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7199{"e_lhz", OP(22), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7200{"e_sth", OP(23), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7201
7202{"se_bclri", SE_IM5(24,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7203{"se_bgeni", SE_IM5(24,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7204{"se_bseti", SE_IM5(25,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7205{"se_btsti", SE_IM5(25,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7206{"se_srwi", SE_IM5(26,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7207{"se_srawi", SE_IM5(26,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7208{"se_slwi", SE_IM5(27,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7209
7210{"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7211{"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7212{"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7213{"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7214{"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7215{"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
7216{"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
7217{"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
14b57c7c
AM		 7218{"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7219{"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
14b57c7c
AM		 7220{"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
7221{"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7222{"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
7223{"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7224{"e_li", LI20(28,0), LI20_MASK, PPCVLE, 0, {RT, IMM20}},
7225{"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}},
7226{"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RT, SH, MBE, ME}},
7227{"e_b", BD24(30,0,0), BD24_MASK, PPCVLE, 0, {B24}},
7228{"e_bl", BD24(30,0,1), BD24_MASK, PPCVLE, 0, {B24}},
7229{"e_bdnz", EBD15(30,8,BO32DNZ,0), EBD15_MASK, PPCVLE, 0, {B15}},
7230{"e_bdnzl", EBD15(30,8,BO32DNZ,1), EBD15_MASK, PPCVLE, 0, {B15}},
7231{"e_bdz", EBD15(30,8,BO32DZ,0), EBD15_MASK, PPCVLE, 0, {B15}},
7232{"e_bdzl", EBD15(30,8,BO32DZ,1), EBD15_MASK, PPCVLE, 0, {B15}},
7233{"e_bge", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7234{"e_bgel", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7235{"e_bnl", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7236{"e_bnll", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7237{"e_blt", EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7238{"e_bltl", EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7239{"e_bgt", EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7240{"e_bgtl", EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7241{"e_ble", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7242{"e_blel", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7243{"e_bng", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7244{"e_bngl", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7245{"e_bne", EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7246{"e_bnel", EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7247{"e_beq", EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7248{"e_beql", EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7249{"e_bso", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7250{"e_bsol", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7251{"e_bun", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7252{"e_bunl", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7253{"e_bns", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7254{"e_bnsl", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7255{"e_bnu", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7256{"e_bnul", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7257{"e_bc", BD15(30,8,0), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
7258{"e_bcl", BD15(30,8,1), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
7259
7260{"e_bf", EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7261{"e_bfl", EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7262{"e_bt", EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7263{"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7264
7265{"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
7266{"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
7267{"e_crandc", XL(31,129), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7268{"e_crnand", XL(31,225), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7269{"e_crnot", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BBA}},
7270{"e_crnor", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7271{"e_crclr", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}},
7272{"e_crxor", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7273{"e_mcrf", XL(31,16), XL_MASK, PPCVLE, 0, {CRD, CR}},
7274{"e_slwi", EX(31,112), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7275{"e_slwi.", EX(31,113), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7276
7277{"e_crand", XL(31,257), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7278
7279{"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
7280{"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
7281
7282{"e_crset", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}},
7283{"e_creqv", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7284
7285{"e_rlwi", EX(31,624), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7286{"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7287
7288{"e_crorc", XL(31,417), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7289
7290{"e_crmove", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BBA}},
7291{"e_cror", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7292
7293{"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, 0, {RS}},
7294
7295{"e_srwi", EX(31,1136), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7296{"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7297
7298{"se_lbz", SD4(8), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
7299
7300{"se_stb", SD4(9), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
7301
7302{"se_lhz", SD4(10), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
7303
7304{"se_sth", SD4(11), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
7305
7306{"se_lwz", SD4(12), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
7307
7308{"se_stw", SD4(13), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
7309
7310{"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7311{"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7312{"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7313{"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7314{"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7315{"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7316{"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7317{"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}},
7318{"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7319{"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7320{"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7321{"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7322{"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7323{"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}},
7324{"se_bc", BD8IO(28), BD8IO_MASK, PPCVLE, 0, {BO16, BI16, B8}},
7325{"se_b", BD8(58,0,0), BD8_MASK, PPCVLE, 0, {B8}},
7326{"se_bl", BD8(58,0,1), BD8_MASK, PPCVLE, 0, {B8}},
b9c361e0
JL		 7327};
7328
7329const int vle_num_opcodes =
7330 sizeof (vle_opcodes) / sizeof (vle_opcodes[0]);
7331\f
252b5132
RH		 7332/* The macro table. This is only used by the assembler. */
7333
7334/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
7335 when x=0; 32-x when x is between 1 and 31; are negative if x is
7336 negative; and are 32 or more otherwise. This is what you want
7337 when, for instance, you are emulating a right shift by a
7338 rotate-left-and-mask, because the underlying instructions support
7339 shifts of size 0 but not shifts of size 32. By comparison, when
7340 extracting x bits from some word you want to use just 32-x, because
7341 the underlying instructions don't support extracting 0 bits but do
7342 support extracting the whole word (32 bits in this case). */
7343
7344const struct powerpc_macro powerpc_macros[] = {
de866fcc
AM		 7345{"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"},
7346{"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"},
bdc7fcfe
AM		 7347{"extrdi", 4, PPC64, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
7348{"extrdi.", 4, PPC64, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
de866fcc
AM		 7349{"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"},
7350{"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"},
7351{"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
7352{"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
7353{"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"},
7354{"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"},
7355{"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
7356{"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
7357{"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"},
7358{"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"},
7359{"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"},
14b57c7c 7360{"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"},
de866fcc
AM		 7361
7362{"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
7363{"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
7364{"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7365{"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7366{"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7367{"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7368{"insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
7369{"insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
7370{"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7371{"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7372{"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"},
7373{"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
7374{"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"},
7375{"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"},
7376{"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7377{"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7378{"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7379{"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7380{"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"},
7381{"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
7382{"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
7383{"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
a4ebc835
AM		 7384
7385{"e_extlwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"},
7386{"e_extrwi", 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7387{"e_inslwi", 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7388{"e_insrwi", 4, PPCVLE, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
7389{"e_rotlwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31"},
7390{"e_rotrwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7391{"e_slwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31-(%2)"},
7392{"e_srwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7393{"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"},
7394{"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"},
7395{"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
252b5132
RH		 7396};
7397
7398const int powerpc_num_macros =
7399 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
GDB Binutils - Deliverables
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