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[deliverable/binutils-gdb.git] / opcodes / ppc-opc.c
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252b5132 1/* ppc-opc.c -- PowerPC opcode list
5e8cb021
AM		 2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
3 2005 Free Software Foundation, Inc.
252b5132
RH		 4 Written by Ian Lance Taylor, Cygnus Support
5
112290ab 6 This file is part of GDB, GAS, and the GNU binutils.
252b5132 7
112290ab
NC		 8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 2, or (at your option) any later version.
252b5132 12
112290ab
NC		 13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
252b5132 17
112290ab
NC		 18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
f4321104
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132
RH		 22
23#include <stdio.h>
0d8dfecf 24#include "sysdep.h"
252b5132
RH		 25#include "opcode/ppc.h"
26#include "opintl.h"
27
28/* This file holds the PowerPC opcode table. The opcode table
29 includes almost all of the extended instruction mnemonics. This
30 permits the disassembler to use them, and simplifies the assembler
31 logic, at the cost of increasing the table size. The table is
32 strictly constant data, so the compiler should be able to put it in
33 the .text section.
34
35 This file also holds the operand table. All knowledge about
36 inserting operands into instructions and vice-versa is kept in this
37 file. */
38\f
39/* Local insertion and extraction functions. */
40
c168870a
AM		 41static unsigned long insert_bat (unsigned long, long, int, const char **);
42static long extract_bat (unsigned long, int, int *);
43static unsigned long insert_bba (unsigned long, long, int, const char **);
44static long extract_bba (unsigned long, int, int *);
45static unsigned long insert_bd (unsigned long, long, int, const char **);
46static long extract_bd (unsigned long, int, int *);
47static unsigned long insert_bdm (unsigned long, long, int, const char **);
48static long extract_bdm (unsigned long, int, int *);
49static unsigned long insert_bdp (unsigned long, long, int, const char **);
50static long extract_bdp (unsigned long, int, int *);
c168870a
AM		 51static unsigned long insert_bo (unsigned long, long, int, const char **);
52static long extract_bo (unsigned long, int, int *);
53static unsigned long insert_boe (unsigned long, long, int, const char **);
54static long extract_boe (unsigned long, int, int *);
55static unsigned long insert_dq (unsigned long, long, int, const char **);
56static long extract_dq (unsigned long, int, int *);
57static unsigned long insert_ds (unsigned long, long, int, const char **);
58static long extract_ds (unsigned long, int, int *);
59static unsigned long insert_de (unsigned long, long, int, const char **);
60static long extract_de (unsigned long, int, int *);
61static unsigned long insert_des (unsigned long, long, int, const char **);
62static long extract_des (unsigned long, int, int *);
63static unsigned long insert_fxm (unsigned long, long, int, const char **);
64static long extract_fxm (unsigned long, int, int *);
65static unsigned long insert_li (unsigned long, long, int, const char **);
66static long extract_li (unsigned long, int, int *);
67static unsigned long insert_mbe (unsigned long, long, int, const char **);
68static long extract_mbe (unsigned long, int, int *);
69static unsigned long insert_mb6 (unsigned long, long, int, const char **);
70static long extract_mb6 (unsigned long, int, int *);
71static unsigned long insert_nb (unsigned long, long, int, const char **);
72static long extract_nb (unsigned long, int, int *);
73static unsigned long insert_nsi (unsigned long, long, int, const char **);
74static long extract_nsi (unsigned long, int, int *);
75static unsigned long insert_ral (unsigned long, long, int, const char **);
76static unsigned long insert_ram (unsigned long, long, int, const char **);
77static unsigned long insert_raq (unsigned long, long, int, const char **);
78static unsigned long insert_ras (unsigned long, long, int, const char **);
79static unsigned long insert_rbs (unsigned long, long, int, const char **);
80static long extract_rbs (unsigned long, int, int *);
81static unsigned long insert_rsq (unsigned long, long, int, const char **);
82static unsigned long insert_rtq (unsigned long, long, int, const char **);
83static unsigned long insert_sh6 (unsigned long, long, int, const char **);
84static long extract_sh6 (unsigned long, int, int *);
85static unsigned long insert_spr (unsigned long, long, int, const char **);
86static long extract_spr (unsigned long, int, int *);
da99ee72
AM		 87static unsigned long insert_sprg (unsigned long, long, int, const char **);
88static long extract_sprg (unsigned long, int, int *);
c168870a
AM		 89static unsigned long insert_tbr (unsigned long, long, int, const char **);
90static long extract_tbr (unsigned long, int, int *);
91static unsigned long insert_ev2 (unsigned long, long, int, const char **);
92static long extract_ev2 (unsigned long, int, int *);
93static unsigned long insert_ev4 (unsigned long, long, int, const char **);
94static long extract_ev4 (unsigned long, int, int *);
95static unsigned long insert_ev8 (unsigned long, long, int, const char **);
96static long extract_ev8 (unsigned long, int, int *);
252b5132
RH		 97\f
98/* The operands table.
99
100 The fields are bits, shift, insert, extract, flags.
101
102 We used to put parens around the various additions, like the one
103 for BA just below. However, that caused trouble with feeble
104 compilers with a limit on depth of a parenthesized expression, like
105 (reportedly) the compiler in Microsoft Developer Studio 5. So we
106 omit the parens, since the macros are never used in a context where
107 the addition will be ambiguous. */
108
109const struct powerpc_operand powerpc_operands[] =
110{
111 /* The zero index is used to indicate the end of the list of
112 operands. */
113#define UNUSED 0
bbac1f2a 114 { 0, 0, NULL, NULL, 0 },
252b5132
RH		 115
116 /* The BA field in an XL form instruction. */
117#define BA UNUSED + 1
118#define BA_MASK (0x1f << 16)
bbac1f2a 119 { 5, 16, NULL, NULL, PPC_OPERAND_CR },
252b5132
RH		 120
121 /* The BA field in an XL form instruction when it must be the same
122 as the BT field in the same instruction. */
123#define BAT BA + 1
11b37b7b 124 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
252b5132
RH		 125
126 /* The BB field in an XL form instruction. */
127#define BB BAT + 1
128#define BB_MASK (0x1f << 11)
bbac1f2a 129 { 5, 11, NULL, NULL, PPC_OPERAND_CR },
252b5132
RH		 130
131 /* The BB field in an XL form instruction when it must be the same
132 as the BA field in the same instruction. */
133#define BBA BB + 1
11b37b7b 134 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
252b5132
RH		 135
136 /* The BD field in a B form instruction. The lower two bits are
137 forced to zero. */
138#define BD BBA + 1
11b37b7b 139 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 140
141 /* The BD field in a B form instruction when absolute addressing is
142 used. */
143#define BDA BD + 1
11b37b7b 144 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 145
146 /* The BD field in a B form instruction when the - modifier is used.
147 This sets the y bit of the BO field appropriately. */
148#define BDM BDA + 1
11b37b7b
AM		 149 { 16, 0, insert_bdm, extract_bdm,
150 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 151
152 /* The BD field in a B form instruction when the - modifier is used
153 and absolute address is used. */
154#define BDMA BDM + 1
11b37b7b
AM		 155 { 16, 0, insert_bdm, extract_bdm,
156 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 157
158 /* The BD field in a B form instruction when the + modifier is used.
159 This sets the y bit of the BO field appropriately. */
160#define BDP BDMA + 1
11b37b7b
AM		 161 { 16, 0, insert_bdp, extract_bdp,
162 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 163
164 /* The BD field in a B form instruction when the + modifier is used
165 and absolute addressing is used. */
166#define BDPA BDP + 1
11b37b7b
AM		 167 { 16, 0, insert_bdp, extract_bdp,
168 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 169
170 /* The BF field in an X or XL form instruction. */
171#define BF BDPA + 1
bbac1f2a 172 { 3, 23, NULL, NULL, PPC_OPERAND_CR },
252b5132
RH		 173
174 /* An optional BF field. This is used for comparison instructions,
175 in which an omitted BF field is taken as zero. */
176#define OBF BF + 1
bbac1f2a 177 { 3, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
252b5132
RH		 178
179 /* The BFA field in an X or XL form instruction. */
180#define BFA OBF + 1
bbac1f2a 181 { 3, 18, NULL, NULL, PPC_OPERAND_CR },
252b5132
RH		 182
183 /* The BI field in a B form or XL form instruction. */
184#define BI BFA + 1
185#define BI_MASK (0x1f << 16)
bbac1f2a 186 { 5, 16, NULL, NULL, PPC_OPERAND_CR },
252b5132
RH		 187
188 /* The BO field in a B form instruction. Certain values are
189 illegal. */
190#define BO BI + 1
191#define BO_MASK (0x1f << 21)
11b37b7b 192 { 5, 21, insert_bo, extract_bo, 0 },
252b5132
RH		 193
194 /* The BO field in a B form instruction when the + or - modifier is
195 used. This is like the BO field, but it must be even. */
196#define BOE BO + 1
11b37b7b 197 { 5, 21, insert_boe, extract_boe, 0 },
252b5132 198
d0618d1c 199#define BH BOE + 1
bbac1f2a 200 { 2, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
d0618d1c 201
252b5132 202 /* The BT field in an X or XL form instruction. */
d0618d1c 203#define BT BH + 1
bbac1f2a 204 { 5, 21, NULL, NULL, PPC_OPERAND_CR },
252b5132
RH		 205
206 /* The condition register number portion of the BI field in a B form
207 or XL form instruction. This is used for the extended
208 conditional branch mnemonics, which set the lower two bits of the
209 BI field. This field is optional. */
210#define CR BT + 1
bbac1f2a 211 { 3, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
252b5132 212
23976049
EZ		 213 /* The CRB field in an X form instruction. */
214#define CRB CR + 1
bbac1f2a 215 { 5, 6, NULL, NULL, 0 },
23976049
EZ		 216
217 /* The CRFD field in an X form instruction. */
218#define CRFD CRB + 1
bbac1f2a 219 { 3, 23, NULL, NULL, PPC_OPERAND_CR },
23976049
EZ		 220
221 /* The CRFS field in an X form instruction. */
222#define CRFS CRFD + 1
bbac1f2a 223 { 3, 0, NULL, NULL, PPC_OPERAND_CR },
23976049 224
418c1742 225 /* The CT field in an X form instruction. */
23976049 226#define CT CRFS + 1
bbac1f2a 227 { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
418c1742 228
252b5132
RH		 229 /* The D field in a D form instruction. This is a displacement off
230 a register, and implies that the next operand is a register in
231 parentheses. */
418c1742 232#define D CT + 1
bbac1f2a 233 { 16, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
252b5132 234
418c1742
MG		 235 /* The DE field in a DE form instruction. This is like D, but is 12
236 bits only. */
237#define DE D + 1
238 { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
239
240 /* The DES field in a DES form instruction. This is like DS, but is 14
241 bits only (12 stored.) */
242#define DES DE + 1
243 { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
244
adadcc0c
AM		 245 /* The DQ field in a DQ form instruction. This is like D, but the
246 lower four bits are forced to zero. */
247#define DQ DES + 1
248 { 16, 0, insert_dq, extract_dq,
249 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
250
252b5132
RH		 251 /* The DS field in a DS form instruction. This is like D, but the
252 lower two bits are forced to zero. */
adadcc0c 253#define DS DQ + 1
6ba045b1
AM		 254 { 16, 0, insert_ds, extract_ds,
255 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
252b5132
RH		 256
257 /* The E field in a wrteei instruction. */
258#define E DS + 1
bbac1f2a 259 { 1, 15, NULL, NULL, 0 },
252b5132
RH		 260
261 /* The FL1 field in a POWER SC form instruction. */
262#define FL1 E + 1
bbac1f2a 263 { 4, 12, NULL, NULL, 0 },
252b5132
RH		 264
265 /* The FL2 field in a POWER SC form instruction. */
266#define FL2 FL1 + 1
bbac1f2a 267 { 3, 2, NULL, NULL, 0 },
252b5132
RH		 268
269 /* The FLM field in an XFL form instruction. */
270#define FLM FL2 + 1
bbac1f2a 271 { 8, 17, NULL, NULL, 0 },
252b5132
RH		 272
273 /* The FRA field in an X or A form instruction. */
274#define FRA FLM + 1
275#define FRA_MASK (0x1f << 16)
bbac1f2a 276 { 5, 16, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 277
278 /* The FRB field in an X or A form instruction. */
279#define FRB FRA + 1
280#define FRB_MASK (0x1f << 11)
bbac1f2a 281 { 5, 11, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 282
283 /* The FRC field in an A form instruction. */
284#define FRC FRB + 1
285#define FRC_MASK (0x1f << 6)
bbac1f2a 286 { 5, 6, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 287
288 /* The FRS field in an X form instruction or the FRT field in a D, X
289 or A form instruction. */
290#define FRS FRC + 1
291#define FRT FRS
bbac1f2a 292 { 5, 21, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 293
294 /* The FXM field in an XFX instruction. */
295#define FXM FRS + 1
296#define FXM_MASK (0xff << 12)
c168870a
AM		 297 { 8, 12, insert_fxm, extract_fxm, 0 },
298
299 /* Power4 version for mfcr. */
300#define FXM4 FXM + 1
301 { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
252b5132
RH		 302
303 /* The L field in a D or X form instruction. */
c168870a 304#define L FXM4 + 1
e612bb4d 305 { 1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
252b5132 306
1ed8e1e4
AM		 307 /* The LEV field in a POWER SVC form instruction. */
308#define SVC_LEV L + 1
bbac1f2a 309 { 7, 5, NULL, NULL, 0 },
252b5132 310
1ed8e1e4
AM		 311 /* The LEV field in an SC form instruction. */
312#define LEV SVC_LEV + 1
313 { 7, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
314
252b5132
RH		 315 /* The LI field in an I form instruction. The lower two bits are
316 forced to zero. */
317#define LI LEV + 1
11b37b7b 318 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 319
320 /* The LI field in an I form instruction when used as an absolute
321 address. */
322#define LIA LI + 1
11b37b7b 323 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132 324
6ba045b1
AM		 325 /* The LS field in an X (sync) form instruction. */
326#define LS LIA + 1
bbac1f2a 327 { 2, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
6ba045b1 328
252b5132 329 /* The MB field in an M form instruction. */
6ba045b1 330#define MB LS + 1
252b5132 331#define MB_MASK (0x1f << 6)
bbac1f2a 332 { 5, 6, NULL, NULL, 0 },
252b5132
RH		 333
334 /* The ME field in an M form instruction. */
335#define ME MB + 1
336#define ME_MASK (0x1f << 1)
bbac1f2a 337 { 5, 1, NULL, NULL, 0 },
252b5132
RH		 338
339 /* The MB and ME fields in an M form instruction expressed a single
340 operand which is a bitmask indicating which bits to select. This
341 is a two operand form using PPC_OPERAND_NEXT. See the
342 description in opcode/ppc.h for what this means. */
343#define MBE ME + 1
bbac1f2a 344 { 5, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
11b37b7b 345 { 32, 0, insert_mbe, extract_mbe, 0 },
252b5132
RH		 346
347 /* The MB or ME field in an MD or MDS form instruction. The high
348 bit is wrapped to the low end. */
349#define MB6 MBE + 2
350#define ME6 MB6
351#define MB6_MASK (0x3f << 5)
11b37b7b 352 { 6, 5, insert_mb6, extract_mb6, 0 },
252b5132 353
9fa87a06
MG		 354 /* The MO field in an mbar instruction. */
355#define MO MB6 + 1
bbac1f2a 356 { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
9fa87a06 357
252b5132
RH		 358 /* The NB field in an X form instruction. The value 32 is stored as
359 0. */
9fa87a06 360#define NB MO + 1
11b37b7b 361 { 6, 11, insert_nb, extract_nb, 0 },
252b5132
RH		 362
363 /* The NSI field in a D form instruction. This is the same as the
364 SI field, only negated. */
365#define NSI NB + 1
366 { 16, 0, insert_nsi, extract_nsi,
11b37b7b 367 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
252b5132 368
adadcc0c 369 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
914749f6 370#define RA NSI + 1
252b5132 371#define RA_MASK (0x1f << 16)
bbac1f2a 372 { 5, 16, NULL, NULL, PPC_OPERAND_GPR },
252b5132 373
fdd12ef3
AM		 374 /* As above, but 0 in the RA field means zero, not r0. */
375#define RA0 RA + 1
bbac1f2a 376 { 5, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
fdd12ef3
AM		 377
378 /* The RA field in the DQ form lq instruction, which has special
adadcc0c 379 value restrictions. */
fdd12ef3 380#define RAQ RA0 + 1
bbac1f2a 381 { 5, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
adadcc0c 382
252b5132
RH		 383 /* The RA field in a D or X form instruction which is an updating
384 load, which means that the RA field may not be zero and may not
385 equal the RT field. */
adadcc0c 386#define RAL RAQ + 1
bbac1f2a 387 { 5, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
252b5132
RH		 388
389 /* The RA field in an lmw instruction, which has special value
390 restrictions. */
391#define RAM RAL + 1
bbac1f2a 392 { 5, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
252b5132
RH		 393
394 /* The RA field in a D or X form instruction which is an updating
395 store or an updating floating point load, which means that the RA
396 field may not be zero. */
397#define RAS RAM + 1
bbac1f2a 398 { 5, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
252b5132 399
1f6c9eb0 400 /* The RA field of the tlbwe instruction, which is optional. */
fdd12ef3 401#define RAOPT RAS + 1
bbac1f2a 402 { 5, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
1f6c9eb0 403
252b5132 404 /* The RB field in an X, XO, M, or MDS form instruction. */
fdd12ef3 405#define RB RAOPT + 1
252b5132 406#define RB_MASK (0x1f << 11)
bbac1f2a 407 { 5, 11, NULL, NULL, PPC_OPERAND_GPR },
252b5132
RH		 408
409 /* The RB field in an X form instruction when it must be the same as
410 the RS field in the instruction. This is used for extended
411 mnemonics like mr. */
412#define RBS RB + 1
11b37b7b 413 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
252b5132
RH		 414
415 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
416 instruction or the RT field in a D, DS, X, XFX or XO form
417 instruction. */
418#define RS RBS + 1
419#define RT RS
420#define RT_MASK (0x1f << 21)
bbac1f2a 421 { 5, 21, NULL, NULL, PPC_OPERAND_GPR },
252b5132 422
fdd12ef3 423 /* The RS field of the DS form stq instruction, which has special
adadcc0c
AM		 424 value restrictions. */
425#define RSQ RS + 1
bbac1f2a 426 { 5, 21, insert_rsq, NULL, PPC_OPERAND_GPR_0 },
adadcc0c
AM		 427
428 /* The RT field of the DQ form lq instruction, which has special
429 value restrictions. */
430#define RTQ RSQ + 1
bbac1f2a 431 { 5, 21, insert_rtq, NULL, PPC_OPERAND_GPR_0 },
adadcc0c 432
1f6c9eb0
ZW		 433 /* The RS field of the tlbwe instruction, which is optional. */
434#define RSO RTQ + 1
eed0d89a 435#define RTO RSO
bbac1f2a 436 { 5, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
1f6c9eb0 437
252b5132 438 /* The SH field in an X or M form instruction. */
1f6c9eb0 439#define SH RSO + 1
252b5132 440#define SH_MASK (0x1f << 11)
bbac1f2a 441 { 5, 11, NULL, NULL, 0 },
252b5132
RH		 442
443 /* The SH field in an MD form instruction. This is split. */
444#define SH6 SH + 1
445#define SH6_MASK ((0x1f << 11) | (1 << 1))
11b37b7b 446 { 6, 1, insert_sh6, extract_sh6, 0 },
252b5132 447
1f6c9eb0
ZW		 448 /* The SH field of the tlbwe instruction, which is optional. */
449#define SHO SH6 + 1
bbac1f2a 450 { 5, 11,NULL, NULL, PPC_OPERAND_OPTIONAL },
1f6c9eb0 451
252b5132 452 /* The SI field in a D form instruction. */
1f6c9eb0 453#define SI SHO + 1
bbac1f2a 454 { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED },
252b5132
RH		 455
456 /* The SI field in a D form instruction when we accept a wide range
457 of positive values. */
458#define SISIGNOPT SI + 1
bbac1f2a 459 { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
252b5132
RH		 460
461 /* The SPR field in an XFX form instruction. This is flipped--the
462 lower 5 bits are stored in the upper 5 and vice- versa. */
463#define SPR SISIGNOPT + 1
914749f6 464#define PMR SPR
252b5132 465#define SPR_MASK (0x3ff << 11)
11b37b7b 466 { 10, 11, insert_spr, extract_spr, 0 },
252b5132
RH		 467
468 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
469#define SPRBAT SPR + 1
470#define SPRBAT_MASK (0x3 << 17)
bbac1f2a 471 { 2, 17, NULL, NULL, 0 },
252b5132
RH		 472
473 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
474#define SPRG SPRBAT + 1
da99ee72 475 { 5, 16, insert_sprg, extract_sprg, 0 },
252b5132
RH		 476
477 /* The SR field in an X form instruction. */
478#define SR SPRG + 1
bbac1f2a 479 { 4, 16, NULL, NULL, 0 },
252b5132 480
f5c120c5
MG		 481 /* The STRM field in an X AltiVec form instruction. */
482#define STRM SR + 1
483#define STRM_MASK (0x3 << 21)
bbac1f2a 484 { 2, 21, NULL, NULL, 0 },
f5c120c5 485
252b5132 486 /* The SV field in a POWER SC form instruction. */
f5c120c5 487#define SV STRM + 1
bbac1f2a 488 { 14, 2, NULL, NULL, 0 },
252b5132
RH		 489
490 /* The TBR field in an XFX form instruction. This is like the SPR
491 field, but it is optional. */
492#define TBR SV + 1
11b37b7b 493 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
252b5132
RH		 494
495 /* The TO field in a D or X form instruction. */
496#define TO TBR + 1
497#define TO_MASK (0x1f << 21)
bbac1f2a 498 { 5, 21, NULL, NULL, 0 },
252b5132
RH		 499
500 /* The U field in an X form instruction. */
501#define U TO + 1
bbac1f2a 502 { 4, 12, NULL, NULL, 0 },
252b5132
RH		 503
504 /* The UI field in a D form instruction. */
505#define UI U + 1
bbac1f2a 506 { 16, 0, NULL, NULL, 0 },
786e2c0f 507
112290ab 508 /* The VA field in a VA, VX or VXR form instruction. */
786e2c0f
C		 509#define VA UI + 1
510#define VA_MASK (0x1f << 16)
bbac1f2a 511 { 5, 16, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 512
112290ab 513 /* The VB field in a VA, VX or VXR form instruction. */
786e2c0f
C		 514#define VB VA + 1
515#define VB_MASK (0x1f << 11)
bbac1f2a 516 { 5, 11, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 517
112290ab 518 /* The VC field in a VA form instruction. */
786e2c0f
C		 519#define VC VB + 1
520#define VC_MASK (0x1f << 6)
bbac1f2a 521 { 5, 6, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 522
112290ab 523 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
786e2c0f
C		 524#define VD VC + 1
525#define VS VD
526#define VD_MASK (0x1f << 21)
bbac1f2a 527 { 5, 21, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 528
112290ab 529 /* The SIMM field in a VX form instruction. */
786e2c0f 530#define SIMM VD + 1
bbac1f2a 531 { 5, 16, NULL, NULL, PPC_OPERAND_SIGNED},
786e2c0f 532
112290ab 533 /* The UIMM field in a VX form instruction. */
786e2c0f 534#define UIMM SIMM + 1
bbac1f2a 535 { 5, 16, NULL, NULL, 0 },
786e2c0f 536
112290ab 537 /* The SHB field in a VA form instruction. */
786e2c0f 538#define SHB UIMM + 1
bbac1f2a 539 { 4, 6, NULL, NULL, 0 },
ff3a6ee3 540
112290ab 541 /* The other UIMM field in a EVX form instruction. */
23976049 542#define EVUIMM SHB + 1
bbac1f2a 543 { 5, 11, NULL, NULL, 0 },
23976049 544
112290ab 545 /* The other UIMM field in a half word EVX form instruction. */
23976049 546#define EVUIMM_2 EVUIMM + 1
95e172a5 547 { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
23976049 548
112290ab 549 /* The other UIMM field in a word EVX form instruction. */
23976049 550#define EVUIMM_4 EVUIMM_2 + 1
95e172a5 551 { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
23976049 552
112290ab 553 /* The other UIMM field in a double EVX form instruction. */
23976049 554#define EVUIMM_8 EVUIMM_4 + 1
ced05688 555 { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
23976049 556
ff3a6ee3 557 /* The WS field. */
23976049 558#define WS EVUIMM_8 + 1
ff3a6ee3 559#define WS_MASK (0x7 << 11)
bbac1f2a 560 { 3, 11, NULL, NULL, 0 },
ff3a6ee3 561
702f0fb4 562 /* The L field in an mtmsrd or A form instruction. */
5ae2e65e 563#define MTMSRD_L WS + 1
702f0fb4 564#define A_L MTMSRD_L
bbac1f2a 565 { 1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
5ae2e65e 566
702f0fb4
PB		 567 /* The DCM field in a Z form instruction. */
568#define DCM MTMSRD_L + 1
569 { 6, 16, NULL, NULL, 0 },
570
571 /* Likewise, the DGM field in a Z form instruction. */
572#define DGM DCM + 1
573 { 6, 16, NULL, NULL, 0 },
574
575#define TE DGM + 1
576 { 5, 11, NULL, NULL, 0 },
577
578#define RMC TE + 1
579 { 2, 21, NULL, NULL, 0 },
580
581#define R RMC + 1
582 { 1, 15, NULL, NULL, 0 },
583
584#define SP R + 1
585 { 2, 11, NULL, NULL, 0 },
586
587#define S SP + 1
588 { 1, 11, NULL, NULL, 0 },
589
590 /* SH field starting at bit position 16. */
591#define SH16 S + 1
592 { 6, 10, NULL, NULL, 0 },
593
594 /* The L field in an X form with the RT field fixed instruction. */
595#define XRT_L SH16 + 1
596 { 2, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
597
598 /* The EH field in larx instruction. */
599#define EH XRT_L + 1
600 { 1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
252b5132
RH		 601};
602
603/* The functions used to insert and extract complicated operands. */
604
605/* The BA field in an XL form instruction when it must be the same as
606 the BT field in the same instruction. This operand is marked FAKE.
607 The insertion function just copies the BT field into the BA field,
608 and the extraction function just checks that the fields are the
609 same. */
610
252b5132 611static unsigned long
2fbfdc41
AM		 612insert_bat (unsigned long insn,
613 long value ATTRIBUTE_UNUSED,
614 int dialect ATTRIBUTE_UNUSED,
615 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 616{
617 return insn | (((insn >> 21) & 0x1f) << 16);
618}
619
620static long
2fbfdc41
AM		 621extract_bat (unsigned long insn,
622 int dialect ATTRIBUTE_UNUSED,
623 int *invalid)
252b5132 624{
8427c424 625 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
252b5132
RH		 626 *invalid = 1;
627 return 0;
628}
629
630/* The BB field in an XL form instruction when it must be the same as
631 the BA field in the same instruction. This operand is marked FAKE.
632 The insertion function just copies the BA field into the BB field,
633 and the extraction function just checks that the fields are the
634 same. */
635
252b5132 636static unsigned long
2fbfdc41
AM		 637insert_bba (unsigned long insn,
638 long value ATTRIBUTE_UNUSED,
639 int dialect ATTRIBUTE_UNUSED,
640 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 641{
642 return insn | (((insn >> 16) & 0x1f) << 11);
643}
644
645static long
2fbfdc41
AM		 646extract_bba (unsigned long insn,
647 int dialect ATTRIBUTE_UNUSED,
648 int *invalid)
252b5132 649{
8427c424 650 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
252b5132
RH		 651 *invalid = 1;
652 return 0;
653}
654
655/* The BD field in a B form instruction. The lower two bits are
656 forced to zero. */
657
252b5132 658static unsigned long
2fbfdc41
AM		 659insert_bd (unsigned long insn,
660 long value,
661 int dialect ATTRIBUTE_UNUSED,
662 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 663{
664 return insn | (value & 0xfffc);
665}
666
252b5132 667static long
2fbfdc41
AM		 668extract_bd (unsigned long insn,
669 int dialect ATTRIBUTE_UNUSED,
670 int *invalid ATTRIBUTE_UNUSED)
252b5132 671{
802a735e 672 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 673}
674
675/* The BD field in a B form instruction when the - modifier is used.
676 This modifier means that the branch is not expected to be taken.
94efba12
AM		 677 For chips built to versions of the architecture prior to version 2
678 (ie. not Power4 compatible), we set the y bit of the BO field to 1
679 if the offset is negative. When extracting, we require that the y
680 bit be 1 and that the offset be positive, since if the y bit is 0
681 we just want to print the normal form of the instruction.
682 Power4 compatible targets use two bits, "a", and "t", instead of
683 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
684 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
685 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
686 for branch on CTR. We only handle the taken/not-taken hint here. */
252b5132 687
252b5132 688static unsigned long
2fbfdc41
AM		 689insert_bdm (unsigned long insn,
690 long value,
691 int dialect,
692 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 693{
94efba12 694 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e
AM		 695 {
696 if ((value & 0x8000) != 0)
697 insn |= 1 << 21;
698 }
699 else
700 {
701 if ((insn & (0x14 << 21)) == (0x04 << 21))
702 insn |= 0x02 << 21;
703 else if ((insn & (0x14 << 21)) == (0x10 << 21))
704 insn |= 0x08 << 21;
705 }
252b5132
RH		 706 return insn | (value & 0xfffc);
707}
708
709static long
2fbfdc41
AM		 710extract_bdm (unsigned long insn,
711 int dialect,
712 int *invalid)
252b5132 713{
8427c424 714 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e 715 {
8427c424
AM		 716 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
717 *invalid = 1;
802a735e 718 }
8427c424
AM		 719 else
720 {
721 if ((insn & (0x17 << 21)) != (0x06 << 21)
722 && (insn & (0x1d << 21)) != (0x18 << 21))
723 *invalid = 1;
724 }
725
802a735e 726 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 727}
728
729/* The BD field in a B form instruction when the + modifier is used.
730 This is like BDM, above, except that the branch is expected to be
731 taken. */
732
252b5132 733static unsigned long
2fbfdc41
AM		 734insert_bdp (unsigned long insn,
735 long value,
736 int dialect,
737 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 738{
94efba12 739 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e
AM		 740 {
741 if ((value & 0x8000) == 0)
742 insn |= 1 << 21;
743 }
744 else
745 {
746 if ((insn & (0x14 << 21)) == (0x04 << 21))
747 insn |= 0x03 << 21;
748 else if ((insn & (0x14 << 21)) == (0x10 << 21))
749 insn |= 0x09 << 21;
750 }
252b5132
RH		 751 return insn | (value & 0xfffc);
752}
753
754static long
2fbfdc41
AM		 755extract_bdp (unsigned long insn,
756 int dialect,
757 int *invalid)
252b5132 758{
8427c424 759 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e 760 {
8427c424
AM		 761 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
762 *invalid = 1;
763 }
764 else
765 {
766 if ((insn & (0x17 << 21)) != (0x07 << 21)
767 && (insn & (0x1d << 21)) != (0x19 << 21))
768 *invalid = 1;
802a735e 769 }
8427c424 770
802a735e 771 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 772}
773
774/* Check for legal values of a BO field. */
775
776static int
2fbfdc41 777valid_bo (long value, int dialect)
252b5132 778{
94efba12 779 if ((dialect & PPC_OPCODE_POWER4) == 0)
252b5132 780 {
802a735e
AM		 781 /* Certain encodings have bits that are required to be zero.
782 These are (z must be zero, y may be anything):
783 001zy
784 011zy
785 1z00y
786 1z01y
787 1z1zz
788 */
789 switch (value & 0x14)
790 {
791 default:
792 case 0:
793 return 1;
794 case 0x4:
795 return (value & 0x2) == 0;
796 case 0x10:
797 return (value & 0x8) == 0;
798 case 0x14:
799 return value == 0x14;
800 }
801 }
802 else
803 {
804 /* Certain encodings have bits that are required to be zero.
805 These are (z must be zero, a & t may be anything):
806 0000z
807 0001z
808 0100z
809 0101z
810 001at
811 011at
812 1a00t
813 1a01t
814 1z1zz
815 */
816 if ((value & 0x14) == 0)
817 return (value & 0x1) == 0;
818 else if ((value & 0x14) == 0x14)
819 return value == 0x14;
820 else
821 return 1;
252b5132
RH		 822 }
823}
824
825/* The BO field in a B form instruction. Warn about attempts to set
826 the field to an illegal value. */
827
828static unsigned long
2fbfdc41
AM		 829insert_bo (unsigned long insn,
830 long value,
831 int dialect,
832 const char **errmsg)
252b5132 833{
8427c424 834 if (!valid_bo (value, dialect))
252b5132
RH		 835 *errmsg = _("invalid conditional option");
836 return insn | ((value & 0x1f) << 21);
837}
838
839static long
2fbfdc41
AM		 840extract_bo (unsigned long insn,
841 int dialect,
842 int *invalid)
252b5132
RH		 843{
844 long value;
845
846 value = (insn >> 21) & 0x1f;
8427c424 847 if (!valid_bo (value, dialect))
252b5132
RH		 848 *invalid = 1;
849 return value;
850}
851
852/* The BO field in a B form instruction when the + or - modifier is
853 used. This is like the BO field, but it must be even. When
854 extracting it, we force it to be even. */
855
856static unsigned long
2fbfdc41
AM		 857insert_boe (unsigned long insn,
858 long value,
859 int dialect,
860 const char **errmsg)
252b5132 861{
8427c424
AM		 862 if (!valid_bo (value, dialect))
863 *errmsg = _("invalid conditional option");
864 else if ((value & 1) != 0)
865 *errmsg = _("attempt to set y bit when using + or - modifier");
866
252b5132
RH		 867 return insn | ((value & 0x1f) << 21);
868}
869
870static long
2fbfdc41
AM		 871extract_boe (unsigned long insn,
872 int dialect,
873 int *invalid)
252b5132
RH		 874{
875 long value;
876
877 value = (insn >> 21) & 0x1f;
8427c424 878 if (!valid_bo (value, dialect))
252b5132
RH		 879 *invalid = 1;
880 return value & 0x1e;
881}
882
8427c424
AM		 883/* The DQ field in a DQ form instruction. This is like D, but the
884 lower four bits are forced to zero. */
adadcc0c 885
adadcc0c 886static unsigned long
2fbfdc41
AM		 887insert_dq (unsigned long insn,
888 long value,
889 int dialect ATTRIBUTE_UNUSED,
8427c424 890 const char **errmsg)
adadcc0c 891{
8427c424 892 if ((value & 0xf) != 0)
adadcc0c
AM		 893 *errmsg = _("offset not a multiple of 16");
894 return insn | (value & 0xfff0);
895}
896
adadcc0c 897static long
2fbfdc41
AM		 898extract_dq (unsigned long insn,
899 int dialect ATTRIBUTE_UNUSED,
900 int *invalid ATTRIBUTE_UNUSED)
adadcc0c
AM		 901{
902 return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
903}
904
23976049 905static unsigned long
2fbfdc41
AM		 906insert_ev2 (unsigned long insn,
907 long value,
908 int dialect ATTRIBUTE_UNUSED,
8427c424 909 const char **errmsg)
23976049 910{
8427c424 911 if ((value & 1) != 0)
23976049 912 *errmsg = _("offset not a multiple of 2");
8427c424 913 if ((value > 62) != 0)
23976049 914 *errmsg = _("offset greater than 62");
914749f6 915 return insn | ((value & 0x3e) << 10);
23976049
EZ		 916}
917
918static long
2fbfdc41
AM		 919extract_ev2 (unsigned long insn,
920 int dialect ATTRIBUTE_UNUSED,
921 int *invalid ATTRIBUTE_UNUSED)
23976049 922{
914749f6 923 return (insn >> 10) & 0x3e;
23976049
EZ		 924}
925
926static unsigned long
2fbfdc41
AM		 927insert_ev4 (unsigned long insn,
928 long value,
929 int dialect ATTRIBUTE_UNUSED,
8427c424 930 const char **errmsg)
23976049 931{
8427c424 932 if ((value & 3) != 0)
23976049 933 *errmsg = _("offset not a multiple of 4");
8427c424 934 if ((value > 124) != 0)
23976049 935 *errmsg = _("offset greater than 124");
914749f6 936 return insn | ((value & 0x7c) << 9);
23976049
EZ		 937}
938
939static long
2fbfdc41
AM		 940extract_ev4 (unsigned long insn,
941 int dialect ATTRIBUTE_UNUSED,
942 int *invalid ATTRIBUTE_UNUSED)
23976049 943{
914749f6 944 return (insn >> 9) & 0x7c;
23976049
EZ		 945}
946
947static unsigned long
2fbfdc41
AM		 948insert_ev8 (unsigned long insn,
949 long value,
950 int dialect ATTRIBUTE_UNUSED,
8427c424 951 const char **errmsg)
23976049 952{
8427c424 953 if ((value & 7) != 0)
23976049 954 *errmsg = _("offset not a multiple of 8");
8427c424 955 if ((value > 248) != 0)
23976049
EZ		 956 *errmsg = _("offset greater than 248");
957 return insn | ((value & 0xf8) << 8);
958}
959
960static long
2fbfdc41
AM		 961extract_ev8 (unsigned long insn,
962 int dialect ATTRIBUTE_UNUSED,
8427c424 963 int *invalid ATTRIBUTE_UNUSED)
23976049
EZ		 964{
965 return (insn >> 8) & 0xf8;
966}
967
252b5132
RH		 968/* The DS field in a DS form instruction. This is like D, but the
969 lower two bits are forced to zero. */
970
252b5132 971static unsigned long
2fbfdc41
AM		 972insert_ds (unsigned long insn,
973 long value,
974 int dialect ATTRIBUTE_UNUSED,
975 const char **errmsg)
252b5132 976{
8427c424 977 if ((value & 3) != 0)
6ba045b1 978 *errmsg = _("offset not a multiple of 4");
252b5132
RH		 979 return insn | (value & 0xfffc);
980}
981
252b5132 982static long
2fbfdc41
AM		 983extract_ds (unsigned long insn,
984 int dialect ATTRIBUTE_UNUSED,
985 int *invalid ATTRIBUTE_UNUSED)
252b5132 986{
802a735e 987 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 988}
989
418c1742
MG		 990/* The DE field in a DE form instruction. */
991
418c1742 992static unsigned long
2fbfdc41
AM		 993insert_de (unsigned long insn,
994 long value,
995 int dialect ATTRIBUTE_UNUSED,
996 const char **errmsg)
418c1742 997{
8427c424 998 if (value > 2047 || value < -2048)
418c1742
MG		 999 *errmsg = _("offset not between -2048 and 2047");
1000 return insn | ((value << 4) & 0xfff0);
1001}
1002
418c1742 1003static long
2fbfdc41
AM		 1004extract_de (unsigned long insn,
1005 int dialect ATTRIBUTE_UNUSED,
1006 int *invalid ATTRIBUTE_UNUSED)
418c1742
MG		 1007{
1008 return (insn & 0xfff0) >> 4;
1009}
1010
1011/* The DES field in a DES form instruction. */
1012
418c1742 1013static unsigned long
2fbfdc41
AM		 1014insert_des (unsigned long insn,
1015 long value,
1016 int dialect ATTRIBUTE_UNUSED,
1017 const char **errmsg)
418c1742 1018{
8427c424 1019 if (value > 8191 || value < -8192)
418c1742 1020 *errmsg = _("offset not between -8192 and 8191");
8427c424 1021 else if ((value & 3) != 0)
418c1742
MG		 1022 *errmsg = _("offset not a multiple of 4");
1023 return insn | ((value << 2) & 0xfff0);
1024}
1025
418c1742 1026static long
2fbfdc41
AM		 1027extract_des (unsigned long insn,
1028 int dialect ATTRIBUTE_UNUSED,
1029 int *invalid ATTRIBUTE_UNUSED)
418c1742 1030{
802a735e 1031 return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
418c1742
MG		 1032}
1033
2fbfdc41
AM		 1034/* FXM mask in mfcr and mtcrf instructions. */
1035
1036static unsigned long
1037insert_fxm (unsigned long insn,
1038 long value,
1039 int dialect,
1040 const char **errmsg)
c168870a 1041{
98e69875
AM		 1042 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1043 one bit of the mask field is set. */
1044 if ((insn & (1 << 20)) != 0)
1045 {
1046 if (value == 0 || (value & -value) != value)
1047 {
1048 *errmsg = _("invalid mask field");
1049 value = 0;
1050 }
1051 }
1052
c168870a
AM		 1053 /* If the optional field on mfcr is missing that means we want to use
1054 the old form of the instruction that moves the whole cr. In that
1055 case we'll have VALUE zero. There doesn't seem to be a way to
1056 distinguish this from the case where someone writes mfcr %r3,0. */
98e69875 1057 else if (value == 0)
c168870a
AM		 1058 ;
1059
1060 /* If only one bit of the FXM field is set, we can use the new form
661bd698 1061 of the instruction, which is faster. Unlike the Power4 branch hint
a30e9cc4
AM		 1062 encoding, this is not backward compatible. Do not generate the
1063 new form unless -mpower4 has been given, or -many and the two
1064 operand form of mfcr was used. */
1065 else if ((value & -value) == value
1066 && ((dialect & PPC_OPCODE_POWER4) != 0
1067 || ((dialect & PPC_OPCODE_ANY) != 0
1068 && (insn & (0x3ff << 1)) == 19 << 1)))
c168870a
AM		 1069 insn |= 1 << 20;
1070
1071 /* Any other value on mfcr is an error. */
1072 else if ((insn & (0x3ff << 1)) == 19 << 1)
1073 {
8427c424 1074 *errmsg = _("ignoring invalid mfcr mask");
c168870a
AM		 1075 value = 0;
1076 }
1077
1078 return insn | ((value & 0xff) << 12);
1079}
1080
2fbfdc41
AM		 1081static long
1082extract_fxm (unsigned long insn,
98e69875 1083 int dialect ATTRIBUTE_UNUSED,
2fbfdc41 1084 int *invalid)
c168870a
AM		 1085{
1086 long mask = (insn >> 12) & 0xff;
1087
1088 /* Is this a Power4 insn? */
1089 if ((insn & (1 << 20)) != 0)
1090 {
98e69875
AM		 1091 /* Exactly one bit of MASK should be set. */
1092 if (mask == 0 || (mask & -mask) != mask)
8427c424 1093 *invalid = 1;
c168870a
AM		 1094 }
1095
1096 /* Check that non-power4 form of mfcr has a zero MASK. */
1097 else if ((insn & (0x3ff << 1)) == 19 << 1)
1098 {
8427c424 1099 if (mask != 0)
c168870a
AM		 1100 *invalid = 1;
1101 }
1102
1103 return mask;
1104}
1105
252b5132
RH		 1106/* The LI field in an I form instruction. The lower two bits are
1107 forced to zero. */
1108
252b5132 1109static unsigned long
2fbfdc41
AM		 1110insert_li (unsigned long insn,
1111 long value,
1112 int dialect ATTRIBUTE_UNUSED,
1113 const char **errmsg)
252b5132 1114{
8427c424 1115 if ((value & 3) != 0)
252b5132
RH		 1116 *errmsg = _("ignoring least significant bits in branch offset");
1117 return insn | (value & 0x3fffffc);
1118}
1119
252b5132 1120static long
2fbfdc41
AM		 1121extract_li (unsigned long insn,
1122 int dialect ATTRIBUTE_UNUSED,
1123 int *invalid ATTRIBUTE_UNUSED)
252b5132 1124{
802a735e 1125 return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
252b5132
RH		 1126}
1127
1128/* The MB and ME fields in an M form instruction expressed as a single
1129 operand which is itself a bitmask. The extraction function always
1130 marks it as invalid, since we never want to recognize an
1131 instruction which uses a field of this type. */
1132
1133static unsigned long
2fbfdc41
AM		 1134insert_mbe (unsigned long insn,
1135 long value,
1136 int dialect ATTRIBUTE_UNUSED,
1137 const char **errmsg)
252b5132
RH		 1138{
1139 unsigned long uval, mask;
1140 int mb, me, mx, count, last;
1141
1142 uval = value;
1143
1144 if (uval == 0)
1145 {
8427c424 1146 *errmsg = _("illegal bitmask");
252b5132
RH		 1147 return insn;
1148 }
1149
1150 mb = 0;
1151 me = 32;
1152 if ((uval & 1) != 0)
1153 last = 1;
1154 else
1155 last = 0;
1156 count = 0;
1157
1158 /* mb: location of last 0->1 transition */
1159 /* me: location of last 1->0 transition */
1160 /* count: # transitions */
1161
0deb7ac5 1162 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
252b5132
RH		 1163 {
1164 if ((uval & mask) && !last)
1165 {
1166 ++count;
1167 mb = mx;
1168 last = 1;
1169 }
1170 else if (!(uval & mask) && last)
1171 {
1172 ++count;
1173 me = mx;
1174 last = 0;
1175 }
1176 }
1177 if (me == 0)
1178 me = 32;
1179
1180 if (count != 2 && (count != 0 || ! last))
8427c424 1181 *errmsg = _("illegal bitmask");
252b5132
RH		 1182
1183 return insn | (mb << 6) | ((me - 1) << 1);
1184}
1185
1186static long
2fbfdc41
AM		 1187extract_mbe (unsigned long insn,
1188 int dialect ATTRIBUTE_UNUSED,
1189 int *invalid)
252b5132
RH		 1190{
1191 long ret;
1192 int mb, me;
1193 int i;
1194
8427c424 1195 *invalid = 1;
252b5132
RH		 1196
1197 mb = (insn >> 6) & 0x1f;
1198 me = (insn >> 1) & 0x1f;
1199 if (mb < me + 1)
1200 {
1201 ret = 0;
1202 for (i = mb; i <= me; i++)
0deb7ac5 1203 ret |= 1L << (31 - i);
252b5132
RH		 1204 }
1205 else if (mb == me + 1)
8427c424 1206 ret = ~0;
252b5132
RH		 1207 else /* (mb > me + 1) */
1208 {
2fbfdc41 1209 ret = ~0;
252b5132 1210 for (i = me + 1; i < mb; i++)
0deb7ac5 1211 ret &= ~(1L << (31 - i));
252b5132
RH		 1212 }
1213 return ret;
1214}
1215
1216/* The MB or ME field in an MD or MDS form instruction. The high bit
1217 is wrapped to the low end. */
1218
252b5132 1219static unsigned long
2fbfdc41
AM		 1220insert_mb6 (unsigned long insn,
1221 long value,
1222 int dialect ATTRIBUTE_UNUSED,
1223 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1224{
1225 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1226}
1227
252b5132 1228static long
2fbfdc41
AM		 1229extract_mb6 (unsigned long insn,
1230 int dialect ATTRIBUTE_UNUSED,
1231 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1232{
1233 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1234}
1235
1236/* The NB field in an X form instruction. The value 32 is stored as
1237 0. */
1238
1239static unsigned long
2fbfdc41
AM		 1240insert_nb (unsigned long insn,
1241 long value,
1242 int dialect ATTRIBUTE_UNUSED,
1243 const char **errmsg)
252b5132
RH		 1244{
1245 if (value < 0 || value > 32)
1246 *errmsg = _("value out of range");
1247 if (value == 32)
1248 value = 0;
1249 return insn | ((value & 0x1f) << 11);
1250}
1251
252b5132 1252static long
2fbfdc41
AM		 1253extract_nb (unsigned long insn,
1254 int dialect ATTRIBUTE_UNUSED,
1255 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1256{
1257 long ret;
1258
1259 ret = (insn >> 11) & 0x1f;
1260 if (ret == 0)
1261 ret = 32;
1262 return ret;
1263}
1264
1265/* The NSI field in a D form instruction. This is the same as the SI
1266 field, only negated. The extraction function always marks it as
1267 invalid, since we never want to recognize an instruction which uses
1268 a field of this type. */
1269
252b5132 1270static unsigned long
2fbfdc41
AM		 1271insert_nsi (unsigned long insn,
1272 long value,
1273 int dialect ATTRIBUTE_UNUSED,
1274 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 1275{
2fbfdc41 1276 return insn | (-value & 0xffff);
252b5132
RH		 1277}
1278
1279static long
2fbfdc41
AM		 1280extract_nsi (unsigned long insn,
1281 int dialect ATTRIBUTE_UNUSED,
1282 int *invalid)
252b5132 1283{
8427c424 1284 *invalid = 1;
2fbfdc41 1285 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
252b5132
RH		 1286}
1287
1288/* The RA field in a D or X form instruction which is an updating
1289 load, which means that the RA field may not be zero and may not
1290 equal the RT field. */
1291
1292static unsigned long
2fbfdc41
AM		 1293insert_ral (unsigned long insn,
1294 long value,
1295 int dialect ATTRIBUTE_UNUSED,
1296 const char **errmsg)
252b5132
RH		 1297{
1298 if (value == 0
1299 || (unsigned long) value == ((insn >> 21) & 0x1f))
1300 *errmsg = "invalid register operand when updating";
1301 return insn | ((value & 0x1f) << 16);
1302}
1303
1304/* The RA field in an lmw instruction, which has special value
1305 restrictions. */
1306
1307static unsigned long
2fbfdc41
AM		 1308insert_ram (unsigned long insn,
1309 long value,
1310 int dialect ATTRIBUTE_UNUSED,
1311 const char **errmsg)
252b5132
RH		 1312{
1313 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1314 *errmsg = _("index register in load range");
1315 return insn | ((value & 0x1f) << 16);
1316}
1317
fdd12ef3 1318/* The RA field in the DQ form lq instruction, which has special
8427c424 1319 value restrictions. */
adadcc0c 1320
adadcc0c 1321static unsigned long
2fbfdc41
AM		 1322insert_raq (unsigned long insn,
1323 long value,
1324 int dialect ATTRIBUTE_UNUSED,
1325 const char **errmsg)
adadcc0c
AM		 1326{
1327 long rtvalue = (insn & RT_MASK) >> 21;
1328
8427c424 1329 if (value == rtvalue)
adadcc0c
AM		 1330 *errmsg = _("source and target register operands must be different");
1331 return insn | ((value & 0x1f) << 16);
1332}
1333
252b5132
RH		 1334/* The RA field in a D or X form instruction which is an updating
1335 store or an updating floating point load, which means that the RA
1336 field may not be zero. */
1337
1338static unsigned long
2fbfdc41
AM		 1339insert_ras (unsigned long insn,
1340 long value,
1341 int dialect ATTRIBUTE_UNUSED,
1342 const char **errmsg)
252b5132
RH		 1343{
1344 if (value == 0)
1345 *errmsg = _("invalid register operand when updating");
1346 return insn | ((value & 0x1f) << 16);
1347}
1348
1349/* The RB field in an X form instruction when it must be the same as
1350 the RS field in the instruction. This is used for extended
1351 mnemonics like mr. This operand is marked FAKE. The insertion
1352 function just copies the BT field into the BA field, and the
1353 extraction function just checks that the fields are the same. */
1354
252b5132 1355static unsigned long
2fbfdc41
AM		 1356insert_rbs (unsigned long insn,
1357 long value ATTRIBUTE_UNUSED,
1358 int dialect ATTRIBUTE_UNUSED,
1359 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1360{
1361 return insn | (((insn >> 21) & 0x1f) << 11);
1362}
1363
1364static long
2fbfdc41
AM		 1365extract_rbs (unsigned long insn,
1366 int dialect ATTRIBUTE_UNUSED,
1367 int *invalid)
252b5132 1368{
8427c424 1369 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
252b5132
RH		 1370 *invalid = 1;
1371 return 0;
1372}
1373
8427c424
AM		 1374/* The RT field of the DQ form lq instruction, which has special
1375 value restrictions. */
adadcc0c 1376
adadcc0c 1377static unsigned long
2fbfdc41
AM		 1378insert_rtq (unsigned long insn,
1379 long value,
1380 int dialect ATTRIBUTE_UNUSED,
1381 const char **errmsg)
adadcc0c 1382{
8427c424 1383 if ((value & 1) != 0)
adadcc0c
AM		 1384 *errmsg = _("target register operand must be even");
1385 return insn | ((value & 0x1f) << 21);
1386}
1387
fdd12ef3 1388/* The RS field of the DS form stq instruction, which has special
8427c424 1389 value restrictions. */
adadcc0c 1390
adadcc0c 1391static unsigned long
2fbfdc41
AM		 1392insert_rsq (unsigned long insn,
1393 long value ATTRIBUTE_UNUSED,
1394 int dialect ATTRIBUTE_UNUSED,
1395 const char **errmsg)
adadcc0c 1396{
8427c424 1397 if ((value & 1) != 0)
adadcc0c
AM		 1398 *errmsg = _("source register operand must be even");
1399 return insn | ((value & 0x1f) << 21);
1400}
1401
252b5132
RH		 1402/* The SH field in an MD form instruction. This is split. */
1403
252b5132 1404static unsigned long
2fbfdc41
AM		 1405insert_sh6 (unsigned long insn,
1406 long value,
1407 int dialect ATTRIBUTE_UNUSED,
1408 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1409{
1410 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1411}
1412
252b5132 1413static long
2fbfdc41
AM		 1414extract_sh6 (unsigned long insn,
1415 int dialect ATTRIBUTE_UNUSED,
1416 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1417{
1418 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1419}
1420
1421/* The SPR field in an XFX form instruction. This is flipped--the
1422 lower 5 bits are stored in the upper 5 and vice- versa. */
1423
1424static unsigned long
2fbfdc41
AM		 1425insert_spr (unsigned long insn,
1426 long value,
1427 int dialect ATTRIBUTE_UNUSED,
1428 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1429{
1430 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1431}
1432
1433static long
2fbfdc41
AM		 1434extract_spr (unsigned long insn,
1435 int dialect ATTRIBUTE_UNUSED,
1436 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1437{
1438 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1439}
1440
da99ee72
AM		 1441/* Some dialects have 8 SPRG registers instead of the standard 4. */
1442
1443static unsigned long
1444insert_sprg (unsigned long insn,
1445 long value,
1446 int dialect,
1447 const char **errmsg)
1448{
1449 /* This check uses PPC_OPCODE_403 because PPC405 is later defined
1450 as a synonym. If ever a 405 specific dialect is added this
1451 check should use that instead. */
1452 if (value > 7
1453 || (value > 3
1454 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1455 *errmsg = _("invalid sprg number");
1456
1457 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1458 user mode. Anything else must use spr 272..279. */
1459 if (value <= 3 || (insn & 0x100) != 0)
1460 value |= 0x10;
1461
1462 return insn | ((value & 0x17) << 16);
1463}
1464
1465static long
1466extract_sprg (unsigned long insn,
1467 int dialect,
1468 int *invalid)
1469{
1470 unsigned long val = (insn >> 16) & 0x1f;
1471
1472 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1473 If not BOOKE or 405, then both use only 272..275. */
1474 if (val <= 3
1475 || (val < 0x10 && (insn & 0x100) != 0)
1476 || (val - 0x10 > 3
1477 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1478 *invalid = 1;
1479 return val & 7;
1480}
1481
252b5132
RH		 1482/* The TBR field in an XFX instruction. This is just like SPR, but it
1483 is optional. When TBR is omitted, it must be inserted as 268 (the
1484 magic number of the TB register). These functions treat 0
1485 (indicating an omitted optional operand) as 268. This means that
1486 ``mftb 4,0'' is not handled correctly. This does not matter very
1487 much, since the architecture manual does not define mftb as
1488 accepting any values other than 268 or 269. */
1489
1490#define TB (268)
1491
1492static unsigned long
2fbfdc41
AM		 1493insert_tbr (unsigned long insn,
1494 long value,
1495 int dialect ATTRIBUTE_UNUSED,
1496 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1497{
1498 if (value == 0)
1499 value = TB;
1500 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1501}
1502
1503static long
2fbfdc41
AM		 1504extract_tbr (unsigned long insn,
1505 int dialect ATTRIBUTE_UNUSED,
1506 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1507{
1508 long ret;
1509
1510 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1511 if (ret == TB)
1512 ret = 0;
1513 return ret;
1514}
1515\f
1516/* Macros used to form opcodes. */
1517
1518/* The main opcode. */
1519#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1520#define OP_MASK OP (0x3f)
1521
1522/* The main opcode combined with a trap code in the TO field of a D
1523 form instruction. Used for extended mnemonics for the trap
1524 instructions. */
1525#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1526#define OPTO_MASK (OP_MASK | TO_MASK)
1527
1528/* The main opcode combined with a comparison size bit in the L field
1529 of a D form or X form instruction. Used for extended mnemonics for
1530 the comparison instructions. */
1531#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1532#define OPL_MASK OPL (0x3f,1)
1533
1534/* An A form instruction. */
1535#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1536#define A_MASK A (0x3f, 0x1f, 1)
1537
1538/* An A_MASK with the FRB field fixed. */
1539#define AFRB_MASK (A_MASK | FRB_MASK)
1540
1541/* An A_MASK with the FRC field fixed. */
1542#define AFRC_MASK (A_MASK | FRC_MASK)
1543
1544/* An A_MASK with the FRA and FRC fields fixed. */
1545#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1546
702f0fb4
PB		 1547/* An AFRAFRC_MASK, but with L bit clear. */
1548#define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
1549
252b5132
RH		 1550/* A B form instruction. */
1551#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1552#define B_MASK B (0x3f, 1, 1)
1553
1554/* A B form instruction setting the BO field. */
1555#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1556#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1557
1558/* A BBO_MASK with the y bit of the BO field removed. This permits
1559 matching a conditional branch regardless of the setting of the y
94efba12 1560 bit. Similarly for the 'at' bits used for power4 branch hints. */
802a735e
AM		 1561#define Y_MASK (((unsigned long) 1) << 21)
1562#define AT1_MASK (((unsigned long) 3) << 21)
1563#define AT2_MASK (((unsigned long) 9) << 21)
1564#define BBOY_MASK (BBO_MASK &~ Y_MASK)
1565#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
252b5132
RH		 1566
1567/* A B form instruction setting the BO field and the condition bits of
1568 the BI field. */
1569#define BBOCB(op, bo, cb, aa, lk) \
1570 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1571#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1572
1573/* A BBOCB_MASK with the y bit of the BO field removed. */
1574#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
802a735e
AM		 1575#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1576#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
252b5132
RH		 1577
1578/* A BBOYCB_MASK in which the BI field is fixed. */
1579#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
802a735e 1580#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
252b5132 1581
23976049
EZ		 1582/* An Context form instruction. */
1583#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
fdd12ef3 1584#define CTX_MASK CTX(0x3f, 0x7)
23976049
EZ		 1585
1586/* An User Context form instruction. */
1587#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
fdd12ef3 1588#define UCTX_MASK UCTX(0x3f, 0x1f)
23976049 1589
252b5132
RH		 1590/* The main opcode mask with the RA field clear. */
1591#define DRA_MASK (OP_MASK | RA_MASK)
1592
1593/* A DS form instruction. */
1594#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1595#define DS_MASK DSO (0x3f, 3)
1596
418c1742
MG		 1597/* A DE form instruction. */
1598#define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1599#define DE_MASK DEO (0x3e, 0xf)
1600
23976049
EZ		 1601/* An EVSEL form instruction. */
1602#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1603#define EVSEL_MASK EVSEL(0x3f, 0xff)
1604
252b5132
RH		 1605/* An M form instruction. */
1606#define M(op, rc) (OP (op) | ((rc) & 1))
1607#define M_MASK M (0x3f, 1)
1608
1609/* An M form instruction with the ME field specified. */
1610#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1611
1612/* An M_MASK with the MB and ME fields fixed. */
1613#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1614
1615/* An M_MASK with the SH and ME fields fixed. */
1616#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1617
1618/* An MD form instruction. */
1619#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1620#define MD_MASK MD (0x3f, 0x7, 1)
1621
1622/* An MD_MASK with the MB field fixed. */
1623#define MDMB_MASK (MD_MASK | MB6_MASK)
1624
1625/* An MD_MASK with the SH field fixed. */
1626#define MDSH_MASK (MD_MASK | SH6_MASK)
1627
1628/* An MDS form instruction. */
1629#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1630#define MDS_MASK MDS (0x3f, 0xf, 1)
1631
1632/* An MDS_MASK with the MB field fixed. */
1633#define MDSMB_MASK (MDS_MASK | MB6_MASK)
1634
1635/* An SC form instruction. */
1636#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1637#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1638
112290ab 1639/* An VX form instruction. */
786e2c0f
C		 1640#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1641
112290ab 1642/* The mask for an VX form instruction. */
786e2c0f
C		 1643#define VX_MASK VX(0x3f, 0x7ff)
1644
112290ab 1645/* An VA form instruction. */
2613489e 1646#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
786e2c0f 1647
112290ab 1648/* The mask for an VA form instruction. */
2613489e 1649#define VXA_MASK VXA(0x3f, 0x3f)
786e2c0f 1650
112290ab 1651/* An VXR form instruction. */
786e2c0f
C		 1652#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1653
112290ab 1654/* The mask for a VXR form instruction. */
786e2c0f
C		 1655#define VXR_MASK VXR(0x3f, 0x3ff, 1)
1656
252b5132
RH		 1657/* An X form instruction. */
1658#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1659
702f0fb4
PB		 1660/* A Z form instruction. */
1661#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1662
252b5132
RH		 1663/* An X form instruction with the RC bit specified. */
1664#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1665
702f0fb4
PB		 1666/* A Z form instruction with the RC bit specified. */
1667#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
1668
252b5132
RH		 1669/* The mask for an X form instruction. */
1670#define X_MASK XRC (0x3f, 0x3ff, 1)
1671
702f0fb4
PB		 1672/* The mask for a Z form instruction. */
1673#define Z_MASK ZRC (0x3f, 0x1ff, 1)
1674
252b5132
RH		 1675/* An X_MASK with the RA field fixed. */
1676#define XRA_MASK (X_MASK | RA_MASK)
1677
1678/* An X_MASK with the RB field fixed. */
1679#define XRB_MASK (X_MASK | RB_MASK)
1680
1681/* An X_MASK with the RT field fixed. */
1682#define XRT_MASK (X_MASK | RT_MASK)
1683
702f0fb4
PB		 1684/* An XRT_MASK mask with the L bits clear. */
1685#define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
1686
252b5132
RH		 1687/* An X_MASK with the RA and RB fields fixed. */
1688#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1689
112290ab 1690/* An XRARB_MASK, but with the L bit clear. */
5ae2e65e
AM		 1691#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1692
252b5132
RH		 1693/* An X_MASK with the RT and RA fields fixed. */
1694#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1695
98acc1c5
AM		 1696/* An XRTRA_MASK, but with L bit clear. */
1697#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1698
f3806e43
BE		 1699/* An X form instruction with the L bit specified. */
1700#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
252b5132
RH		 1701
1702/* The mask for an X form comparison instruction. */
1703#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1704
520ceea4
BE		 1705/* The mask for an X form comparison instruction with the L field
1706 fixed. */
1707#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
252b5132
RH		 1708
1709/* An X form trap instruction with the TO field specified. */
1710#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1711#define XTO_MASK (X_MASK | TO_MASK)
1712
e0c21649
GK		 1713/* An X form tlb instruction with the SH field specified. */
1714#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1715#define XTLB_MASK (X_MASK | SH_MASK)
1716
6ba045b1
AM		 1717/* An X form sync instruction. */
1718#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1719
1720/* An X form sync instruction with everything filled in except the LS field. */
1721#define XSYNC_MASK (0xff9fffff)
1722
702f0fb4
PB		 1723/* An X_MASK, but with the EH bit clear. */
1724#define XEH_MASK (X_MASK & ~((unsigned long )1))
1725
f5c120c5
MG		 1726/* An X form AltiVec dss instruction. */
1727#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1728#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1729
252b5132
RH		 1730/* An XFL form instruction. */
1731#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1732#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1733
23976049
EZ		 1734/* An X form isel instruction. */
1735#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1736#define XISEL_MASK XISEL(0x3f, 0x1f)
1737
252b5132
RH		 1738/* An XL form instruction with the LK field set to 0. */
1739#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1740
1741/* An XL form instruction which uses the LK field. */
1742#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1743
1744/* The mask for an XL form instruction. */
1745#define XL_MASK XLLK (0x3f, 0x3ff, 1)
1746
1747/* An XL form instruction which explicitly sets the BO field. */
1748#define XLO(op, bo, xop, lk) \
1749 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1750#define XLO_MASK (XL_MASK | BO_MASK)
1751
1752/* An XL form instruction which explicitly sets the y bit of the BO
1753 field. */
1754#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1755#define XLYLK_MASK (XL_MASK | Y_MASK)
1756
1757/* An XL form instruction which sets the BO field and the condition
1758 bits of the BI field. */
1759#define XLOCB(op, bo, cb, xop, lk) \
1760 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1761#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1762
1763/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1764#define XLBB_MASK (XL_MASK | BB_MASK)
1765#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1766#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1767
d0618d1c
AM		 1768/* A mask for branch instructions using the BH field. */
1769#define XLBH_MASK (XL_MASK | (0x1c << 11))
1770
252b5132
RH		 1771/* An XL_MASK with the BO and BB fields fixed. */
1772#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1773
1774/* An XL_MASK with the BO, BI and BB fields fixed. */
1775#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1776
1777/* An XO form instruction. */
1778#define XO(op, xop, oe, rc) \
1779 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1780#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1781
1782/* An XO_MASK with the RB field fixed. */
1783#define XORB_MASK (XO_MASK | RB_MASK)
1784
1785/* An XS form instruction. */
1786#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1787#define XS_MASK XS (0x3f, 0x1ff, 1)
1788
1789/* A mask for the FXM version of an XFX form instruction. */
98e69875 1790#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
252b5132
RH		 1791
1792/* An XFX form instruction with the FXM field filled in. */
98e69875
AM		 1793#define XFXM(op, xop, fxm, p4) \
1794 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1795 | ((unsigned long)(p4) << 20))
252b5132
RH		 1796
1797/* An XFX form instruction with the SPR field filled in. */
1798#define XSPR(op, xop, spr) \
1799 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1800#define XSPR_MASK (X_MASK | SPR_MASK)
1801
1802/* An XFX form instruction with the SPR field filled in except for the
1803 SPRBAT field. */
1804#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1805
1806/* An XFX form instruction with the SPR field filled in except for the
1807 SPRG field. */
da99ee72 1808#define XSPRG_MASK (XSPR_MASK & ~(0x17 << 16))
252b5132
RH		 1809
1810/* An X form instruction with everything filled in except the E field. */
1811#define XE_MASK (0xffff7fff)
1812
23976049
EZ		 1813/* An X form user context instruction. */
1814#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1815#define XUC_MASK XUC(0x3f, 0x1f)
1816
252b5132
RH		 1817/* The BO encodings used in extended conditional branch mnemonics. */
1818#define BODNZF (0x0)
1819#define BODNZFP (0x1)
1820#define BODZF (0x2)
1821#define BODZFP (0x3)
252b5132
RH		 1822#define BODNZT (0x8)
1823#define BODNZTP (0x9)
1824#define BODZT (0xa)
1825#define BODZTP (0xb)
802a735e
AM		 1826
1827#define BOF (0x4)
1828#define BOFP (0x5)
94efba12
AM		 1829#define BOFM4 (0x6)
1830#define BOFP4 (0x7)
252b5132
RH		 1831#define BOT (0xc)
1832#define BOTP (0xd)
94efba12
AM		 1833#define BOTM4 (0xe)
1834#define BOTP4 (0xf)
802a735e 1835
252b5132
RH		 1836#define BODNZ (0x10)
1837#define BODNZP (0x11)
1838#define BODZ (0x12)
1839#define BODZP (0x13)
94efba12
AM		 1840#define BODNZM4 (0x18)
1841#define BODNZP4 (0x19)
1842#define BODZM4 (0x1a)
1843#define BODZP4 (0x1b)
802a735e 1844
252b5132
RH		 1845#define BOU (0x14)
1846
1847/* The BI condition bit encodings used in extended conditional branch
1848 mnemonics. */
1849#define CBLT (0)
1850#define CBGT (1)
1851#define CBEQ (2)
1852#define CBSO (3)
1853
1854/* The TO encodings used in extended trap mnemonics. */
1855#define TOLGT (0x1)
1856#define TOLLT (0x2)
1857#define TOEQ (0x4)
1858#define TOLGE (0x5)
1859#define TOLNL (0x5)
1860#define TOLLE (0x6)
1861#define TOLNG (0x6)
1862#define TOGT (0x8)
1863#define TOGE (0xc)
1864#define TONL (0xc)
1865#define TOLT (0x10)
1866#define TOLE (0x14)
1867#define TONG (0x14)
1868#define TONE (0x18)
1869#define TOU (0x1f)
1870\f
1871/* Smaller names for the flags so each entry in the opcodes table will
1872 fit on a single line. */
1873#undef PPC
661bd698
AM		 1874#define PPC PPC_OPCODE_PPC
1875#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
94efba12 1876#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
661bd698 1877#define POWER4 PPC_OPCODE_POWER4
1ed8e1e4 1878#define POWER5 PPC_OPCODE_POWER5
702f0fb4 1879#define POWER6 PPC_OPCODE_POWER6
ede602d7 1880#define CELL PPC_OPCODE_CELL
661bd698
AM		 1881#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
1882#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
418c1742 1883#define PPC403 PPC_OPCODE_403
e0c21649 1884#define PPC405 PPC403
7d5b217e 1885#define PPC440 PPC_OPCODE_440
252b5132
RH		 1886#define PPC750 PPC
1887#define PPC860 PPC
a404d431 1888#define PPCVEC PPC_OPCODE_ALTIVEC
661bd698
AM		 1889#define POWER PPC_OPCODE_POWER
1890#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1891#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1892#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1893#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1894#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1895#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
1896#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
252b5132 1897#define MFDEC1 PPC_OPCODE_POWER
dde1b132 1898#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
418c1742
MG		 1899#define BOOKE PPC_OPCODE_BOOKE
1900#define BOOKE64 PPC_OPCODE_BOOKE64
23976049 1901#define CLASSIC PPC_OPCODE_CLASSIC
36ae0db3 1902#define PPCE300 PPC_OPCODE_E300
23976049
EZ		 1903#define PPCSPE PPC_OPCODE_SPE
1904#define PPCISEL PPC_OPCODE_ISEL
1905#define PPCEFS PPC_OPCODE_EFS
1906#define PPCBRLK PPC_OPCODE_BRLOCK
1907#define PPCPMR PPC_OPCODE_PMR
1908#define PPCCHLK PPC_OPCODE_CACHELCK
dde1b132 1909#define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
23976049 1910#define PPCRFMCI PPC_OPCODE_RFMCI
252b5132
RH		 1911\f
1912/* The opcode table.
1913
1914 The format of the opcode table is:
1915
1916 NAME OPCODE MASK FLAGS { OPERANDS }
1917
1918 NAME is the name of the instruction.
1919 OPCODE is the instruction opcode.
1920 MASK is the opcode mask; this is used to tell the disassembler
1921 which bits in the actual opcode must match OPCODE.
1922 FLAGS are flags indicated what processors support the instruction.
1923 OPERANDS is the list of operands.
1924
1925 The disassembler reads the table in order and prints the first
1926 instruction which matches, so this table is sorted to put more
1927 specific instructions before more general instructions. It is also
1928 sorted by major opcode. */
1929
1930const struct powerpc_opcode powerpc_opcodes[] = {
adadcc0c 1931{ "attn", X(0,256), X_MASK, POWER4, { 0 } },
252b5132
RH		 1932{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
1933{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
1934{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
1935{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
1936{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
1937{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1938{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
1939{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
1940{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
1941{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
1942{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
1943{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
1944{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
1945{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
1946{ "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
1947
1948{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
1949{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
1950{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
1951{ "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
1952{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
1953{ "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
1954{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
1955{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
1956{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
1957{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
1958{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1959{ "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
1960{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
1961{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
1962{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
1963{ "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
1964{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
1965{ "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
1966{ "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
1967{ "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
1968{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
1969{ "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
1970{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
1971{ "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
1972{ "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
1973{ "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
1974{ "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
1975{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
1976{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
1977{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
e0c21649 1978
7d5b217e
AM		 1979{ "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1980{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1981{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1982{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1983{ "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1984{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1985{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1986{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1987{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1988{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1989{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1990{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1991{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1992{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1993{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1994{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1995{ "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1996{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1997{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1998{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1999{ "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2000{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2001{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2002{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2003{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2004{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2005{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2006{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2007{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2008{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2009{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2010{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2011{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2012{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2013{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2014{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2015{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2016{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2017{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2018{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2019{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2020{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2021{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2022{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2023{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2024{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2025{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2026{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2027{ "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2028{ "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2029{ "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2030{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2031{ "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2032{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2033{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2034{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2035{ "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2036{ "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2037{ "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2038{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2039{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2040{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2041{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2042{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2043{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2044{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2045{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2046{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2047{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2048{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2049{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2050{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2051{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2052{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2053{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2054{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2055{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2056{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2057{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2058{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2059{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2060{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2061{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2062{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
786e2c0f 2063{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
f5c120c5 2064{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
12c64a4e
AH		 2065
2066 /* Double-precision opcodes. */
2067 /* Some of these conflict with AltiVec, so move them before, since
2068 PPCVEC includes the PPC_OPCODE_PPC set. */
0e06657a 2069{ "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RB } },
12c64a4e
AH		 2070{ "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA } },
2071{ "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA } },
2072{ "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA } },
2073{ "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } },
2074{ "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } },
2075{ "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } },
2076{ "efddiv", VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB } },
2077{ "efdcmpgt", VX(4, 748), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2078{ "efdcmplt", VX(4, 749), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2079{ "efdcmpeq", VX(4, 750), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2080{ "efdtstgt", VX(4, 764), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2081{ "efdtstlt", VX(4, 765), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2082{ "efdtsteq", VX(4, 766), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2083{ "efdcfsi", VX(4, 753), VX_MASK, PPCEFS, { RS, RB } },
2084{ "efdcfsid", VX(4, 739), VX_MASK, PPCEFS, { RS, RB } },
2085{ "efdcfui", VX(4, 752), VX_MASK, PPCEFS, { RS, RB } },
2086{ "efdcfuid", VX(4, 738), VX_MASK, PPCEFS, { RS, RB } },
2087{ "efdcfsf", VX(4, 755), VX_MASK, PPCEFS, { RS, RB } },
2088{ "efdcfuf", VX(4, 754), VX_MASK, PPCEFS, { RS, RB } },
2089{ "efdctsi", VX(4, 757), VX_MASK, PPCEFS, { RS, RB } },
2090{ "efdctsidz",VX(4, 747), VX_MASK, PPCEFS, { RS, RB } },
2091{ "efdctsiz", VX(4, 762), VX_MASK, PPCEFS, { RS, RB } },
2092{ "efdctui", VX(4, 756), VX_MASK, PPCEFS, { RS, RB } },
2093{ "efdctuidz",VX(4, 746), VX_MASK, PPCEFS, { RS, RB } },
2094{ "efdctuiz", VX(4, 760), VX_MASK, PPCEFS, { RS, RB } },
2095{ "efdctsf", VX(4, 759), VX_MASK, PPCEFS, { RS, RB } },
2096{ "efdctuf", VX(4, 758), VX_MASK, PPCEFS, { RS, RB } },
2097{ "efdcfs", VX(4, 751), VX_MASK, PPCEFS, { RS, RB } },
2098 /* End of double-precision opcodes. */
2099
786e2c0f
C		 2100{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
2101{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
2102{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
2103{ "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
2104{ "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
2105{ "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
2106{ "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
2107{ "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
2108{ "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
2109{ "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
2110{ "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
2111{ "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
2112{ "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
2113{ "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
2114{ "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
2115{ "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
2116{ "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
2117{ "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
2118{ "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
2119{ "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2120{ "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2121{ "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2122{ "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2123{ "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2124{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2125{ "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2126{ "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2127{ "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2128{ "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2129{ "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2130{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2131{ "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2132{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2133{ "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2134{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2135{ "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2136{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2137{ "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2138{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2139{ "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2140{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2141{ "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2142{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2143{ "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2144{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2145{ "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2146{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2147{ "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2148{ "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2149{ "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
2150{ "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
294b41b3 2151{ "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
786e2c0f
C		 2152{ "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
2153{ "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
2154{ "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
2155{ "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
2156{ "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
2157{ "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
2158{ "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
2159{ "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2160{ "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2161{ "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
2162{ "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
2163{ "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
2164{ "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
2165{ "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
2166{ "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
2167{ "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
2168{ "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2169{ "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
2170{ "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
2171{ "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
2172{ "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
2173{ "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
2174{ "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
2175{ "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2176{ "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2177{ "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
d2f75a6f
GK		 2178{ "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2179{ "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2180{ "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
786e2c0f
C		 2181{ "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
2182{ "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
2183{ "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
2184{ "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
2185{ "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
2186{ "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
2187{ "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
2188{ "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
2189{ "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2190{ "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
2191{ "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
2192{ "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2193{ "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
2194{ "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
2195{ "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
2196{ "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
2197{ "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
2198{ "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
2199{ "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
2200{ "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
2201{ "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
2202{ "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
2203{ "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
2204{ "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
2205{ "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
2206{ "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
2207{ "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
2208{ "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
2209{ "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
2210{ "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
2211{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2212{ "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
2213{ "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
2214{ "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
2215{ "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
2216{ "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
1da5001c 2217{ "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
786e2c0f
C		 2218{ "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2219{ "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2220{ "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
2221{ "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
2222{ "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
2223{ "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2224{ "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
2225{ "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
2226{ "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
2227{ "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
2228{ "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
2229{ "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
2230{ "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
2231{ "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
2232{ "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
2233{ "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
2234{ "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
2235{ "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
2236{ "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
2237{ "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
2238{ "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
2239{ "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
2240{ "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
2241{ "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
2242{ "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
2243{ "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
2244{ "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
2245{ "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
2246{ "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
2247{ "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
2248{ "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
2249{ "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
2250{ "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
2251{ "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
2252{ "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
2253{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
2254{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
252b5132 2255
914749f6
AH		 2256{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
2257{ "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2258{ "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
2259{ "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
2260{ "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
2261{ "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2262{ "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
2263{ "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
2264{ "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
2265{ "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
2266{ "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
2267{ "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
2268{ "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
2269
2270{ "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2271
2272{ "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2273{ "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
dde1b132 2274{ "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
914749f6
AH		 2275{ "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2276{ "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2277{ "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2278{ "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2279{ "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
dde1b132 2280{ "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
914749f6
AH		 2281{ "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2282
2283{ "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2284{ "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2285{ "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2286{ "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2287{ "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2288{ "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2289{ "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2290{ "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2291{ "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
2292{ "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
fe587977
AH		 2293{ "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2294{ "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2295{ "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2296{ "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
23976049
EZ		 2297
2298{ "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2299{ "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2300{ "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2301{ "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2302{ "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
914749f6 2303{ "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
23976049
EZ		 2304
2305{ "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2306{ "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2307{ "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2308{ "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2309{ "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2310{ "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2311{ "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2312{ "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2313{ "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2314{ "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2315{ "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2316{ "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2317{ "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2318{ "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2319{ "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2320{ "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2321{ "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2322{ "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2323{ "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2324{ "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2325{ "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2326{ "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2327
2328{ "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2329{ "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2330{ "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2331{ "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2332{ "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2333{ "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2334{ "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2335{ "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2336{ "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2337{ "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2338{ "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2339{ "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2340{ "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2341{ "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2342
914749f6
AH		 2343{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
2344{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
2345{ "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
2346{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2347{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2348{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2349{ "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
23976049
EZ		 2350{ "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2351{ "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2352{ "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2353{ "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2354{ "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2355{ "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
914749f6
AH		 2356{ "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2357{ "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2358{ "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2359{ "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2360{ "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2361{ "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2362{ "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2363{ "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2364{ "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2365{ "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2366
2367{ "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
2368{ "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
2369{ "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
2370{ "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2371{ "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2372{ "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2373{ "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
23976049
EZ		 2374{ "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2375{ "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2376{ "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2377{ "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2378{ "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2379{ "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
914749f6
AH		 2380{ "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
2381{ "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
2382{ "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
2383{ "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
2384{ "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
2385{ "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
2386{ "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
2387{ "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
2388{ "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
2389{ "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
2390
914749f6
AH		 2391{ "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2392{ "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2393{ "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2394{ "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2395{ "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2396{ "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2397{ "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2398{ "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2399{ "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2400{ "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2401{ "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2402{ "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2403{ "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2404{ "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2405{ "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2406{ "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2407
2408{ "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2409{ "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2410{ "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2411{ "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2412{ "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2413{ "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2414{ "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2415{ "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2416{ "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2417{ "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2418{ "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2419{ "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2420
2421{ "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2422{ "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2423{ "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2424{ "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2425{ "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2426{ "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2427{ "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2428{ "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2429{ "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2430{ "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2431{ "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2432{ "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2433
2434{ "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2435{ "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2436{ "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2437{ "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2438{ "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2439{ "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2440
2441{ "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2442{ "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2443{ "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2444{ "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2445{ "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2446{ "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2447
2448{ "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2449{ "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2450{ "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2451{ "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2452{ "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2453{ "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2454{ "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2455{ "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2456
914749f6
AH		 2457{ "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2458{ "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2459
914749f6 2460{ "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
914749f6
AH		 2461{ "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2462{ "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2463{ "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2464
914749f6 2465{ "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
914749f6
AH		 2466{ "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2467{ "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2468{ "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2469
914749f6
AH		 2470{ "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2471{ "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2472{ "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2473{ "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2474{ "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2475{ "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2476{ "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2477{ "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2478
2479{ "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2480{ "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2481{ "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2482{ "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2483
2484{ "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2485{ "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2486{ "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2487{ "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2488
2489{ "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
2490{ "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
2491{ "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
2492{ "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
2493
2494{ "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
2495{ "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
2496{ "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
2497{ "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
2498
2499{ "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
2500
2501{ "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2502{ "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
23976049 2503
252b5132
RH		 2504{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
2505{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2506
2507{ "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
2508{ "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2509
2510{ "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
2511
418c1742
MG		 2512{ "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } },
2513{ "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } },
2514{ "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } },
2515{ "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } },
2516
252b5132
RH		 2517{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
2518{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
661bd698 2519{ "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
252b5132
RH		 2520{ "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2521
2522{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
2523{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
661bd698 2524{ "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
252b5132
RH		 2525{ "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2526
2527{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
2528{ "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2529{ "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
2530
2531{ "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
2532{ "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
2533{ "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
2534
2535{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
2536{ "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
fdd12ef3
AM		 2537{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } },
2538{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } },
2539{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2540{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } },
252b5132
RH		 2541
2542{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
2543{ "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
fdd12ef3
AM		 2544{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } },
2545{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } },
2546{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } },
252b5132 2547
112290ab
NC		 2548{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2549{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2550{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
2551{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
2552{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2553{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2554{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
2555{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
2556{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2557{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2558{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
2559{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
2560{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2561{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2562{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
2563{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
2564{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2565{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2566{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
2567{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2568{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2569{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
2570{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2571{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2572{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
2573{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2574{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2575{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
802a735e
AM		 2576{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2577{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2578{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2579{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2580{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2581{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2582{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2583{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2584{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2585{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2586{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2587{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2588{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2589{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2590{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2591{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2592{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2593{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2594{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2595{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2596{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2597{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2598{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2599{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2600{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2601{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2602{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2603{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2604{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2605{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2606{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2607{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2608{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2609{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2610{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2611{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2612{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2613{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2614{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2615{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2616{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2617{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2618{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2619{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2620{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2621{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2622{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2623{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2624{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2625{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2626{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2627{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2628{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2629{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2630{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2631{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2632{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2633{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2634{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2635{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2636{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2637{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2638{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2639{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2640{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2641{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2642{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2643{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2644{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2645{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2646{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2647{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2648{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2649{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2650{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2651{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2652{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2653{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2654{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2655{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2656{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2657{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2658{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2659{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2660{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2661{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2662{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2663{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2664{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2665{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2666{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2667{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2668{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2669{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2670{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2671{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2672{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2673{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2674{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2675{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2676{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2677{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2678{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2679{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2680{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2681{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2682{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2683{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2684{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2685{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2686{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2687{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2688{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2689{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2690{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2691{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2692{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2693{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2694{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2695{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2696{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2697{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2698{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2699{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2700{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2701{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2702{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2703{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2704{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2705{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2706{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2707{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2708{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2709{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2710{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2711{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2712{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2713{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2714{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2715{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2716{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2717{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2718{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2719{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
94efba12
AM		 2720{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2721{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2722{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2723{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2724{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2725{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2726{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2727{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2728{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2729{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2730{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2731{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2732{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2733{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2734{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2735{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2736{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2737{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2738{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2739{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2740{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2741{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2742{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2743{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
802a735e
AM		 2744{ "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2745{ "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2746{ "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2747{ "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2748{ "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2749{ "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2750{ "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2751{ "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2752{ "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2753{ "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2754{ "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2755{ "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2756{ "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2757{ "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2758{ "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2759{ "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2760{ "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2761{ "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2762{ "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2763{ "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2764{ "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2765{ "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2766{ "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2767{ "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2768{ "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2769{ "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2770{ "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2771{ "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2772{ "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2773{ "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2774{ "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2775{ "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
94efba12
AM		 2776{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2777{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2778{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2779{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2780{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2781{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2782{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2783{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2784{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2785{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2786{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2787{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2788{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2789{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2790{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2791{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2792{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2793{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2794{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2795{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2796{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2797{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2798{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2799{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
d2f75a6f
GK		 2800{ "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
2801{ "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
252b5132 2802{ "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
d2f75a6f
GK		 2803{ "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } },
2804{ "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } },
252b5132 2805{ "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
d2f75a6f
GK		 2806{ "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2807{ "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } },
252b5132 2808{ "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
d2f75a6f
GK		 2809{ "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2810{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
252b5132
RH		 2811{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
2812
1ed8e1e4
AM		 2813{ "sc", SC(17,1,0), SC_MASK, PPC, { LEV } },
2814{ "svc", SC(17,0,0), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } },
2815{ "svcl", SC(17,0,1), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } },
252b5132
RH		 2816{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
2817{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
2818
418c1742
MG		 2819{ "b", B(18,0,0), B_MASK, COM, { LI } },
2820{ "bl", B(18,0,1), B_MASK, COM, { LI } },
2821{ "ba", B(18,1,0), B_MASK, COM, { LIA } },
2822{ "bla", B(18,1,1), B_MASK, COM, { LIA } },
252b5132 2823
112290ab 2824{ "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } },
252b5132
RH		 2825
2826{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2827{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
2828{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2829{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
2830{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
94efba12 2831{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
94efba12 2832{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
823bbe9d 2833{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
94efba12 2834{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
252b5132 2835{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
94efba12 2836{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
94efba12 2837{ "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
823bbe9d 2838{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
94efba12 2839{ "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
252b5132 2840{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
94efba12 2841{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
94efba12 2842{ "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
823bbe9d 2843{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
94efba12 2844{ "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
252b5132 2845{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
94efba12 2846{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
94efba12 2847{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
823bbe9d 2848{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
94efba12 2849{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
252b5132 2850{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2851{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2852{ "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2853{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2854{ "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2855{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2856{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2857{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2858{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2859{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2860{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2861{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2862{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2863{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2864{ "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2865{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2866{ "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2867{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2868{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2869{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2870{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2871{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2872{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2873{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2874{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2875{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2876{ "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2877{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2878{ "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2879{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2880{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2881{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2882{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2883{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2884{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2885{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2886{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2887{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2888{ "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2889{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2890{ "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2891{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2892{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2893{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2894{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2895{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2896{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2897{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2898{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2899{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2900{ "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2901{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2902{ "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2903{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2904{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2905{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2906{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2907{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2908{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2909{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2910{ "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2911{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2912{ "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2913{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2914{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2915{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2916{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2917{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2918{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2919{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2920{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2921{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2922{ "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2923{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2924{ "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2925{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2926{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2927{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2928{ "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2929{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2930{ "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2931{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2932{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2933{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2934{ "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2935{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2936{ "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2937{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2938{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2939{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2940{ "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2941{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2942{ "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2943{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2944{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2945{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2946{ "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2947{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2948{ "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2949{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2950{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2951{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2952{ "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2953{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2954{ "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2955{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2956{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2957{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2958{ "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2959{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2960{ "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2961{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2962{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2963{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2964{ "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2965{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2966{ "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2967{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2968{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2969{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2970{ "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2971{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2972{ "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2973{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2974{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2975{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2976{ "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2977{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2978{ "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2979{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2980{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2981{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2982{ "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2983{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2984{ "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2985{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2986{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2987{ "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2988{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2989{ "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2990{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12 2991{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 2992{ "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
823bbe9d 2993{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 2994{ "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
252b5132
RH		 2995{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2996{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12 2997{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 2998{ "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
823bbe9d 2999{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 3000{ "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
252b5132
RH		 3001{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
3002{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12 3003{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 3004{ "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
823bbe9d 3005{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 3006{ "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } },
252b5132
RH		 3007{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
3008{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12 3009{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 3010{ "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
823bbe9d 3011{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 3012{ "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
252b5132
RH		 3013{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
3014{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 3015{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3016{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 3017{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 3018{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3019{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 3020{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 3021{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3022{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 3023{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 3024{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3025{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 3026{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 3027{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3028{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 3029{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 3030{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3031{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 3032{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 3033{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3034{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 3035{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 3036{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3037{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
d2f75a6f
GK		 3038{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3039{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3040{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3041{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
d0618d1c
AM		 3042{ "bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3043{ "bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
252b5132
RH		 3044{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
3045{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
418c1742
MG		 3046{ "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } },
3047{ "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } },
252b5132 3048
f509565f
GK		 3049{ "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
3050
252b5132
RH		 3051{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
3052{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
112290ab 3053{ "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
252b5132
RH		 3054
3055{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
823bbe9d 3056{ "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } },
252b5132
RH		 3057
3058{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
3059
3060{ "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
3061
3062{ "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
3063{ "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
3064
3065{ "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
3066{ "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
3067
3068{ "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
3069
3070{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
3071
ede602d7 3072{ "hrfid", XL(19,274), 0xffffffff, POWER5 | CELL, { 0 } },
1ed8e1e4 3073
252b5132
RH		 3074{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
3075{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
3076
702f0fb4
PB		 3077{ "doze", XL(19,402), 0xffffffff, POWER6, { 0 } },
3078
252b5132
RH		 3079{ "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
3080
702f0fb4
PB		 3081{ "nap", XL(19,434), 0xffffffff, POWER6, { 0 } },
3082
252b5132
RH		 3083{ "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
3084{ "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
3085
702f0fb4
PB		 3086{ "sleep", XL(19,466), 0xffffffff, POWER6, { 0 } },
3087{ "rvwinkle", XL(19,498), 0xffffffff, POWER6, { 0 } },
3088
252b5132
RH		 3089{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
3090{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
3091{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3092{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3093{ "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3094{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3095{ "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3096{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3097{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3098{ "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3099{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3100{ "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3101{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3102{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3103{ "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3104{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3105{ "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3106{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3107{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3108{ "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3109{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3110{ "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3111{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3112{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3113{ "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3114{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3115{ "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3116{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3117{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3118{ "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3119{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3120{ "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3121{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3122{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3123{ "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3124{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3125{ "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3126{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3127{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3128{ "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3129{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3130{ "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3131{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3132{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3133{ "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3134{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3135{ "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3136{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3137{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3138{ "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3139{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3140{ "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3141{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3142{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3143{ "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3144{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3145{ "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3146{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3147{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3148{ "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3149{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3150{ "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3151{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3152{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3153{ "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3154{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3155{ "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3156{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3157{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3158{ "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3159{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3160{ "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3161{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3162{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3163{ "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3164{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3165{ "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3166{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3167{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3168{ "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3169{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3170{ "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3171{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3172{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3173{ "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3174{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3175{ "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3176{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3177{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3178{ "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3179{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3180{ "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3181{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3182{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3183{ "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3184{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3185{ "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3186{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3187{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3188{ "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3189{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3190{ "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3191{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3192{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3193{ "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3194{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3195{ "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3196{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3197{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3198{ "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3199{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3200{ "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3201{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3202{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3203{ "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3204{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3205{ "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3206{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3207{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3208{ "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3209{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3210{ "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3211{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12 3212{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 3213{ "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
823bbe9d 3214{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 3215{ "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
252b5132 3216{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12 3217{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 3218{ "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
823bbe9d 3219{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 3220{ "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
252b5132 3221{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12 3222{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 3223{ "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
823bbe9d 3224{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 3225{ "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
252b5132 3226{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12 3227{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 3228{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
823bbe9d 3229{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 3230{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
d2f75a6f
GK		 3231{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3232{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
d2f75a6f
GK		 3233{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3234{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
d0618d1c
AM		 3235{ "bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3236{ "bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
252b5132
RH		 3237{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
3238{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
418c1742
MG		 3239{ "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } },
3240{ "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } },
252b5132
RH		 3241
3242{ "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3243{ "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3244
3245{ "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3246{ "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3247
3248{ "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
3249{ "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3250{ "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3251{ "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3252{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
3253{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3254{ "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3255{ "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3256
3257{ "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3258{ "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3259
418c1742
MG		 3260{ "be", B(22,0,0), B_MASK, BOOKE64, { LI } },
3261{ "bel", B(22,0,1), B_MASK, BOOKE64, { LI } },
3262{ "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } },
3263{ "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } },
3264
252b5132
RH		 3265{ "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3266{ "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3267{ "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3268{ "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3269{ "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3270{ "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3271
3272{ "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
3273{ "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
3274{ "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
3275
3276{ "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
3277{ "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
3278
3279{ "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
3280{ "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
3281
3282{ "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
3283{ "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
3284
3285{ "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
3286{ "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
3287
3288{ "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
3289{ "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
3290
3291{ "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3292{ "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3293{ "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3294{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3295{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3296{ "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3297
3298{ "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3299{ "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3300
3301{ "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3302{ "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3303
3304{ "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3305{ "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3306
3307{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
3308{ "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3309{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
3310{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3311
3312{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3313{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3314
520ceea4
BE		 3315{ "cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3316{ "cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
661bd698 3317{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
520ceea4 3318{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
252b5132
RH		 3319
3320{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
3321{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
3322{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
3323{ "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
3324{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
3325{ "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
3326{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
3327{ "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
3328{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
3329{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
3330{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3331{ "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3332{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
3333{ "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
3334{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
3335{ "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
3336{ "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
3337{ "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
3338{ "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
3339{ "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
3340{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
3341{ "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
3342{ "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
3343{ "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
3344{ "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
3345{ "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
3346{ "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
3347{ "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
3348{ "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
3349{ "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
3350{ "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
3351
3352{ "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3353{ "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3354{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
3355{ "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3356{ "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3357{ "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
3358{ "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3359{ "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3360{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
3361{ "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3362{ "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3363{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
3364
3365{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3366{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3367
3368{ "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3369{ "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3370{ "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3371{ "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3372{ "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3373{ "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3374{ "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3375{ "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3376
3377{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
3378{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
3379
dde1b132
NC		 3380{ "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3381{ "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3382{ "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3383{ "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
23976049 3384
98e69875 3385{ "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } },
a9353e60 3386{ "mfcr", X(31,19), XRARB_MASK, NOPOWER4 | COM, { RT } },
c168870a 3387{ "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
252b5132 3388
702f0fb4 3389{ "lwarx", X(31,20), XEH_MASK, PPC, { RT, RA0, RB, EH } },
252b5132 3390
fdd12ef3 3391{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } },
252b5132 3392
36ae0db3 3393{ "icbt", X(31,22), X_MASK, BOOKE|PPCE300, { CT, RA, RB } },
823bbe9d 3394{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
418c1742 3395
fdd12ef3 3396{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } },
252b5132
RH		 3397{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
3398
3399{ "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
3400{ "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
3401{ "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
3402{ "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
3403
3404{ "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
3405{ "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
3406{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
3407{ "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
3408
3409{ "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
3410{ "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
3411
3412{ "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
3413{ "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
3414
3415{ "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
3416{ "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
3417
418c1742
MG		 3418{ "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
3419
fdd12ef3 3420{ "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } },
418c1742 3421
520ceea4
BE		 3422{ "cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3423{ "cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
661bd698 3424{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
520ceea4 3425{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
252b5132
RH		 3426
3427{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
3428{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
3429{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
3430{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
3431{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
3432{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
3433{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
3434{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
3435
3436{ "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
3437
3438{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
3439
3440{ "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
3441{ "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3442
418c1742
MG		 3443{ "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
3444
3445{ "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
3446
252b5132
RH		 3447{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
3448{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
3449
418c1742
MG		 3450{ "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
3451{ "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
252b5132
RH		 3452
3453{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
3454{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
3455{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
3456{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
3457{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
3458{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
3459{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
3460{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
3461{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
3462{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
3463{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
3464{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
3465{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
3466{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
3467{ "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3468
3469{ "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3470{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3471
3472{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
3473{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3474
7d5b217e
AM		 3475{ "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3476{ "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3477
f509565f
GK		 3478{ "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
3479
252b5132
RH		 3480{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
3481
702f0fb4 3482{ "ldarx", X(31,84), XEH_MASK, PPC64, { RT, RA0, RB, EH } },
252b5132 3483
702f0fb4
PB		 3484{ "dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, { RA, RB } },
3485{ "dcbf", X(31,86), XLRT_MASK, PPC, { RA, RB, XRT_L } },
252b5132 3486
fdd12ef3 3487{ "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
252b5132 3488
418c1742
MG		 3489{ "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
3490
fdd12ef3 3491{ "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } },
418c1742 3492
252b5132
RH		 3493{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
3494{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
3495{ "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
3496{ "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
3497
3498{ "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
3499{ "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
3500{ "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
3501{ "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
3502
f509565f
GK		 3503{ "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
3504
2dd46b8b 3505{ "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
252b5132
RH		 3506
3507{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3508
1ed8e1e4
AM		 3509{ "popcntb", X(31,122), XRB_MASK, POWER5, { RA, RS } },
3510
252b5132
RH		 3511{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
3512{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3513{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
3514{ "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3515
fdd12ef3 3516{ "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } },
418c1742
MG		 3517
3518{ "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3519
823bbe9d 3520{ "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } },
252b5132 3521
23976049
EZ		 3522{ "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
3523
252b5132
RH		 3524{ "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3525{ "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3526{ "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3527{ "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3528{ "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3529{ "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3530{ "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3531{ "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3532
3533{ "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3534{ "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3535{ "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3536{ "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3537{ "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3538{ "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3539{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3540{ "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3541
dde1b132 3542{ "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
23976049 3543
98e69875
AM		 3544{ "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } },
3545{ "mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, { RS }},
252b5132
RH		 3546{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
3547
3548{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
3549
fdd12ef3 3550{ "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } },
252b5132 3551
fdd12ef3 3552{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } },
252b5132 3553
fdd12ef3 3554{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } },
252b5132
RH		 3555{ "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3556
fdd12ef3 3557{ "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } },
418c1742 3558
fdd12ef3 3559{ "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } },
418c1742 3560
252b5132
RH		 3561{ "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3562{ "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
3563
3564{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3565{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3566
702f0fb4
PB		 3567{ "prtyw", X(31,154), XRB_MASK, POWER6, { RA, RS } },
3568
823bbe9d 3569{ "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } },
252b5132 3570
23976049 3571{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
dde1b132 3572{ "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
23976049 3573
82674a1f 3574{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } },
f509565f 3575
252b5132
RH		 3576{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
3577
3578{ "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
fdd12ef3 3579{ "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } },
252b5132
RH		 3580
3581{ "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
3582{ "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
3583
702f0fb4
PB		 3584{ "prtyd", X(31,186), XRB_MASK, POWER6, { RA, RS } },
3585
418c1742
MG		 3586{ "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
3587
252b5132
RH		 3588{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3589{ "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3590{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3591{ "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3592{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3593{ "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3594{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3595{ "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3596
3597{ "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3598{ "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3599{ "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3600{ "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3601{ "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3602{ "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3603{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3604{ "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3605
3606{ "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
3607
fdd12ef3 3608{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } },
252b5132 3609
fdd12ef3 3610{ "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } },
252b5132
RH		 3611
3612{ "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3613{ "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
3614
3615{ "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3616{ "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3617
fdd12ef3 3618{ "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } },
418c1742 3619
23976049
EZ		 3620{ "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
3621
252b5132
RH		 3622{ "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3623{ "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3624{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3625{ "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3626{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3627{ "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3628{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3629{ "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3630
3631{ "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3632{ "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3633{ "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3634{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3635
3636{ "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3637{ "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3638{ "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3639{ "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3640{ "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3641{ "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3642{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3643{ "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3644
3645{ "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3646{ "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3647{ "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3648{ "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3649{ "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3650{ "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3651{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3652{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3653
dde1b132 3654{ "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
252b5132
RH		 3655{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3656{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3657
e5d2b64f 3658{ "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } },
252b5132
RH		 3659
3660{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3661
3662{ "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3663{ "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3664
418c1742
MG		 3665{ "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3666
3667{ "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3668
9fa87a06
MG		 3669{ "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3670
252b5132
RH		 3671{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3672{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3673{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3674{ "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3675
3676{ "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3677{ "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3678{ "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3679{ "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3680{ "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3681{ "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3682{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3683{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3684
5e8cb021 3685{ "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
c1a34e60 3686
418c1742
MG		 3687{ "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3688
252b5132
RH		 3689{ "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3690{ "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3691
ede602d7 3692{ "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } },
252b5132 3693
fdd12ef3 3694{ "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } },
252b5132 3695
252b5132
RH		 3696{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3697{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3698
418c1742
MG		 3699{ "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3700
fdd12ef3 3701{ "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } },
418c1742 3702
98acc1c5 3703{ "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
fdd12ef3 3704{ "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } },
252b5132
RH		 3705
3706{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3707
3708{ "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3709
3710{ "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3711{ "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3712
418c1742
MG		 3713{ "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3714
dde1b132
NC		 3715{ "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3716{ "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3717{ "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3718{ "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3719{ "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3720{ "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3721{ "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3722{ "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3723{ "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3724{ "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3725{ "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3726{ "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3727{ "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
252b5132
RH		 3728{ "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3729{ "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3730{ "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3731{ "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3732{ "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3733{ "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3734{ "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3735{ "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3736{ "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
3737{ "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
3738{ "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
3739{ "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
3740{ "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
3741{ "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
3742{ "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
3743{ "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
3744{ "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
3745{ "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
3746{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
3747{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
dde1b132 3748{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
823bbe9d 3749{ "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } },
252b5132
RH		 3750
3751{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3752{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3753{ "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3754{ "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3755
914749f6 3756{ "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
23976049 3757
dde1b132
NC		 3758{ "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
3759{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
3760{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
3761{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
3762{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
823bbe9d 3763{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
dde1b132
NC		 3764{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
3765{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
3766{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
3767{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
3768{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
dde1b132
NC		 3769{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
3770{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
3771{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
3772{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
702f0fb4 3773{ "mfcfar", XSPR(31,339,28), XSPR_MASK, POWER6, { RT } },
dde1b132 3774{ "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3775{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
dde1b132
NC		 3776{ "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
3777{ "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
3778{ "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3779{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
dde1b132 3780{ "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3781{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
dde1b132
NC		 3782{ "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
3783{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
3784{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
3785{ "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
3786{ "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
3787{ "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
3788{ "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
3789{ "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
3790{ "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
3791{ "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
3792{ "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
3793{ "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
3794{ "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
3795{ "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
3796{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
3797{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
3798{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
3799{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
3800{ "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3801{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
661bd698 3802{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3803{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
661bd698 3804{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3805{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
661bd698 3806{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
da99ee72 3807{ "mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, { RT, SPRG } },
dde1b132
NC		 3808{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
3809{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
3810{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
3811{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
da99ee72
AM		 3812{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405 | BOOKE, { RT } },
3813{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405 | BOOKE, { RT } },
3814{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405 | BOOKE, { RT } },
3815{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405 | BOOKE, { RT } },
dde1b132
NC		 3816{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
3817{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
3818{ "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
3819{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
3820{ "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3821{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
dde1b132 3822{ "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3823{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
dde1b132 3824{ "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3825{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
dde1b132
NC		 3826{ "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
3827{ "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3828{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
dde1b132 3829{ "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3830{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
dde1b132 3831{ "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3832{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
dde1b132 3833{ "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3834{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
dde1b132 3835{ "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3836{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
dde1b132 3837{ "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3838{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
dde1b132 3839{ "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3840{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
dde1b132 3841{ "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3842{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
dde1b132 3843{ "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3844{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
dde1b132 3845{ "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3846{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
dde1b132
NC		 3847{ "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
3848{ "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
3849{ "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
3850{ "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } },
3851{ "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } },
3852{ "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } },
3853{ "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } },
3854{ "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } },
3855{ "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } },
3856{ "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } },
3857{ "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } },
3858{ "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } },
3859{ "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } },
3860{ "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } },
3861{ "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } },
3862{ "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
3863{ "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
3864{ "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
914749f6 3865{ "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
f0b26da6
AH		 3866{ "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT } },
3867{ "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT } },
3868{ "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT } },
2f3b8700 3869{ "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
dde1b132
NC		 3870{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3871{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3872{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3873{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3874{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
3875{ "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
3876{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
3877{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3878{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
dde1b132 3879{ "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
1f04b05f 3880{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
dde1b132
NC		 3881{ "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
3882{ "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
23d59c56 3883{ "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } },
dde1b132
NC		 3884{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3885{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3886{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
3887{ "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
3888{ "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
3889{ "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
3890{ "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
3891{ "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
3892{ "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
3893{ "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
3894{ "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
3895{ "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
3896{ "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
3897{ "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
3898{ "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
3899{ "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
3900{ "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
3901{ "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
3902{ "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
3903{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
3904{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
3905{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
3906{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
3907{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
3908{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
3909{ "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
3910{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
3911{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
3912{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
3913{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
dde1b132 3914{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
252b5132
RH		 3915{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
3916{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
e0c21649 3917{ "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
252b5132 3918{ "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
e0c21649 3919{ "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
252b5132 3920{ "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
e0c21649 3921{ "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
252b5132 3922{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
e0c21649 3923{ "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
252b5132
RH		 3924{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
3925{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
dde1b132 3926{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
dde1b132
NC		 3927{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
3928{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
dde1b132
NC		 3929{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
3930{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
3931{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
3932{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
3933{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
dde1b132
NC		 3934{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
3935{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
3936{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
3937{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
3938{ "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
3939{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
3940{ "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
3941{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
3942{ "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
3943{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
3944{ "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
3945{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
252b5132 3946
fdd12ef3 3947{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } },
252b5132 3948
f5c120c5
MG		 3949{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3950{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3951
fdd12ef3 3952{ "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } },
252b5132 3953
fdd12ef3 3954{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } },
418c1742 3955
f5c120c5
MG		 3956{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3957{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3958
7d5b217e 3959{ "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } },
252b5132
RH		 3960
3961{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
3962{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
3963{ "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
3964{ "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
3965
3966{ "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
3967{ "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
3968{ "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
3969{ "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
3970
3971{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
3972
252b5132
RH		 3973{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
3974
3975{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
3976
418c1742
MG		 3977{ "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
3978
9fa87a06
MG		 3979{ "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
3980
23976049
EZ		 3981{ "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
3982
418c1742
MG		 3983{ "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3984{ "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3985
3986{ "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3987{ "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3988
dde1b132 3989{ "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
23976049 3990
6ba045b1
AM		 3991{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
3992
fdd12ef3 3993{ "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
252b5132 3994
702f0fb4
PB		 3995{ "cmpb", X(31,508), X_MASK, POWER6, { RA, RS, RB } },
3996
252b5132
RH		 3997{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
3998
702f0fb4
PB		 3999{ "lfdpx", X(31,791), X_MASK, POWER6, { FRT, RA, RB } },
4000
252b5132
RH		 4001{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
4002
4003{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
4004
702f0fb4
PB		 4005{ "stfdpx", X(31,919), X_MASK, POWER6, { FRS, RA, RB } },
4006
252b5132
RH		 4007{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
4008
4009{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
4010{ "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
4011
4012{ "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
4013{ "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
4014
fdd12ef3 4015{ "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } },
418c1742 4016
252b5132
RH		 4017{ "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
4018
4019{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
4020
4021{ "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
4022
418c1742
MG		 4023{ "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
4024
252b5132
RH		 4025{ "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
4026{ "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
4027{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
4028{ "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
4029
823bbe9d
AM		 4030{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } },
4031{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } },
4032{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } },
4033{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } },
4034{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } },
4035{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } },
4036{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } },
4037{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } },
4038{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } },
4039{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } },
4040{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } },
4041{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } },
4042{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } },
4043{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } },
4044{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } },
4045{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } },
4046{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } },
4047{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } },
4048{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } },
4049{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } },
4050{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } },
4051{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } },
4052{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } },
4053{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } },
4054{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } },
4055{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } },
4056{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } },
4057{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } },
4058{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } },
4059{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } },
4060{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } },
4061{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } },
4062{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } },
4063{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } },
4064{ "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } },
252b5132 4065
418c1742
MG		 4066{ "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4067{ "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4068
252b5132
RH		 4069{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4070{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4071{ "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4072{ "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4073
418c1742
MG		 4074{ "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4075{ "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4076
252b5132
RH		 4077{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
4078{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
4079{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
4080{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
4081
dde1b132
NC		 4082{ "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
4083{ "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
4084{ "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
4085{ "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
4086{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
4087{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
4088{ "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
4089{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
4090{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
4091{ "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
4092{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
4093{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
4094{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
4095{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
702f0fb4 4096{ "mtcfar", XSPR(31,467,28), XSPR_MASK, POWER6, { RS } },
dde1b132 4097{ "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4098{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } },
dde1b132
NC		 4099{ "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
4100{ "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
4101{ "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
4102{ "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4103{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } },
dde1b132 4104{ "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4105{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } },
dde1b132 4106{ "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
823bbe9d
AM		 4107{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } },
4108{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } },
4109{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } },
4110{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } },
4111{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } },
4112{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } },
4113{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } },
4114{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } },
4115{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } },
4116{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } },
4117{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } },
4118{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } },
4119{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } },
4120{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } },
4121{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } },
4122{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } },
4123{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } },
dde1b132 4124{ "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
da99ee72 4125{ "mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, { SPRG, RS } },
823bbe9d
AM		 4126{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } },
4127{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } },
4128{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } },
4129{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } },
4130{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } },
4131{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } },
4132{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } },
4133{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } },
dde1b132
NC		 4134{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
4135{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
4136{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
4137{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
4138{ "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4139{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } },
dde1b132 4140{ "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4141{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } },
dde1b132 4142{ "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4143{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } },
dde1b132
NC		 4144{ "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
4145{ "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4146{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } },
dde1b132 4147{ "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4148{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } },
dde1b132 4149{ "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4150{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } },
dde1b132 4151{ "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4152{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } },
dde1b132 4153{ "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4154{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } },
dde1b132 4155{ "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4156{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } },
dde1b132 4157{ "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4158{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } },
dde1b132 4159{ "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4160{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } },
dde1b132 4161{ "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4162{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } },
dde1b132 4163{ "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4164{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } },
dde1b132
NC		 4165{ "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
4166{ "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
4167{ "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
4168{ "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } },
4169{ "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } },
4170{ "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } },
4171{ "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } },
4172{ "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } },
4173{ "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } },
4174{ "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } },
4175{ "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } },
4176{ "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } },
4177{ "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } },
4178{ "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } },
4179{ "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } },
4180{ "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
42a2f80a 4181{ "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
dde1b132 4182{ "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
914749f6 4183{ "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
f0b26da6
AH		 4184{ "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS } },
4185{ "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS } },
4186{ "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS } },
2f3b8700 4187{ "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
dde1b132
NC		 4188{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4189{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4190{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4191{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4192{ "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
4193{ "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
4194{ "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
823bbe9d
AM		 4195{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } },
4196{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } },
4197{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } },
4198{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } },
4199{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } },
4200{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } },
4201{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } },
4202{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } },
4203{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } },
4204{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } },
4205{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } },
4206{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } },
4207{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } },
4208{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } },
4209{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } },
4210{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } },
4211{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } },
4212{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } },
4213{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } },
4214{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } },
4215{ "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } },
4216{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } },
4217{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } },
4218{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } },
4219{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } },
4220{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } },
4221{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } },
4222{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } },
4223{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } },
4224{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } },
4225{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } },
4226{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } },
4227{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } },
4228{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } },
4229{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } },
4230{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } },
4231{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } },
4232{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } },
4233{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } },
dde1b132 4234{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
252b5132
RH		 4235
4236{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
4237
4238{ "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
4239{ "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
4240
418c1742
MG		 4241{ "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
4242
7d5b217e 4243{ "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
252b5132 4244
914749f6 4245{ "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
23976049
EZ		 4246
4247{ "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
4248
252b5132 4249{ "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
418c1742 4250{ "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
252b5132
RH		 4251{ "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
4252{ "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
418c1742 4253{ "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
252b5132
RH		 4254{ "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
4255
4256{ "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4257{ "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4258{ "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4259{ "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4260
418c1742
MG		 4261{ "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4262{ "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4263
252b5132
RH		 4264{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4265{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4266{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4267{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4268
dde1b132 4269{ "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
23976049 4270
252b5132
RH		 4271{ "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
4272
4273{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
4274
418c1742
MG		 4275{ "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
4276
252b5132
RH		 4277{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
4278
23976049 4279{ "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }},
dde1b132 4280{ "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } },
418c1742 4281
252b5132
RH		 4282{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
4283
ede602d7
AM		 4284{ "ldbrx", X(31,532), X_MASK, CELL, { RT, RA0, RB } },
4285
fdd12ef3 4286{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } },
252b5132
RH		 4287{ "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4288
fdd12ef3 4289{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } },
252b5132
RH		 4290{ "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
4291
fdd12ef3 4292{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } },
252b5132
RH		 4293
4294{ "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4295{ "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4296{ "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4297{ "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
4298
4299{ "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
4300{ "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
4301
4302{ "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
4303{ "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
4304
4305{ "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4306{ "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4307
fdd12ef3 4308{ "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } },
418c1742 4309
fdd12ef3 4310{ "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } },
418c1742 4311
23976049 4312{ "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }},
fdd12ef3 4313
252b5132
RH		 4314{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
4315
4316{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
4317
418c1742
MG		 4318{ "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
4319
252b5132
RH		 4320{ "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
4321
fdd12ef3
AM		 4322{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } },
4323{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } },
252b5132 4324
661bd698 4325{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } },
6ba045b1 4326{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
b6be6416 4327{ "msync", X(31,598), 0xffffffff, BOOKE, { 0 } },
6ba045b1 4328{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
252b5132
RH		 4329{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4330
fdd12ef3 4331{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } },
252b5132 4332
fdd12ef3 4333{ "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } },
418c1742 4334
702f0fb4
PB		 4335{ "mffgpr", XRC(31,607,0), XRA_MASK, POWER6, { FRT, RB } },
4336
252b5132
RH		 4337{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4338
4339{ "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
4340
4341{ "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
4342
418c1742
MG		 4343{ "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
4344
252b5132
RH		 4345{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4346
ede602d7
AM		 4347{ "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB } },
4348
fdd12ef3
AM		 4349{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } },
4350{ "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } },
252b5132 4351
fdd12ef3
AM		 4352{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } },
4353{ "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } },
252b5132 4354
fdd12ef3 4355{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } },
252b5132
RH		 4356
4357{ "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4358{ "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
4359
4360{ "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4361{ "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
4362
fdd12ef3 4363{ "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } },
418c1742 4364
fdd12ef3
AM		 4365{ "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } },
4366
252b5132
RH		 4367{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
4368
4369{ "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
4370{ "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
4371
418c1742
MG		 4372{ "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
4373
fdd12ef3
AM		 4374{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } },
4375{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } },
252b5132 4376
fdd12ef3 4377{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } },
252b5132
RH		 4378
4379{ "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4380{ "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
4381
4382{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4383{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4384
fdd12ef3
AM		 4385{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } },
4386
702f0fb4
PB		 4387{ "mftgpr", XRC(31,735,0), XRA_MASK, POWER6, { RT, FRB } },
4388
823bbe9d 4389{ "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } },
e0c21649 4390
252b5132
RH		 4391{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
4392
4393{ "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
4394{ "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
4395
418c1742
MG		 4396{ "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
4397
4398{ "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
4399
4400{ "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
dde1b132 4401{ "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
418c1742 4402
702f0fb4
PB		 4403{ "lwzcix", X(31,789), X_MASK, POWER6, { RT, RA0, RB } },
4404
fdd12ef3 4405{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } },
252b5132
RH		 4406
4407{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4408{ "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
4409{ "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4410{ "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
4411
4412{ "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4413{ "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
4414
fdd12ef3 4415{ "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } },
418c1742 4416
fdd12ef3
AM		 4417{ "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } },
4418{ "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } },
418c1742 4419
252b5132
RH		 4420{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4421
702f0fb4
PB		 4422{ "lhzcix", X(31,821), X_MASK, POWER6, { RT, RA0, RB } },
4423
f5c120c5 4424{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
eb0fdfed 4425{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } },
f5c120c5 4426
252b5132
RH		 4427{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
4428{ "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
4429{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
4430{ "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
4431
6ba045b1
AM		 4432{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4433
702f0fb4
PB		 4434{ "lbzcix", X(31,853), X_MASK, POWER6, { RT, RA0, RB } },
4435
b6be6416 4436{ "mbar", X(31,854), X_MASK, BOOKE, { MO } },
252b5132
RH		 4437{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
4438
702f0fb4
PB		 4439{ "lfiwax", X(31,855), X_MASK, POWER6, { FRT, RA0, RB } },
4440
4441{ "ldcix", X(31,885), X_MASK, POWER6, { RT, RA0, RB } },
4442
eed0d89a
AM		 4443{ "tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4444{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
dde1b132
NC		 4445{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } },
4446{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } },
418c1742 4447
6ba045b1
AM		 4448{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4449
702f0fb4
PB		 4450{ "stwcix", X(31,917), X_MASK, POWER6, { RS, RA0, RB } },
4451
fdd12ef3 4452{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } },
252b5132
RH		 4453
4454{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4455{ "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
4456
4457{ "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
4458{ "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
4459
4460{ "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
4461{ "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
4462{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
4463{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
4464
fdd12ef3 4465{ "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } },
418c1742 4466
fdd12ef3 4467{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } },
418c1742 4468
e0c21649
GK		 4469{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
4470{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
eed0d89a 4471{ "tlbre", X(31,946), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
252b5132 4472
702f0fb4
PB		 4473{ "sthcix", X(31,949), X_MASK, POWER6, { RS, RA0, RB } },
4474
252b5132
RH		 4475{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
4476{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
4477
4478{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
4479{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
4480
418c1742
MG		 4481{ "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
4482
7d5b217e 4483{ "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } },
252b5132 4484
e0c21649
GK		 4485{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
4486{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
fdd12ef3 4487{ "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
823bbe9d 4488{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
252b5132 4489
702f0fb4
PB		 4490{ "stbcix", X(31,981), X_MASK, POWER6, { RS, RA0, RB } },
4491
252b5132
RH		 4492{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
4493
fdd12ef3 4494{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } },
252b5132 4495
dde1b132
NC		 4496{ "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
4497{ "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
252b5132 4498
7d5b217e 4499{ "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } },
252b5132 4500
418c1742 4501{ "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
fdd12ef3 4502{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } },
418c1742 4503
252b5132
RH		 4504{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
4505
702f0fb4
PB		 4506{ "stdcix", X(31,1013), X_MASK, POWER6, { RS, RA0, RB } },
4507
f3806e43 4508{ "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } },
252b5132
RH		 4509{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4510{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4511
418c1742
MG		 4512{ "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
4513
786e2c0f
C		 4514{ "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
4515{ "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
4516{ "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4517{ "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4518{ "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4519{ "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4520{ "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4521{ "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4522{ "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4523{ "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4524{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4525{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4526
ede602d7
AM		 4527/* New load/store left/right index vector instructions that are in the Cell only. */
4528{ "lvlx", X(31, 519), X_MASK, CELL, { VD, RA0, RB } },
4529{ "lvlxl", X(31, 775), X_MASK, CELL, { VD, RA0, RB } },
4530{ "lvrx", X(31, 551), X_MASK, CELL, { VD, RA0, RB } },
4531{ "lvrxl", X(31, 807), X_MASK, CELL, { VD, RA0, RB } },
4532{ "stvlx", X(31, 647), X_MASK, CELL, { VS, RA0, RB } },
4533{ "stvlxl", X(31, 903), X_MASK, CELL, { VS, RA0, RB } },
4534{ "stvrx", X(31, 679), X_MASK, CELL, { VS, RA0, RB } },
4535{ "stvrxl", X(31, 935), X_MASK, CELL, { VS, RA0, RB } },
4536
fdd12ef3
AM		 4537{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } },
4538{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
252b5132
RH		 4539
4540{ "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
fdd12ef3 4541{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } },
252b5132 4542
fdd12ef3 4543{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } },
252b5132
RH		 4544
4545{ "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
4546
fdd12ef3
AM		 4547{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } },
4548{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } },
252b5132
RH		 4549
4550{ "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
fdd12ef3 4551{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } },
252b5132 4552
fdd12ef3 4553{ "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } },
252b5132
RH		 4554
4555{ "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
4556
fdd12ef3 4557{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } },
252b5132
RH		 4558
4559{ "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
4560
fdd12ef3 4561{ "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } },
252b5132
RH		 4562
4563{ "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
4564
fdd12ef3 4565{ "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } },
252b5132
RH		 4566
4567{ "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
4568
4569{ "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
fdd12ef3 4570{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } },
252b5132 4571
fdd12ef3
AM		 4572{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } },
4573{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } },
252b5132 4574
fdd12ef3 4575{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } },
252b5132
RH		 4576
4577{ "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
4578
fdd12ef3 4579{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } },
252b5132
RH		 4580
4581{ "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
4582
fdd12ef3 4583{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } },
252b5132
RH		 4584
4585{ "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
4586
fdd12ef3 4587{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } },
252b5132
RH		 4588
4589{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
4590
adadcc0c
AM		 4591{ "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
4592
fdd12ef3 4593{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } },
252b5132 4594
fdd12ef3 4595{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } },
252b5132 4596
702f0fb4
PB		 4597{ "lfdp", OP(57), OP_MASK, POWER6, { FRT, D, RA0 } },
4598
fdd12ef3 4599{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } },
418c1742 4600{ "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
fdd12ef3 4601{ "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } },
418c1742 4602{ "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
fdd12ef3 4603{ "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA0 } },
418c1742 4604{ "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
fdd12ef3 4605{ "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA0 } },
418c1742 4606{ "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
fdd12ef3 4607{ "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA0 } },
418c1742 4608{ "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
fdd12ef3 4609{ "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA0 } },
418c1742 4610{ "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
fdd12ef3 4611{ "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA0 } },
418c1742
MG		 4612{ "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
4613
fdd12ef3 4614{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } },
802a735e
AM		 4615
4616{ "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
4617
fdd12ef3
AM		 4618{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } },
4619
702f0fb4
PB		 4620{ "dadd", XRC(59,2,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4621{ "dadd.", XRC(59,2,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4622
4623{ "dqua", ZRC(59,3,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4624{ "dqua.", ZRC(59,3,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4625
252b5132
RH		 4626{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4627{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4628
4629{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4630{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4631
4632{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4633{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4634
4635{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4636{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4637
702f0fb4
PB		 4638{ "fres", A(59,24,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4639{ "fres.", A(59,24,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
252b5132
RH		 4640
4641{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4642{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4643
702f0fb4
PB		 4644{ "frsqrtes", A(59,26,0), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } },
4645{ "frsqrtes.",A(59,26,1), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } },
1ed8e1e4 4646
252b5132
RH		 4647{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4648{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4649
4650{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4651{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4652
4653{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4654{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4655
4656{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4657{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4658
702f0fb4
PB		 4659{ "dmul", XRC(59,34,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4660{ "dmul.", XRC(59,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4661
4662{ "drrnd", ZRC(59,35,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4663{ "drrnd.", ZRC(59,35,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4664
4665{ "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4666{ "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4667
4668{ "dquai", ZRC(59,67,0), Z_MASK, POWER6, { TE, FRT, FRB, RMC } },
4669{ "dquai.", ZRC(59,67,1), Z_MASK, POWER6, { TE, FRT, FRB, RMC } },
4670
4671{ "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4672{ "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4673
4674{ "drintx", ZRC(59,99,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
4675{ "drintx.", ZRC(59,99,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
4676
4677{ "dcmpo", X(59,130), X_MASK, POWER6, { BF, FRA, FRB } },
4678
4679{ "dtstex", X(59,162), X_MASK, POWER6, { BF, FRA, FRB } },
4680{ "dtstdc", Z(59,194), Z_MASK, POWER6, { BF, FRA, DCM } },
4681{ "dtstdg", Z(59,226), Z_MASK, POWER6, { BF, FRA, DGM } },
4682
4683{ "drintn", ZRC(59,227,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
4684{ "drintn.", ZRC(59,227,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
4685
4686{ "dctdp", XRC(59,258,0), X_MASK, POWER6, { FRT, FRB } },
4687{ "dctdp.", XRC(59,258,1), X_MASK, POWER6, { FRT, FRB } },
4688
4689{ "dctfix", XRC(59,290,0), X_MASK, POWER6, { FRT, FRB } },
4690{ "dctfix.", XRC(59,290,1), X_MASK, POWER6, { FRT, FRB } },
4691
4692{ "ddedpd", XRC(59,322,0), X_MASK, POWER6, { SP, FRT, FRB } },
4693{ "ddedpd.", XRC(59,322,1), X_MASK, POWER6, { SP, FRT, FRB } },
4694
4695{ "dxex", XRC(59,354,0), X_MASK, POWER6, { FRT, FRB } },
4696{ "dxex.", XRC(59,354,1), X_MASK, POWER6, { FRT, FRB } },
4697
4698{ "dsub", XRC(59,514,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4699{ "dsub.", XRC(59,514,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4700
4701{ "ddiv", XRC(59,546,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4702{ "ddiv.", XRC(59,546,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4703
4704{ "dcmpu", X(59,642), X_MASK, POWER6, { BF, FRA, FRB } },
4705
4706{ "dtstsf", X(59,674), X_MASK, POWER6, { BF, FRA, FRB } },
4707
4708{ "drsp", XRC(59,770,0), X_MASK, POWER6, { FRT, FRB } },
4709{ "drsp.", XRC(59,770,1), X_MASK, POWER6, { FRT, FRB } },
4710
4711{ "dcffix", XRC(59,802,0), X_MASK, POWER6, { FRT, FRB } },
4712{ "dcffix.", XRC(59,802,1), X_MASK, POWER6, { FRT, FRB } },
4713
4714{ "denbcd", XRC(59,834,0), X_MASK, POWER6, { S, FRT, FRB } },
4715{ "denbcd.", XRC(59,834,1), X_MASK, POWER6, { S, FRT, FRB } },
4716
4717{ "diex", XRC(59,866,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4718{ "diex.", XRC(59,866,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4719
252b5132
RH		 4720{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
4721
4722{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
4723
702f0fb4
PB		 4724{ "stfdp", OP(61), OP_MASK, POWER6, { FRT, D, RA0 } },
4725
fdd12ef3
AM		 4726{ "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4727{ "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4728{ "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
418c1742 4729{ "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } },
fdd12ef3 4730{ "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
418c1742 4731{ "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
fdd12ef3 4732{ "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA0 } },
418c1742 4733{ "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
fdd12ef3 4734{ "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
418c1742 4735{ "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
fdd12ef3 4736{ "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
418c1742
MG		 4737{ "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4738
fdd12ef3 4739{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } },
802a735e
AM		 4740
4741{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
4742
fdd12ef3
AM		 4743{ "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } },
4744
252b5132
RH		 4745{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4746
702f0fb4
PB		 4747{ "daddq", XRC(63,2,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4748{ "daddq.", XRC(63,2,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4749
4750{ "dquaq", ZRC(63,3,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4751{ "dquaq.", ZRC(63,3,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4752
4753{ "fcpsgn", XRC(63,8,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4754{ "fcpsgn.", XRC(63,8,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4755
252b5132
RH		 4756{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
4757{ "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
4758
4759{ "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4760{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
4761{ "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4762{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
4763
4764{ "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4765{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
4766{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4767{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
4768
4769{ "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4770{ "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4771{ "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4772{ "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4773
4774{ "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4775{ "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4776{ "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4777{ "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4778
4779{ "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4780{ "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4781{ "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4782{ "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4783
4784{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4785{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4786
4787{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4788{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4789
702f0fb4
PB		 4790{ "fre", A(63,24,0), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } },
4791{ "fre.", A(63,24,1), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } },
1ed8e1e4 4792
252b5132
RH		 4793{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4794{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4795{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4796{ "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4797
702f0fb4
PB		 4798{ "frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4799{ "frsqrte.",A(63,26,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
252b5132
RH		 4800
4801{ "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4802{ "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4803{ "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4804{ "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4805
4806{ "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4807{ "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4808{ "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4809{ "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4810
4811{ "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4812{ "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4813{ "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4814{ "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4815
4816{ "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4817{ "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4818{ "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4819{ "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4820
4821{ "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4822
702f0fb4
PB		 4823{ "dmulq", XRC(63,34,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4824{ "dmulq.", XRC(63,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4825
4826{ "drrndq", ZRC(63,35,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4827{ "drrndq.", ZRC(63,35,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4828
252b5132
RH		 4829{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
4830{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
4831
4832{ "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
4833{ "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
4834
4835{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
4836
702f0fb4
PB		 4837{ "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4838{ "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4839
4840{ "dquaiq", ZRC(63,67,0), Z_MASK, POWER6, { TE, FRT, FRB, RMC } },
4841{ "dquaiq.", ZRC(63,67,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4842
252b5132
RH		 4843{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
4844{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
4845
4846{ "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
4847{ "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
4848
702f0fb4
PB		 4849{ "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4850{ "dscriq.", ZRC(63,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4851
4852{ "drintxq", ZRC(63,99,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
4853{ "drintxq.",ZRC(63,99,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
4854
4855{ "dcmpoq", X(63,130), X_MASK, POWER6, { BF, FRA, FRB } },
4856
252b5132
RH		 4857{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4858{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4859
4860{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
4861{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
4862
702f0fb4
PB		 4863{ "dtstexq", X(63,162), X_MASK, POWER6, { BF, FRA, FRB } },
4864{ "dtstdcq", Z(63,194), Z_MASK, POWER6, { BF, FRA, DCM } },
4865{ "dtstdgq", Z(63,226), Z_MASK, POWER6, { BF, FRA, DGM } },
4866
4867{ "drintnq", ZRC(63,227,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
4868{ "drintnq.",ZRC(63,227,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
4869
4870{ "dctqpq", XRC(63,258,0), X_MASK, POWER6, { FRT, FRB } },
4871{ "dctqpq.", XRC(63,258,1), X_MASK, POWER6, { FRT, FRB } },
4872
252b5132
RH		 4873{ "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
4874{ "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
4875
702f0fb4
PB		 4876{ "dctfixq", XRC(63,290,0), X_MASK, POWER6, { FRT, FRB } },
4877{ "dctfixq.",XRC(63,290,1), X_MASK, POWER6, { FRT, FRB } },
4878
4879{ "ddedpdq", XRC(63,322,0), X_MASK, POWER6, { SP, FRT, FRB } },
4880{ "ddedpdq.",XRC(63,322,1), X_MASK, POWER6, { SP, FRT, FRB } },
4881
4882{ "dxexq", XRC(63,354,0), X_MASK, POWER6, { FRT, FRB } },
4883{ "dxexq.", XRC(63,354,1), X_MASK, POWER6, { FRT, FRB } },
4884
ce7a772b
AM		 4885{ "frin", XRC(63,392,0), XRA_MASK, POWER5, { FRT, FRB } },
4886{ "frin.", XRC(63,392,1), XRA_MASK, POWER5, { FRT, FRB } },
4887{ "friz", XRC(63,424,0), XRA_MASK, POWER5, { FRT, FRB } },
4888{ "friz.", XRC(63,424,1), XRA_MASK, POWER5, { FRT, FRB } },
4889{ "frip", XRC(63,456,0), XRA_MASK, POWER5, { FRT, FRB } },
4890{ "frip.", XRC(63,456,1), XRA_MASK, POWER5, { FRT, FRB } },
4891{ "frim", XRC(63,488,0), XRA_MASK, POWER5, { FRT, FRB } },
4892{ "frim.", XRC(63,488,1), XRA_MASK, POWER5, { FRT, FRB } },
4893
702f0fb4
PB		 4894{ "dsubq", XRC(63,514,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4895{ "dsubq.", XRC(63,514,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4896
4897{ "ddivq", XRC(63,546,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4898{ "ddivq.", XRC(63,546,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4899
252b5132
RH		 4900{ "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
4901{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
4902
702f0fb4
PB		 4903{ "dcmpuq", X(63,642), X_MASK, POWER6, { BF, FRA, FRB } },
4904
4905{ "dtstsfq", X(63,674), X_MASK, POWER6, { BF, FRA, FRB } },
4906
252b5132
RH		 4907{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },
4908{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } },
4909
702f0fb4
PB		 4910{ "drdpq", XRC(63,770,0), X_MASK, POWER6, { FRT, FRB } },
4911{ "drdpq.", XRC(63,770,1), X_MASK, POWER6, { FRT, FRB } },
4912
4913{ "dcffixq", XRC(63,802,0), X_MASK, POWER6, { FRT, FRB } },
4914{ "dcffixq.",XRC(63,802,1), X_MASK, POWER6, { FRT, FRB } },
4915
252b5132
RH		 4916{ "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
4917{ "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
4918
4919{ "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
4920{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
4921
702f0fb4
PB		 4922{ "denbcdq", XRC(63,834,0), X_MASK, POWER6, { S, FRT, FRB } },
4923{ "denbcdq.",XRC(63,834,1), X_MASK, POWER6, { S, FRT, FRB } },
4924
252b5132
RH		 4925{ "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
4926{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
4927
702f0fb4
PB		 4928{ "diexq", XRC(63,866,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4929{ "diexq.", XRC(63,866,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4930
252b5132
RH		 4931};
4932
4933const int powerpc_num_opcodes =
4934 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
4935\f
4936/* The macro table. This is only used by the assembler. */
4937
4938/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4939 when x=0; 32-x when x is between 1 and 31; are negative if x is
4940 negative; and are 32 or more otherwise. This is what you want
4941 when, for instance, you are emulating a right shift by a
4942 rotate-left-and-mask, because the underlying instructions support
4943 shifts of size 0 but not shifts of size 32. By comparison, when
4944 extracting x bits from some word you want to use just 32-x, because
4945 the underlying instructions don't support extracting 0 bits but do
4946 support extracting the whole word (32 bits in this case). */
4947
4948const struct powerpc_macro powerpc_macros[] = {
4949{ "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
4950{ "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
4951{ "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4952{ "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4953{ "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
4954{ "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4955{ "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4956{ "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4957{ "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
4958{ "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
4959{ "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4960{ "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4961{ "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
4962{ "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
4963{ "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
4964{ "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
4965
4966{ "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
4967{ "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
29ef7e54
AM		 4968{ "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4969{ "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
252b5132
RH		 4970{ "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4971{ "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4972{ "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4973{ "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4974{ "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4975{ "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4976{ "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
4977{ "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
4978{ "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
4979{ "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
4980{ "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4981{ "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4982{ "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4983{ "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4984{ "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
4985{ "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
4986{ "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4987{ "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
252b5132
RH		 4988};
4989
4990const int powerpc_num_macros =
4991 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
GDB Binutils - Deliverables
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