projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| a85d7ed0 | 1 | /* s390-opc.c -- S390 opcode list |
| aa820537 AM |
2 | Copyright 2000, 2001, 2003, 2005, 2007, 2008, 2009 |
| 3 | Free Software Foundation, Inc. | |
| a85d7ed0 NC |
4 | Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). |
| 5 | ||
| 9b201bb5 | 6 | This file is part of the GNU opcodes library. |
| a85d7ed0 | 7 | |
| 9b201bb5 | 8 | This library is free software; you can redistribute it and/or modify |
| a85d7ed0 | 9 | it under the terms of the GNU General Public License as published by |
| 9b201bb5 NC |
10 | the Free Software Foundation; either version 3, or (at your option) |
| 11 | any later version. | |
| a85d7ed0 | 12 | |
| 9b201bb5 NC |
13 | It is distributed in the hope that it will be useful, but WITHOUT |
| 14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
| 16 | License for more details. | |
| a85d7ed0 NC |
17 | |
| 18 | You should have received a copy of the GNU General Public License | |
| 9b201bb5 NC |
19 | along with this file; see the file COPYING. If not, write to the |
| 20 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
| 21 | MA 02110-1301, USA. */ | |
| a85d7ed0 NC |
22 | |
| 23 | #include <stdio.h> | |
| 24 | #include "ansidecl.h" | |
| 25 | #include "opcode/s390.h" | |
| 26 | ||
| 27 | /* This file holds the S390 opcode table. The opcode table | |
| 28 | includes almost all of the extended instruction mnemonics. This | |
| 29 | permits the disassembler to use them, and simplifies the assembler | |
| 30 | logic, at the cost of increasing the table size. The table is | |
| 31 | strictly constant data, so the compiler should be able to put it in | |
| 32 | the .text section. | |
| 33 | ||
| 34 | This file also holds the operand table. All knowledge about | |
| 35 | inserting operands into instructions and vice-versa is kept in this | |
| 36 | file. */ | |
| 37 | ||
| 38 | /* The operands table. | |
| 39 | The fields are bits, shift, insert, extract, flags. */ | |
| 40 | ||
| 41 | const struct s390_operand s390_operands[] = | |
| 42 | { | |
| 43 | #define UNUSED 0 | |
| 44 | { 0, 0, 0 }, /* Indicates the end of the operand list */ | |
| 45 | ||
| 5746fb46 AK |
46 | /* General purpose register operands. */ |
| 47 | ||
| a85d7ed0 NC |
48 | #define R_8 1 /* GPR starting at position 8 */ |
| 49 | { 4, 8, S390_OPERAND_GPR }, | |
| 50 | #define R_12 2 /* GPR starting at position 12 */ | |
| 355d475e | 51 | { 4, 12, S390_OPERAND_GPR }, |
| ce21feb4 MS |
52 | #define RO_12 3 /* optional GPR starting at position 12 */ |
| 53 | { 4, 12, S390_OPERAND_GPR|S390_OPERAND_OPTIONAL }, | |
| 54 | #define R_16 4 /* GPR starting at position 16 */ | |
| 355d475e | 55 | { 4, 16, S390_OPERAND_GPR }, |
| ce21feb4 | 56 | #define R_20 5 /* GPR starting at position 20 */ |
| 355d475e | 57 | { 4, 20, S390_OPERAND_GPR }, |
| ce21feb4 | 58 | #define R_24 6 /* GPR starting at position 24 */ |
| 355d475e | 59 | { 4, 24, S390_OPERAND_GPR }, |
| ce21feb4 | 60 | #define R_28 7 /* GPR starting at position 28 */ |
| 355d475e | 61 | { 4, 28, S390_OPERAND_GPR }, |
| ce21feb4 | 62 | #define RO_28 8 /* optional GPR starting at position 28 */ |
| 5746fb46 | 63 | { 4, 28, (S390_OPERAND_GPR | S390_OPERAND_OPTIONAL) }, |
| ce21feb4 | 64 | #define R_32 9 /* GPR starting at position 32 */ |
| a85d7ed0 NC |
65 | { 4, 32, S390_OPERAND_GPR }, |
| 66 | ||
| 5746fb46 AK |
67 | /* Floating point register operands. */ |
| 68 | ||
| ce21feb4 | 69 | #define F_8 10 /* FPR starting at position 8 */ |
| a85d7ed0 | 70 | { 4, 8, S390_OPERAND_FPR }, |
| ce21feb4 | 71 | #define F_12 11 /* FPR starting at position 12 */ |
| a85d7ed0 | 72 | { 4, 12, S390_OPERAND_FPR }, |
| ce21feb4 | 73 | #define F_16 12 /* FPR starting at position 16 */ |
| a85d7ed0 | 74 | { 4, 16, S390_OPERAND_FPR }, |
| ce21feb4 | 75 | #define F_20 13 /* FPR starting at position 16 */ |
| a85d7ed0 | 76 | { 4, 16, S390_OPERAND_FPR }, |
| ce21feb4 | 77 | #define F_24 14 /* FPR starting at position 24 */ |
| a85d7ed0 | 78 | { 4, 24, S390_OPERAND_FPR }, |
| ce21feb4 | 79 | #define F_28 15 /* FPR starting at position 28 */ |
| a85d7ed0 | 80 | { 4, 28, S390_OPERAND_FPR }, |
| ce21feb4 | 81 | #define F_32 16 /* FPR starting at position 32 */ |
| a85d7ed0 NC |
82 | { 4, 32, S390_OPERAND_FPR }, |
| 83 | ||
| 5746fb46 AK |
84 | /* Access register operands. */ |
| 85 | ||
| ce21feb4 | 86 | #define A_8 17 /* Access reg. starting at position 8 */ |
| a85d7ed0 | 87 | { 4, 8, S390_OPERAND_AR }, |
| ce21feb4 | 88 | #define A_12 18 /* Access reg. starting at position 12 */ |
| a85d7ed0 | 89 | { 4, 12, S390_OPERAND_AR }, |
| ce21feb4 | 90 | #define A_24 19 /* Access reg. starting at position 24 */ |
| a85d7ed0 | 91 | { 4, 24, S390_OPERAND_AR }, |
| ce21feb4 | 92 | #define A_28 20 /* Access reg. starting at position 28 */ |
| a85d7ed0 NC |
93 | { 4, 28, S390_OPERAND_AR }, |
| 94 | ||
| 5746fb46 AK |
95 | /* Control register operands. */ |
| 96 | ||
| ce21feb4 | 97 | #define C_8 21 /* Control reg. starting at position 8 */ |
| a85d7ed0 | 98 | { 4, 8, S390_OPERAND_CR }, |
| ce21feb4 | 99 | #define C_12 22 /* Control reg. starting at position 12 */ |
| a85d7ed0 NC |
100 | { 4, 12, S390_OPERAND_CR }, |
| 101 | ||
| 5746fb46 AK |
102 | /* Base register operands. */ |
| 103 | ||
| ce21feb4 | 104 | #define B_16 23 /* Base register starting at position 16 */ |
| 355d475e | 105 | { 4, 16, S390_OPERAND_BASE|S390_OPERAND_GPR }, |
| ce21feb4 | 106 | #define B_32 24 /* Base register starting at position 32 */ |
| 355d475e | 107 | { 4, 32, S390_OPERAND_BASE|S390_OPERAND_GPR }, |
| a85d7ed0 | 108 | |
| ce21feb4 | 109 | #define X_12 25 /* Index register starting at position 12 */ |
| 355d475e | 110 | { 4, 12, S390_OPERAND_INDEX|S390_OPERAND_GPR }, |
| a85d7ed0 | 111 | |
| 5746fb46 AK |
112 | /* Address displacement operands. */ |
| 113 | ||
| ce21feb4 | 114 | #define D_20 26 /* Displacement starting at position 20 */ |
| 355d475e | 115 | { 12, 20, S390_OPERAND_DISP }, |
| ce21feb4 MS |
116 | #define DO_20 27 /* optional Displ. starting at position 20 */ |
| 117 | { 12, 20, S390_OPERAND_DISP|S390_OPERAND_OPTIONAL }, | |
| 118 | #define D_36 28 /* Displacement starting at position 36 */ | |
| 355d475e | 119 | { 12, 36, S390_OPERAND_DISP }, |
| ce21feb4 | 120 | #define D20_20 29 /* 20 bit displacement starting at 20 */ |
| bac02689 | 121 | { 20, 20, S390_OPERAND_DISP|S390_OPERAND_SIGNED }, |
| a85d7ed0 | 122 | |
| 5746fb46 AK |
123 | /* Length operands. */ |
| 124 | ||
| ce21feb4 | 125 | #define L4_8 30 /* 4 bit length starting at position 8 */ |
| 355d475e | 126 | { 4, 8, S390_OPERAND_LENGTH }, |
| ce21feb4 | 127 | #define L4_12 31 /* 4 bit length starting at position 12 */ |
| a85d7ed0 | 128 | { 4, 12, S390_OPERAND_LENGTH }, |
| ce21feb4 | 129 | #define L8_8 32 /* 8 bit length starting at position 8 */ |
| 355d475e | 130 | { 8, 8, S390_OPERAND_LENGTH }, |
| a85d7ed0 | 131 | |
| 5746fb46 AK |
132 | /* Signed immediate operands. */ |
| 133 | ||
| ce21feb4 | 134 | #define I8_8 33 /* 8 bit signed value starting at 8 */ |
| 5746fb46 | 135 | { 8, 8, S390_OPERAND_SIGNED }, |
| ce21feb4 | 136 | #define I8_32 34 /* 8 bit signed value starting at 32 */ |
| 5746fb46 | 137 | { 8, 32, S390_OPERAND_SIGNED }, |
| ce21feb4 | 138 | #define I16_16 35 /* 16 bit signed value starting at 16 */ |
| 5746fb46 | 139 | { 16, 16, S390_OPERAND_SIGNED }, |
| ce21feb4 | 140 | #define I16_32 36 /* 16 bit signed value starting at 32 */ |
| 5746fb46 | 141 | { 16, 32, S390_OPERAND_SIGNED }, |
| ce21feb4 | 142 | #define I32_16 37 /* 32 bit signed value starting at 16 */ |
| 5746fb46 AK |
143 | { 32, 16, S390_OPERAND_SIGNED }, |
| 144 | ||
| 145 | /* Unsigned immediate operands. */ | |
| 146 | ||
| ce21feb4 | 147 | #define U4_8 38 /* 4 bit unsigned value starting at 8 */ |
| a85d7ed0 | 148 | { 4, 8, 0 }, |
| ce21feb4 | 149 | #define U4_12 39 /* 4 bit unsigned value starting at 12 */ |
| a85d7ed0 | 150 | { 4, 12, 0 }, |
| ce21feb4 | 151 | #define U4_16 40 /* 4 bit unsigned value starting at 16 */ |
| a85d7ed0 | 152 | { 4, 16, 0 }, |
| ce21feb4 | 153 | #define U4_20 41 /* 4 bit unsigned value starting at 20 */ |
| a85d7ed0 | 154 | { 4, 20, 0 }, |
| ce21feb4 | 155 | #define U4_32 42 /* 4 bit unsigned value starting at 32 */ |
| 5746fb46 | 156 | { 4, 32, 0 }, |
| ce21feb4 | 157 | #define U8_8 43 /* 8 bit unsigned value starting at 8 */ |
| 355d475e | 158 | { 8, 8, 0 }, |
| ce21feb4 | 159 | #define U8_16 44 /* 8 bit unsigned value starting at 16 */ |
| a85d7ed0 | 160 | { 8, 16, 0 }, |
| ce21feb4 | 161 | #define U8_24 45 /* 8 bit unsigned value starting at 24 */ |
| 5746fb46 | 162 | { 8, 24, 0 }, |
| ce21feb4 | 163 | #define U8_32 46 /* 8 bit unsigned value starting at 32 */ |
| 5746fb46 | 164 | { 8, 32, 0 }, |
| ce21feb4 | 165 | #define U16_16 47 /* 16 bit unsigned value starting at 16 */ |
| 355d475e | 166 | { 16, 16, 0 }, |
| ce21feb4 | 167 | #define U16_32 48 /* 16 bit unsigned value starting at 32 */ |
| 5746fb46 | 168 | { 16, 32, 0 }, |
| ce21feb4 | 169 | #define U32_16 49 /* 32 bit unsigned value starting at 16 */ |
| 5746fb46 AK |
170 | { 32, 16, 0 }, |
| 171 | ||
| 172 | /* PC-relative address operands. */ | |
| 173 | ||
| ce21feb4 | 174 | #define J16_16 50 /* PC relative jump offset at 16 */ |
| 355d475e | 175 | { 16, 16, S390_OPERAND_PCREL }, |
| ce21feb4 | 176 | #define J32_16 51 /* PC relative long offset at 16 */ |
| ad101263 | 177 | { 32, 16, S390_OPERAND_PCREL }, |
| 5746fb46 AK |
178 | |
| 179 | /* Conditional mask operands. */ | |
| 180 | ||
| d9aee5d7 | 181 | #define M_16OPT 52 /* 4 bit optional mask starting at 16 */ |
| b8e55848 | 182 | { 4, 16, S390_OPERAND_OPTIONAL }, |
| b8e55848 | 183 | |
| a85d7ed0 NC |
184 | }; |
| 185 | ||
| 186 | ||
| 187 | /* Macros used to form opcodes. */ | |
| 188 | ||
| b6849f55 | 189 | /* 8/16/48 bit opcodes. */ |
| a85d7ed0 | 190 | #define OP8(x) { x, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 82b66b23 NC |
191 | #define OP16(x) { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 } |
| 192 | #define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \ | |
| 193 | (x >> 16) & 255, (x >> 8) & 255, x & 255} | |
| a85d7ed0 | 194 | |
| b6849f55 NC |
195 | /* The new format of the INSTR_x_y and MASK_x_y defines is based |
| 196 | on the following rules: | |
| 197 | 1) the middle part of the definition (x in INSTR_x_y) is the official | |
| 198 | names of the instruction format that you can find in the principals | |
| 199 | of operation. | |
| 200 | 2) the last part of the definition (y in INSTR_x_y) gives you an idea | |
| 201 | which operands the binary represenation of the instruction has. | |
| 202 | The meanings of the letters in y are: | |
| 203 | a - access register | |
| 204 | c - control register | |
| 205 | d - displacement, 12 bit | |
| 206 | f - floating pointer register | |
| ad101263 | 207 | i - signed integer, 4, 8, 16 or 32 bit |
| b6849f55 NC |
208 | l - length, 4 or 8 bit |
| 209 | p - pc relative | |
| 210 | r - general purpose register | |
| ad101263 MS |
211 | u - unsigned integer, 4, 8, 16 or 32 bit |
| 212 | m - mode field, 4 bit | |
| b6849f55 NC |
213 | 0 - operand skipped. |
| 214 | The order of the letters reflects the layout of the format in | |
| 215 | storage and not the order of the paramaters of the instructions. | |
| 216 | The use of the letters is not a 100% match with the PoP but it is | |
| 217 | quite close. | |
| 218 | ||
| 219 | For example the instruction "mvo" is defined in the PoP as follows: | |
| 220 | ||
| 221 | MVO D1(L1,B1),D2(L2,B2) [SS] | |
| 222 | ||
| 223 | -------------------------------------- | |
| 224 | | 'F1' | L1 | L2 | B1 | D1 | B2 | D2 | | |
| 225 | -------------------------------------- | |
| 226 | 0 8 12 16 20 32 36 | |
| 227 | ||
| 228 | The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD. */ | |
| 229 | ||
| 230 | #define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */ | |
| 231 | #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */ | |
| 5746fb46 AK |
232 | #define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */ |
| 233 | #define INSTR_RIE_RRP0 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. crjne */ | |
| d9aee5d7 | 234 | #define INSTR_RIE_RRI0 6, { R_8,R_12,I16_16,0,0,0 } /* e.g. ahik */ |
| 5746fb46 AK |
235 | #define INSTR_RIE_RUPI 6, { R_8,I8_32,U4_12,J16_16,0,0 } /* e.g. cij */ |
| 236 | #define INSTR_RIE_R0PI 6, { R_8,I8_32,J16_16,0,0,0 } /* e.g. cijne */ | |
| 237 | #define INSTR_RIE_RUPU 6, { R_8,U8_32,U4_12,J16_16,0,0 } /* e.g. clij */ | |
| 238 | #define INSTR_RIE_R0PU 6, { R_8,U8_32,J16_16,0,0,0 } /* e.g. clijne */ | |
| 239 | #define INSTR_RIE_R0IU 6, { R_8,I16_16,U4_32,0,0,0 } /* e.g. cit */ | |
| 240 | #define INSTR_RIE_R0I0 6, { R_8,I16_16,0,0,0,0 } /* e.g. citne */ | |
| 241 | #define INSTR_RIE_R0UU 6, { R_8,U16_16,U4_32,0,0,0 } /* e.g. clfit */ | |
| 242 | #define INSTR_RIE_R0U0 6, { R_8,U16_16,0,0,0,0 } /* e.g. clfitne */ | |
| 243 | #define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */ | |
| b6849f55 NC |
244 | #define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */ |
| 245 | #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */ | |
| 246 | #define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */ | |
| ad101263 MS |
247 | #define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */ |
| 248 | #define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */ | |
| b6849f55 NC |
249 | #define INSTR_RI_0P 4, { J16_16,0,0,0,0,0 } /* e.g. j */ |
| 250 | #define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */ | |
| 251 | #define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */ | |
| 252 | #define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */ | |
| 253 | #define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */ | |
| 5746fb46 AK |
254 | #define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */ |
| 255 | #define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */ | |
| 256 | #define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */ | |
| 257 | #define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/ | |
| b6849f55 NC |
258 | #define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */ |
| 259 | #define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */ | |
| 260 | #define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */ | |
| 261 | #define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */ | |
| 262 | #define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. sqer */ | |
| 263 | #define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */ | |
| 264 | #define INSTR_RRE_R0 4, { R_24,0,0,0,0,0 } /* e.g. ipm */ | |
| 265 | #define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */ | |
| 266 | #define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. cefbr */ | |
| 267 | #define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */ | |
| b5639b37 | 268 | #define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */ |
| b8e55848 MS |
269 | /* Actually efpc and sfpc do not take an optional operand. |
| 270 | This is just a workaround for existing code e.g. glibc. */ | |
| 271 | #define INSTR_RRE_RR_OPT 4, { R_24,RO_28,0,0,0,0 } /* efpc, sfpc */ | |
| b6849f55 | 272 | #define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */ |
| b5639b37 MS |
273 | #define INSTR_RRF_F0FF2 4, { F_24,F_16,F_28,0,0,0 } /* e.g. cpsdr */ |
| 274 | #define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */ | |
| b6849f55 | 275 | #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ |
| d9aee5d7 | 276 | #define INSTR_RRF_FUFF2 4, { F_24,F_28,F_16,U4_20,0,0 } /* e.g. adtra */ |
| b6849f55 | 277 | #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ |
| 725a9891 | 278 | #define INSTR_RRF_R0RR 4, { R_24,R_16,R_28,0,0,0 } /* e.g. idte */ |
| d9aee5d7 | 279 | #define INSTR_RRF_R0RR2 4, { R_24,R_28,R_16,0,0,0 } /* e.g. ark */ |
| 929e4d1a MS |
280 | #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */ |
| 281 | #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */ | |
| b5639b37 MS |
282 | #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ |
| 283 | #define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ | |
| 7dc6076f | 284 | #define INSTR_RRF_FFRU 4, { F_24,F_16,R_28,U4_20,0,0 } /* e.g. rrdtr */ |
| d9aee5d7 | 285 | #define INSTR_RRF_M0RR 4, { R_24,R_28,M_16OPT,0,0,0 } /* e.g. sske */ |
| 5746fb46 AK |
286 | #define INSTR_RRF_U0RR 4, { R_24,R_28,U4_16,0,0,0 } /* e.g. clrt */ |
| 287 | #define INSTR_RRF_00RR 4, { R_24,R_28,0,0,0,0 } /* e.g. clrtne */ | |
| d9aee5d7 AK |
288 | #define INSTR_RRF_UUFR 4, { F_24,U4_16,R_28,U4_20,0,0 } /* e.g. cdgtra */ |
| 289 | #define INSTR_RRF_UURF 4, { R_24,U4_16,F_28,U4_20,0,0 } /* e.g. cgdtra */ | |
| b6849f55 | 290 | #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */ |
| ce21feb4 | 291 | #define INSTR_RR_0R_OPT 2, { RO_12, 0,0,0,0,0 } /* e.g. nopr */ |
| b6849f55 NC |
292 | #define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */ |
| 293 | #define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */ | |
| 294 | #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */ | |
| 295 | #define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */ | |
| 296 | #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */ | |
| b5639b37 | 297 | #define INSTR_RRR_F0FF 4, { F_24,F_28,F_16,0,0,0 } /* e.g. ddtr */ |
| 5746fb46 AK |
298 | #define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */ |
| 299 | #define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */ | |
| b6849f55 | 300 | #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ |
| ad101263 | 301 | #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ |
| b6849f55 | 302 | #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ |
| 98c3d905 | 303 | #define INSTR_RSL_R0RD 6, { D_20,L4_8,B_16,0,0,0 } /* e.g. tp */ |
| b6849f55 | 304 | #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */ |
| bac02689 MS |
305 | #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ |
| 306 | #define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ | |
| 307 | #define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */ | |
| ad101263 | 308 | #define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. lamy */ |
| d9aee5d7 AK |
309 | #define INSTR_RSY_RDRM 6, { R_8,D20_20,B_16,U4_12,0,0 } /* e.g. loc */ |
| 310 | #define INSTR_RSY_RDR0 6, { R_8,D20_20,B_16,0,0,0 } /* e.g. loc */ | |
| b6849f55 NC |
311 | #define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */ |
| 312 | #define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */ | |
| 313 | #define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */ | |
| 314 | #define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */ | |
| 315 | #define INSTR_RS_RURD 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */ | |
| 316 | #define INSTR_RXE_FRRD 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. axbr */ | |
| 317 | #define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */ | |
| 318 | #define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */ | |
| 319 | #define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */ | |
| bac02689 MS |
320 | #define INSTR_RXY_RRRD 6, { R_8,D20_20,X_12,B_16,0,0 } /* e.g. ly */ |
| 321 | #define INSTR_RXY_FRRD 6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */ | |
| 5746fb46 | 322 | #define INSTR_RXY_URRD 6, { U4_8,D20_20,X_12,B_16,0,0 } /* e.g. pfd */ |
| b6849f55 | 323 | #define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */ |
| ce21feb4 | 324 | #define INSTR_RX_0RRD_OPT 4, { DO_20,X_12,B_16,0,0,0 } /* e.g. nop */ |
| b6849f55 NC |
325 | #define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */ |
| 326 | #define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */ | |
| 327 | #define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */ | |
| 328 | #define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */ | |
| bac02689 | 329 | #define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */ |
| 5746fb46 AK |
330 | #define INSTR_SIY_IRD 6, { D20_20,B_16,I8_8,0,0,0 } /* e.g. asi */ |
| 331 | #define INSTR_SIL_RDI 6, { D_20,B_16,I16_32,0,0,0 } /* e.g. chhsi */ | |
| 332 | #define INSTR_SIL_RDU 6, { D_20,B_16,U16_32,0,0,0 } /* e.g. clfhsi */ | |
| b6849f55 NC |
333 | #define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */ |
| 334 | #define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */ | |
| b2e818b7 | 335 | #define INSTR_SS_L2RDRD 6, { D_20,B_16,D_36,L8_8,B_32,0 } /* e.g. pka */ |
| b6849f55 NC |
336 | #define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */ |
| 337 | #define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */ | |
| 338 | #define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */ | |
| 339 | #define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */ | |
| 340 | #define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */ | |
| 5746fb46 | 341 | #define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */ |
| d9aee5d7 | 342 | #define INSTR_SSF_RRDRD2 6, { R_8,D_20,B_16,D_36,B_32,0 } /* e.g. lpd */ |
| b6849f55 NC |
343 | #define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */ |
| 344 | #define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */ | |
| 345 | ||
| 346 | #define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } | |
| 347 | #define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } | |
| 5746fb46 AK |
348 | #define MASK_RIE_RRPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 349 | #define MASK_RIE_RRP0 { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } | |
| d9aee5d7 | 350 | #define MASK_RIE_RRI0 { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } |
| 5746fb46 AK |
351 | #define MASK_RIE_RUPI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 352 | #define MASK_RIE_R0PI { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } | |
| 353 | #define MASK_RIE_RUPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } | |
| 354 | #define MASK_RIE_R0PU { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } | |
| 355 | #define MASK_RIE_R0IU { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff } | |
| 356 | #define MASK_RIE_R0I0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } | |
| 357 | #define MASK_RIE_R0UU { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff } | |
| 358 | #define MASK_RIE_R0U0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } | |
| 359 | #define MASK_RIE_RRUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } | |
| b6849f55 NC |
360 | #define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 361 | #define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| 362 | #define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| ad101263 MS |
363 | #define MASK_RIL_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
| 364 | #define MASK_RIL_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| b6849f55 NC |
365 | #define MASK_RI_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 366 | #define MASK_RI_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| 367 | #define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| 368 | #define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| 369 | #define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| 5746fb46 AK |
370 | #define MASK_RIS_RURDI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 371 | #define MASK_RIS_R0RDI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } | |
| 372 | #define MASK_RIS_RURDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } | |
| 373 | #define MASK_RIS_R0RDU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } | |
| b6849f55 NC |
374 | #define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } |
| 375 | #define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 } | |
| 376 | #define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } | |
| 377 | #define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } | |
| 378 | #define MASK_RRE_F0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } | |
| 379 | #define MASK_RRE_FF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } | |
| 380 | #define MASK_RRE_R0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } | |
| 381 | #define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } | |
| 382 | #define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } | |
| 383 | #define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } | |
| b5639b37 | 384 | #define MASK_RRE_FR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
| b8e55848 | 385 | #define MASK_RRE_RR_OPT { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
| b6849f55 | 386 | #define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| b5639b37 MS |
387 | #define MASK_RRF_F0FF2 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| 388 | #define MASK_RRF_F0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } | |
| b6849f55 | 389 | #define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| d9aee5d7 | 390 | #define MASK_RRF_FUFF2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| b6849f55 | 391 | #define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| bac02689 | 392 | #define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| d9aee5d7 | 393 | #define MASK_RRF_R0RR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| b6849f55 | 394 | #define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| 929e4d1a | 395 | #define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| b5639b37 MS |
396 | #define MASK_RRF_UUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 397 | #define MASK_RRF_0UFF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } | |
| 7dc6076f | 398 | #define MASK_RRF_FFRU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| ad101263 | 399 | #define MASK_RRF_M0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| 5746fb46 AK |
400 | #define MASK_RRF_U0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| 401 | #define MASK_RRF_00RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } | |
| d9aee5d7 AK |
402 | #define MASK_RRF_UUFR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 403 | #define MASK_RRF_UURF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } | |
| b6849f55 | 404 | #define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } |
| ce21feb4 | 405 | #define MASK_RR_0R_OPT { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } |
| b6849f55 NC |
406 | #define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 407 | #define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| 408 | #define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 409 | #define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 410 | #define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| b5639b37 | 411 | #define MASK_RRR_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| 5746fb46 AK |
412 | #define MASK_RRS_RRRDU { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } |
| 413 | #define MASK_RRS_RRRD0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } | |
| 02cbf767 AK |
414 | #define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } |
| 415 | #define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } | |
| 416 | #define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } | |
| 417 | #define MASK_RSL_R0RD { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } | |
| b6849f55 NC |
418 | #define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 419 | #define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 420 | #define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 421 | #define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| 422 | #define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 423 | #define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| bac02689 MS |
424 | #define MASK_RSY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 425 | #define MASK_RSY_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } | |
| 426 | #define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } | |
| ad101263 | 427 | #define MASK_RSY_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| d9aee5d7 | 428 | #define MASK_RSY_RDRM { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| a3ec2691 | 429 | #define MASK_RSY_RDR0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } |
| 02cbf767 AK |
430 | #define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } |
| 431 | #define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } | |
| 432 | #define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } | |
| 433 | #define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } | |
| bac02689 MS |
434 | #define MASK_RXY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 435 | #define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } | |
| 5746fb46 | 436 | #define MASK_RXY_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| b6849f55 | 437 | #define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } |
| ce21feb4 | 438 | #define MASK_RX_0RRD_OPT { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } |
| b6849f55 NC |
439 | #define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 440 | #define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 441 | #define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 442 | #define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| bac02689 | 443 | #define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 5746fb46 AK |
444 | #define MASK_SIY_IRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 445 | #define MASK_SIL_RDI { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } | |
| 446 | #define MASK_SIL_RDU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } | |
| b6849f55 NC |
447 | #define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 448 | #define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| b2e818b7 | 449 | #define MASK_SS_L2RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| b6849f55 NC |
450 | #define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 451 | #define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 452 | #define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 453 | #define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 454 | #define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 5746fb46 | 455 | #define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
| d9aee5d7 | 456 | #define MASK_SSF_RRDRD2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
| b6849f55 NC |
457 | #define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } |
| 458 | #define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } | |
| 5746fb46 | 459 | |
| b6849f55 NC |
460 | |
| 461 | /* The opcode formats table (blueprints for .insn pseudo mnemonic). */ | |
| a85d7ed0 | 462 | |
| 82b66b23 NC |
463 | const struct s390_opcode s390_opformats[] = |
| 464 | { | |
| af169f23 MS |
465 | { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 }, |
| 466 | { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 }, | |
| 467 | { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 }, | |
| 468 | { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 }, | |
| ad101263 | 469 | { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0 }, |
| 5746fb46 | 470 | { "ris", OP8(0x00LL), MASK_RIS_RURDI, INSTR_RIS_RURDI,3, 6 }, |
| af169f23 MS |
471 | { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 }, |
| 472 | { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 }, | |
| 473 | { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 }, | |
| 5746fb46 | 474 | { "rrs", OP8(0x00LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU,3, 6 }, |
| af169f23 MS |
475 | { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 }, |
| 476 | { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 }, | |
| 477 | { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 }, | |
| bac02689 | 478 | { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3 }, |
| af169f23 MS |
479 | { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 }, |
| 480 | { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 }, | |
| 481 | { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3, 0 }, | |
| bac02689 | 482 | { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3 }, |
| af169f23 MS |
483 | { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 }, |
| 484 | { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 }, | |
| bac02689 | 485 | { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 }, |
| 5746fb46 | 486 | { "sil", OP8(0x00LL), MASK_SIL_RDI, INSTR_SIL_RDI, 3, 6 }, |
| af169f23 MS |
487 | { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 }, |
| 488 | { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 }, | |
| ad101263 | 489 | { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD,3, 0 }, |
| a85d7ed0 NC |
490 | }; |
| 491 | ||
| 492 | const int s390_num_opformats = | |
| 493 | sizeof (s390_opformats) / sizeof (s390_opformats[0]); | |
| 494 | ||
| b6849f55 | 495 | #include "s390-opc.tab" |