projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| a85d7ed0 | 1 | /* s390-opc.c -- S390 opcode list |
| aa820537 AM |
2 | Copyright 2000, 2001, 2003, 2005, 2007, 2008, 2009 |
| 3 | Free Software Foundation, Inc. | |
| a85d7ed0 NC |
4 | Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). |
| 5 | ||
| 9b201bb5 | 6 | This file is part of the GNU opcodes library. |
| a85d7ed0 | 7 | |
| 9b201bb5 | 8 | This library is free software; you can redistribute it and/or modify |
| a85d7ed0 | 9 | it under the terms of the GNU General Public License as published by |
| 9b201bb5 NC |
10 | the Free Software Foundation; either version 3, or (at your option) |
| 11 | any later version. | |
| a85d7ed0 | 12 | |
| 9b201bb5 NC |
13 | It is distributed in the hope that it will be useful, but WITHOUT |
| 14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
| 16 | License for more details. | |
| a85d7ed0 NC |
17 | |
| 18 | You should have received a copy of the GNU General Public License | |
| 9b201bb5 NC |
19 | along with this file; see the file COPYING. If not, write to the |
| 20 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
| 21 | MA 02110-1301, USA. */ | |
| a85d7ed0 NC |
22 | |
| 23 | #include <stdio.h> | |
| 24 | #include "ansidecl.h" | |
| 25 | #include "opcode/s390.h" | |
| 26 | ||
| 27 | /* This file holds the S390 opcode table. The opcode table | |
| 28 | includes almost all of the extended instruction mnemonics. This | |
| 29 | permits the disassembler to use them, and simplifies the assembler | |
| 30 | logic, at the cost of increasing the table size. The table is | |
| 31 | strictly constant data, so the compiler should be able to put it in | |
| 32 | the .text section. | |
| 33 | ||
| 34 | This file also holds the operand table. All knowledge about | |
| 35 | inserting operands into instructions and vice-versa is kept in this | |
| 36 | file. */ | |
| 37 | ||
| 38 | /* The operands table. | |
| 39 | The fields are bits, shift, insert, extract, flags. */ | |
| 40 | ||
| 41 | const struct s390_operand s390_operands[] = | |
| 42 | { | |
| 43 | #define UNUSED 0 | |
| 44 | { 0, 0, 0 }, /* Indicates the end of the operand list */ | |
| 45 | ||
| 5746fb46 AK |
46 | /* General purpose register operands. */ |
| 47 | ||
| a85d7ed0 NC |
48 | #define R_8 1 /* GPR starting at position 8 */ |
| 49 | { 4, 8, S390_OPERAND_GPR }, | |
| 50 | #define R_12 2 /* GPR starting at position 12 */ | |
| 355d475e | 51 | { 4, 12, S390_OPERAND_GPR }, |
| ce21feb4 | 52 | #define RO_12 3 /* optional GPR starting at position 12 */ |
| 5e4b319c | 53 | { 4, 12, S390_OPERAND_GPR | S390_OPERAND_OPTIONAL }, |
| ce21feb4 | 54 | #define R_16 4 /* GPR starting at position 16 */ |
| 355d475e | 55 | { 4, 16, S390_OPERAND_GPR }, |
| ce21feb4 | 56 | #define R_20 5 /* GPR starting at position 20 */ |
| 355d475e | 57 | { 4, 20, S390_OPERAND_GPR }, |
| ce21feb4 | 58 | #define R_24 6 /* GPR starting at position 24 */ |
| 355d475e | 59 | { 4, 24, S390_OPERAND_GPR }, |
| ce21feb4 | 60 | #define R_28 7 /* GPR starting at position 28 */ |
| 355d475e | 61 | { 4, 28, S390_OPERAND_GPR }, |
| ce21feb4 | 62 | #define RO_28 8 /* optional GPR starting at position 28 */ |
| 5746fb46 | 63 | { 4, 28, (S390_OPERAND_GPR | S390_OPERAND_OPTIONAL) }, |
| ce21feb4 | 64 | #define R_32 9 /* GPR starting at position 32 */ |
| a85d7ed0 NC |
65 | { 4, 32, S390_OPERAND_GPR }, |
| 66 | ||
| 5e4b319c AK |
67 | /* General purpose register pair operands. */ |
| 68 | ||
| 69 | #define RE_8 10 /* GPR starting at position 8 */ | |
| c8fa16ed | 70 | { 4, 8, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, |
| 5e4b319c | 71 | #define RE_12 11 /* GPR starting at position 12 */ |
| c8fa16ed | 72 | { 4, 12, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, |
| 5e4b319c | 73 | #define RE_16 12 /* GPR starting at position 16 */ |
| c8fa16ed | 74 | { 4, 16, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, |
| 5e4b319c | 75 | #define RE_20 13 /* GPR starting at position 20 */ |
| c8fa16ed | 76 | { 4, 20, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, |
| 5e4b319c | 77 | #define RE_24 14 /* GPR starting at position 24 */ |
| c8fa16ed | 78 | { 4, 24, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, |
| 5e4b319c | 79 | #define RE_28 15 /* GPR starting at position 28 */ |
| c8fa16ed | 80 | { 4, 28, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, |
| 5e4b319c | 81 | #define RE_32 16 /* GPR starting at position 32 */ |
| c8fa16ed | 82 | { 4, 32, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, |
| 5e4b319c AK |
83 | |
| 84 | ||
| 5746fb46 AK |
85 | /* Floating point register operands. */ |
| 86 | ||
| 5e4b319c | 87 | #define F_8 17 /* FPR starting at position 8 */ |
| a85d7ed0 | 88 | { 4, 8, S390_OPERAND_FPR }, |
| 5e4b319c | 89 | #define F_12 18 /* FPR starting at position 12 */ |
| a85d7ed0 | 90 | { 4, 12, S390_OPERAND_FPR }, |
| 5e4b319c | 91 | #define F_16 19 /* FPR starting at position 16 */ |
| a85d7ed0 | 92 | { 4, 16, S390_OPERAND_FPR }, |
| 5e4b319c | 93 | #define F_20 20 /* FPR starting at position 16 */ |
| a85d7ed0 | 94 | { 4, 16, S390_OPERAND_FPR }, |
| 5e4b319c | 95 | #define F_24 21 /* FPR starting at position 24 */ |
| a85d7ed0 | 96 | { 4, 24, S390_OPERAND_FPR }, |
| 5e4b319c | 97 | #define F_28 22 /* FPR starting at position 28 */ |
| a85d7ed0 | 98 | { 4, 28, S390_OPERAND_FPR }, |
| 5e4b319c | 99 | #define F_32 23 /* FPR starting at position 32 */ |
| a85d7ed0 NC |
100 | { 4, 32, S390_OPERAND_FPR }, |
| 101 | ||
| 5e4b319c AK |
102 | /* Floating point register pair operands. */ |
| 103 | ||
| 104 | #define FE_8 24 /* FPR starting at position 8 */ | |
| c8fa16ed | 105 | { 4, 8, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, |
| 5e4b319c | 106 | #define FE_12 25 /* FPR starting at position 12 */ |
| c8fa16ed | 107 | { 4, 12, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, |
| 5e4b319c | 108 | #define FE_16 26 /* FPR starting at position 16 */ |
| c8fa16ed | 109 | { 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, |
| 5e4b319c | 110 | #define FE_20 27 /* FPR starting at position 16 */ |
| c8fa16ed | 111 | { 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, |
| 5e4b319c | 112 | #define FE_24 28 /* FPR starting at position 24 */ |
| c8fa16ed | 113 | { 4, 24, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, |
| 5e4b319c | 114 | #define FE_28 29 /* FPR starting at position 28 */ |
| c8fa16ed | 115 | { 4, 28, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, |
| 5e4b319c | 116 | #define FE_32 30 /* FPR starting at position 32 */ |
| c8fa16ed | 117 | { 4, 32, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, |
| 5e4b319c AK |
118 | |
| 119 | ||
| 5746fb46 AK |
120 | /* Access register operands. */ |
| 121 | ||
| 5e4b319c | 122 | #define A_8 31 /* Access reg. starting at position 8 */ |
| a85d7ed0 | 123 | { 4, 8, S390_OPERAND_AR }, |
| 5e4b319c | 124 | #define A_12 32 /* Access reg. starting at position 12 */ |
| a85d7ed0 | 125 | { 4, 12, S390_OPERAND_AR }, |
| 5e4b319c | 126 | #define A_24 33 /* Access reg. starting at position 24 */ |
| a85d7ed0 | 127 | { 4, 24, S390_OPERAND_AR }, |
| 5e4b319c | 128 | #define A_28 34 /* Access reg. starting at position 28 */ |
| a85d7ed0 NC |
129 | { 4, 28, S390_OPERAND_AR }, |
| 130 | ||
| 5746fb46 AK |
131 | /* Control register operands. */ |
| 132 | ||
| 5e4b319c | 133 | #define C_8 35 /* Control reg. starting at position 8 */ |
| a85d7ed0 | 134 | { 4, 8, S390_OPERAND_CR }, |
| 5e4b319c | 135 | #define C_12 36 /* Control reg. starting at position 12 */ |
| a85d7ed0 NC |
136 | { 4, 12, S390_OPERAND_CR }, |
| 137 | ||
| 5746fb46 AK |
138 | /* Base register operands. */ |
| 139 | ||
| 5e4b319c AK |
140 | #define B_16 37 /* Base register starting at position 16 */ |
| 141 | { 4, 16, S390_OPERAND_BASE | S390_OPERAND_GPR }, | |
| 142 | #define B_32 38 /* Base register starting at position 32 */ | |
| 143 | { 4, 32, S390_OPERAND_BASE | S390_OPERAND_GPR }, | |
| a85d7ed0 | 144 | |
| 5e4b319c AK |
145 | #define X_12 39 /* Index register starting at position 12 */ |
| 146 | { 4, 12, S390_OPERAND_INDEX | S390_OPERAND_GPR }, | |
| a85d7ed0 | 147 | |
| 5746fb46 AK |
148 | /* Address displacement operands. */ |
| 149 | ||
| 5e4b319c | 150 | #define D_20 40 /* Displacement starting at position 20 */ |
| 355d475e | 151 | { 12, 20, S390_OPERAND_DISP }, |
| 5e4b319c AK |
152 | #define DO_20 41 /* optional Displ. starting at position 20 */ |
| 153 | { 12, 20, S390_OPERAND_DISP | S390_OPERAND_OPTIONAL }, | |
| 154 | #define D_36 42 /* Displacement starting at position 36 */ | |
| 355d475e | 155 | { 12, 36, S390_OPERAND_DISP }, |
| 5e4b319c AK |
156 | #define D20_20 43 /* 20 bit displacement starting at 20 */ |
| 157 | { 20, 20, S390_OPERAND_DISP | S390_OPERAND_SIGNED }, | |
| a85d7ed0 | 158 | |
| 5746fb46 AK |
159 | /* Length operands. */ |
| 160 | ||
| 5e4b319c | 161 | #define L4_8 44 /* 4 bit length starting at position 8 */ |
| 355d475e | 162 | { 4, 8, S390_OPERAND_LENGTH }, |
| 5e4b319c | 163 | #define L4_12 45 /* 4 bit length starting at position 12 */ |
| a85d7ed0 | 164 | { 4, 12, S390_OPERAND_LENGTH }, |
| 5e4b319c | 165 | #define L8_8 46 /* 8 bit length starting at position 8 */ |
| 355d475e | 166 | { 8, 8, S390_OPERAND_LENGTH }, |
| a85d7ed0 | 167 | |
| 5746fb46 AK |
168 | /* Signed immediate operands. */ |
| 169 | ||
| 5e4b319c | 170 | #define I8_8 47 /* 8 bit signed value starting at 8 */ |
| 5746fb46 | 171 | { 8, 8, S390_OPERAND_SIGNED }, |
| 5e4b319c | 172 | #define I8_32 48 /* 8 bit signed value starting at 32 */ |
| 5746fb46 | 173 | { 8, 32, S390_OPERAND_SIGNED }, |
| cfc72779 AK |
174 | #define I12_12 49 /* 12 bit signed value starting at 12 */ |
| 175 | { 12, 12, S390_OPERAND_SIGNED }, | |
| 176 | #define I16_16 50 /* 16 bit signed value starting at 16 */ | |
| 5746fb46 | 177 | { 16, 16, S390_OPERAND_SIGNED }, |
| cfc72779 | 178 | #define I16_32 51 /* 16 bit signed value starting at 32 */ |
| 5746fb46 | 179 | { 16, 32, S390_OPERAND_SIGNED }, |
| cfc72779 AK |
180 | #define I24_24 52 /* 24 bit signed value starting at 24 */ |
| 181 | { 24, 24, S390_OPERAND_SIGNED }, | |
| 182 | #define I32_16 53 /* 32 bit signed value starting at 16 */ | |
| 5746fb46 AK |
183 | { 32, 16, S390_OPERAND_SIGNED }, |
| 184 | ||
| 185 | /* Unsigned immediate operands. */ | |
| 186 | ||
| cfc72779 | 187 | #define U4_8 54 /* 4 bit unsigned value starting at 8 */ |
| a85d7ed0 | 188 | { 4, 8, 0 }, |
| cfc72779 | 189 | #define U4_12 55 /* 4 bit unsigned value starting at 12 */ |
| a85d7ed0 | 190 | { 4, 12, 0 }, |
| cfc72779 | 191 | #define U4_16 56 /* 4 bit unsigned value starting at 16 */ |
| a85d7ed0 | 192 | { 4, 16, 0 }, |
| cfc72779 | 193 | #define U4_20 57 /* 4 bit unsigned value starting at 20 */ |
| a85d7ed0 | 194 | { 4, 20, 0 }, |
| cfc72779 AK |
195 | #define U4_24 58 /* 4 bit unsigned value starting at 24 */ |
| 196 | { 4, 24, 0 }, | |
| 197 | #define U4_28 59 /* 4 bit unsigned value starting at 28 */ | |
| 198 | { 4, 28, 0 }, | |
| 199 | #define U4_32 60 /* 4 bit unsigned value starting at 32 */ | |
| 5746fb46 | 200 | { 4, 32, 0 }, |
| cfc72779 AK |
201 | #define U4_36 61 /* 4 bit unsigned value starting at 36 */ |
| 202 | { 4, 36, 0 }, | |
| 203 | #define U8_8 62 /* 8 bit unsigned value starting at 8 */ | |
| 355d475e | 204 | { 8, 8, 0 }, |
| cfc72779 | 205 | #define U8_16 63 /* 8 bit unsigned value starting at 16 */ |
| a85d7ed0 | 206 | { 8, 16, 0 }, |
| cfc72779 | 207 | #define U8_24 64 /* 8 bit unsigned value starting at 24 */ |
| 5746fb46 | 208 | { 8, 24, 0 }, |
| cfc72779 | 209 | #define U8_32 65 /* 8 bit unsigned value starting at 32 */ |
| 5746fb46 | 210 | { 8, 32, 0 }, |
| cfc72779 | 211 | #define U16_16 66 /* 16 bit unsigned value starting at 16 */ |
| 355d475e | 212 | { 16, 16, 0 }, |
| cfc72779 | 213 | #define U16_32 67 /* 16 bit unsigned value starting at 32 */ |
| 5746fb46 | 214 | { 16, 32, 0 }, |
| cfc72779 | 215 | #define U32_16 68 /* 32 bit unsigned value starting at 16 */ |
| 5746fb46 AK |
216 | { 32, 16, 0 }, |
| 217 | ||
| 218 | /* PC-relative address operands. */ | |
| 219 | ||
| cfc72779 AK |
220 | #define J12_12 69 /* PC relative offset at 12 */ |
| 221 | { 12, 12, S390_OPERAND_PCREL }, | |
| 222 | #define J16_16 70 /* PC relative offset at 16 */ | |
| 355d475e | 223 | { 16, 16, S390_OPERAND_PCREL }, |
| cfc72779 AK |
224 | #define J16_32 71 /* PC relative offset at 16 */ |
| 225 | { 16, 32, S390_OPERAND_PCREL }, | |
| 226 | #define J32_16 72 /* PC relative offset at 16 */ | |
| ad101263 | 227 | { 32, 16, S390_OPERAND_PCREL }, |
| 5746fb46 AK |
228 | |
| 229 | /* Conditional mask operands. */ | |
| 230 | ||
| cfc72779 | 231 | #define M_16OPT 73 /* 4 bit optional mask starting at 16 */ |
| b8e55848 | 232 | { 4, 16, S390_OPERAND_OPTIONAL }, |
| aac129d7 AK |
233 | #define M_20OPT 74 /* 4 bit optional mask starting at 20 */ |
| 234 | { 4, 20, S390_OPERAND_OPTIONAL }, | |
| b8e55848 | 235 | |
| a85d7ed0 NC |
236 | }; |
| 237 | ||
| 238 | ||
| 239 | /* Macros used to form opcodes. */ | |
| 240 | ||
| b6849f55 | 241 | /* 8/16/48 bit opcodes. */ |
| a85d7ed0 | 242 | #define OP8(x) { x, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 82b66b23 NC |
243 | #define OP16(x) { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 } |
| 244 | #define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \ | |
| 245 | (x >> 16) & 255, (x >> 8) & 255, x & 255} | |
| a85d7ed0 | 246 | |
| b6849f55 NC |
247 | /* The new format of the INSTR_x_y and MASK_x_y defines is based |
| 248 | on the following rules: | |
| 249 | 1) the middle part of the definition (x in INSTR_x_y) is the official | |
| 250 | names of the instruction format that you can find in the principals | |
| 251 | of operation. | |
| 252 | 2) the last part of the definition (y in INSTR_x_y) gives you an idea | |
| 253 | which operands the binary represenation of the instruction has. | |
| 254 | The meanings of the letters in y are: | |
| 255 | a - access register | |
| 256 | c - control register | |
| 257 | d - displacement, 12 bit | |
| 258 | f - floating pointer register | |
| cfc72779 | 259 | fe - fpr extended operand, a valid floating pointer register pair |
| ad101263 | 260 | i - signed integer, 4, 8, 16 or 32 bit |
| b6849f55 NC |
261 | l - length, 4 or 8 bit |
| 262 | p - pc relative | |
| 263 | r - general purpose register | |
| 5e4b319c | 264 | ro - optional register operand |
| cfc72779 | 265 | re - gpr extended operand, a valid general purpose register pair |
| ad101263 MS |
266 | u - unsigned integer, 4, 8, 16 or 32 bit |
| 267 | m - mode field, 4 bit | |
| b6849f55 NC |
268 | 0 - operand skipped. |
| 269 | The order of the letters reflects the layout of the format in | |
| 270 | storage and not the order of the paramaters of the instructions. | |
| 271 | The use of the letters is not a 100% match with the PoP but it is | |
| 272 | quite close. | |
| 273 | ||
| 274 | For example the instruction "mvo" is defined in the PoP as follows: | |
| 275 | ||
| 276 | MVO D1(L1,B1),D2(L2,B2) [SS] | |
| 277 | ||
| 278 | -------------------------------------- | |
| 279 | | 'F1' | L1 | L2 | B1 | D1 | B2 | D2 | | |
| 280 | -------------------------------------- | |
| 281 | 0 8 12 16 20 32 36 | |
| 282 | ||
| 283 | The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD. */ | |
| 284 | ||
| 285 | #define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */ | |
| cfc72779 AK |
286 | #define INSTR_IE_UU 4, { U4_24,U4_28,0,0,0,0 } /* e.g. niai */ |
| 287 | #define INSTR_MII_UPI 6, { U4_8,J12_12,I24_24 } /* e.g. bprp */ | |
| b6849f55 | 288 | #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */ |
| 5746fb46 AK |
289 | #define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */ |
| 290 | #define INSTR_RIE_RRP0 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. crjne */ | |
| d9aee5d7 | 291 | #define INSTR_RIE_RRI0 6, { R_8,R_12,I16_16,0,0,0 } /* e.g. ahik */ |
| 5746fb46 AK |
292 | #define INSTR_RIE_RUPI 6, { R_8,I8_32,U4_12,J16_16,0,0 } /* e.g. cij */ |
| 293 | #define INSTR_RIE_R0PI 6, { R_8,I8_32,J16_16,0,0,0 } /* e.g. cijne */ | |
| 294 | #define INSTR_RIE_RUPU 6, { R_8,U8_32,U4_12,J16_16,0,0 } /* e.g. clij */ | |
| 295 | #define INSTR_RIE_R0PU 6, { R_8,U8_32,J16_16,0,0,0 } /* e.g. clijne */ | |
| 296 | #define INSTR_RIE_R0IU 6, { R_8,I16_16,U4_32,0,0,0 } /* e.g. cit */ | |
| 297 | #define INSTR_RIE_R0I0 6, { R_8,I16_16,0,0,0,0 } /* e.g. citne */ | |
| 298 | #define INSTR_RIE_R0UU 6, { R_8,U16_16,U4_32,0,0,0 } /* e.g. clfit */ | |
| 299 | #define INSTR_RIE_R0U0 6, { R_8,U16_16,0,0,0,0 } /* e.g. clfitne */ | |
| 300 | #define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */ | |
| b6849f55 NC |
301 | #define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */ |
| 302 | #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */ | |
| 303 | #define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */ | |
| ad101263 MS |
304 | #define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */ |
| 305 | #define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */ | |
| b6849f55 NC |
306 | #define INSTR_RI_0P 4, { J16_16,0,0,0,0,0 } /* e.g. j */ |
| 307 | #define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */ | |
| 308 | #define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */ | |
| 309 | #define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */ | |
| 310 | #define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */ | |
| 5746fb46 AK |
311 | #define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */ |
| 312 | #define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */ | |
| 313 | #define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */ | |
| 314 | #define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/ | |
| b6849f55 NC |
315 | #define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */ |
| 316 | #define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */ | |
| 317 | #define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */ | |
| 318 | #define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */ | |
| 319 | #define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. sqer */ | |
| 5e4b319c | 320 | #define INSTR_RRE_FE0 4, { FE_24,0,0,0,0,0 } /* e.g. lzxr */ |
| b6849f55 | 321 | #define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */ |
| 5e4b319c AK |
322 | #define INSTR_RRE_FEF 4, { FE_24,F_28,0,0,0,0 } /* e.g. lxdbr */ |
| 323 | #define INSTR_RRE_FFE 4, { F_24,FE_28,0,0,0,0 } /* e.g. lexr */ | |
| 324 | #define INSTR_RRE_FEFE 4, { FE_24,FE_28,0,0,0,0 } /* e.g. dxr */ | |
| b6849f55 NC |
325 | #define INSTR_RRE_R0 4, { R_24,0,0,0,0,0 } /* e.g. ipm */ |
| 326 | #define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */ | |
| 327 | #define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. cefbr */ | |
| 5e4b319c | 328 | #define INSTR_RRE_RFE 4, { R_24,FE_28,0,0,0,0 } /* e.g. csxtr */ |
| b6849f55 | 329 | #define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */ |
| 5e4b319c AK |
330 | #define INSTR_RRE_RER 4, { RE_24,R_28,0,0,0,0 } /* e.g. tre */ |
| 331 | #define INSTR_RRE_RERE 4, { RE_24,RE_28,0,0,0,0 } /* e.g. cuse */ | |
| b5639b37 | 332 | #define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */ |
| 5e4b319c | 333 | #define INSTR_RRE_FER 4, { FE_24,R_28,0,0,0,0 } /* e.g. cxfbr */ |
| b8e55848 MS |
334 | /* Actually efpc and sfpc do not take an optional operand. |
| 335 | This is just a workaround for existing code e.g. glibc. */ | |
| 336 | #define INSTR_RRE_RR_OPT 4, { R_24,RO_28,0,0,0,0 } /* efpc, sfpc */ | |
| b6849f55 | 337 | #define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */ |
| 5e4b319c | 338 | #define INSTR_RRF_FE0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. myr */ |
| b5639b37 MS |
339 | #define INSTR_RRF_F0FF2 4, { F_24,F_16,F_28,0,0,0 } /* e.g. cpsdr */ |
| 340 | #define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */ | |
| 5e4b319c | 341 | #define INSTR_RRF_FE0FER 4, { FE_24,FE_16,R_28,0,0,0 } /* e.g. iextr */ |
| b6849f55 | 342 | #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ |
| 5e4b319c | 343 | #define INSTR_RRF_FEUFEFE 4, { FE_24,FE_16,FE_28,U4_20,0,0 } /* e.g. qaxtr */ |
| d9aee5d7 | 344 | #define INSTR_RRF_FUFF2 4, { F_24,F_28,F_16,U4_20,0,0 } /* e.g. adtra */ |
| 5e4b319c | 345 | #define INSTR_RRF_FEUFEFE2 4, { FE_24,FE_28,FE_16,U4_20,0,0 } /* e.g. axtra */ |
| b6849f55 | 346 | #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ |
| aac129d7 | 347 | #define INSTR_RRF_RURR2 4, { R_24,R_16,R_28,U4_20,0,0 } /* e.g. lptea */ |
| 725a9891 | 348 | #define INSTR_RRF_R0RR 4, { R_24,R_16,R_28,0,0,0 } /* e.g. idte */ |
| d9aee5d7 | 349 | #define INSTR_RRF_R0RR2 4, { R_24,R_28,R_16,0,0,0 } /* e.g. ark */ |
| aac129d7 | 350 | #define INSTR_RRF_RMRR 4, { R_24,R_16,R_28,M_20OPT,0,0 } /* e.g. crdte */ |
| 929e4d1a | 351 | #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */ |
| 5e4b319c | 352 | #define INSTR_RRF_U0FEFE 4, { FE_24,U4_16,FE_28,0,0,0 } /* e.g. fixbr */ |
| 929e4d1a | 353 | #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */ |
| 5e4b319c | 354 | #define INSTR_RRF_U0RFE 4, { R_24,U4_16,FE_28,0,0,0 } /* e.g. cfxbr */ |
| b5639b37 | 355 | #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ |
| 5e4b319c AK |
356 | #define INSTR_RRF_UUFFE 4, { F_24,U4_16,FE_28,U4_20,0,0 } /* e.g. ldxtr */ |
| 357 | #define INSTR_RRF_UUFEFE 4, { FE_24,U4_16,FE_28,U4_20,0,0 } /* e.g. fixtr */ | |
| b5639b37 | 358 | #define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ |
| c8fa16ed | 359 | #define INSTR_RRF_0UFEF 4, { FE_24,F_28,U4_20,0,0,0 } /* e.g. lxdtr */ |
| 7dc6076f | 360 | #define INSTR_RRF_FFRU 4, { F_24,F_16,R_28,U4_20,0,0 } /* e.g. rrdtr */ |
| 5e4b319c | 361 | #define INSTR_RRF_FEFERU 4, { FE_24,FE_16,R_28,U4_20,0,0 } /* e.g. rrxtr */ |
| d9aee5d7 | 362 | #define INSTR_RRF_M0RR 4, { R_24,R_28,M_16OPT,0,0,0 } /* e.g. sske */ |
| 5e4b319c AK |
363 | #define INSTR_RRF_M0RER 4, { RE_24,R_28,M_16OPT,0,0,0 } /* e.g. trte */ |
| 364 | #define INSTR_RRF_M0RERE 4, { RE_24,RE_28,M_16OPT,0,0,0 } /* e.g. troo */ | |
| 5746fb46 AK |
365 | #define INSTR_RRF_U0RR 4, { R_24,R_28,U4_16,0,0,0 } /* e.g. clrt */ |
| 366 | #define INSTR_RRF_00RR 4, { R_24,R_28,0,0,0,0 } /* e.g. clrtne */ | |
| d9aee5d7 | 367 | #define INSTR_RRF_UUFR 4, { F_24,U4_16,R_28,U4_20,0,0 } /* e.g. cdgtra */ |
| 5e4b319c | 368 | #define INSTR_RRF_UUFER 4, { FE_24,U4_16,R_28,U4_20,0,0 } /* e.g. cxfbra */ |
| d9aee5d7 | 369 | #define INSTR_RRF_UURF 4, { R_24,U4_16,F_28,U4_20,0,0 } /* e.g. cgdtra */ |
| 5e4b319c | 370 | #define INSTR_RRF_UURFE 4, { R_24,U4_16,FE_28,U4_20,0,0 } /* e.g. cfxbra */ |
| b6849f55 | 371 | #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */ |
| ce21feb4 | 372 | #define INSTR_RR_0R_OPT 2, { RO_12, 0,0,0,0,0 } /* e.g. nopr */ |
| b6849f55 | 373 | #define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */ |
| 5e4b319c AK |
374 | #define INSTR_RR_FEF 2, { FE_8,F_12,0,0,0,0 } /* e.g. mxdr */ |
| 375 | #define INSTR_RR_FFE 2, { F_8,FE_12,0,0,0,0 } /* e.g. ldxr */ | |
| 376 | #define INSTR_RR_FEFE 2, { FE_8,FE_12,0,0,0,0 } /* e.g. axr */ | |
| b6849f55 NC |
377 | #define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */ |
| 378 | #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */ | |
| 5e4b319c | 379 | #define INSTR_RR_RER 2, { RE_8,R_12,0,0,0,0 } /* e.g. dr */ |
| b6849f55 NC |
380 | #define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */ |
| 381 | #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */ | |
| b5639b37 | 382 | #define INSTR_RRR_F0FF 4, { F_24,F_28,F_16,0,0,0 } /* e.g. ddtr */ |
| 5e4b319c | 383 | #define INSTR_RRR_FE0FEFE 4, { FE_24,FE_28,FE_16,0,0,0 } /* e.g. axtr */ |
| 5746fb46 AK |
384 | #define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */ |
| 385 | #define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */ | |
| b6849f55 | 386 | #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ |
| 5e4b319c | 387 | #define INSTR_RSE_RERERD 6, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. mvclu */ |
| ad101263 | 388 | #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ |
| b6849f55 | 389 | #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ |
| 98c3d905 | 390 | #define INSTR_RSL_R0RD 6, { D_20,L4_8,B_16,0,0,0 } /* e.g. tp */ |
| 6cf1d90c AK |
391 | #define INSTR_RSL_LRDFU 6, { F_32,D_20,L8_8,B_16,U4_36,0 } /* e.g. cdzt */ |
| 392 | #define INSTR_RSL_LRDFEU 6, { FE_32,D_20,L8_8,B_16,U4_36,0 } /* e.g. cxzt */ | |
| b6849f55 | 393 | #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */ |
| bac02689 | 394 | #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ |
| 5e4b319c | 395 | #define INSTR_RSY_RERERD 6, { RE_8,RE_12,D20_20,B_16,0,0 } /* e.g. cdsy */ |
| bac02689 | 396 | #define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ |
| cfc72779 AK |
397 | #define INSTR_RSY_RURD2 6, { R_8,D20_20,B_16,U4_12,0,0 } /* e.g. loc */ |
| 398 | #define INSTR_RSY_R0RD 6, { R_8,D20_20,B_16,0,0,0 } /* e.g. locgt */ | |
| bac02689 | 399 | #define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */ |
| cfc72779 | 400 | #define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. stctg */ |
| b6849f55 NC |
401 | #define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */ |
| 402 | #define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */ | |
| 403 | #define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */ | |
| 5e4b319c | 404 | #define INSTR_RS_RE0RD 4, { RE_8,D_20,B_16,0,0,0 } /* e.g. slda */ |
| b6849f55 | 405 | #define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */ |
| 5e4b319c | 406 | #define INSTR_RS_RERERD 4, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. cds */ |
| b6849f55 NC |
407 | #define INSTR_RS_RURD 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */ |
| 408 | #define INSTR_RXE_FRRD 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. axbr */ | |
| 5e4b319c | 409 | #define INSTR_RXE_FERRD 6, { FE_8,D_20,X_12,B_16,0,0 } /* e.g. lxdb */ |
| b6849f55 | 410 | #define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */ |
| 5e4b319c | 411 | #define INSTR_RXE_RERRD 6, { RE_8,D_20,X_12,B_16,0,0 } /* e.g. dsg */ |
| b6849f55 | 412 | #define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */ |
| 5e4b319c AK |
413 | #define INSTR_RXF_FRRDFE 6, { FE_32,F_8,D_20,X_12,B_16,0 } /* e.g. my */ |
| 414 | #define INSTR_RXF_FERRDFE 6, { FE_32,FE_8,D_20,X_12,B_16,0 } /* e.g. slxt */ | |
| b6849f55 | 415 | #define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */ |
| bac02689 | 416 | #define INSTR_RXY_RRRD 6, { R_8,D20_20,X_12,B_16,0,0 } /* e.g. ly */ |
| 5e4b319c | 417 | #define INSTR_RXY_RERRD 6, { RE_8,D20_20,X_12,B_16,0,0 } /* e.g. dsg */ |
| bac02689 | 418 | #define INSTR_RXY_FRRD 6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */ |
| 5746fb46 | 419 | #define INSTR_RXY_URRD 6, { U4_8,D20_20,X_12,B_16,0,0 } /* e.g. pfd */ |
| b6849f55 | 420 | #define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */ |
| ce21feb4 | 421 | #define INSTR_RX_0RRD_OPT 4, { DO_20,X_12,B_16,0,0,0 } /* e.g. nop */ |
| b6849f55 | 422 | #define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */ |
| 5e4b319c | 423 | #define INSTR_RX_FERRD 4, { FE_8,D_20,X_12,B_16,0,0 } /* e.g. mxd */ |
| b6849f55 | 424 | #define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */ |
| 5e4b319c | 425 | #define INSTR_RX_RERRD 4, { RE_8,D_20,X_12,B_16,0,0 } /* e.g. d */ |
| b6849f55 NC |
426 | #define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */ |
| 427 | #define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */ | |
| bac02689 | 428 | #define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */ |
| 5746fb46 AK |
429 | #define INSTR_SIY_IRD 6, { D20_20,B_16,I8_8,0,0,0 } /* e.g. asi */ |
| 430 | #define INSTR_SIL_RDI 6, { D_20,B_16,I16_32,0,0,0 } /* e.g. chhsi */ | |
| 431 | #define INSTR_SIL_RDU 6, { D_20,B_16,U16_32,0,0,0 } /* e.g. clfhsi */ | |
| cfc72779 | 432 | #define INSTR_SMI_U0RDP 6, { U4_8,J16_32,D_20,B_16,0,0 } /* e.g. bpp */ |
| b6849f55 NC |
433 | #define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */ |
| 434 | #define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */ | |
| b2e818b7 | 435 | #define INSTR_SS_L2RDRD 6, { D_20,B_16,D_36,L8_8,B_32,0 } /* e.g. pka */ |
| b6849f55 NC |
436 | #define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */ |
| 437 | #define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */ | |
| 438 | #define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */ | |
| 439 | #define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */ | |
| 440 | #define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */ | |
| 5746fb46 | 441 | #define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */ |
| 5e4b319c AK |
442 | #define INSTR_SSF_RRDRD2 6, { R_8,D_20,B_16,D_36,B_32,0 } |
| 443 | #define INSTR_SSF_RERDRD2 6, { RE_8,D_20,B_16,D_36,B_32,0 } /* e.g. lpd */ | |
| b6849f55 NC |
444 | #define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */ |
| 445 | #define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */ | |
| 446 | ||
| 447 | #define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } | |
| cfc72779 AK |
448 | #define MASK_IE_UU { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
| 449 | #define MASK_MII_UPI { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| b6849f55 | 450 | #define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 5746fb46 AK |
451 | #define MASK_RIE_RRPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 452 | #define MASK_RIE_RRP0 { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } | |
| d9aee5d7 | 453 | #define MASK_RIE_RRI0 { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } |
| 5746fb46 AK |
454 | #define MASK_RIE_RUPI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 455 | #define MASK_RIE_R0PI { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } | |
| 456 | #define MASK_RIE_RUPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } | |
| 457 | #define MASK_RIE_R0PU { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } | |
| 458 | #define MASK_RIE_R0IU { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff } | |
| 459 | #define MASK_RIE_R0I0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } | |
| 460 | #define MASK_RIE_R0UU { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff } | |
| 461 | #define MASK_RIE_R0U0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } | |
| 462 | #define MASK_RIE_RRUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } | |
| b6849f55 NC |
463 | #define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 464 | #define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| 465 | #define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| ad101263 MS |
466 | #define MASK_RIL_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
| 467 | #define MASK_RIL_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| b6849f55 NC |
468 | #define MASK_RI_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 469 | #define MASK_RI_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| 470 | #define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| 471 | #define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| 472 | #define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| 5746fb46 AK |
473 | #define MASK_RIS_RURDI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 474 | #define MASK_RIS_R0RDI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } | |
| 475 | #define MASK_RIS_RURDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } | |
| 476 | #define MASK_RIS_R0RDU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } | |
| b6849f55 NC |
477 | #define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } |
| 478 | #define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 } | |
| 479 | #define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } | |
| 480 | #define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } | |
| 481 | #define MASK_RRE_F0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } | |
| 5e4b319c | 482 | #define MASK_RRE_FE0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } |
| b6849f55 | 483 | #define MASK_RRE_FF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
| 5e4b319c AK |
484 | #define MASK_RRE_FEF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
| 485 | #define MASK_RRE_FFE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } | |
| 486 | #define MASK_RRE_FEFE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } | |
| b6849f55 NC |
487 | #define MASK_RRE_R0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } |
| 488 | #define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } | |
| 489 | #define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } | |
| 5e4b319c | 490 | #define MASK_RRE_RFE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
| b6849f55 | 491 | #define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
| 5e4b319c AK |
492 | #define MASK_RRE_RER { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
| 493 | #define MASK_RRE_RERE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } | |
| b5639b37 | 494 | #define MASK_RRE_FR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
| 5e4b319c | 495 | #define MASK_RRE_FER { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
| b8e55848 | 496 | #define MASK_RRE_RR_OPT { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
| b6849f55 | 497 | #define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| 5e4b319c | 498 | #define MASK_RRF_FE0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| b5639b37 MS |
499 | #define MASK_RRF_F0FF2 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| 500 | #define MASK_RRF_F0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } | |
| 5e4b319c | 501 | #define MASK_RRF_FE0FER { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| b6849f55 | 502 | #define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 5e4b319c | 503 | #define MASK_RRF_FEUFEFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| d9aee5d7 | 504 | #define MASK_RRF_FUFF2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 5e4b319c | 505 | #define MASK_RRF_FEUFEFE2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| b6849f55 | 506 | #define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| aac129d7 | 507 | #define MASK_RRF_RURR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| bac02689 | 508 | #define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| d9aee5d7 | 509 | #define MASK_RRF_R0RR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| aac129d7 | 510 | #define MASK_RRF_RMRR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| b6849f55 | 511 | #define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| 5e4b319c | 512 | #define MASK_RRF_U0FEFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| 929e4d1a | 513 | #define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| 5e4b319c | 514 | #define MASK_RRF_U0RFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| b5639b37 | 515 | #define MASK_RRF_UUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 5e4b319c AK |
516 | #define MASK_RRF_UUFFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 517 | #define MASK_RRF_UUFEFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } | |
| b5639b37 | 518 | #define MASK_RRF_0UFF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } |
| 5e4b319c | 519 | #define MASK_RRF_0UFEF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } |
| 7dc6076f | 520 | #define MASK_RRF_FFRU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 5e4b319c | 521 | #define MASK_RRF_FEFERU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| ad101263 | 522 | #define MASK_RRF_M0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| 5e4b319c AK |
523 | #define MASK_RRF_M0RER { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| 524 | #define MASK_RRF_M0RERE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } | |
| 5746fb46 AK |
525 | #define MASK_RRF_U0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| 526 | #define MASK_RRF_00RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } | |
| d9aee5d7 | 527 | #define MASK_RRF_UUFR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 5e4b319c | 528 | #define MASK_RRF_UUFER { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| d9aee5d7 | 529 | #define MASK_RRF_UURF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 5e4b319c | 530 | #define MASK_RRF_UURFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| b6849f55 | 531 | #define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } |
| ce21feb4 | 532 | #define MASK_RR_0R_OPT { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } |
| b6849f55 | 533 | #define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 5e4b319c AK |
534 | #define MASK_RR_FEF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 535 | #define MASK_RR_FFE { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 536 | #define MASK_RR_FEFE { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| b6849f55 NC |
537 | #define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
| 538 | #define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 5e4b319c | 539 | #define MASK_RR_RER { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| b6849f55 NC |
540 | #define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 541 | #define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| b5639b37 | 542 | #define MASK_RRR_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| 5e4b319c | 543 | #define MASK_RRR_FE0FEFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| 5746fb46 AK |
544 | #define MASK_RRS_RRRDU { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } |
| 545 | #define MASK_RRS_RRRD0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } | |
| 02cbf767 | 546 | #define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } |
| 5e4b319c | 547 | #define MASK_RSE_RERERD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } |
| 02cbf767 AK |
548 | #define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } |
| 549 | #define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } | |
| 550 | #define MASK_RSL_R0RD { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } | |
| cfc72779 AK |
551 | #define MASK_RSL_LRDFU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 552 | #define MASK_RSL_LRDFEU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } | |
| b6849f55 NC |
553 | #define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 554 | #define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 555 | #define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 556 | #define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| 5e4b319c | 557 | #define MASK_RS_RE0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
| b6849f55 | 558 | #define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 5e4b319c | 559 | #define MASK_RS_RERERD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| b6849f55 | 560 | #define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| bac02689 | 561 | #define MASK_RSY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 5e4b319c | 562 | #define MASK_RSY_RERERD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| bac02689 | 563 | #define MASK_RSY_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| cfc72779 AK |
564 | #define MASK_RSY_RURD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 565 | #define MASK_RSY_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } | |
| bac02689 | 566 | #define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| ad101263 | 567 | #define MASK_RSY_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 02cbf767 | 568 | #define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } |
| 5e4b319c | 569 | #define MASK_RXE_FERRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } |
| 02cbf767 | 570 | #define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } |
| 5e4b319c | 571 | #define MASK_RXE_RERRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } |
| 02cbf767 | 572 | #define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } |
| 5e4b319c AK |
573 | #define MASK_RXF_FRRDFE { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } |
| 574 | #define MASK_RXF_FERRDFE { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } | |
| 02cbf767 | 575 | #define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } |
| bac02689 | 576 | #define MASK_RXY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 5e4b319c | 577 | #define MASK_RXY_RERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| bac02689 | 578 | #define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 5746fb46 | 579 | #define MASK_RXY_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| b6849f55 | 580 | #define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } |
| ce21feb4 | 581 | #define MASK_RX_0RRD_OPT { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } |
| b6849f55 | 582 | #define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 5e4b319c | 583 | #define MASK_RX_FERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| b6849f55 | 584 | #define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 5e4b319c | 585 | #define MASK_RX_RERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| b6849f55 NC |
586 | #define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 587 | #define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| bac02689 | 588 | #define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 5746fb46 AK |
589 | #define MASK_SIY_IRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 590 | #define MASK_SIL_RDI { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } | |
| 591 | #define MASK_SIL_RDU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } | |
| cfc72779 | 592 | #define MASK_SMI_U0RDP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
| b6849f55 NC |
593 | #define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 594 | #define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| b2e818b7 | 595 | #define MASK_SS_L2RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| b6849f55 NC |
596 | #define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 597 | #define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 598 | #define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 599 | #define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 600 | #define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 5746fb46 | 601 | #define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
| d9aee5d7 | 602 | #define MASK_SSF_RRDRD2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
| 5e4b319c | 603 | #define MASK_SSF_RERDRD2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
| b6849f55 NC |
604 | #define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } |
| 605 | #define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } | |
| 5746fb46 | 606 | |
| b6849f55 NC |
607 | |
| 608 | /* The opcode formats table (blueprints for .insn pseudo mnemonic). */ | |
| a85d7ed0 | 609 | |
| 82b66b23 NC |
610 | const struct s390_opcode s390_opformats[] = |
| 611 | { | |
| af169f23 MS |
612 | { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 }, |
| 613 | { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 }, | |
| 614 | { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 }, | |
| 615 | { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 }, | |
| ad101263 | 616 | { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0 }, |
| 5746fb46 | 617 | { "ris", OP8(0x00LL), MASK_RIS_RURDI, INSTR_RIS_RURDI,3, 6 }, |
| af169f23 MS |
618 | { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 }, |
| 619 | { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 }, | |
| 620 | { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 }, | |
| 5746fb46 | 621 | { "rrs", OP8(0x00LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU,3, 6 }, |
| af169f23 MS |
622 | { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 }, |
| 623 | { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 }, | |
| 624 | { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 }, | |
| bac02689 | 625 | { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3 }, |
| af169f23 MS |
626 | { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 }, |
| 627 | { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 }, | |
| 628 | { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3, 0 }, | |
| bac02689 | 629 | { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3 }, |
| af169f23 MS |
630 | { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 }, |
| 631 | { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 }, | |
| bac02689 | 632 | { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 }, |
| 5746fb46 | 633 | { "sil", OP8(0x00LL), MASK_SIL_RDI, INSTR_SIL_RDI, 3, 6 }, |
| af169f23 MS |
634 | { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 }, |
| 635 | { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 }, | |
| ad101263 | 636 | { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD,3, 0 }, |
| a85d7ed0 NC |
637 | }; |
| 638 | ||
| 639 | const int s390_num_opformats = | |
| 640 | sizeof (s390_opformats) / sizeof (s390_opformats[0]); | |
| 641 | ||
| b6849f55 | 642 | #include "s390-opc.tab" |