projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| a85d7ed0 | 1 | /* s390-opc.c -- S390 opcode list |
| aef6203b | 2 | Copyright 2000, 2001, 2003 Free Software Foundation, Inc. |
| a85d7ed0 NC |
3 | Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). |
| 4 | ||
| 5 | This file is part of GDB, GAS, and the GNU binutils. | |
| 6 | ||
| 7 | This program is free software; you can redistribute it and/or modify | |
| 8 | it under the terms of the GNU General Public License as published by | |
| 9 | the Free Software Foundation; either version 2 of the License, or | |
| 10 | (at your option) any later version. | |
| 11 | ||
| 12 | This program is distributed in the hope that it will be useful, | |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | GNU General Public License for more details. | |
| 16 | ||
| 17 | You should have received a copy of the GNU General Public License | |
| 18 | along with this program; if not, write to the Free Software | |
| f4321104 NC |
19 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA |
| 20 | 02110-1301, USA. */ | |
| a85d7ed0 NC |
21 | |
| 22 | #include <stdio.h> | |
| 23 | #include "ansidecl.h" | |
| 24 | #include "opcode/s390.h" | |
| 25 | ||
| 26 | /* This file holds the S390 opcode table. The opcode table | |
| 27 | includes almost all of the extended instruction mnemonics. This | |
| 28 | permits the disassembler to use them, and simplifies the assembler | |
| 29 | logic, at the cost of increasing the table size. The table is | |
| 30 | strictly constant data, so the compiler should be able to put it in | |
| 31 | the .text section. | |
| 32 | ||
| 33 | This file also holds the operand table. All knowledge about | |
| 34 | inserting operands into instructions and vice-versa is kept in this | |
| 35 | file. */ | |
| 36 | ||
| 37 | /* The operands table. | |
| 38 | The fields are bits, shift, insert, extract, flags. */ | |
| 39 | ||
| 40 | const struct s390_operand s390_operands[] = | |
| 41 | { | |
| 42 | #define UNUSED 0 | |
| 43 | { 0, 0, 0 }, /* Indicates the end of the operand list */ | |
| 44 | ||
| 45 | #define R_8 1 /* GPR starting at position 8 */ | |
| 46 | { 4, 8, S390_OPERAND_GPR }, | |
| 47 | #define R_12 2 /* GPR starting at position 12 */ | |
| 355d475e | 48 | { 4, 12, S390_OPERAND_GPR }, |
| a85d7ed0 | 49 | #define R_16 3 /* GPR starting at position 16 */ |
| 355d475e | 50 | { 4, 16, S390_OPERAND_GPR }, |
| a85d7ed0 | 51 | #define R_20 4 /* GPR starting at position 20 */ |
| 355d475e | 52 | { 4, 20, S390_OPERAND_GPR }, |
| a85d7ed0 | 53 | #define R_24 5 /* GPR starting at position 24 */ |
| 355d475e | 54 | { 4, 24, S390_OPERAND_GPR }, |
| a85d7ed0 | 55 | #define R_28 6 /* GPR starting at position 28 */ |
| 355d475e | 56 | { 4, 28, S390_OPERAND_GPR }, |
| a85d7ed0 NC |
57 | #define R_32 7 /* GPR starting at position 32 */ |
| 58 | { 4, 32, S390_OPERAND_GPR }, | |
| 59 | ||
| 60 | #define F_8 8 /* FPR starting at position 8 */ | |
| 61 | { 4, 8, S390_OPERAND_FPR }, | |
| 62 | #define F_12 9 /* FPR starting at position 12 */ | |
| 63 | { 4, 12, S390_OPERAND_FPR }, | |
| 64 | #define F_16 10 /* FPR starting at position 16 */ | |
| 65 | { 4, 16, S390_OPERAND_FPR }, | |
| 66 | #define F_20 11 /* FPR starting at position 16 */ | |
| 67 | { 4, 16, S390_OPERAND_FPR }, | |
| 68 | #define F_24 12 /* FPR starting at position 24 */ | |
| 69 | { 4, 24, S390_OPERAND_FPR }, | |
| 70 | #define F_28 13 /* FPR starting at position 28 */ | |
| 71 | { 4, 28, S390_OPERAND_FPR }, | |
| 72 | #define F_32 14 /* FPR starting at position 32 */ | |
| 73 | { 4, 32, S390_OPERAND_FPR }, | |
| 74 | ||
| 75 | #define A_8 15 /* Access reg. starting at position 8 */ | |
| 76 | { 4, 8, S390_OPERAND_AR }, | |
| 77 | #define A_12 16 /* Access reg. starting at position 12 */ | |
| 78 | { 4, 12, S390_OPERAND_AR }, | |
| 79 | #define A_24 17 /* Access reg. starting at position 24 */ | |
| 80 | { 4, 24, S390_OPERAND_AR }, | |
| 81 | #define A_28 18 /* Access reg. starting at position 28 */ | |
| 82 | { 4, 28, S390_OPERAND_AR }, | |
| 83 | ||
| 84 | #define C_8 19 /* Control reg. starting at position 8 */ | |
| 85 | { 4, 8, S390_OPERAND_CR }, | |
| 86 | #define C_12 20 /* Control reg. starting at position 12 */ | |
| 87 | { 4, 12, S390_OPERAND_CR }, | |
| 88 | ||
| 89 | #define B_16 21 /* Base register starting at position 16 */ | |
| 355d475e | 90 | { 4, 16, S390_OPERAND_BASE|S390_OPERAND_GPR }, |
| a85d7ed0 | 91 | #define B_32 22 /* Base register starting at position 32 */ |
| 355d475e | 92 | { 4, 32, S390_OPERAND_BASE|S390_OPERAND_GPR }, |
| a85d7ed0 NC |
93 | |
| 94 | #define X_12 23 /* Index register starting at position 12 */ | |
| 355d475e | 95 | { 4, 12, S390_OPERAND_INDEX|S390_OPERAND_GPR }, |
| a85d7ed0 NC |
96 | |
| 97 | #define D_20 24 /* Displacement starting at position 20 */ | |
| 355d475e | 98 | { 12, 20, S390_OPERAND_DISP }, |
| a85d7ed0 | 99 | #define D_36 25 /* Displacement starting at position 36 */ |
| 355d475e | 100 | { 12, 36, S390_OPERAND_DISP }, |
| bac02689 MS |
101 | #define D20_20 26 /* 20 bit displacement starting at 20 */ |
| 102 | { 20, 20, S390_OPERAND_DISP|S390_OPERAND_SIGNED }, | |
| a85d7ed0 | 103 | |
| bac02689 | 104 | #define L4_8 27 /* 4 bit length starting at position 8 */ |
| 355d475e | 105 | { 4, 8, S390_OPERAND_LENGTH }, |
| bac02689 | 106 | #define L4_12 28 /* 4 bit length starting at position 12 */ |
| a85d7ed0 | 107 | { 4, 12, S390_OPERAND_LENGTH }, |
| bac02689 | 108 | #define L8_8 29 /* 8 bit length starting at position 8 */ |
| 355d475e | 109 | { 8, 8, S390_OPERAND_LENGTH }, |
| a85d7ed0 | 110 | |
| bac02689 | 111 | #define U4_8 30 /* 4 bit unsigned value starting at 8 */ |
| a85d7ed0 | 112 | { 4, 8, 0 }, |
| bac02689 | 113 | #define U4_12 31 /* 4 bit unsigned value starting at 12 */ |
| a85d7ed0 | 114 | { 4, 12, 0 }, |
| bac02689 | 115 | #define U4_16 32 /* 4 bit unsigned value starting at 16 */ |
| a85d7ed0 | 116 | { 4, 16, 0 }, |
| bac02689 | 117 | #define U4_20 33 /* 4 bit unsigned value starting at 20 */ |
| a85d7ed0 | 118 | { 4, 20, 0 }, |
| bac02689 | 119 | #define U8_8 34 /* 8 bit unsigned value starting at 8 */ |
| 355d475e | 120 | { 8, 8, 0 }, |
| bac02689 | 121 | #define U8_16 35 /* 8 bit unsigned value starting at 16 */ |
| a85d7ed0 | 122 | { 8, 16, 0 }, |
| bac02689 | 123 | #define I16_16 36 /* 16 bit signed value starting at 16 */ |
| a85d7ed0 | 124 | { 16, 16, S390_OPERAND_SIGNED }, |
| bac02689 | 125 | #define U16_16 37 /* 16 bit unsigned value starting at 16 */ |
| 355d475e | 126 | { 16, 16, 0 }, |
| bac02689 | 127 | #define J16_16 38 /* PC relative jump offset at 16 */ |
| 355d475e | 128 | { 16, 16, S390_OPERAND_PCREL }, |
| bac02689 | 129 | #define J32_16 39 /* PC relative long offset at 16 */ |
| ad101263 MS |
130 | { 32, 16, S390_OPERAND_PCREL }, |
| 131 | #define I32_16 40 /* 32 bit signed value starting at 16 */ | |
| 132 | { 32, 16, S390_OPERAND_SIGNED }, | |
| 133 | #define U32_16 41 /* 32 bit unsigned value starting at 16 */ | |
| 134 | { 32, 16, 0 }, | |
| 135 | #define M_16 42 /* 4 bit optional mask starting at 16 */ | |
| b8e55848 MS |
136 | { 4, 16, S390_OPERAND_OPTIONAL }, |
| 137 | #define RO_28 43 /* optional GPR starting at position 28 */ | |
| 138 | { 4, 28, (S390_OPERAND_GPR | S390_OPERAND_OPTIONAL) } | |
| 139 | ||
| a85d7ed0 NC |
140 | }; |
| 141 | ||
| 142 | ||
| 143 | /* Macros used to form opcodes. */ | |
| 144 | ||
| b6849f55 | 145 | /* 8/16/48 bit opcodes. */ |
| a85d7ed0 | 146 | #define OP8(x) { x, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 82b66b23 NC |
147 | #define OP16(x) { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 } |
| 148 | #define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \ | |
| 149 | (x >> 16) & 255, (x >> 8) & 255, x & 255} | |
| a85d7ed0 | 150 | |
| b6849f55 NC |
151 | /* The new format of the INSTR_x_y and MASK_x_y defines is based |
| 152 | on the following rules: | |
| 153 | 1) the middle part of the definition (x in INSTR_x_y) is the official | |
| 154 | names of the instruction format that you can find in the principals | |
| 155 | of operation. | |
| 156 | 2) the last part of the definition (y in INSTR_x_y) gives you an idea | |
| 157 | which operands the binary represenation of the instruction has. | |
| 158 | The meanings of the letters in y are: | |
| 159 | a - access register | |
| 160 | c - control register | |
| 161 | d - displacement, 12 bit | |
| 162 | f - floating pointer register | |
| ad101263 | 163 | i - signed integer, 4, 8, 16 or 32 bit |
| b6849f55 NC |
164 | l - length, 4 or 8 bit |
| 165 | p - pc relative | |
| 166 | r - general purpose register | |
| ad101263 MS |
167 | u - unsigned integer, 4, 8, 16 or 32 bit |
| 168 | m - mode field, 4 bit | |
| b6849f55 NC |
169 | 0 - operand skipped. |
| 170 | The order of the letters reflects the layout of the format in | |
| 171 | storage and not the order of the paramaters of the instructions. | |
| 172 | The use of the letters is not a 100% match with the PoP but it is | |
| 173 | quite close. | |
| 174 | ||
| 175 | For example the instruction "mvo" is defined in the PoP as follows: | |
| 176 | ||
| 177 | MVO D1(L1,B1),D2(L2,B2) [SS] | |
| 178 | ||
| 179 | -------------------------------------- | |
| 180 | | 'F1' | L1 | L2 | B1 | D1 | B2 | D2 | | |
| 181 | -------------------------------------- | |
| 182 | 0 8 12 16 20 32 36 | |
| 183 | ||
| 184 | The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD. */ | |
| 185 | ||
| 186 | #define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */ | |
| 187 | #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */ | |
| 188 | #define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */ | |
| 189 | #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */ | |
| 190 | #define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */ | |
| ad101263 MS |
191 | #define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */ |
| 192 | #define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */ | |
| b6849f55 NC |
193 | #define INSTR_RI_0P 4, { J16_16,0,0,0,0,0 } /* e.g. j */ |
| 194 | #define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */ | |
| 195 | #define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */ | |
| 196 | #define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */ | |
| 197 | #define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */ | |
| 198 | #define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */ | |
| 199 | #define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */ | |
| 200 | #define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */ | |
| 201 | #define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */ | |
| 202 | #define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. sqer */ | |
| 203 | #define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */ | |
| 204 | #define INSTR_RRE_R0 4, { R_24,0,0,0,0,0 } /* e.g. ipm */ | |
| 205 | #define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */ | |
| 206 | #define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. cefbr */ | |
| 207 | #define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */ | |
| b5639b37 | 208 | #define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */ |
| b8e55848 MS |
209 | /* Actually efpc and sfpc do not take an optional operand. |
| 210 | This is just a workaround for existing code e.g. glibc. */ | |
| 211 | #define INSTR_RRE_RR_OPT 4, { R_24,RO_28,0,0,0,0 } /* efpc, sfpc */ | |
| b6849f55 | 212 | #define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */ |
| b5639b37 MS |
213 | #define INSTR_RRF_F0FF2 4, { F_24,F_16,F_28,0,0,0 } /* e.g. cpsdr */ |
| 214 | #define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */ | |
| b6849f55 NC |
215 | #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ |
| 216 | #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ | |
| bac02689 | 217 | #define INSTR_RRF_R0RR 4, { R_24,R_28,R_16,0,0,0 } /* e.g. idte */ |
| 929e4d1a MS |
218 | #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */ |
| 219 | #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */ | |
| b5639b37 MS |
220 | #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ |
| 221 | #define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ | |
| 222 | #define INSTR_RRF_FFFU 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. qadtr */ | |
| ad101263 | 223 | #define INSTR_RRF_M0RR 4, { R_24,R_28,M_16,0,0,0 } /* e.g. sske */ |
| b6849f55 NC |
224 | #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */ |
| 225 | #define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */ | |
| 226 | #define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */ | |
| 227 | #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */ | |
| 228 | #define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */ | |
| 229 | #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */ | |
| b5639b37 | 230 | #define INSTR_RRR_F0FF 4, { F_24,F_28,F_16,0,0,0 } /* e.g. ddtr */ |
| b6849f55 | 231 | #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ |
| ad101263 | 232 | #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ |
| b6849f55 | 233 | #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ |
| bac02689 | 234 | #define INSTR_RSL_R0RD 6, { R_8,D_20,B_16,0,0,0 } /* e.g. tp */ |
| b6849f55 | 235 | #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */ |
| bac02689 MS |
236 | #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ |
| 237 | #define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ | |
| 238 | #define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */ | |
| ad101263 | 239 | #define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. lamy */ |
| b6849f55 NC |
240 | #define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */ |
| 241 | #define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */ | |
| 242 | #define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */ | |
| 243 | #define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */ | |
| 244 | #define INSTR_RS_RURD 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */ | |
| 245 | #define INSTR_RXE_FRRD 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. axbr */ | |
| 246 | #define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */ | |
| 247 | #define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */ | |
| 248 | #define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */ | |
| bac02689 MS |
249 | #define INSTR_RXY_RRRD 6, { R_8,D20_20,X_12,B_16,0,0 } /* e.g. ly */ |
| 250 | #define INSTR_RXY_FRRD 6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */ | |
| b6849f55 NC |
251 | #define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */ |
| 252 | #define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */ | |
| 253 | #define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */ | |
| 254 | #define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */ | |
| 255 | #define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */ | |
| bac02689 | 256 | #define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */ |
| b6849f55 NC |
257 | #define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */ |
| 258 | #define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */ | |
| b2e818b7 | 259 | #define INSTR_SS_L2RDRD 6, { D_20,B_16,D_36,L8_8,B_32,0 } /* e.g. pka */ |
| b6849f55 NC |
260 | #define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */ |
| 261 | #define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */ | |
| 262 | #define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */ | |
| 263 | #define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */ | |
| 264 | #define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */ | |
| 265 | #define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */ | |
| 266 | #define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */ | |
| ad101263 | 267 | #define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */ |
| b6849f55 NC |
268 | |
| 269 | #define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } | |
| 270 | #define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } | |
| 271 | #define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } | |
| 272 | #define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| 273 | #define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| ad101263 MS |
274 | #define MASK_RIL_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
| 275 | #define MASK_RIL_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| b6849f55 NC |
276 | #define MASK_RI_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 277 | #define MASK_RI_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| 278 | #define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| 279 | #define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| 280 | #define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| 281 | #define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } | |
| 282 | #define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 } | |
| 283 | #define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } | |
| 284 | #define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } | |
| 285 | #define MASK_RRE_F0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } | |
| 286 | #define MASK_RRE_FF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } | |
| 287 | #define MASK_RRE_R0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } | |
| 288 | #define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } | |
| 289 | #define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } | |
| 290 | #define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } | |
| b5639b37 | 291 | #define MASK_RRE_FR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
| b8e55848 | 292 | #define MASK_RRE_RR_OPT { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
| b6849f55 | 293 | #define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| b5639b37 MS |
294 | #define MASK_RRF_F0FF2 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| 295 | #define MASK_RRF_F0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } | |
| b6849f55 NC |
296 | #define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 297 | #define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } | |
| bac02689 | 298 | #define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| b6849f55 | 299 | #define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| 929e4d1a | 300 | #define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| b5639b37 MS |
301 | #define MASK_RRF_UUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 302 | #define MASK_RRF_0UFF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } | |
| 303 | #define MASK_RRF_FFFU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } | |
| ad101263 | 304 | #define MASK_RRF_M0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| b6849f55 NC |
305 | #define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } |
| 306 | #define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 307 | #define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| 308 | #define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 309 | #define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 310 | #define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| b5639b37 | 311 | #define MASK_RRR_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| b6849f55 | 312 | #define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| ad101263 | 313 | #define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| b6849f55 | 314 | #define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| bac02689 | 315 | #define MASK_RSL_R0RD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| b6849f55 NC |
316 | #define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 317 | #define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 318 | #define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 319 | #define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } | |
| 320 | #define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 321 | #define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| bac02689 MS |
322 | #define MASK_RSY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 323 | #define MASK_RSY_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } | |
| 324 | #define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } | |
| ad101263 | 325 | #define MASK_RSY_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| b6849f55 NC |
326 | #define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 327 | #define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } | |
| 328 | #define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } | |
| 329 | #define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } | |
| bac02689 MS |
330 | #define MASK_RXY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 331 | #define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } | |
| b6849f55 NC |
332 | #define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } |
| 333 | #define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 334 | #define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 335 | #define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 336 | #define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| bac02689 | 337 | #define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| b6849f55 NC |
338 | #define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 339 | #define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| b2e818b7 | 340 | #define MASK_SS_L2RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| b6849f55 NC |
341 | #define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 342 | #define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 343 | #define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 344 | #define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 345 | #define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } | |
| 346 | #define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } | |
| 347 | #define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } | |
| dacc8b01 | 348 | #define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
| b6849f55 NC |
349 | |
| 350 | /* The opcode formats table (blueprints for .insn pseudo mnemonic). */ | |
| a85d7ed0 | 351 | |
| 82b66b23 NC |
352 | const struct s390_opcode s390_opformats[] = |
| 353 | { | |
| af169f23 MS |
354 | { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 }, |
| 355 | { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 }, | |
| 356 | { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 }, | |
| 357 | { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 }, | |
| ad101263 | 358 | { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0 }, |
| af169f23 MS |
359 | { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 }, |
| 360 | { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 }, | |
| 361 | { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 }, | |
| 362 | { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 }, | |
| 363 | { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 }, | |
| 364 | { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 }, | |
| bac02689 | 365 | { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3 }, |
| af169f23 MS |
366 | { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 }, |
| 367 | { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 }, | |
| 368 | { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3, 0 }, | |
| bac02689 | 369 | { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3 }, |
| af169f23 MS |
370 | { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 }, |
| 371 | { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 }, | |
| bac02689 | 372 | { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 }, |
| af169f23 MS |
373 | { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 }, |
| 374 | { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 }, | |
| ad101263 | 375 | { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD,3, 0 }, |
| a85d7ed0 NC |
376 | }; |
| 377 | ||
| 378 | const int s390_num_opformats = | |
| 379 | sizeof (s390_opformats) / sizeof (s390_opformats[0]); | |
| 380 | ||
| b6849f55 | 381 | #include "s390-opc.tab" |