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252b5132 1/* Print SPARC instructions.
6f2750fe 2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
252b5132 3
9b201bb5
NC		 4 This file is part of the GNU opcodes library.
5
6 This library is free software; you can redistribute it and/or modify
0f6ab988 7 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
252b5132 10
9b201bb5
NC		 11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
252b5132 15
0f6ab988
NC		 16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
47b0e7ad
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
252b5132 21#include "sysdep.h"
df7b86aa 22#include <stdio.h>
252b5132
RH		 23#include "opcode/sparc.h"
24#include "dis-asm.h"
25#include "libiberty.h"
26#include "opintl.h"
27
28/* Bitmask of v9 architectures. */
29#define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
19f7b010
JJ		 30 | (1 << SPARC_OPCODE_ARCH_V9A) \
31 | (1 << SPARC_OPCODE_ARCH_V9B))
252b5132
RH		 32/* 1 if INSN is for v9 only. */
33#define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
34/* 1 if INSN is for v9. */
35#define V9_P(insn) (((insn)->architecture & MASK_V9) != 0)
36
37/* The sorted opcode table. */
47b0e7ad 38static const sparc_opcode **sorted_opcodes;
252b5132
RH		 39
40/* For faster lookup, after insns are sorted they are hashed. */
41/* ??? I think there is room for even more improvement. */
42
43#define HASH_SIZE 256
44/* It is important that we only look at insn code bits as that is how the
45 opcode table is hashed. OPCODE_BITS is a table of valid bits for each
46 of the main types (0,1,2,3). */
47static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
48#define HASH_INSN(INSN) \
49 ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
47b0e7ad 50typedef struct sparc_opcode_hash
0f6ab988 51{
47b0e7ad
NC		 52 struct sparc_opcode_hash *next;
53 const sparc_opcode *opcode;
54} sparc_opcode_hash;
252b5132 55
47b0e7ad 56static sparc_opcode_hash *opcode_hash_table[HASH_SIZE];
252b5132
RH		 57
58/* Sign-extend a value which is N bits long. */
59#define SEX(value, bits) \
60 ((((int)(value)) << ((8 * sizeof (int)) - bits)) \
61 >> ((8 * sizeof (int)) - bits) )
62
63static char *reg_names[] =
47b0e7ad
NC		 64{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
65 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
66 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
67 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
68 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
69 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
252b5132
RH		 70 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
71 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
47b0e7ad
NC		 72 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
73 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
252b5132
RH		 74 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
75 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
76/* psr, wim, tbr, fpsr, cpsr are v8 only. */
77 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
78};
79
80#define freg_names (&reg_names[4 * 8])
81
82/* These are ordered according to there register number in
83 rdpr and wrpr insns. */
84static char *v9_priv_reg_names[] =
85{
86 "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
87 "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
ff3f9d5b 88 "wstate", "fq", "gl"
38074311 89 /* "ver" and "pmcdper" - special cased */
252b5132
RH		 90};
91
ff3f9d5b
DM		 92/* These are ordered according to there register number in
93 rdhpr and wrhpr insns. */
94static char *v9_hpriv_reg_names[] =
95{
96 "hpstate", "htstate", "resv2", "hintp", "resv4", "htba", "hver",
43e65147 97 "resv7", "resv8", "resv9", "resv10", "resv11", "resv12", "resv13",
ff3f9d5b
DM		 98 "resv14", "resv15", "resv16", "resv17", "resv18", "resv19", "resv20",
99 "resv21", "resv22", "resv23", "resv24", "resv25", "resv26", "resv27",
ec92c392 100 "hstick_offset", "hstick_enable", "resv30", "hstick_cmpr"
ff3f9d5b
DM		 101};
102
252b5132
RH		 103/* These are ordered according to there register number in
104 rd and wr insns (-16). */
105static char *v9a_asr_reg_names[] =
106{
107 "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
2e52845b 108 "softint", "tick_cmpr", "stick", "stick_cmpr", "cfr",
3d68f91c 109 "pause", "mwait"
252b5132
RH		 110};
111
112/* Macros used to extract instruction fields. Not all fields have
113 macros defined here, only those which are actually used. */
114
47b0e7ad
NC		 115#define X_RD(i) (((i) >> 25) & 0x1f)
116#define X_RS1(i) (((i) >> 14) & 0x1f)
117#define X_LDST_I(i) (((i) >> 13) & 1)
118#define X_ASI(i) (((i) >> 5) & 0xff)
119#define X_RS2(i) (((i) >> 0) & 0x1f)
ea783ef3 120#define X_RS3(i) (((i) >> 9) & 0x1f)
47b0e7ad
NC		 121#define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1))
122#define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n))
123#define X_DISP22(i) (((i) >> 0) & 0x3fffff)
124#define X_IMM22(i) X_DISP22 (i)
125#define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
252b5132
RH		 126
127/* These are for v9. */
47b0e7ad 128#define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
2615994e 129#define X_DISP10(i) (((((i) >> 19) & 3) << 8) | (((i) >> 5) & 0xff))
47b0e7ad
NC		 130#define X_DISP19(i) (((i) >> 0) & 0x7ffff)
131#define X_MEMBAR(i) ((i) & 0x7f)
252b5132
RH		 132
133/* Here is the union which was used to extract instruction fields
134 before the shift and mask macros were written.
135
136 union sparc_insn
137 {
138 unsigned long int code;
139 struct
140 {
141 unsigned int anop:2;
142 #define op ldst.anop
143 unsigned int anrd:5;
144 #define rd ldst.anrd
145 unsigned int op3:6;
146 unsigned int anrs1:5;
147 #define rs1 ldst.anrs1
148 unsigned int i:1;
149 unsigned int anasi:8;
150 #define asi ldst.anasi
151 unsigned int anrs2:5;
152 #define rs2 ldst.anrs2
153 #define shcnt rs2
154 } ldst;
155 struct
156 {
157 unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
158 unsigned int IMM13:13;
159 #define imm13 IMM13.IMM13
160 } IMM13;
161 struct
162 {
163 unsigned int anop:2;
164 unsigned int a:1;
165 unsigned int cond:4;
166 unsigned int op2:3;
167 unsigned int DISP22:22;
168 #define disp22 branch.DISP22
169 #define imm22 disp22
170 } branch;
171 struct
172 {
173 unsigned int anop:2;
174 unsigned int a:1;
175 unsigned int z:1;
176 unsigned int rcond:3;
177 unsigned int op2:3;
178 unsigned int DISP16HI:2;
179 unsigned int p:1;
180 unsigned int _rs1:5;
181 unsigned int DISP16LO:14;
182 } branch16;
183 struct
184 {
185 unsigned int anop:2;
186 unsigned int adisp30:30;
187 #define disp30 call.adisp30
188 } call;
47b0e7ad 189 }; */
252b5132
RH		 190
191/* Nonzero if INSN is the opcode for a delayed branch. */
47b0e7ad 192
252b5132 193static int
47b0e7ad 194is_delayed_branch (unsigned long insn)
252b5132 195{
47b0e7ad 196 sparc_opcode_hash *op;
252b5132
RH		 197
198 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
199 {
47b0e7ad
NC		 200 const sparc_opcode *opcode = op->opcode;
201
252b5132
RH		 202 if ((opcode->match & insn) == opcode->match
203 && (opcode->lose & insn) == 0)
47b0e7ad 204 return opcode->flags & F_DELAYED;
252b5132
RH		 205 }
206 return 0;
207}
208
209/* extern void qsort (); */
210
211/* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value
212 to compare_opcodes. */
213static unsigned int current_arch_mask;
214
47b0e7ad
NC		 215/* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */
216
217static int
218compute_arch_mask (unsigned long mach)
219{
220 switch (mach)
221 {
222 case 0 :
223 case bfd_mach_sparc :
d6787ef9
EB		 224 return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)
225 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_LEON));
47b0e7ad
NC		 226 case bfd_mach_sparc_sparclet :
227 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
228 case bfd_mach_sparc_sparclite :
229 case bfd_mach_sparc_sparclite_le :
230 /* sparclites insns are recognized by default (because that's how
231 they've always been treated, for better or worse). Kludge this by
232 indicating generic v8 is also selected. */
233 return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
234 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8));
235 case bfd_mach_sparc_v8plus :
236 case bfd_mach_sparc_v9 :
237 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
238 case bfd_mach_sparc_v8plusa :
239 case bfd_mach_sparc_v9a :
240 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
241 case bfd_mach_sparc_v8plusb :
242 case bfd_mach_sparc_v9b :
243 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B);
244 }
245 abort ();
246}
247
248/* Compare opcodes A and B. */
249
250static int
251compare_opcodes (const void * a, const void * b)
252{
253 sparc_opcode *op0 = * (sparc_opcode **) a;
254 sparc_opcode *op1 = * (sparc_opcode **) b;
255 unsigned long int match0 = op0->match, match1 = op1->match;
256 unsigned long int lose0 = op0->lose, lose1 = op1->lose;
257 register unsigned int i;
258
259 /* If one (and only one) insn isn't supported by the current architecture,
260 prefer the one that is. If neither are supported, but they're both for
261 the same architecture, continue processing. Otherwise (both unsupported
262 and for different architectures), prefer lower numbered arch's (fudged
263 by comparing the bitmasks). */
264 if (op0->architecture & current_arch_mask)
265 {
266 if (! (op1->architecture & current_arch_mask))
267 return -1;
268 }
269 else
270 {
271 if (op1->architecture & current_arch_mask)
272 return 1;
273 else if (op0->architecture != op1->architecture)
274 return op0->architecture - op1->architecture;
275 }
276
277 /* If a bit is set in both match and lose, there is something
278 wrong with the opcode table. */
279 if (match0 & lose0)
280 {
281 fprintf
282 (stderr,
283 /* xgettext:c-format */
284 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
285 op0->name, match0, lose0);
286 op0->lose &= ~op0->match;
287 lose0 = op0->lose;
288 }
289
290 if (match1 & lose1)
291 {
292 fprintf
293 (stderr,
294 /* xgettext:c-format */
295 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
296 op1->name, match1, lose1);
297 op1->lose &= ~op1->match;
298 lose1 = op1->lose;
299 }
300
301 /* Because the bits that are variable in one opcode are constant in
302 another, it is important to order the opcodes in the right order. */
303 for (i = 0; i < 32; ++i)
304 {
305 unsigned long int x = 1 << i;
306 int x0 = (match0 & x) != 0;
307 int x1 = (match1 & x) != 0;
308
309 if (x0 != x1)
310 return x1 - x0;
311 }
312
313 for (i = 0; i < 32; ++i)
314 {
315 unsigned long int x = 1 << i;
316 int x0 = (lose0 & x) != 0;
317 int x1 = (lose1 & x) != 0;
318
319 if (x0 != x1)
320 return x1 - x0;
321 }
322
323 /* They are functionally equal. So as long as the opcode table is
324 valid, we can put whichever one first we want, on aesthetic grounds. */
325
326 /* Our first aesthetic ground is that aliases defer to real insns. */
327 {
328 int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
329
330 if (alias_diff != 0)
331 /* Put the one that isn't an alias first. */
332 return alias_diff;
333 }
334
335 /* Except for aliases, two "identical" instructions had
336 better have the same opcode. This is a sanity check on the table. */
337 i = strcmp (op0->name, op1->name);
338 if (i)
339 {
0afd1215
DM		 340 if (op0->flags & F_ALIAS)
341 {
342 if (op0->flags & F_PREFERRED)
343 return -1;
344 if (op1->flags & F_PREFERRED)
345 return 1;
346
347 /* If they're both aliases, and neither is marked as preferred,
348 be arbitrary. */
349 return i;
350 }
47b0e7ad
NC		 351 else
352 fprintf (stderr,
353 /* xgettext:c-format */
354 _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
355 op0->name, op1->name);
356 }
357
358 /* Fewer arguments are preferred. */
359 {
360 int length_diff = strlen (op0->args) - strlen (op1->args);
361
362 if (length_diff != 0)
363 /* Put the one with fewer arguments first. */
364 return length_diff;
365 }
366
367 /* Put 1+i before i+1. */
368 {
369 char *p0 = (char *) strchr (op0->args, '+');
370 char *p1 = (char *) strchr (op1->args, '+');
371
372 if (p0 && p1)
373 {
374 /* There is a plus in both operands. Note that a plus
375 sign cannot be the first character in args,
376 so the following [-1]'s are valid. */
377 if (p0[-1] == 'i' && p1[1] == 'i')
378 /* op0 is i+1 and op1 is 1+i, so op1 goes first. */
379 return 1;
380 if (p0[1] == 'i' && p1[-1] == 'i')
381 /* op0 is 1+i and op1 is i+1, so op0 goes first. */
382 return -1;
383 }
384 }
385
386 /* Put 1,i before i,1. */
387 {
388 int i0 = strncmp (op0->args, "i,1", 3) == 0;
389 int i1 = strncmp (op1->args, "i,1", 3) == 0;
390
391 if (i0 ^ i1)
392 return i0 - i1;
393 }
394
395 /* They are, as far as we can tell, identical.
396 Since qsort may have rearranged the table partially, there is
397 no way to tell which one was first in the opcode table as
398 written, so just say there are equal. */
399 /* ??? This is no longer true now that we sort a vector of pointers,
400 not the table itself. */
401 return 0;
402}
403
404/* Build a hash table from the opcode table.
405 OPCODE_TABLE is a sorted list of pointers into the opcode table. */
406
407static void
408build_hash_table (const sparc_opcode **opcode_table,
409 sparc_opcode_hash **hash_table,
410 int num_opcodes)
411{
412 int i;
413 int hash_count[HASH_SIZE];
414 static sparc_opcode_hash *hash_buf = NULL;
415
416 /* Start at the end of the table and work backwards so that each
417 chain is sorted. */
418
419 memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
420 memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
421 if (hash_buf != NULL)
422 free (hash_buf);
423 hash_buf = xmalloc (sizeof (* hash_buf) * num_opcodes);
424 for (i = num_opcodes - 1; i >= 0; --i)
425 {
426 int hash = HASH_INSN (opcode_table[i]->match);
427 sparc_opcode_hash *h = &hash_buf[i];
428
429 h->next = hash_table[hash];
430 h->opcode = opcode_table[i];
431 hash_table[hash] = h;
432 ++hash_count[hash];
433 }
434
435#if 0 /* for debugging */
436 {
437 int min_count = num_opcodes, max_count = 0;
438 int total;
439
440 for (i = 0; i < HASH_SIZE; ++i)
441 {
442 if (hash_count[i] < min_count)
443 min_count = hash_count[i];
444 if (hash_count[i] > max_count)
445 max_count = hash_count[i];
446 total += hash_count[i];
447 }
448
449 printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
450 min_count, max_count, (double) total / HASH_SIZE);
451 }
452#endif
453}
454
252b5132
RH		 455/* Print one instruction from MEMADDR on INFO->STREAM.
456
457 We suffix the instruction with a comment that gives the absolute
458 address involved, as well as its symbolic form, if the instruction
459 is preceded by a findable `sethi' and it either adds an immediate
460 displacement to that register, or it is an `add' or `or' instruction
461 on that register. */
462
463int
47b0e7ad 464print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
252b5132
RH		 465{
466 FILE *stream = info->stream;
467 bfd_byte buffer[4];
468 unsigned long insn;
47b0e7ad 469 sparc_opcode_hash *op;
252b5132
RH		 470 /* Nonzero of opcode table has been initialized. */
471 static int opcodes_initialized = 0;
472 /* bfd mach number of last call. */
473 static unsigned long current_mach = 0;
7bfeee7b 474 bfd_vma (*getword) (const void *);
252b5132
RH		 475
476 if (!opcodes_initialized
477 || info->mach != current_mach)
478 {
479 int i;
480
481 current_arch_mask = compute_arch_mask (info->mach);
482
483 if (!opcodes_initialized)
47b0e7ad
NC		 484 sorted_opcodes =
485 xmalloc (sparc_num_opcodes * sizeof (sparc_opcode *));
252b5132
RH		 486 /* Reset the sorted table so we can resort it. */
487 for (i = 0; i < sparc_num_opcodes; ++i)
488 sorted_opcodes[i] = &sparc_opcodes[i];
489 qsort ((char *) sorted_opcodes, sparc_num_opcodes,
490 sizeof (sorted_opcodes[0]), compare_opcodes);
491
492 build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes);
493 current_mach = info->mach;
494 opcodes_initialized = 1;
495 }
496
497 {
498 int status =
499 (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
47b0e7ad 500
252b5132
RH		 501 if (status != 0)
502 {
503 (*info->memory_error_func) (status, memaddr, info);
504 return -1;
505 }
506 }
507
508 /* On SPARClite variants such as DANlite (sparc86x), instructions
0f6ab988 509 are always big-endian even when the machine is in little-endian mode. */
252b5132
RH		 510 if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite)
511 getword = bfd_getb32;
512 else
513 getword = bfd_getl32;
514
515 insn = getword (buffer);
516
0f6ab988
NC		 517 info->insn_info_valid = 1; /* We do return this info. */
518 info->insn_type = dis_nonbranch; /* Assume non branch insn. */
519 info->branch_delay_insns = 0; /* Assume no delay. */
520 info->target = 0; /* Assume no target known. */
252b5132
RH		 521
522 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
523 {
47b0e7ad 524 const sparc_opcode *opcode = op->opcode;
252b5132
RH		 525
526 /* If the insn isn't supported by the current architecture, skip it. */
527 if (! (opcode->architecture & current_arch_mask))
528 continue;
529
530 if ((opcode->match & insn) == opcode->match
531 && (opcode->lose & insn) == 0)
532 {
533 /* Nonzero means that we have found an instruction which has
534 the effect of adding or or'ing the imm13 field to rs1. */
535 int imm_added_to_rs1 = 0;
9df31319 536 int imm_ored_to_rs1 = 0;
252b5132
RH		 537
538 /* Nonzero means that we have found a plus sign in the args
539 field of the opcode table. */
540 int found_plus = 0;
47b0e7ad 541
252b5132
RH		 542 /* Nonzero means we have an annulled branch. */
543 int is_annulled = 0;
544
545 /* Do we have an `add' or `or' instruction combining an
546 immediate with rs1? */
9df31319
RH		 547 if (opcode->match == 0x80102000) /* or */
548 imm_ored_to_rs1 = 1;
549 if (opcode->match == 0x80002000) /* add */
252b5132
RH		 550 imm_added_to_rs1 = 1;
551
552 if (X_RS1 (insn) != X_RD (insn)
553 && strchr (opcode->args, 'r') != 0)
554 /* Can't do simple format if source and dest are different. */
555 continue;
556 if (X_RS2 (insn) != X_RD (insn)
557 && strchr (opcode->args, 'O') != 0)
558 /* Can't do simple format if source and dest are different. */
559 continue;
560
d908c8af 561 (*info->fprintf_func) (stream, "%s", opcode->name);
252b5132
RH		 562
563 {
47b0e7ad 564 const char *s;
252b5132
RH		 565
566 if (opcode->args[0] != ',')
567 (*info->fprintf_func) (stream, " ");
0f6ab988 568
252b5132
RH		 569 for (s = opcode->args; *s != '\0'; ++s)
570 {
571 while (*s == ',')
572 {
573 (*info->fprintf_func) (stream, ",");
574 ++s;
0f6ab988
NC		 575 switch (*s)
576 {
577 case 'a':
578 (*info->fprintf_func) (stream, "a");
579 is_annulled = 1;
580 ++s;
581 continue;
582 case 'N':
583 (*info->fprintf_func) (stream, "pn");
584 ++s;
585 continue;
586
587 case 'T':
588 (*info->fprintf_func) (stream, "pt");
589 ++s;
590 continue;
591
592 default:
593 break;
594 }
595 }
252b5132
RH		 596
597 (*info->fprintf_func) (stream, " ");
47b0e7ad 598
252b5132
RH		 599 switch (*s)
600 {
601 case '+':
602 found_plus = 1;
47b0e7ad 603 /* Fall through. */
252b5132 604
252b5132
RH		 605 default:
606 (*info->fprintf_func) (stream, "%c", *s);
607 break;
608
609 case '#':
610 (*info->fprintf_func) (stream, "0");
611 break;
612
613#define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n])
614 case '1':
615 case 'r':
616 reg (X_RS1 (insn));
617 break;
618
619 case '2':
620 case 'O':
621 reg (X_RS2 (insn));
622 break;
623
624 case 'd':
625 reg (X_RD (insn));
626 break;
627#undef reg
628
629#define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n])
630#define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)])
631 case 'e':
632 freg (X_RS1 (insn));
633 break;
47b0e7ad
NC		 634 case 'v': /* Double/even. */
635 case 'V': /* Quad/multiple of 4. */
252b5132
RH		 636 fregx (X_RS1 (insn));
637 break;
638
639 case 'f':
640 freg (X_RS2 (insn));
641 break;
47b0e7ad
NC		 642 case 'B': /* Double/even. */
643 case 'R': /* Quad/multiple of 4. */
252b5132
RH		 644 fregx (X_RS2 (insn));
645 break;
646
ea783ef3
DM		 647 case '4':
648 freg (X_RS3 (insn));
649 break;
650 case '5': /* Double/even. */
651 fregx (X_RS3 (insn));
652 break;
653
252b5132
RH		 654 case 'g':
655 freg (X_RD (insn));
656 break;
47b0e7ad
NC		 657 case 'H': /* Double/even. */
658 case 'J': /* Quad/multiple of 4. */
3d68f91c 659 case '}': /* Double/even. */
252b5132
RH		 660 fregx (X_RD (insn));
661 break;
662#undef freg
663#undef fregx
664
665#define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n))
666 case 'b':
667 creg (X_RS1 (insn));
668 break;
669
670 case 'c':
671 creg (X_RS2 (insn));
672 break;
673
674 case 'D':
675 creg (X_RD (insn));
676 break;
677#undef creg
678
679 case 'h':
680 (*info->fprintf_func) (stream, "%%hi(%#x)",
56930d37 681 ((unsigned) 0xFFFFFFFF
252b5132
RH		 682 & ((int) X_IMM22 (insn) << 10)));
683 break;
684
47b0e7ad
NC		 685 case 'i': /* 13 bit immediate. */
686 case 'I': /* 11 bit immediate. */
687 case 'j': /* 10 bit immediate. */
252b5132
RH		 688 {
689 int imm;
690
691 if (*s == 'i')
692 imm = X_SIMM (insn, 13);
693 else if (*s == 'I')
694 imm = X_SIMM (insn, 11);
695 else
696 imm = X_SIMM (insn, 10);
697
698 /* Check to see whether we have a 1+i, and take
699 note of that fact.
700
701 Note: because of the way we sort the table,
702 we will be matching 1+i rather than i+1,
703 so it is OK to assume that i is after +,
704 not before it. */
705 if (found_plus)
706 imm_added_to_rs1 = 1;
47b0e7ad 707
252b5132
RH		 708 if (imm <= 9)
709 (*info->fprintf_func) (stream, "%d", imm);
710 else
711 (*info->fprintf_func) (stream, "%#x", imm);
712 }
713 break;
714
6cda1326 715 case ')': /* 5 bit unsigned immediate from RS3. */
d908c8af 716 (info->fprintf_func) (stream, "%#x", (unsigned int) X_RS3 (insn));
6cda1326
DM		 717 break;
718
47b0e7ad
NC		 719 case 'X': /* 5 bit unsigned immediate. */
720 case 'Y': /* 6 bit unsigned immediate. */
252b5132
RH		 721 {
722 int imm = X_IMM (insn, *s == 'X' ? 5 : 6);
723
724 if (imm <= 9)
725 (info->fprintf_func) (stream, "%d", imm);
726 else
727 (info->fprintf_func) (stream, "%#x", (unsigned) imm);
728 }
729 break;
730
19f7b010 731 case '3':
0fd3a477 732 (info->fprintf_func) (stream, "%ld", X_IMM (insn, 3));
19f7b010
JJ		 733 break;
734
252b5132
RH		 735 case 'K':
736 {
737 int mask = X_MEMBAR (insn);
738 int bit = 0x40, printed_one = 0;
739 const char *name;
740
741 if (mask == 0)
742 (info->fprintf_func) (stream, "0");
743 else
744 while (bit)
745 {
746 if (mask & bit)
747 {
748 if (printed_one)
749 (info->fprintf_func) (stream, "|");
750 name = sparc_decode_membar (bit);
751 (info->fprintf_func) (stream, "%s", name);
752 printed_one = 1;
753 }
754 bit >>= 1;
755 }
756 break;
757 }
758
2615994e
DM		 759 case '=':
760 info->target = memaddr + SEX (X_DISP10 (insn), 10) * 4;
761 (*info->print_address_func) (info->target, info);
762 break;
763
252b5132
RH		 764 case 'k':
765 info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4;
766 (*info->print_address_func) (info->target, info);
767 break;
768
769 case 'G':
770 info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4;
771 (*info->print_address_func) (info->target, info);
772 break;
773
774 case '6':
775 case '7':
776 case '8':
777 case '9':
778 (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0');
779 break;
780
781 case 'z':
782 (*info->fprintf_func) (stream, "%%icc");
783 break;
784
785 case 'Z':
786 (*info->fprintf_func) (stream, "%%xcc");
787 break;
788
789 case 'E':
790 (*info->fprintf_func) (stream, "%%ccr");
791 break;
792
793 case 's':
794 (*info->fprintf_func) (stream, "%%fprs");
795 break;
796
3d68f91c
JM		 797 case '{':
798 (*info->fprintf_func) (stream, "%%mcdper");
799 break;
800
252b5132
RH		 801 case 'o':
802 (*info->fprintf_func) (stream, "%%asi");
803 break;
47b0e7ad 804
252b5132
RH		 805 case 'W':
806 (*info->fprintf_func) (stream, "%%tick");
807 break;
808
809 case 'P':
810 (*info->fprintf_func) (stream, "%%pc");
811 break;
812
813 case '?':
814 if (X_RS1 (insn) == 31)
815 (*info->fprintf_func) (stream, "%%ver");
38074311
JM		 816 else if (X_RS1 (insn) == 23)
817 (*info->fprintf_func) (stream, "%%pmcdper");
ff3f9d5b 818 else if ((unsigned) X_RS1 (insn) < 17)
252b5132
RH		 819 (*info->fprintf_func) (stream, "%%%s",
820 v9_priv_reg_names[X_RS1 (insn)]);
821 else
822 (*info->fprintf_func) (stream, "%%reserved");
823 break;
824
825 case '!':
38074311
JM		 826 if (X_RD (insn) == 23)
827 (*info->fprintf_func) (stream, "%%pmcdper");
828 else if ((unsigned) X_RD (insn) < 17)
252b5132
RH		 829 (*info->fprintf_func) (stream, "%%%s",
830 v9_priv_reg_names[X_RD (insn)]);
831 else
832 (*info->fprintf_func) (stream, "%%reserved");
833 break;
834
ff3f9d5b
DM		 835 case '$':
836 if ((unsigned) X_RS1 (insn) < 32)
837 (*info->fprintf_func) (stream, "%%%s",
838 v9_hpriv_reg_names[X_RS1 (insn)]);
839 else
840 (*info->fprintf_func) (stream, "%%reserved");
841 break;
842
843 case '%':
844 if ((unsigned) X_RD (insn) < 32)
845 (*info->fprintf_func) (stream, "%%%s",
846 v9_hpriv_reg_names[X_RD (insn)]);
847 else
848 (*info->fprintf_func) (stream, "%%reserved");
849 break;
850
252b5132 851 case '/':
ea783ef3 852 if (X_RS1 (insn) < 16 || X_RS1 (insn) > 28)
252b5132
RH		 853 (*info->fprintf_func) (stream, "%%reserved");
854 else
855 (*info->fprintf_func) (stream, "%%%s",
856 v9a_asr_reg_names[X_RS1 (insn)-16]);
857 break;
858
859 case '_':
ea783ef3 860 if (X_RD (insn) < 16 || X_RD (insn) > 28)
252b5132
RH		 861 (*info->fprintf_func) (stream, "%%reserved");
862 else
863 (*info->fprintf_func) (stream, "%%%s",
864 v9a_asr_reg_names[X_RD (insn)-16]);
865 break;
866
867 case '*':
868 {
869 const char *name = sparc_decode_prefetch (X_RD (insn));
870
871 if (name)
872 (*info->fprintf_func) (stream, "%s", name);
873 else
0fd3a477 874 (*info->fprintf_func) (stream, "%ld", X_RD (insn));
252b5132
RH		 875 break;
876 }
47b0e7ad 877
252b5132 878 case 'M':
0fd3a477 879 (*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn));
252b5132 880 break;
47b0e7ad 881
252b5132 882 case 'm':
0fd3a477 883 (*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn));
252b5132 884 break;
47b0e7ad 885
252b5132
RH		 886 case 'L':
887 info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4;
888 (*info->print_address_func) (info->target, info);
889 break;
890
891 case 'n':
892 (*info->fprintf_func)
893 (stream, "%#x", SEX (X_DISP22 (insn), 22));
894 break;
895
896 case 'l':
897 info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4;
898 (*info->print_address_func) (info->target, info);
899 break;
900
901 case 'A':
902 {
903 const char *name = sparc_decode_asi (X_ASI (insn));
904
905 if (name)
906 (*info->fprintf_func) (stream, "%s", name);
907 else
0fd3a477 908 (*info->fprintf_func) (stream, "(%ld)", X_ASI (insn));
252b5132
RH		 909 break;
910 }
911
912 case 'C':
913 (*info->fprintf_func) (stream, "%%csr");
914 break;
915
916 case 'F':
917 (*info->fprintf_func) (stream, "%%fsr");
918 break;
919
ea783ef3
DM		 920 case '(':
921 (*info->fprintf_func) (stream, "%%efsr");
922 break;
923
252b5132
RH		 924 case 'p':
925 (*info->fprintf_func) (stream, "%%psr");
926 break;
927
928 case 'q':
929 (*info->fprintf_func) (stream, "%%fq");
930 break;
931
932 case 'Q':
933 (*info->fprintf_func) (stream, "%%cq");
934 break;
935
936 case 't':
937 (*info->fprintf_func) (stream, "%%tbr");
938 break;
939
940 case 'w':
941 (*info->fprintf_func) (stream, "%%wim");
942 break;
943
944 case 'x':
0fd3a477 945 (*info->fprintf_func) (stream, "%ld",
252b5132
RH		 946 ((X_LDST_I (insn) << 8)
947 + X_ASI (insn)));
948 break;
949
950 case 'y':
951 (*info->fprintf_func) (stream, "%%y");
952 break;
953
954 case 'u':
955 case 'U':
956 {
957 int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn);
958 const char *name = sparc_decode_sparclet_cpreg (val);
959
960 if (name)
961 (*info->fprintf_func) (stream, "%s", name);
962 else
963 (*info->fprintf_func) (stream, "%%cpreg(%d)", val);
964 break;
965 }
966 }
967 }
968 }
969
970 /* If we are adding or or'ing something to rs1, then
971 check to see whether the previous instruction was
972 a sethi to the same register as in the sethi.
973 If so, attempt to print the result of the add or
974 or (in this context add and or do the same thing)
975 and its symbolic value. */
9df31319 976 if (imm_ored_to_rs1 || imm_added_to_rs1)
252b5132
RH		 977 {
978 unsigned long prev_insn;
979 int errcode;
980
0f6ab988
NC		 981 if (memaddr >= 4)
982 errcode =
983 (*info->read_memory_func)
252b5132 984 (memaddr - 4, buffer, sizeof (buffer), info);
0f6ab988
NC		 985 else
986 errcode = 1;
987
252b5132
RH		 988 prev_insn = getword (buffer);
989
990 if (errcode == 0)
991 {
992 /* If it is a delayed branch, we need to look at the
993 instruction before the delayed branch. This handles
0f6ab988 994 sequences such as:
252b5132
RH		 995
996 sethi %o1, %hi(_foo), %o1
997 call _printf
0f6ab988 998 or %o1, %lo(_foo), %o1 */
252b5132
RH		 999
1000 if (is_delayed_branch (prev_insn))
1001 {
0f6ab988
NC		 1002 if (memaddr >= 8)
1003 errcode = (*info->read_memory_func)
1004 (memaddr - 8, buffer, sizeof (buffer), info);
1005 else
1006 errcode = 1;
1007
252b5132
RH		 1008 prev_insn = getword (buffer);
1009 }
1010 }
1011
1012 /* If there was a problem reading memory, then assume
1013 the previous instruction was not sethi. */
1014 if (errcode == 0)
1015 {
1016 /* Is it sethi to the same register? */
1017 if ((prev_insn & 0xc1c00000) == 0x01000000
1018 && X_RD (prev_insn) == X_RS1 (insn))
1019 {
1020 (*info->fprintf_func) (stream, "\t! ");
47b0e7ad 1021 info->target =
56930d37
AO		 1022 ((unsigned) 0xFFFFFFFF
1023 & ((int) X_IMM22 (prev_insn) << 10));
9df31319
RH		 1024 if (imm_added_to_rs1)
1025 info->target += X_SIMM (insn, 13);
1026 else
1027 info->target |= X_SIMM (insn, 13);
252b5132
RH		 1028 (*info->print_address_func) (info->target, info);
1029 info->insn_type = dis_dref;
1030 info->data_size = 4; /* FIXME!!! */
1031 }
1032 }
1033 }
1034
1035 if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
1036 {
c7e2358a
AM		 1037 /* FIXME -- check is_annulled flag. */
1038 (void) is_annulled;
252b5132
RH		 1039 if (opcode->flags & F_UNBR)
1040 info->insn_type = dis_branch;
1041 if (opcode->flags & F_CONDBR)
1042 info->insn_type = dis_condbranch;
1043 if (opcode->flags & F_JSR)
1044 info->insn_type = dis_jsr;
1045 if (opcode->flags & F_DELAYED)
1046 info->branch_delay_insns = 1;
1047 }
1048
1049 return sizeof (buffer);
1050 }
1051 }
1052
0f6ab988 1053 info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */
252b5132
RH		 1054 (*info->fprintf_func) (stream, _("unknown"));
1055 return sizeof (buffer);
1056}
GDB Binutils - Deliverables
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