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Move sparc opcode hwcaps out of sparc_opcode flags field.
[deliverable/binutils-gdb.git] / opcodes / sparc-dis.c
CommitLineData
252b5132 1/* Print SPARC instructions.
060d22b0 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
c7e2358a 3 2000, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010
aa820537 4 Free Software Foundation, Inc.
252b5132 5
9b201bb5
NC		 6 This file is part of the GNU opcodes library.
7
8 This library is free software; you can redistribute it and/or modify
0f6ab988 9 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
0f6ab988
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
47b0e7ad
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132
RH		 22
23#include <stdio.h>
24
252b5132
RH		 25#include "sysdep.h"
26#include "opcode/sparc.h"
27#include "dis-asm.h"
28#include "libiberty.h"
29#include "opintl.h"
30
31/* Bitmask of v9 architectures. */
32#define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
19f7b010
JJ		 33 | (1 << SPARC_OPCODE_ARCH_V9A) \
34 | (1 << SPARC_OPCODE_ARCH_V9B))
252b5132
RH		 35/* 1 if INSN is for v9 only. */
36#define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
37/* 1 if INSN is for v9. */
38#define V9_P(insn) (((insn)->architecture & MASK_V9) != 0)
39
40/* The sorted opcode table. */
47b0e7ad 41static const sparc_opcode **sorted_opcodes;
252b5132
RH		 42
43/* For faster lookup, after insns are sorted they are hashed. */
44/* ??? I think there is room for even more improvement. */
45
46#define HASH_SIZE 256
47/* It is important that we only look at insn code bits as that is how the
48 opcode table is hashed. OPCODE_BITS is a table of valid bits for each
49 of the main types (0,1,2,3). */
50static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
51#define HASH_INSN(INSN) \
52 ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
47b0e7ad 53typedef struct sparc_opcode_hash
0f6ab988 54{
47b0e7ad
NC		 55 struct sparc_opcode_hash *next;
56 const sparc_opcode *opcode;
57} sparc_opcode_hash;
252b5132 58
47b0e7ad 59static sparc_opcode_hash *opcode_hash_table[HASH_SIZE];
252b5132
RH		 60
61/* Sign-extend a value which is N bits long. */
62#define SEX(value, bits) \
63 ((((int)(value)) << ((8 * sizeof (int)) - bits)) \
64 >> ((8 * sizeof (int)) - bits) )
65
66static char *reg_names[] =
47b0e7ad
NC		 67{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
68 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
69 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
70 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
71 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
72 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
252b5132
RH		 73 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
74 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
47b0e7ad
NC		 75 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
76 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
252b5132
RH		 77 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
78 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
79/* psr, wim, tbr, fpsr, cpsr are v8 only. */
80 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
81};
82
83#define freg_names (&reg_names[4 * 8])
84
85/* These are ordered according to there register number in
86 rdpr and wrpr insns. */
87static char *v9_priv_reg_names[] =
88{
89 "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
90 "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
ff3f9d5b 91 "wstate", "fq", "gl"
252b5132
RH		 92 /* "ver" - special cased */
93};
94
ff3f9d5b
DM		 95/* These are ordered according to there register number in
96 rdhpr and wrhpr insns. */
97static char *v9_hpriv_reg_names[] =
98{
99 "hpstate", "htstate", "resv2", "hintp", "resv4", "htba", "hver",
100 "resv7", "resv8", "resv9", "resv10", "resv11", "resv12", "resv13",
101 "resv14", "resv15", "resv16", "resv17", "resv18", "resv19", "resv20",
102 "resv21", "resv22", "resv23", "resv24", "resv25", "resv26", "resv27",
103 "resv28", "resv29", "resv30", "hstick_cmpr"
104};
105
252b5132
RH		 106/* These are ordered according to there register number in
107 rd and wr insns (-16). */
108static char *v9a_asr_reg_names[] =
109{
110 "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
ea783ef3
DM		 111 "softint", "tick_cmpr", "stick", "stick_cmpr", "resv26",
112 "resv27", "cps"
252b5132
RH		 113};
114
115/* Macros used to extract instruction fields. Not all fields have
116 macros defined here, only those which are actually used. */
117
47b0e7ad
NC		 118#define X_RD(i) (((i) >> 25) & 0x1f)
119#define X_RS1(i) (((i) >> 14) & 0x1f)
120#define X_LDST_I(i) (((i) >> 13) & 1)
121#define X_ASI(i) (((i) >> 5) & 0xff)
122#define X_RS2(i) (((i) >> 0) & 0x1f)
ea783ef3 123#define X_RS3(i) (((i) >> 9) & 0x1f)
47b0e7ad
NC		 124#define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1))
125#define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n))
126#define X_DISP22(i) (((i) >> 0) & 0x3fffff)
127#define X_IMM22(i) X_DISP22 (i)
128#define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
252b5132
RH		 129
130/* These are for v9. */
47b0e7ad 131#define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
2615994e 132#define X_DISP10(i) (((((i) >> 19) & 3) << 8) | (((i) >> 5) & 0xff))
47b0e7ad
NC		 133#define X_DISP19(i) (((i) >> 0) & 0x7ffff)
134#define X_MEMBAR(i) ((i) & 0x7f)
252b5132
RH		 135
136/* Here is the union which was used to extract instruction fields
137 before the shift and mask macros were written.
138
139 union sparc_insn
140 {
141 unsigned long int code;
142 struct
143 {
144 unsigned int anop:2;
145 #define op ldst.anop
146 unsigned int anrd:5;
147 #define rd ldst.anrd
148 unsigned int op3:6;
149 unsigned int anrs1:5;
150 #define rs1 ldst.anrs1
151 unsigned int i:1;
152 unsigned int anasi:8;
153 #define asi ldst.anasi
154 unsigned int anrs2:5;
155 #define rs2 ldst.anrs2
156 #define shcnt rs2
157 } ldst;
158 struct
159 {
160 unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
161 unsigned int IMM13:13;
162 #define imm13 IMM13.IMM13
163 } IMM13;
164 struct
165 {
166 unsigned int anop:2;
167 unsigned int a:1;
168 unsigned int cond:4;
169 unsigned int op2:3;
170 unsigned int DISP22:22;
171 #define disp22 branch.DISP22
172 #define imm22 disp22
173 } branch;
174 struct
175 {
176 unsigned int anop:2;
177 unsigned int a:1;
178 unsigned int z:1;
179 unsigned int rcond:3;
180 unsigned int op2:3;
181 unsigned int DISP16HI:2;
182 unsigned int p:1;
183 unsigned int _rs1:5;
184 unsigned int DISP16LO:14;
185 } branch16;
186 struct
187 {
188 unsigned int anop:2;
189 unsigned int adisp30:30;
190 #define disp30 call.adisp30
191 } call;
47b0e7ad 192 }; */
252b5132
RH		 193
194/* Nonzero if INSN is the opcode for a delayed branch. */
47b0e7ad 195
252b5132 196static int
47b0e7ad 197is_delayed_branch (unsigned long insn)
252b5132 198{
47b0e7ad 199 sparc_opcode_hash *op;
252b5132
RH		 200
201 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
202 {
47b0e7ad
NC		 203 const sparc_opcode *opcode = op->opcode;
204
252b5132
RH		 205 if ((opcode->match & insn) == opcode->match
206 && (opcode->lose & insn) == 0)
47b0e7ad 207 return opcode->flags & F_DELAYED;
252b5132
RH		 208 }
209 return 0;
210}
211
212/* extern void qsort (); */
213
214/* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value
215 to compare_opcodes. */
216static unsigned int current_arch_mask;
217
47b0e7ad
NC		 218/* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */
219
220static int
221compute_arch_mask (unsigned long mach)
222{
223 switch (mach)
224 {
225 case 0 :
226 case bfd_mach_sparc :
227 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8);
228 case bfd_mach_sparc_sparclet :
229 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
230 case bfd_mach_sparc_sparclite :
231 case bfd_mach_sparc_sparclite_le :
232 /* sparclites insns are recognized by default (because that's how
233 they've always been treated, for better or worse). Kludge this by
234 indicating generic v8 is also selected. */
235 return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
236 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8));
237 case bfd_mach_sparc_v8plus :
238 case bfd_mach_sparc_v9 :
239 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
240 case bfd_mach_sparc_v8plusa :
241 case bfd_mach_sparc_v9a :
242 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
243 case bfd_mach_sparc_v8plusb :
244 case bfd_mach_sparc_v9b :
245 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B);
246 }
247 abort ();
248}
249
250/* Compare opcodes A and B. */
251
252static int
253compare_opcodes (const void * a, const void * b)
254{
255 sparc_opcode *op0 = * (sparc_opcode **) a;
256 sparc_opcode *op1 = * (sparc_opcode **) b;
257 unsigned long int match0 = op0->match, match1 = op1->match;
258 unsigned long int lose0 = op0->lose, lose1 = op1->lose;
259 register unsigned int i;
260
261 /* If one (and only one) insn isn't supported by the current architecture,
262 prefer the one that is. If neither are supported, but they're both for
263 the same architecture, continue processing. Otherwise (both unsupported
264 and for different architectures), prefer lower numbered arch's (fudged
265 by comparing the bitmasks). */
266 if (op0->architecture & current_arch_mask)
267 {
268 if (! (op1->architecture & current_arch_mask))
269 return -1;
270 }
271 else
272 {
273 if (op1->architecture & current_arch_mask)
274 return 1;
275 else if (op0->architecture != op1->architecture)
276 return op0->architecture - op1->architecture;
277 }
278
279 /* If a bit is set in both match and lose, there is something
280 wrong with the opcode table. */
281 if (match0 & lose0)
282 {
283 fprintf
284 (stderr,
285 /* xgettext:c-format */
286 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
287 op0->name, match0, lose0);
288 op0->lose &= ~op0->match;
289 lose0 = op0->lose;
290 }
291
292 if (match1 & lose1)
293 {
294 fprintf
295 (stderr,
296 /* xgettext:c-format */
297 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
298 op1->name, match1, lose1);
299 op1->lose &= ~op1->match;
300 lose1 = op1->lose;
301 }
302
303 /* Because the bits that are variable in one opcode are constant in
304 another, it is important to order the opcodes in the right order. */
305 for (i = 0; i < 32; ++i)
306 {
307 unsigned long int x = 1 << i;
308 int x0 = (match0 & x) != 0;
309 int x1 = (match1 & x) != 0;
310
311 if (x0 != x1)
312 return x1 - x0;
313 }
314
315 for (i = 0; i < 32; ++i)
316 {
317 unsigned long int x = 1 << i;
318 int x0 = (lose0 & x) != 0;
319 int x1 = (lose1 & x) != 0;
320
321 if (x0 != x1)
322 return x1 - x0;
323 }
324
325 /* They are functionally equal. So as long as the opcode table is
326 valid, we can put whichever one first we want, on aesthetic grounds. */
327
328 /* Our first aesthetic ground is that aliases defer to real insns. */
329 {
330 int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
331
332 if (alias_diff != 0)
333 /* Put the one that isn't an alias first. */
334 return alias_diff;
335 }
336
337 /* Except for aliases, two "identical" instructions had
338 better have the same opcode. This is a sanity check on the table. */
339 i = strcmp (op0->name, op1->name);
340 if (i)
341 {
342 if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */
343 return i;
344 else
345 fprintf (stderr,
346 /* xgettext:c-format */
347 _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
348 op0->name, op1->name);
349 }
350
351 /* Fewer arguments are preferred. */
352 {
353 int length_diff = strlen (op0->args) - strlen (op1->args);
354
355 if (length_diff != 0)
356 /* Put the one with fewer arguments first. */
357 return length_diff;
358 }
359
360 /* Put 1+i before i+1. */
361 {
362 char *p0 = (char *) strchr (op0->args, '+');
363 char *p1 = (char *) strchr (op1->args, '+');
364
365 if (p0 && p1)
366 {
367 /* There is a plus in both operands. Note that a plus
368 sign cannot be the first character in args,
369 so the following [-1]'s are valid. */
370 if (p0[-1] == 'i' && p1[1] == 'i')
371 /* op0 is i+1 and op1 is 1+i, so op1 goes first. */
372 return 1;
373 if (p0[1] == 'i' && p1[-1] == 'i')
374 /* op0 is 1+i and op1 is i+1, so op0 goes first. */
375 return -1;
376 }
377 }
378
379 /* Put 1,i before i,1. */
380 {
381 int i0 = strncmp (op0->args, "i,1", 3) == 0;
382 int i1 = strncmp (op1->args, "i,1", 3) == 0;
383
384 if (i0 ^ i1)
385 return i0 - i1;
386 }
387
388 /* They are, as far as we can tell, identical.
389 Since qsort may have rearranged the table partially, there is
390 no way to tell which one was first in the opcode table as
391 written, so just say there are equal. */
392 /* ??? This is no longer true now that we sort a vector of pointers,
393 not the table itself. */
394 return 0;
395}
396
397/* Build a hash table from the opcode table.
398 OPCODE_TABLE is a sorted list of pointers into the opcode table. */
399
400static void
401build_hash_table (const sparc_opcode **opcode_table,
402 sparc_opcode_hash **hash_table,
403 int num_opcodes)
404{
405 int i;
406 int hash_count[HASH_SIZE];
407 static sparc_opcode_hash *hash_buf = NULL;
408
409 /* Start at the end of the table and work backwards so that each
410 chain is sorted. */
411
412 memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
413 memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
414 if (hash_buf != NULL)
415 free (hash_buf);
416 hash_buf = xmalloc (sizeof (* hash_buf) * num_opcodes);
417 for (i = num_opcodes - 1; i >= 0; --i)
418 {
419 int hash = HASH_INSN (opcode_table[i]->match);
420 sparc_opcode_hash *h = &hash_buf[i];
421
422 h->next = hash_table[hash];
423 h->opcode = opcode_table[i];
424 hash_table[hash] = h;
425 ++hash_count[hash];
426 }
427
428#if 0 /* for debugging */
429 {
430 int min_count = num_opcodes, max_count = 0;
431 int total;
432
433 for (i = 0; i < HASH_SIZE; ++i)
434 {
435 if (hash_count[i] < min_count)
436 min_count = hash_count[i];
437 if (hash_count[i] > max_count)
438 max_count = hash_count[i];
439 total += hash_count[i];
440 }
441
442 printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
443 min_count, max_count, (double) total / HASH_SIZE);
444 }
445#endif
446}
447
252b5132
RH		 448/* Print one instruction from MEMADDR on INFO->STREAM.
449
450 We suffix the instruction with a comment that gives the absolute
451 address involved, as well as its symbolic form, if the instruction
452 is preceded by a findable `sethi' and it either adds an immediate
453 displacement to that register, or it is an `add' or `or' instruction
454 on that register. */
455
456int
47b0e7ad 457print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
252b5132
RH		 458{
459 FILE *stream = info->stream;
460 bfd_byte buffer[4];
461 unsigned long insn;
47b0e7ad 462 sparc_opcode_hash *op;
252b5132
RH		 463 /* Nonzero of opcode table has been initialized. */
464 static int opcodes_initialized = 0;
465 /* bfd mach number of last call. */
466 static unsigned long current_mach = 0;
7bfeee7b 467 bfd_vma (*getword) (const void *);
252b5132
RH		 468
469 if (!opcodes_initialized
470 || info->mach != current_mach)
471 {
472 int i;
473
474 current_arch_mask = compute_arch_mask (info->mach);
475
476 if (!opcodes_initialized)
47b0e7ad
NC		 477 sorted_opcodes =
478 xmalloc (sparc_num_opcodes * sizeof (sparc_opcode *));
252b5132
RH		 479 /* Reset the sorted table so we can resort it. */
480 for (i = 0; i < sparc_num_opcodes; ++i)
481 sorted_opcodes[i] = &sparc_opcodes[i];
482 qsort ((char *) sorted_opcodes, sparc_num_opcodes,
483 sizeof (sorted_opcodes[0]), compare_opcodes);
484
485 build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes);
486 current_mach = info->mach;
487 opcodes_initialized = 1;
488 }
489
490 {
491 int status =
492 (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
47b0e7ad 493
252b5132
RH		 494 if (status != 0)
495 {
496 (*info->memory_error_func) (status, memaddr, info);
497 return -1;
498 }
499 }
500
501 /* On SPARClite variants such as DANlite (sparc86x), instructions
0f6ab988 502 are always big-endian even when the machine is in little-endian mode. */
252b5132
RH		 503 if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite)
504 getword = bfd_getb32;
505 else
506 getword = bfd_getl32;
507
508 insn = getword (buffer);
509
0f6ab988
NC		 510 info->insn_info_valid = 1; /* We do return this info. */
511 info->insn_type = dis_nonbranch; /* Assume non branch insn. */
512 info->branch_delay_insns = 0; /* Assume no delay. */
513 info->target = 0; /* Assume no target known. */
252b5132
RH		 514
515 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
516 {
47b0e7ad 517 const sparc_opcode *opcode = op->opcode;
252b5132
RH		 518
519 /* If the insn isn't supported by the current architecture, skip it. */
520 if (! (opcode->architecture & current_arch_mask))
521 continue;
522
523 if ((opcode->match & insn) == opcode->match
524 && (opcode->lose & insn) == 0)
525 {
526 /* Nonzero means that we have found an instruction which has
527 the effect of adding or or'ing the imm13 field to rs1. */
528 int imm_added_to_rs1 = 0;
9df31319 529 int imm_ored_to_rs1 = 0;
252b5132
RH		 530
531 /* Nonzero means that we have found a plus sign in the args
532 field of the opcode table. */
533 int found_plus = 0;
47b0e7ad 534
252b5132
RH		 535 /* Nonzero means we have an annulled branch. */
536 int is_annulled = 0;
537
538 /* Do we have an `add' or `or' instruction combining an
539 immediate with rs1? */
9df31319
RH		 540 if (opcode->match == 0x80102000) /* or */
541 imm_ored_to_rs1 = 1;
542 if (opcode->match == 0x80002000) /* add */
252b5132
RH		 543 imm_added_to_rs1 = 1;
544
545 if (X_RS1 (insn) != X_RD (insn)
546 && strchr (opcode->args, 'r') != 0)
547 /* Can't do simple format if source and dest are different. */
548 continue;
549 if (X_RS2 (insn) != X_RD (insn)
550 && strchr (opcode->args, 'O') != 0)
551 /* Can't do simple format if source and dest are different. */
552 continue;
553
554 (*info->fprintf_func) (stream, opcode->name);
555
556 {
47b0e7ad 557 const char *s;
252b5132
RH		 558
559 if (opcode->args[0] != ',')
560 (*info->fprintf_func) (stream, " ");
0f6ab988 561
252b5132
RH		 562 for (s = opcode->args; *s != '\0'; ++s)
563 {
564 while (*s == ',')
565 {
566 (*info->fprintf_func) (stream, ",");
567 ++s;
0f6ab988
NC		 568 switch (*s)
569 {
570 case 'a':
571 (*info->fprintf_func) (stream, "a");
572 is_annulled = 1;
573 ++s;
574 continue;
575 case 'N':
576 (*info->fprintf_func) (stream, "pn");
577 ++s;
578 continue;
579
580 case 'T':
581 (*info->fprintf_func) (stream, "pt");
582 ++s;
583 continue;
584
585 default:
586 break;
587 }
588 }
252b5132
RH		 589
590 (*info->fprintf_func) (stream, " ");
47b0e7ad 591
252b5132
RH		 592 switch (*s)
593 {
594 case '+':
595 found_plus = 1;
47b0e7ad 596 /* Fall through. */
252b5132 597
252b5132
RH		 598 default:
599 (*info->fprintf_func) (stream, "%c", *s);
600 break;
601
602 case '#':
603 (*info->fprintf_func) (stream, "0");
604 break;
605
606#define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n])
607 case '1':
608 case 'r':
609 reg (X_RS1 (insn));
610 break;
611
612 case '2':
613 case 'O':
614 reg (X_RS2 (insn));
615 break;
616
617 case 'd':
618 reg (X_RD (insn));
619 break;
620#undef reg
621
622#define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n])
623#define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)])
624 case 'e':
625 freg (X_RS1 (insn));
626 break;
47b0e7ad
NC		 627 case 'v': /* Double/even. */
628 case 'V': /* Quad/multiple of 4. */
252b5132
RH		 629 fregx (X_RS1 (insn));
630 break;
631
632 case 'f':
633 freg (X_RS2 (insn));
634 break;
47b0e7ad
NC		 635 case 'B': /* Double/even. */
636 case 'R': /* Quad/multiple of 4. */
252b5132
RH		 637 fregx (X_RS2 (insn));
638 break;
639
ea783ef3
DM		 640 case '4':
641 freg (X_RS3 (insn));
642 break;
643 case '5': /* Double/even. */
644 fregx (X_RS3 (insn));
645 break;
646
252b5132
RH		 647 case 'g':
648 freg (X_RD (insn));
649 break;
47b0e7ad
NC		 650 case 'H': /* Double/even. */
651 case 'J': /* Quad/multiple of 4. */
252b5132
RH		 652 fregx (X_RD (insn));
653 break;
654#undef freg
655#undef fregx
656
657#define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n))
658 case 'b':
659 creg (X_RS1 (insn));
660 break;
661
662 case 'c':
663 creg (X_RS2 (insn));
664 break;
665
666 case 'D':
667 creg (X_RD (insn));
668 break;
669#undef creg
670
671 case 'h':
672 (*info->fprintf_func) (stream, "%%hi(%#x)",
56930d37 673 ((unsigned) 0xFFFFFFFF
252b5132
RH		 674 & ((int) X_IMM22 (insn) << 10)));
675 break;
676
47b0e7ad
NC		 677 case 'i': /* 13 bit immediate. */
678 case 'I': /* 11 bit immediate. */
679 case 'j': /* 10 bit immediate. */
252b5132
RH		 680 {
681 int imm;
682
683 if (*s == 'i')
684 imm = X_SIMM (insn, 13);
685 else if (*s == 'I')
686 imm = X_SIMM (insn, 11);
687 else
688 imm = X_SIMM (insn, 10);
689
690 /* Check to see whether we have a 1+i, and take
691 note of that fact.
692
693 Note: because of the way we sort the table,
694 we will be matching 1+i rather than i+1,
695 so it is OK to assume that i is after +,
696 not before it. */
697 if (found_plus)
698 imm_added_to_rs1 = 1;
47b0e7ad 699
252b5132
RH		 700 if (imm <= 9)
701 (*info->fprintf_func) (stream, "%d", imm);
702 else
703 (*info->fprintf_func) (stream, "%#x", imm);
704 }
705 break;
706
47b0e7ad
NC		 707 case 'X': /* 5 bit unsigned immediate. */
708 case 'Y': /* 6 bit unsigned immediate. */
252b5132
RH		 709 {
710 int imm = X_IMM (insn, *s == 'X' ? 5 : 6);
711
712 if (imm <= 9)
713 (info->fprintf_func) (stream, "%d", imm);
714 else
715 (info->fprintf_func) (stream, "%#x", (unsigned) imm);
716 }
717 break;
718
19f7b010 719 case '3':
0fd3a477 720 (info->fprintf_func) (stream, "%ld", X_IMM (insn, 3));
19f7b010
JJ		 721 break;
722
252b5132
RH		 723 case 'K':
724 {
725 int mask = X_MEMBAR (insn);
726 int bit = 0x40, printed_one = 0;
727 const char *name;
728
729 if (mask == 0)
730 (info->fprintf_func) (stream, "0");
731 else
732 while (bit)
733 {
734 if (mask & bit)
735 {
736 if (printed_one)
737 (info->fprintf_func) (stream, "|");
738 name = sparc_decode_membar (bit);
739 (info->fprintf_func) (stream, "%s", name);
740 printed_one = 1;
741 }
742 bit >>= 1;
743 }
744 break;
745 }
746
2615994e
DM		 747 case '=':
748 info->target = memaddr + SEX (X_DISP10 (insn), 10) * 4;
749 (*info->print_address_func) (info->target, info);
750 break;
751
252b5132
RH		 752 case 'k':
753 info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4;
754 (*info->print_address_func) (info->target, info);
755 break;
756
757 case 'G':
758 info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4;
759 (*info->print_address_func) (info->target, info);
760 break;
761
762 case '6':
763 case '7':
764 case '8':
765 case '9':
766 (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0');
767 break;
768
769 case 'z':
770 (*info->fprintf_func) (stream, "%%icc");
771 break;
772
773 case 'Z':
774 (*info->fprintf_func) (stream, "%%xcc");
775 break;
776
777 case 'E':
778 (*info->fprintf_func) (stream, "%%ccr");
779 break;
780
781 case 's':
782 (*info->fprintf_func) (stream, "%%fprs");
783 break;
784
785 case 'o':
786 (*info->fprintf_func) (stream, "%%asi");
787 break;
47b0e7ad 788
252b5132
RH		 789 case 'W':
790 (*info->fprintf_func) (stream, "%%tick");
791 break;
792
793 case 'P':
794 (*info->fprintf_func) (stream, "%%pc");
795 break;
796
797 case '?':
798 if (X_RS1 (insn) == 31)
799 (*info->fprintf_func) (stream, "%%ver");
ff3f9d5b 800 else if ((unsigned) X_RS1 (insn) < 17)
252b5132
RH		 801 (*info->fprintf_func) (stream, "%%%s",
802 v9_priv_reg_names[X_RS1 (insn)]);
803 else
804 (*info->fprintf_func) (stream, "%%reserved");
805 break;
806
807 case '!':
ff3f9d5b 808 if ((unsigned) X_RD (insn) < 17)
252b5132
RH		 809 (*info->fprintf_func) (stream, "%%%s",
810 v9_priv_reg_names[X_RD (insn)]);
811 else
812 (*info->fprintf_func) (stream, "%%reserved");
813 break;
814
ff3f9d5b
DM		 815 case '$':
816 if ((unsigned) X_RS1 (insn) < 32)
817 (*info->fprintf_func) (stream, "%%%s",
818 v9_hpriv_reg_names[X_RS1 (insn)]);
819 else
820 (*info->fprintf_func) (stream, "%%reserved");
821 break;
822
823 case '%':
824 if ((unsigned) X_RD (insn) < 32)
825 (*info->fprintf_func) (stream, "%%%s",
826 v9_hpriv_reg_names[X_RD (insn)]);
827 else
828 (*info->fprintf_func) (stream, "%%reserved");
829 break;
830
252b5132 831 case '/':
ea783ef3 832 if (X_RS1 (insn) < 16 || X_RS1 (insn) > 28)
252b5132
RH		 833 (*info->fprintf_func) (stream, "%%reserved");
834 else
835 (*info->fprintf_func) (stream, "%%%s",
836 v9a_asr_reg_names[X_RS1 (insn)-16]);
837 break;
838
839 case '_':
ea783ef3 840 if (X_RD (insn) < 16 || X_RD (insn) > 28)
252b5132
RH		 841 (*info->fprintf_func) (stream, "%%reserved");
842 else
843 (*info->fprintf_func) (stream, "%%%s",
844 v9a_asr_reg_names[X_RD (insn)-16]);
845 break;
846
847 case '*':
848 {
849 const char *name = sparc_decode_prefetch (X_RD (insn));
850
851 if (name)
852 (*info->fprintf_func) (stream, "%s", name);
853 else
0fd3a477 854 (*info->fprintf_func) (stream, "%ld", X_RD (insn));
252b5132
RH		 855 break;
856 }
47b0e7ad 857
252b5132 858 case 'M':
0fd3a477 859 (*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn));
252b5132 860 break;
47b0e7ad 861
252b5132 862 case 'm':
0fd3a477 863 (*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn));
252b5132 864 break;
47b0e7ad 865
252b5132
RH		 866 case 'L':
867 info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4;
868 (*info->print_address_func) (info->target, info);
869 break;
870
871 case 'n':
872 (*info->fprintf_func)
873 (stream, "%#x", SEX (X_DISP22 (insn), 22));
874 break;
875
876 case 'l':
877 info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4;
878 (*info->print_address_func) (info->target, info);
879 break;
880
881 case 'A':
882 {
883 const char *name = sparc_decode_asi (X_ASI (insn));
884
885 if (name)
886 (*info->fprintf_func) (stream, "%s", name);
887 else
0fd3a477 888 (*info->fprintf_func) (stream, "(%ld)", X_ASI (insn));
252b5132
RH		 889 break;
890 }
891
892 case 'C':
893 (*info->fprintf_func) (stream, "%%csr");
894 break;
895
896 case 'F':
897 (*info->fprintf_func) (stream, "%%fsr");
898 break;
899
ea783ef3
DM		 900 case '(':
901 (*info->fprintf_func) (stream, "%%efsr");
902 break;
903
252b5132
RH		 904 case 'p':
905 (*info->fprintf_func) (stream, "%%psr");
906 break;
907
908 case 'q':
909 (*info->fprintf_func) (stream, "%%fq");
910 break;
911
912 case 'Q':
913 (*info->fprintf_func) (stream, "%%cq");
914 break;
915
916 case 't':
917 (*info->fprintf_func) (stream, "%%tbr");
918 break;
919
920 case 'w':
921 (*info->fprintf_func) (stream, "%%wim");
922 break;
923
924 case 'x':
0fd3a477 925 (*info->fprintf_func) (stream, "%ld",
252b5132
RH		 926 ((X_LDST_I (insn) << 8)
927 + X_ASI (insn)));
928 break;
929
930 case 'y':
931 (*info->fprintf_func) (stream, "%%y");
932 break;
933
934 case 'u':
935 case 'U':
936 {
937 int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn);
938 const char *name = sparc_decode_sparclet_cpreg (val);
939
940 if (name)
941 (*info->fprintf_func) (stream, "%s", name);
942 else
943 (*info->fprintf_func) (stream, "%%cpreg(%d)", val);
944 break;
945 }
946 }
947 }
948 }
949
950 /* If we are adding or or'ing something to rs1, then
951 check to see whether the previous instruction was
952 a sethi to the same register as in the sethi.
953 If so, attempt to print the result of the add or
954 or (in this context add and or do the same thing)
955 and its symbolic value. */
9df31319 956 if (imm_ored_to_rs1 || imm_added_to_rs1)
252b5132
RH		 957 {
958 unsigned long prev_insn;
959 int errcode;
960
0f6ab988
NC		 961 if (memaddr >= 4)
962 errcode =
963 (*info->read_memory_func)
252b5132 964 (memaddr - 4, buffer, sizeof (buffer), info);
0f6ab988
NC		 965 else
966 errcode = 1;
967
252b5132
RH		 968 prev_insn = getword (buffer);
969
970 if (errcode == 0)
971 {
972 /* If it is a delayed branch, we need to look at the
973 instruction before the delayed branch. This handles
0f6ab988 974 sequences such as:
252b5132
RH		 975
976 sethi %o1, %hi(_foo), %o1
977 call _printf
0f6ab988 978 or %o1, %lo(_foo), %o1 */
252b5132
RH		 979
980 if (is_delayed_branch (prev_insn))
981 {
0f6ab988
NC		 982 if (memaddr >= 8)
983 errcode = (*info->read_memory_func)
984 (memaddr - 8, buffer, sizeof (buffer), info);
985 else
986 errcode = 1;
987
252b5132
RH		 988 prev_insn = getword (buffer);
989 }
990 }
991
992 /* If there was a problem reading memory, then assume
993 the previous instruction was not sethi. */
994 if (errcode == 0)
995 {
996 /* Is it sethi to the same register? */
997 if ((prev_insn & 0xc1c00000) == 0x01000000
998 && X_RD (prev_insn) == X_RS1 (insn))
999 {
1000 (*info->fprintf_func) (stream, "\t! ");
47b0e7ad 1001 info->target =
56930d37
AO		 1002 ((unsigned) 0xFFFFFFFF
1003 & ((int) X_IMM22 (prev_insn) << 10));
9df31319
RH		 1004 if (imm_added_to_rs1)
1005 info->target += X_SIMM (insn, 13);
1006 else
1007 info->target |= X_SIMM (insn, 13);
252b5132
RH		 1008 (*info->print_address_func) (info->target, info);
1009 info->insn_type = dis_dref;
1010 info->data_size = 4; /* FIXME!!! */
1011 }
1012 }
1013 }
1014
1015 if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
1016 {
c7e2358a
AM		 1017 /* FIXME -- check is_annulled flag. */
1018 (void) is_annulled;
252b5132
RH		 1019 if (opcode->flags & F_UNBR)
1020 info->insn_type = dis_branch;
1021 if (opcode->flags & F_CONDBR)
1022 info->insn_type = dis_condbranch;
1023 if (opcode->flags & F_JSR)
1024 info->insn_type = dis_jsr;
1025 if (opcode->flags & F_DELAYED)
1026 info->branch_delay_insns = 1;
1027 }
1028
1029 return sizeof (buffer);
1030 }
1031 }
1032
0f6ab988 1033 info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */
252b5132
RH		 1034 (*info->fprintf_func) (stream, _("unknown"));
1035 return sizeof (buffer);
1036}
GDB Binutils - Deliverables
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