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* sparc.h (ELF64_R_TYPE_DATA): Sign extend the value.
[deliverable/binutils-gdb.git] / opcodes / sparc-dis.c
CommitLineData
252b5132
RH		 1/* Print SPARC instructions.
2 Copyright (C) 1989, 91-97, 1998 Free Software Foundation, Inc.
3
4This program is free software; you can redistribute it and/or modify
5it under the terms of the GNU General Public License as published by
6the Free Software Foundation; either version 2 of the License, or
7(at your option) any later version.
8
9This program is distributed in the hope that it will be useful,
10but WITHOUT ANY WARRANTY; without even the implied warranty of
11MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12GNU General Public License for more details.
13
14You should have received a copy of the GNU General Public License
15along with this program; if not, write to the Free Software
16Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
17
18#include <stdio.h>
19
20#include "ansidecl.h"
21#include "sysdep.h"
22#include "opcode/sparc.h"
23#include "dis-asm.h"
24#include "libiberty.h"
25#include "opintl.h"
26
27/* Bitmask of v9 architectures. */
28#define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
29 | (1 << SPARC_OPCODE_ARCH_V9A))
30/* 1 if INSN is for v9 only. */
31#define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
32/* 1 if INSN is for v9. */
33#define V9_P(insn) (((insn)->architecture & MASK_V9) != 0)
34
35/* The sorted opcode table. */
36static const struct sparc_opcode **sorted_opcodes;
37
38/* For faster lookup, after insns are sorted they are hashed. */
39/* ??? I think there is room for even more improvement. */
40
41#define HASH_SIZE 256
42/* It is important that we only look at insn code bits as that is how the
43 opcode table is hashed. OPCODE_BITS is a table of valid bits for each
44 of the main types (0,1,2,3). */
45static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
46#define HASH_INSN(INSN) \
47 ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
48struct opcode_hash {
49 struct opcode_hash *next;
50 const struct sparc_opcode *opcode;
51};
52static struct opcode_hash *opcode_hash_table[HASH_SIZE];
53
54static void build_hash_table
55 PARAMS ((const struct sparc_opcode **, struct opcode_hash **, int));
56static int is_delayed_branch PARAMS ((unsigned long));
57static int compare_opcodes PARAMS ((const PTR, const PTR));
58static int compute_arch_mask PARAMS ((unsigned long));
59
60/* Sign-extend a value which is N bits long. */
61#define SEX(value, bits) \
62 ((((int)(value)) << ((8 * sizeof (int)) - bits)) \
63 >> ((8 * sizeof (int)) - bits) )
64
65static char *reg_names[] =
66{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
67 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
68 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
69 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
70 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
71 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
72 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
73 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
74 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
75 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
76 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
77 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
78/* psr, wim, tbr, fpsr, cpsr are v8 only. */
79 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
80};
81
82#define freg_names (&reg_names[4 * 8])
83
84/* These are ordered according to there register number in
85 rdpr and wrpr insns. */
86static char *v9_priv_reg_names[] =
87{
88 "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
89 "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
90 "wstate", "fq"
91 /* "ver" - special cased */
92};
93
94/* These are ordered according to there register number in
95 rd and wr insns (-16). */
96static char *v9a_asr_reg_names[] =
97{
98 "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
99 "softint", "tick_cmpr"
100};
101
102/* Macros used to extract instruction fields. Not all fields have
103 macros defined here, only those which are actually used. */
104
105#define X_RD(i) (((i) >> 25) & 0x1f)
106#define X_RS1(i) (((i) >> 14) & 0x1f)
107#define X_LDST_I(i) (((i) >> 13) & 1)
108#define X_ASI(i) (((i) >> 5) & 0xff)
109#define X_RS2(i) (((i) >> 0) & 0x1f)
110#define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1))
111#define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n))
112#define X_DISP22(i) (((i) >> 0) & 0x3fffff)
113#define X_IMM22(i) X_DISP22 (i)
114#define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
115
116/* These are for v9. */
117#define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
118#define X_DISP19(i) (((i) >> 0) & 0x7ffff)
119#define X_MEMBAR(i) ((i) & 0x7f)
120
121/* Here is the union which was used to extract instruction fields
122 before the shift and mask macros were written.
123
124 union sparc_insn
125 {
126 unsigned long int code;
127 struct
128 {
129 unsigned int anop:2;
130 #define op ldst.anop
131 unsigned int anrd:5;
132 #define rd ldst.anrd
133 unsigned int op3:6;
134 unsigned int anrs1:5;
135 #define rs1 ldst.anrs1
136 unsigned int i:1;
137 unsigned int anasi:8;
138 #define asi ldst.anasi
139 unsigned int anrs2:5;
140 #define rs2 ldst.anrs2
141 #define shcnt rs2
142 } ldst;
143 struct
144 {
145 unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
146 unsigned int IMM13:13;
147 #define imm13 IMM13.IMM13
148 } IMM13;
149 struct
150 {
151 unsigned int anop:2;
152 unsigned int a:1;
153 unsigned int cond:4;
154 unsigned int op2:3;
155 unsigned int DISP22:22;
156 #define disp22 branch.DISP22
157 #define imm22 disp22
158 } branch;
159 struct
160 {
161 unsigned int anop:2;
162 unsigned int a:1;
163 unsigned int z:1;
164 unsigned int rcond:3;
165 unsigned int op2:3;
166 unsigned int DISP16HI:2;
167 unsigned int p:1;
168 unsigned int _rs1:5;
169 unsigned int DISP16LO:14;
170 } branch16;
171 struct
172 {
173 unsigned int anop:2;
174 unsigned int adisp30:30;
175 #define disp30 call.adisp30
176 } call;
177 };
178
179 */
180
181/* Nonzero if INSN is the opcode for a delayed branch. */
182static int
183is_delayed_branch (insn)
184 unsigned long insn;
185{
186 struct opcode_hash *op;
187
188 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
189 {
190 CONST struct sparc_opcode *opcode = op->opcode;
191 if ((opcode->match & insn) == opcode->match
192 && (opcode->lose & insn) == 0)
193 return (opcode->flags & F_DELAYED);
194 }
195 return 0;
196}
197
198/* extern void qsort (); */
199
200/* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value
201 to compare_opcodes. */
202static unsigned int current_arch_mask;
203
204/* Print one instruction from MEMADDR on INFO->STREAM.
205
206 We suffix the instruction with a comment that gives the absolute
207 address involved, as well as its symbolic form, if the instruction
208 is preceded by a findable `sethi' and it either adds an immediate
209 displacement to that register, or it is an `add' or `or' instruction
210 on that register. */
211
212int
213print_insn_sparc (memaddr, info)
214 bfd_vma memaddr;
215 disassemble_info *info;
216{
217 FILE *stream = info->stream;
218 bfd_byte buffer[4];
219 unsigned long insn;
220 register struct opcode_hash *op;
221 /* Nonzero of opcode table has been initialized. */
222 static int opcodes_initialized = 0;
223 /* bfd mach number of last call. */
224 static unsigned long current_mach = 0;
225 bfd_vma (*getword) PARAMS ((const unsigned char *));
226
227 if (!opcodes_initialized
228 || info->mach != current_mach)
229 {
230 int i;
231
232 current_arch_mask = compute_arch_mask (info->mach);
233
234 if (!opcodes_initialized)
235 sorted_opcodes = (const struct sparc_opcode **)
236 xmalloc (sparc_num_opcodes * sizeof (struct sparc_opcode *));
237 /* Reset the sorted table so we can resort it. */
238 for (i = 0; i < sparc_num_opcodes; ++i)
239 sorted_opcodes[i] = &sparc_opcodes[i];
240 qsort ((char *) sorted_opcodes, sparc_num_opcodes,
241 sizeof (sorted_opcodes[0]), compare_opcodes);
242
243 build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes);
244 current_mach = info->mach;
245 opcodes_initialized = 1;
246 }
247
248 {
249 int status =
250 (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
251 if (status != 0)
252 {
253 (*info->memory_error_func) (status, memaddr, info);
254 return -1;
255 }
256 }
257
258 /* On SPARClite variants such as DANlite (sparc86x), instructions
259 are always big-endian even when the machine is in little-endian mode. */
260 if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite)
261 getword = bfd_getb32;
262 else
263 getword = bfd_getl32;
264
265 insn = getword (buffer);
266
267 info->insn_info_valid = 1; /* We do return this info */
268 info->insn_type = dis_nonbranch; /* Assume non branch insn */
269 info->branch_delay_insns = 0; /* Assume no delay */
270 info->target = 0; /* Assume no target known */
271
272 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
273 {
274 CONST struct sparc_opcode *opcode = op->opcode;
275
276 /* If the insn isn't supported by the current architecture, skip it. */
277 if (! (opcode->architecture & current_arch_mask))
278 continue;
279
280 if ((opcode->match & insn) == opcode->match
281 && (opcode->lose & insn) == 0)
282 {
283 /* Nonzero means that we have found an instruction which has
284 the effect of adding or or'ing the imm13 field to rs1. */
285 int imm_added_to_rs1 = 0;
286
287 /* Nonzero means that we have found a plus sign in the args
288 field of the opcode table. */
289 int found_plus = 0;
290
291 /* Nonzero means we have an annulled branch. */
292 int is_annulled = 0;
293
294 /* Do we have an `add' or `or' instruction combining an
295 immediate with rs1? */
296 if (opcode->match == 0x80102000 || opcode->match == 0x80002000)
297 /* (or) (add) */
298 imm_added_to_rs1 = 1;
299
300 if (X_RS1 (insn) != X_RD (insn)
301 && strchr (opcode->args, 'r') != 0)
302 /* Can't do simple format if source and dest are different. */
303 continue;
304 if (X_RS2 (insn) != X_RD (insn)
305 && strchr (opcode->args, 'O') != 0)
306 /* Can't do simple format if source and dest are different. */
307 continue;
308
309 (*info->fprintf_func) (stream, opcode->name);
310
311 {
312 register CONST char *s;
313
314 if (opcode->args[0] != ',')
315 (*info->fprintf_func) (stream, " ");
316 for (s = opcode->args; *s != '\0'; ++s)
317 {
318 while (*s == ',')
319 {
320 (*info->fprintf_func) (stream, ",");
321 ++s;
322 switch (*s) {
323 case 'a':
324 (*info->fprintf_func) (stream, "a");
325 is_annulled = 1;
326 ++s;
327 continue;
328 case 'N':
329 (*info->fprintf_func) (stream, "pn");
330 ++s;
331 continue;
332
333 case 'T':
334 (*info->fprintf_func) (stream, "pt");
335 ++s;
336 continue;
337
338 default:
339 break;
340 } /* switch on arg */
341 } /* while there are comma started args */
342
343 (*info->fprintf_func) (stream, " ");
344
345 switch (*s)
346 {
347 case '+':
348 found_plus = 1;
349
350 /* note fall-through */
351 default:
352 (*info->fprintf_func) (stream, "%c", *s);
353 break;
354
355 case '#':
356 (*info->fprintf_func) (stream, "0");
357 break;
358
359#define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n])
360 case '1':
361 case 'r':
362 reg (X_RS1 (insn));
363 break;
364
365 case '2':
366 case 'O':
367 reg (X_RS2 (insn));
368 break;
369
370 case 'd':
371 reg (X_RD (insn));
372 break;
373#undef reg
374
375#define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n])
376#define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)])
377 case 'e':
378 freg (X_RS1 (insn));
379 break;
380 case 'v': /* double/even */
381 case 'V': /* quad/multiple of 4 */
382 fregx (X_RS1 (insn));
383 break;
384
385 case 'f':
386 freg (X_RS2 (insn));
387 break;
388 case 'B': /* double/even */
389 case 'R': /* quad/multiple of 4 */
390 fregx (X_RS2 (insn));
391 break;
392
393 case 'g':
394 freg (X_RD (insn));
395 break;
396 case 'H': /* double/even */
397 case 'J': /* quad/multiple of 4 */
398 fregx (X_RD (insn));
399 break;
400#undef freg
401#undef fregx
402
403#define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n))
404 case 'b':
405 creg (X_RS1 (insn));
406 break;
407
408 case 'c':
409 creg (X_RS2 (insn));
410 break;
411
412 case 'D':
413 creg (X_RD (insn));
414 break;
415#undef creg
416
417 case 'h':
418 (*info->fprintf_func) (stream, "%%hi(%#x)",
419 (0xFFFFFFFF
420 & ((int) X_IMM22 (insn) << 10)));
421 break;
422
423 case 'i': /* 13 bit immediate */
424 case 'I': /* 11 bit immediate */
425 case 'j': /* 10 bit immediate */
426 {
427 int imm;
428
429 if (*s == 'i')
430 imm = X_SIMM (insn, 13);
431 else if (*s == 'I')
432 imm = X_SIMM (insn, 11);
433 else
434 imm = X_SIMM (insn, 10);
435
436 /* Check to see whether we have a 1+i, and take
437 note of that fact.
438
439 Note: because of the way we sort the table,
440 we will be matching 1+i rather than i+1,
441 so it is OK to assume that i is after +,
442 not before it. */
443 if (found_plus)
444 imm_added_to_rs1 = 1;
445
446 if (imm <= 9)
447 (*info->fprintf_func) (stream, "%d", imm);
448 else
449 (*info->fprintf_func) (stream, "%#x", imm);
450 }
451 break;
452
453 case 'X': /* 5 bit unsigned immediate */
454 case 'Y': /* 6 bit unsigned immediate */
455 {
456 int imm = X_IMM (insn, *s == 'X' ? 5 : 6);
457
458 if (imm <= 9)
459 (info->fprintf_func) (stream, "%d", imm);
460 else
461 (info->fprintf_func) (stream, "%#x", (unsigned) imm);
462 }
463 break;
464
465 case 'K':
466 {
467 int mask = X_MEMBAR (insn);
468 int bit = 0x40, printed_one = 0;
469 const char *name;
470
471 if (mask == 0)
472 (info->fprintf_func) (stream, "0");
473 else
474 while (bit)
475 {
476 if (mask & bit)
477 {
478 if (printed_one)
479 (info->fprintf_func) (stream, "|");
480 name = sparc_decode_membar (bit);
481 (info->fprintf_func) (stream, "%s", name);
482 printed_one = 1;
483 }
484 bit >>= 1;
485 }
486 break;
487 }
488
489 case 'k':
490 info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4;
491 (*info->print_address_func) (info->target, info);
492 break;
493
494 case 'G':
495 info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4;
496 (*info->print_address_func) (info->target, info);
497 break;
498
499 case '6':
500 case '7':
501 case '8':
502 case '9':
503 (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0');
504 break;
505
506 case 'z':
507 (*info->fprintf_func) (stream, "%%icc");
508 break;
509
510 case 'Z':
511 (*info->fprintf_func) (stream, "%%xcc");
512 break;
513
514 case 'E':
515 (*info->fprintf_func) (stream, "%%ccr");
516 break;
517
518 case 's':
519 (*info->fprintf_func) (stream, "%%fprs");
520 break;
521
522 case 'o':
523 (*info->fprintf_func) (stream, "%%asi");
524 break;
525
526 case 'W':
527 (*info->fprintf_func) (stream, "%%tick");
528 break;
529
530 case 'P':
531 (*info->fprintf_func) (stream, "%%pc");
532 break;
533
534 case '?':
535 if (X_RS1 (insn) == 31)
536 (*info->fprintf_func) (stream, "%%ver");
537 else if ((unsigned) X_RS1 (insn) < 16)
538 (*info->fprintf_func) (stream, "%%%s",
539 v9_priv_reg_names[X_RS1 (insn)]);
540 else
541 (*info->fprintf_func) (stream, "%%reserved");
542 break;
543
544 case '!':
545 if ((unsigned) X_RD (insn) < 15)
546 (*info->fprintf_func) (stream, "%%%s",
547 v9_priv_reg_names[X_RD (insn)]);
548 else
549 (*info->fprintf_func) (stream, "%%reserved");
550 break;
551
552 case '/':
553 if (X_RS1 (insn) < 16 || X_RS1 (insn) > 23)
554 (*info->fprintf_func) (stream, "%%reserved");
555 else
556 (*info->fprintf_func) (stream, "%%%s",
557 v9a_asr_reg_names[X_RS1 (insn)-16]);
558 break;
559
560 case '_':
561 if (X_RD (insn) < 16 || X_RD (insn) > 23)
562 (*info->fprintf_func) (stream, "%%reserved");
563 else
564 (*info->fprintf_func) (stream, "%%%s",
565 v9a_asr_reg_names[X_RD (insn)-16]);
566 break;
567
568 case '*':
569 {
570 const char *name = sparc_decode_prefetch (X_RD (insn));
571
572 if (name)
573 (*info->fprintf_func) (stream, "%s", name);
574 else
575 (*info->fprintf_func) (stream, "%d", X_RD (insn));
576 break;
577 }
578
579 case 'M':
580 (*info->fprintf_func) (stream, "%%asr%d", X_RS1 (insn));
581 break;
582
583 case 'm':
584 (*info->fprintf_func) (stream, "%%asr%d", X_RD (insn));
585 break;
586
587 case 'L':
588 info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4;
589 (*info->print_address_func) (info->target, info);
590 break;
591
592 case 'n':
593 (*info->fprintf_func)
594 (stream, "%#x", SEX (X_DISP22 (insn), 22));
595 break;
596
597 case 'l':
598 info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4;
599 (*info->print_address_func) (info->target, info);
600 break;
601
602 case 'A':
603 {
604 const char *name = sparc_decode_asi (X_ASI (insn));
605
606 if (name)
607 (*info->fprintf_func) (stream, "%s", name);
608 else
609 (*info->fprintf_func) (stream, "(%d)", X_ASI (insn));
610 break;
611 }
612
613 case 'C':
614 (*info->fprintf_func) (stream, "%%csr");
615 break;
616
617 case 'F':
618 (*info->fprintf_func) (stream, "%%fsr");
619 break;
620
621 case 'p':
622 (*info->fprintf_func) (stream, "%%psr");
623 break;
624
625 case 'q':
626 (*info->fprintf_func) (stream, "%%fq");
627 break;
628
629 case 'Q':
630 (*info->fprintf_func) (stream, "%%cq");
631 break;
632
633 case 't':
634 (*info->fprintf_func) (stream, "%%tbr");
635 break;
636
637 case 'w':
638 (*info->fprintf_func) (stream, "%%wim");
639 break;
640
641 case 'x':
642 (*info->fprintf_func) (stream, "%d",
643 ((X_LDST_I (insn) << 8)
644 + X_ASI (insn)));
645 break;
646
647 case 'y':
648 (*info->fprintf_func) (stream, "%%y");
649 break;
650
651 case 'u':
652 case 'U':
653 {
654 int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn);
655 const char *name = sparc_decode_sparclet_cpreg (val);
656
657 if (name)
658 (*info->fprintf_func) (stream, "%s", name);
659 else
660 (*info->fprintf_func) (stream, "%%cpreg(%d)", val);
661 break;
662 }
663 }
664 }
665 }
666
667 /* If we are adding or or'ing something to rs1, then
668 check to see whether the previous instruction was
669 a sethi to the same register as in the sethi.
670 If so, attempt to print the result of the add or
671 or (in this context add and or do the same thing)
672 and its symbolic value. */
673 if (imm_added_to_rs1)
674 {
675 unsigned long prev_insn;
676 int errcode;
677
678 errcode =
679 (*info->read_memory_func)
680 (memaddr - 4, buffer, sizeof (buffer), info);
681 prev_insn = getword (buffer);
682
683 if (errcode == 0)
684 {
685 /* If it is a delayed branch, we need to look at the
686 instruction before the delayed branch. This handles
687 sequences such as
688
689 sethi %o1, %hi(_foo), %o1
690 call _printf
691 or %o1, %lo(_foo), %o1
692 */
693
694 if (is_delayed_branch (prev_insn))
695 {
696 errcode = (*info->read_memory_func)
697 (memaddr - 8, buffer, sizeof (buffer), info);
698 prev_insn = getword (buffer);
699 }
700 }
701
702 /* If there was a problem reading memory, then assume
703 the previous instruction was not sethi. */
704 if (errcode == 0)
705 {
706 /* Is it sethi to the same register? */
707 if ((prev_insn & 0xc1c00000) == 0x01000000
708 && X_RD (prev_insn) == X_RS1 (insn))
709 {
710 (*info->fprintf_func) (stream, "\t! ");
711 info->target =
712 (0xFFFFFFFF & (int) X_IMM22 (prev_insn) << 10)
713 | X_SIMM (insn, 13);
714 (*info->print_address_func) (info->target, info);
715 info->insn_type = dis_dref;
716 info->data_size = 4; /* FIXME!!! */
717 }
718 }
719 }
720
721 if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
722 {
723 /* FIXME -- check is_annulled flag */
724 if (opcode->flags & F_UNBR)
725 info->insn_type = dis_branch;
726 if (opcode->flags & F_CONDBR)
727 info->insn_type = dis_condbranch;
728 if (opcode->flags & F_JSR)
729 info->insn_type = dis_jsr;
730 if (opcode->flags & F_DELAYED)
731 info->branch_delay_insns = 1;
732 }
733
734 return sizeof (buffer);
735 }
736 }
737
738 info->insn_type = dis_noninsn; /* Mark as non-valid instruction */
739 (*info->fprintf_func) (stream, _("unknown"));
740 return sizeof (buffer);
741}
742
743/* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */
744
745static int
746compute_arch_mask (mach)
747 unsigned long mach;
748{
749 switch (mach)
750 {
751 case 0 :
752 case bfd_mach_sparc :
753 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8);
754 case bfd_mach_sparc_sparclet :
755 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
756 case bfd_mach_sparc_sparclite :
757 case bfd_mach_sparc_sparclite_le :
758 /* sparclites insns are recognized by default (because that's how
759 they've always been treated, for better or worse). Kludge this by
760 indicating generic v8 is also selected. */
761 return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
762 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8));
763 case bfd_mach_sparc_v8plus :
764 case bfd_mach_sparc_v9 :
765 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
766 case bfd_mach_sparc_v8plusa :
767 case bfd_mach_sparc_v9a :
768 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
769 }
770 abort ();
771}
772
773/* Compare opcodes A and B. */
774
775static int
776compare_opcodes (a, b)
777 const PTR a;
778 const PTR b;
779{
780 struct sparc_opcode *op0 = * (struct sparc_opcode **) a;
781 struct sparc_opcode *op1 = * (struct sparc_opcode **) b;
782 unsigned long int match0 = op0->match, match1 = op1->match;
783 unsigned long int lose0 = op0->lose, lose1 = op1->lose;
784 register unsigned int i;
785
786 /* If one (and only one) insn isn't supported by the current architecture,
787 prefer the one that is. If neither are supported, but they're both for
788 the same architecture, continue processing. Otherwise (both unsupported
789 and for different architectures), prefer lower numbered arch's (fudged
790 by comparing the bitmasks). */
791 if (op0->architecture & current_arch_mask)
792 {
793 if (! (op1->architecture & current_arch_mask))
794 return -1;
795 }
796 else
797 {
798 if (op1->architecture & current_arch_mask)
799 return 1;
800 else if (op0->architecture != op1->architecture)
801 return op0->architecture - op1->architecture;
802 }
803
804 /* If a bit is set in both match and lose, there is something
805 wrong with the opcode table. */
806 if (match0 & lose0)
807 {
808 fprintf
809 (stderr,
810 /* xgettext:c-format */
811 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
812 op0->name, match0, lose0);
813 op0->lose &= ~op0->match;
814 lose0 = op0->lose;
815 }
816
817 if (match1 & lose1)
818 {
819 fprintf
820 (stderr,
821 /* xgettext:c-format */
822 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
823 op1->name, match1, lose1);
824 op1->lose &= ~op1->match;
825 lose1 = op1->lose;
826 }
827
828 /* Because the bits that are variable in one opcode are constant in
829 another, it is important to order the opcodes in the right order. */
830 for (i = 0; i < 32; ++i)
831 {
832 unsigned long int x = 1 << i;
833 int x0 = (match0 & x) != 0;
834 int x1 = (match1 & x) != 0;
835
836 if (x0 != x1)
837 return x1 - x0;
838 }
839
840 for (i = 0; i < 32; ++i)
841 {
842 unsigned long int x = 1 << i;
843 int x0 = (lose0 & x) != 0;
844 int x1 = (lose1 & x) != 0;
845
846 if (x0 != x1)
847 return x1 - x0;
848 }
849
850 /* They are functionally equal. So as long as the opcode table is
851 valid, we can put whichever one first we want, on aesthetic grounds. */
852
853 /* Our first aesthetic ground is that aliases defer to real insns. */
854 {
855 int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
856 if (alias_diff != 0)
857 /* Put the one that isn't an alias first. */
858 return alias_diff;
859 }
860
861 /* Except for aliases, two "identical" instructions had
862 better have the same opcode. This is a sanity check on the table. */
863 i = strcmp (op0->name, op1->name);
864 if (i)
865 {
866 if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */
867 return i;
868 else
869 fprintf (stderr,
870 /* xgettext:c-format */
871 _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
872 op0->name, op1->name);
873 }
874
875 /* Fewer arguments are preferred. */
876 {
877 int length_diff = strlen (op0->args) - strlen (op1->args);
878 if (length_diff != 0)
879 /* Put the one with fewer arguments first. */
880 return length_diff;
881 }
882
883 /* Put 1+i before i+1. */
884 {
885 char *p0 = (char *) strchr (op0->args, '+');
886 char *p1 = (char *) strchr (op1->args, '+');
887
888 if (p0 && p1)
889 {
890 /* There is a plus in both operands. Note that a plus
891 sign cannot be the first character in args,
892 so the following [-1]'s are valid. */
893 if (p0[-1] == 'i' && p1[1] == 'i')
894 /* op0 is i+1 and op1 is 1+i, so op1 goes first. */
895 return 1;
896 if (p0[1] == 'i' && p1[-1] == 'i')
897 /* op0 is 1+i and op1 is i+1, so op0 goes first. */
898 return -1;
899 }
900 }
901
902 /* Put 1,i before i,1. */
903 {
904 int i0 = strncmp (op0->args, "i,1", 3) == 0;
905 int i1 = strncmp (op1->args, "i,1", 3) == 0;
906
907 if (i0 ^ i1)
908 return i0 - i1;
909 }
910
911 /* They are, as far as we can tell, identical.
912 Since qsort may have rearranged the table partially, there is
913 no way to tell which one was first in the opcode table as
914 written, so just say there are equal. */
915 /* ??? This is no longer true now that we sort a vector of pointers,
916 not the table itself. */
917 return 0;
918}
919
920/* Build a hash table from the opcode table.
921 OPCODE_TABLE is a sorted list of pointers into the opcode table. */
922
923static void
924build_hash_table (opcode_table, hash_table, num_opcodes)
925 const struct sparc_opcode **opcode_table;
926 struct opcode_hash **hash_table;
927 int num_opcodes;
928{
929 register int i;
930 int hash_count[HASH_SIZE];
931 static struct opcode_hash *hash_buf = NULL;
932
933 /* Start at the end of the table and work backwards so that each
934 chain is sorted. */
935
936 memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
937 memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
938 if (hash_buf != NULL)
939 free (hash_buf);
940 hash_buf = (struct opcode_hash *) xmalloc (sizeof (struct opcode_hash) * num_opcodes);
941 for (i = num_opcodes - 1; i >= 0; --i)
942 {
943 register int hash = HASH_INSN (opcode_table[i]->match);
944 register struct opcode_hash *h = &hash_buf[i];
945 h->next = hash_table[hash];
946 h->opcode = opcode_table[i];
947 hash_table[hash] = h;
948 ++hash_count[hash];
949 }
950
951#if 0 /* for debugging */
952 {
953 int min_count = num_opcodes, max_count = 0;
954 int total;
955
956 for (i = 0; i < HASH_SIZE; ++i)
957 {
958 if (hash_count[i] < min_count)
959 min_count = hash_count[i];
960 if (hash_count[i] > max_count)
961 max_count = hash_count[i];
962 total += hash_count[i];
963 }
964
965 printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
966 min_count, max_count, (double) total / HASH_SIZE);
967 }
968#endif
969}
GDB Binutils - Deliverables
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