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f6c1a2d5 | 1 | /* mc9xgate-opc.c -- Freescale XGATE opcode list |
b3adc24a | 2 | Copyright (C) 1999-2020 Free Software Foundation, Inc. |
f6c1a2d5 NC |
3 | Written by Sean Keys (skeys@ipdatasys.com) |
4 | ||
5 | This file is part of the GNU opcodes library. | |
6 | ||
7 | This library is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3, or (at your option) | |
10 | any later version. | |
11 | ||
12 | It is distributed in the hope that it will be useful, but WITHOUT | |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this file; see the file COPYING. If not, write to the | |
19 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
20 | MA 02110-1301, USA. | |
21 | */ | |
22 | ||
23 | #include <stdio.h> | |
24 | #include "ansidecl.h" | |
25 | #include "opcode/xgate.h" | |
26 | ||
27 | #define TABLE_SIZE(X) (sizeof(X) / sizeof(X[0])) | |
28 | ||
29 | /* Combination of CCR flags. */ | |
30 | /* ORDER HI TO LOW NZVC */ | |
31 | #define XGATE_NZ_BIT XGATE_N_BIT|XGATE_Z_BIT | |
32 | #define XGATE_NV_BIT XGATE_N_BIT|XGATE_V_BIT | |
33 | #define XGATE_NC_BIT XGATE_N_BIT|XGATE_C_BIT | |
34 | #define XGATE_ZV_BIT XGATE_Z_BIT|XGATE_V_BIT | |
35 | #define XGATE_ZC_BIT XGATE_Z_BIT|XGATE_C_BIT | |
36 | #define XGATE_VC_BIT XGATE_V_BIT|XGATE_C_BIT | |
37 | #define XGATE_NVC_BIT XGATE_NV_BIT|XGATE_C_BIT | |
38 | #define XGATE_NZC_BIT XGATE_NZ_BIT|XGATE_C_BIT | |
39 | #define XGATE_NZV_BIT XGATE_N_BIT|XGATE_Z_BIT|XGATE_V_BIT | |
40 | #define XGATE_ZVC_BIT XGATE_VC_BIT|XGATE_Z_BIT | |
41 | #define XGATE_NZVC_BIT XGATE_NZV_BIT|XGATE_C_BIT | |
42 | ||
43 | /* Flags when the insn only changes some CCR flags. */ | |
44 | #define CHG_NONE 0,0,0 | |
45 | #define CHG_Z 0,0,XGATE_Z_BIT | |
46 | #define CHG_C 0,0,XGATE_C_BIT | |
47 | #define CHG_ZVC 0,0,XGATE_ZVC_BIT | |
48 | #define CHG_NZC 0,0,XGATE_NZC_BIT | |
49 | #define CHG_NZV 0,0,XGATE_NZV_BIT | |
50 | #define CHG_NZVC 0,0,(XGATE_NZVC_BIT) | |
51 | #define CHG_HNZVC 0,0,XGATE_HNZVC_BIT // TODO DELETE | |
52 | #define CHG_ALL 0,0,0xff | |
53 | ||
54 | /* The insn clears and changes some flags. */ | |
55 | #define CLR_I 0,XG_I_BIT,0 | |
56 | #define CLR_C 0,XGATE_C_BIT,0 | |
57 | #define CLR_V 0,XGATE_V_BIT,0 | |
58 | #define CLR_V_CHG_ZC 0,XGATE_V_BIT,XGATE_ZC_BIT | |
59 | #define CLR_V_CHG_NZ 0,XGATE_V_BIT,XGATE_NZ_BIT | |
60 | #define CLR_V_CHG_ZVC 0,XGATE_V_BIT,XGATE_ZVC_BIT | |
61 | #define CLR_N_CHG_ZVC 0,XGATE_N_BIT,XGATE_ZVC_BIT /* Used by lsr */ | |
62 | #define CLR_VC_CHG_NZ 0,XGATE_VC_BIT,XGATE_NZ_BIT | |
63 | ||
64 | /* The insn sets some flags. */ | |
65 | #define SET_I XGATE_I_BIT,0,0 | |
66 | #define SET_C XGATE_C_BIT,0,0 | |
67 | #define SET_V XGATE_V_BIT,0,0 | |
68 | #define SET_Z_CLR_NVC XGATE_Z_BIT,XGATE_NVC_BIT,0 | |
69 | #define SET_C_CLR_V_CHG_NZ XGATE_C_BIT,XGATE_V_BIT,XGATE_NZ_BIT | |
70 | #define SET_Z_CHG_HNVC XGATE_Z_BIT,0,XGATE_HNVC_BIT | |
71 | ||
72 | /* operand modes */ | |
73 | #define OP_NONE XGATE_OP_NONE | |
74 | #define OP_INH XGATE_OP_INH | |
75 | #define OP_TRI XGATE_OP_TRI | |
76 | #define OP_DYA XGATE_OP_DYA | |
f6c1a2d5 NC |
77 | #define OP_IMM3 XGATE_OP_IMM3 |
78 | #define OP_IMM4 XGATE_OP_IMM4 | |
79 | #define OP_IMM8 XGATE_OP_IMM8 | |
80 | #define OP_IMM16 XGATE_OP_IMM16 | |
81 | #define OP_MON XGATE_OP_MON | |
82 | #define OP_MON_R_C XGATE_OP_MON_R_C | |
83 | #define OP_MON_C_R XGATE_OP_MON_C_R | |
84 | #define OP_MON_R_P XGATE_OP_MON_R_P | |
85 | #define OP_IDR XGATE_OP_IDR | |
86 | #define OP_IDO5 XGATE_OP_IDO5 | |
87 | #define OP_REL9 XGATE_OP_REL9 | |
88 | #define OP_REL10 XGATE_OP_REL10 | |
0e1c2434 | 89 | #define OP_DM XGATE_OP_DYA_MON |
f6c1a2d5 NC |
90 | /* macro operand modes */ |
91 | #define OP_mADD XGATE_OP_IMM16mADD | |
92 | #define OP_mAND XGATE_OP_IMM16mAND | |
93 | #define OP_mCPC XGATE_OP_IMM16mCPC | |
94 | #define OP_mLDW XGATE_OP_IMM16mLDW | |
95 | #define OP_mSUB XGATE_OP_IMM16mSUB | |
96 | ||
97 | #define ALL XGATE_V1|XGATE_V2|XGATE_V3 | |
f6c1a2d5 NC |
98 | |
99 | const struct xgate_opcode xgate_opcodes[] = { | |
0e1c2434 SK |
100 | /* Name -+ +--- CPU |
101 | Constraints --+ +----------- CCR changes | |
102 | Format -------+ +---------------- Max # cycles | |
103 | +------------------- Min # cycles | |
104 | Size -------------------------------------+ +-------------------------- Opcode */ | |
105 | { "adc", OP_TRI, "00011rrrrrrrrr11", 2, 0x1803, 1, 1, CHG_NZVC, ALL}, | |
106 | { "add", OP_TRI, "00011rrrrrrrrr10", 2, 0x1802, 1, 1, CHG_NZVC, ALL}, | |
107 | { "addh", OP_IMM8, "11101rrriiiiiiii", 2, 0xE800, 1, 1, CHG_NZVC, ALL}, | |
108 | { "addl", OP_IMM8, "11100rrriiiiiiii", 2, 0xE000, 1, 1, CHG_NZVC, ALL}, | |
109 | { "and", OP_TRI, "00010rrrrrrrrr00", 2, 0x1000, 1, 1, CHG_NZV, ALL}, | |
110 | { "andh", OP_IMM8, "10001rrriiiiiiii", 2, 0x8800, 1, 1, CHG_NZV, ALL}, | |
111 | { "andl", OP_IMM8, "10000rrriiiiiiii", 2, 0x8000, 1, 1, CHG_NZV, ALL}, | |
112 | { "asr", OP_IMM4, "00001rrriiii1001", 2, 0x0809, 1, 1, CHG_NZVC, ALL}, | |
113 | { "asr", OP_DYA, "00001rrrrrr10001", 2, 0x0811, 1, 1, CHG_NZVC, ALL}, | |
114 | { "bcc", OP_REL9, "0010000iiiiiiiii", 2, 0x2000, 1, 2, CHG_NONE, ALL}, | |
115 | { "bcs", OP_REL9, "0010001iiiiiiiii", 2, 0x2200, 1, 2, CHG_NONE, ALL}, | |
116 | { "beq", OP_REL9, "0010011iiiiiiiii", 2, 0x2600, 1, 2, CHG_NONE, ALL}, | |
117 | { "bfext", OP_TRI, "01100rrrrrrrrr11", 2, 0x6003, 1, 1, CHG_NZV, ALL}, | |
118 | { "bffo", OP_DYA, "00001rrrrrr10000", 2, 0x0810, 1, 1, CHG_NZVC, ALL}, | |
119 | { "bfins", OP_TRI, "01101rrrrrrrrr11", 2, 0x6803, 1, 1, CHG_NZV, ALL}, | |
120 | {"bfinsi", OP_TRI, "01110rrrrrrrrr11", 2, 0x7003, 1, 1, CHG_NZV, ALL}, | |
121 | {"bfinsx", OP_TRI, "01111rrrrrrrrr11", 2, 0x7803, 1, 1, CHG_NZV, ALL}, | |
122 | { "bge", OP_REL9, "0011010iiiiiiiii", 2, 0x3400, 1, 2, CHG_NONE, ALL}, | |
123 | { "bgt", OP_REL9, "0011100iiiiiiiii", 2, 0x3800, 1, 2, CHG_NONE, ALL}, | |
124 | { "bhi", OP_REL9, "0011000iiiiiiiii", 2, 0x3000, 1, 2, CHG_NONE, ALL}, | |
125 | { "bith", OP_IMM8, "10011rrriiiiiiii", 2, 0x9800, 1, 1, CHG_NZV, ALL}, | |
126 | { "bitl", OP_IMM8, "10010rrriiiiiiii", 2, 0x9000, 1, 1, CHG_NZV, ALL}, | |
127 | { "ble", OP_REL9, "0011101iiiiiiiii", 2, 0x3A00, 1, 2, CHG_NONE, ALL}, | |
128 | { "bls", OP_REL9, "0011001iiiiiiiii", 2, 0x3200, 1, 2, CHG_NONE, ALL}, | |
129 | { "blt", OP_REL9, "0011011iiiiiiiii", 2, 0x3600, 1, 2, CHG_NONE, ALL}, | |
130 | { "bmi", OP_REL9, "0010101iiiiiiiii", 2, 0x2A00, 1, 2, CHG_NONE, ALL}, | |
131 | { "bne", OP_REL9, "0010010iiiiiiiii", 2, 0x2400, 1, 2, CHG_NONE, ALL}, | |
132 | { "bpl", OP_REL9, "0010100iiiiiiiii", 2, 0x2800, 1, 2, CHG_NONE, ALL}, | |
133 | { "bra", OP_REL10, "001111iiiiiiiiii", 2, 0x3C00, 2, 2, CHG_NONE, ALL}, | |
134 | { "brk", OP_INH, "0000000000000000", 2, 0x0000, 1, 1, CHG_NONE, ALL}, | |
135 | { "bvc", OP_REL9, "0010110iiiiiiiii", 2, 0x2C00, 1, 2, CHG_NONE, ALL}, | |
136 | { "bvs", OP_REL9, "0010111iiiiiiiii", 2, 0x2E00, 1, 2, CHG_NONE, ALL}, | |
137 | { "cmpl", OP_IMM8, "11010rrriiiiiiii", 2, 0xD000, 1, 1, CHG_NZVC, ALL}, | |
138 | { "cpch", OP_IMM8, "11011rrriiiiiiii", 2, 0xD800, 1, 1, CHG_NZVC, ALL}, | |
139 | { "csem", OP_IMM3, "00000iii11110000", 2, 0x00F0, 1, 1, CHG_NONE, ALL}, | |
140 | { "csem", OP_MON, "00000rrr11110001", 2, 0x00F1, 1, 1, CHG_NONE, ALL}, | |
141 | { "csl", OP_IMM4, "00001rrriiii1010", 2, 0x080A, 1, 1, CHG_NZVC, ALL}, | |
142 | { "csl", OP_DYA, "00001rrrrrr10010", 2, 0x0812, 1, 1, CHG_NZVC, ALL}, | |
143 | { "csr", OP_IMM4, "00001rrriiii1011", 2, 0x080B, 1, 1, CHG_NZVC, ALL}, | |
144 | { "csr", OP_DYA, "00001rrrrrr10011", 2, 0x0813, 1, 1, CHG_NZVC, ALL}, | |
145 | { "jal", OP_MON, "00000rrr11110110", 2, 0x00F6, 2, 2, CHG_NONE, ALL}, | |
146 | { "ldb", OP_IDO5, "01000rrrrrriiiii", 2, 0x4000, 2, 2, CHG_NONE, ALL}, | |
147 | { "ldb", OP_IDR, "01100rrrrrrrrrrr", 2, 0x6000, 2, 2, CHG_NONE, ALL}, | |
148 | { "ldh", OP_IMM8, "11111rrriiiiiiii", 2, 0xF800, 1, 1, CHG_NONE, ALL}, | |
149 | { "ldl", OP_IMM8, "11110rrriiiiiiii", 2, 0xF000, 1, 1, CHG_NONE, ALL}, | |
150 | { "ldw", OP_IDO5, "01001rrrrrriiiii", 2, 0x4800, 2, 2, CHG_NONE, ALL}, | |
151 | { "ldw", OP_IDR, "01101rrrrrrrrrrr", 2, 0x6800, 2, 2, CHG_NONE, ALL}, | |
152 | { "lsl", OP_IMM4, "00001rrriiii1100", 2, 0x080C, 1, 1, CHG_NZVC, ALL}, | |
153 | { "lsl", OP_DYA, "00001rrrrrr10100", 2, 0x0814, 1, 1, CHG_NZVC, ALL}, | |
154 | { "lsr", OP_IMM4, "00001rrriiii1101", 2, 0x080D, 1, 1, CHG_NZVC, ALL}, | |
155 | { "lsr", OP_DYA, "00001rrrrrr10101", 2, 0x0815, 1, 1, CHG_NZVC, ALL}, | |
156 | { "nop", OP_INH, "0000000100000000", 2, 0x0100, 1, 1, CHG_NONE, ALL}, | |
157 | { "or", OP_TRI, "00010rrrrrrrrr10", 2, 0x1002, 1, 1, CHG_NZV, ALL}, | |
158 | { "orh", OP_IMM8, "10101rrriiiiiiii", 2, 0xA800, 1, 1, CHG_NZV, ALL}, | |
159 | { "orl", OP_IMM8, "10100rrriiiiiiii", 2, 0xA000, 1, 1, CHG_NZV, ALL}, | |
160 | { "par", OP_MON, "00000rrr11110101", 2, 0x00F5, 1, 1, CHG_NZV, ALL}, | |
161 | { "rol", OP_IMM4, "00001rrriiii1110", 2, 0x080E, 1, 1, CHG_NZV, ALL}, | |
162 | { "rol", OP_DYA, "00001rrrrrr10110", 2, 0x0816, 1, 1, CHG_NZV, ALL}, | |
163 | { "ror", OP_IMM4, "00001rrriiii1111", 2, 0x080F, 1, 1, CHG_NZV, ALL}, | |
164 | { "ror", OP_DYA, "00001rrrrrr10111", 2, 0x0817, 1, 1, CHG_NZV, ALL}, | |
165 | { "rts", OP_INH, "0000001000000000", 2, 0x0200, 2, 2, CHG_NONE, ALL}, | |
166 | { "sbc", OP_TRI, "00011rrrrrrrrr01", 2, 0x1801, 1, 1, CHG_NZV, ALL}, | |
167 | { "ssem", OP_IMM3, "00000iii11110010", 2, 0x00F2, 2, 2, CHG_C, ALL}, | |
168 | { "ssem", OP_MON, "00000rrr11110011", 2, 0x00F3, 2, 2, CHG_C, ALL}, | |
169 | { "sex", OP_MON, "00000rrr11110100", 2, 0x00F4, 1, 1, CHG_NZV, ALL}, | |
170 | { "sif", OP_INH, "0000001100000000", 2, 0x0300, 2, 2, CHG_NONE, ALL}, | |
171 | { "sif", OP_MON, "00000rrr11110111", 2, 0x00F7, 2, 2, CHG_NONE, ALL}, | |
172 | { "stb", OP_IDO5, "01010rrrrrriiiii", 2, 0x5000, 2, 2, CHG_NONE, ALL}, | |
173 | { "stb", OP_IDR, "01110rrrrrrrrrrr", 2, 0x7000, 2, 2, CHG_NONE, ALL}, | |
174 | { "stw", OP_IDO5, "01011rrrrrriiiii", 2, 0x5800, 2, 2, CHG_NONE, ALL}, | |
175 | { "stw", OP_IDR, "01111rrrrrrrrrrr", 2, 0x7800, 2, 2, CHG_NONE, ALL}, | |
176 | { "sub", OP_TRI, "00011rrrrrrrrr00", 2, 0x1800, 1, 1, CHG_NZVC, ALL}, | |
177 | { "subh", OP_IMM8, "11001rrriiiiiiii", 2, 0xC800, 1, 1, CHG_NZVC, ALL}, | |
178 | { "subl", OP_IMM8, "11000rrriiiiiiii", 2, 0xC000, 1, 1, CHG_NZVC, ALL}, | |
179 | { "tfr", OP_MON_R_C, "00000rrr11111000", 2, 0x00F8, 1, 1, CHG_NONE, ALL}, | |
180 | { "tfr", OP_MON_C_R, "00000rrr11111001", 2, 0x00F9, 1, 1, CHG_NONE, ALL}, | |
181 | { "tfr", OP_MON_R_P, "00000rrr11111010", 2, 0x00FA, 1, 1, CHG_NONE, ALL}, | |
182 | { "xnor", OP_TRI, "00010rrrrrrrrr11", 2, 0x1003, 1, 1, CHG_NZV, ALL}, | |
183 | { "xnorh", OP_IMM8, "10111rrriiiiiiii", 2, 0xB800, 1, 1, CHG_NZV, ALL}, | |
184 | { "xnorl", OP_IMM8, "10110rrriiiiiiii", 2, 0xB000, 1, 1, CHG_NZV, ALL}, | |
f6c1a2d5 | 185 | /* macro and alias codes */ |
0e1c2434 SK |
186 | { "add", OP_mADD, "----------------", 4, 0, 0, 0, CHG_NONE, ALL}, |
187 | { "and", OP_mAND, "----------------", 4, 0, 0, 0, CHG_NONE, ALL}, | |
188 | { "bhs", OP_REL9, "0010000iiiiiiiii", 2, 0x2000, 0, 0, CHG_NONE, ALL}, | |
189 | { "blo", OP_REL9, "0010001iiiiiiiii", 2, 0x2200, 0, 0, CHG_NONE, ALL}, | |
190 | { "cmp", OP_mCPC, "----------------", 4, 0, 0, 0, CHG_NONE, ALL}, | |
191 | { "cmp", OP_DYA, "00011sssrrrrrr00", 2, 0x1800, 0, 0, CHG_NZVC, ALL}, | |
192 | { "com", OP_DM, "00010rrrsssrrr11", 2, 0x1003, 0, 0, CHG_NZVC, ALL}, | |
193 | { "com", OP_DYA, "00010rrrsssrrr11", 2, 0x1003, 0, 0, CHG_NZV, ALL}, | |
194 | { "cpc", OP_DYA, "00011sssrrrrrr01", 2, 0x1801, 0, 0, CHG_NZVC, ALL}, | |
195 | { "ldd", OP_mLDW, "----------------", 4, 0, 0, 0, CHG_NONE, ALL}, | |
196 | { "ldw", OP_mLDW, "----------------", 4, 0, 0, 0, CHG_NONE, ALL}, | |
197 | { "mov", OP_DYA, "00010rrrsssrrr10", 2, 0x1002, 0, 0, CHG_NZVC, ALL}, | |
198 | { "neg", OP_DYA, "00011rrrsssrrr00", 2, 0x1800, 0, 0, CHG_NZVC, ALL}, | |
199 | { "sub", OP_mSUB, "----------------", 4, 0, 0, 0, CHG_NONE, ALL}, | |
200 | { "tst", OP_MON, "00011sssrrrsss00", 2, 0x1800, 0, 0, CHG_NZV, ALL} | |
f6c1a2d5 NC |
201 | }; |
202 | ||
203 | const int xgate_num_opcodes = TABLE_SIZE (xgate_opcodes); |