[deliverable/binutils-gdb.git] / opcodes / xstormy16-dis.c

/* Disassembler interface for targets using CGEN. -*- C -*-
   CGEN: Cpu tools GENerator

   THIS FILE IS MACHINE GENERATED WITH CGEN.
   - the resultant file is machine generated, cgen-dis.in isn't

   Copyright (C) 1996-2016 Free Software Foundation, Inc.

   This file is part of libopcodes.

   This library is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software Foundation, Inc.,
   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */

/* ??? Eventually more and more of this stuff can go to cpu-independent files.
   Keep that in mind.  */

#include "sysdep.h"
#include <stdio.h>
#include "ansidecl.h"
#include "dis-asm.h"
#include "bfd.h"
#include "symcat.h"
#include "libiberty.h"
#include "xstormy16-desc.h"
#include "xstormy16-opc.h"
#include "opintl.h"

/* Default text to print if an instruction isn't recognized.  */
#define UNKNOWN_INSN_MSG _("*unknown*")

static void print_normal
  (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
static void print_address
  (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
static void print_keyword
  (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
static void print_insn_normal
  (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
static int print_insn
  (CGEN_CPU_DESC, bfd_vma,  disassemble_info *, bfd_byte *, unsigned);
static int default_print_insn
  (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
static int read_insn
  (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
   unsigned long *);
\f
/* -- disassembler routines inserted here.  */


void xstormy16_cgen_print_operand
  (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);

/* Main entry point for printing operands.
   XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
   of dis-asm.h on cgen.h.

   This function is basically just a big switch statement.  Earlier versions
   used tables to look up the function to use, but
   - if the table contains both assembler and disassembler functions then
     the disassembler contains much of the assembler and vice-versa,
   - there's a lot of inlining possibilities as things grow,
   - using a switch statement avoids the function call overhead.

   This function could be moved into `print_insn_normal', but keeping it
   separate makes clear the interface between `print_insn_normal' and each of
   the handlers.  */

void
xstormy16_cgen_print_operand (CGEN_CPU_DESC cd,
			   int opindex,
			   void * xinfo,
			   CGEN_FIELDS *fields,
			   void const *attrs ATTRIBUTE_UNUSED,
			   bfd_vma pc,
			   int length)
{
  disassemble_info *info = (disassemble_info *) xinfo;

  switch (opindex)
    {
    case XSTORMY16_OPERAND_RB :
      print_keyword (cd, info, & xstormy16_cgen_opval_gr_Rb_names, fields->f_Rb, 0);
      break;
    case XSTORMY16_OPERAND_RBJ :
      print_keyword (cd, info, & xstormy16_cgen_opval_gr_Rb_names, fields->f_Rbj, 0);
      break;
    case XSTORMY16_OPERAND_RD :
      print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rd, 0);
      break;
    case XSTORMY16_OPERAND_RDM :
      print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rdm, 0);
      break;
    case XSTORMY16_OPERAND_RM :
      print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rm, 0);
      break;
    case XSTORMY16_OPERAND_RS :
      print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rs, 0);
      break;
    case XSTORMY16_OPERAND_ABS24 :
      print_normal (cd, info, fields->f_abs24, 0|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
      break;
    case XSTORMY16_OPERAND_BCOND2 :
      print_keyword (cd, info, & xstormy16_cgen_opval_h_branchcond, fields->f_op2, 0);
      break;
    case XSTORMY16_OPERAND_BCOND5 :
      print_keyword (cd, info, & xstormy16_cgen_opval_h_branchcond, fields->f_op5, 0);
      break;
    case XSTORMY16_OPERAND_HMEM8 :
      print_normal (cd, info, fields->f_hmem8, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
      break;
    case XSTORMY16_OPERAND_IMM12 :
      print_normal (cd, info, fields->f_imm12, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
      break;
    case XSTORMY16_OPERAND_IMM16 :
      print_normal (cd, info, fields->f_imm16, 0|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
      break;
    case XSTORMY16_OPERAND_IMM2 :
      print_normal (cd, info, fields->f_imm2, 0, pc, length);
      break;
    case XSTORMY16_OPERAND_IMM3 :
      print_normal (cd, info, fields->f_imm3, 0, pc, length);
      break;
    case XSTORMY16_OPERAND_IMM3B :
      print_normal (cd, info, fields->f_imm3b, 0, pc, length);
      break;
    case XSTORMY16_OPERAND_IMM4 :
      print_normal (cd, info, fields->f_imm4, 0, pc, length);
      break;
    case XSTORMY16_OPERAND_IMM8 :
      print_normal (cd, info, fields->f_imm8, 0, pc, length);
      break;
    case XSTORMY16_OPERAND_IMM8SMALL :
      print_normal (cd, info, fields->f_imm8, 0, pc, length);
      break;
    case XSTORMY16_OPERAND_LMEM8 :
      print_normal (cd, info, fields->f_lmem8, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
      break;
    case XSTORMY16_OPERAND_REL12 :
      print_normal (cd, info, fields->f_rel12, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
      break;
    case XSTORMY16_OPERAND_REL12A :
      print_normal (cd, info, fields->f_rel12a, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
      break;
    case XSTORMY16_OPERAND_REL8_2 :
      print_normal (cd, info, fields->f_rel8_2, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
      break;
    case XSTORMY16_OPERAND_REL8_4 :
      print_normal (cd, info, fields->f_rel8_4, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
      break;
    case XSTORMY16_OPERAND_WS2 :
      print_keyword (cd, info, & xstormy16_cgen_opval_h_wordsize, fields->f_op2m, 0);
      break;

    default :
      /* xgettext:c-format */
      fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
	       opindex);
    abort ();
  }
}

cgen_print_fn * const xstormy16_cgen_print_handlers[] =
{
  print_insn_normal,
};


void
xstormy16_cgen_init_dis (CGEN_CPU_DESC cd)
{
  xstormy16_cgen_init_opcode_table (cd);
  xstormy16_cgen_init_ibld_table (cd);
  cd->print_handlers = & xstormy16_cgen_print_handlers[0];
  cd->print_operand = xstormy16_cgen_print_operand;
}

\f
/* Default print handler.  */

static void
print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	      void *dis_info,
	      long value,
	      unsigned int attrs,
	      bfd_vma pc ATTRIBUTE_UNUSED,
	      int length ATTRIBUTE_UNUSED)
{
  disassemble_info *info = (disassemble_info *) dis_info;

  /* Print the operand as directed by the attributes.  */
  if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
    ; /* nothing to do */
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
    (*info->fprintf_func) (info->stream, "%ld", value);
  else
    (*info->fprintf_func) (info->stream, "0x%lx", value);
}

/* Default address handler.  */

static void
print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	       void *dis_info,
	       bfd_vma value,
	       unsigned int attrs,
	       bfd_vma pc ATTRIBUTE_UNUSED,
	       int length ATTRIBUTE_UNUSED)
{
  disassemble_info *info = (disassemble_info *) dis_info;

  /* Print the operand as directed by the attributes.  */
  if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
    ; /* Nothing to do.  */
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
    (*info->print_address_func) (value, info);
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
    (*info->print_address_func) (value, info);
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
    (*info->fprintf_func) (info->stream, "%ld", (long) value);
  else
    (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
}

/* Keyword print handler.  */

static void
print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	       void *dis_info,
	       CGEN_KEYWORD *keyword_table,
	       long value,
	       unsigned int attrs ATTRIBUTE_UNUSED)
{
  disassemble_info *info = (disassemble_info *) dis_info;
  const CGEN_KEYWORD_ENTRY *ke;

  ke = cgen_keyword_lookup_value (keyword_table, value);
  if (ke != NULL)
    (*info->fprintf_func) (info->stream, "%s", ke->name);
  else
    (*info->fprintf_func) (info->stream, "???");
}
\f
/* Default insn printer.

   DIS_INFO is defined as `void *' so the disassembler needn't know anything
   about disassemble_info.  */

static void
print_insn_normal (CGEN_CPU_DESC cd,
		   void *dis_info,
		   const CGEN_INSN *insn,
		   CGEN_FIELDS *fields,
		   bfd_vma pc,
		   int length)
{
  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
  disassemble_info *info = (disassemble_info *) dis_info;
  const CGEN_SYNTAX_CHAR_TYPE *syn;

  CGEN_INIT_PRINT (cd);

  for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
    {
      if (CGEN_SYNTAX_MNEMONIC_P (*syn))
	{
	  (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
	  continue;
	}
      if (CGEN_SYNTAX_CHAR_P (*syn))
	{
	  (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
	  continue;
	}

      /* We have an operand.  */
      xstormy16_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
				 fields, CGEN_INSN_ATTRS (insn), pc, length);
    }
}
\f
/* Subroutine of print_insn. Reads an insn into the given buffers and updates
   the extract info.
   Returns 0 if all is well, non-zero otherwise.  */

static int
read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	   bfd_vma pc,
	   disassemble_info *info,
	   bfd_byte *buf,
	   int buflen,
	   CGEN_EXTRACT_INFO *ex_info,
	   unsigned long *insn_value)
{
  int status = (*info->read_memory_func) (pc, buf, buflen, info);

  if (status != 0)
    {
      (*info->memory_error_func) (status, pc, info);
      return -1;
    }

  ex_info->dis_info = info;
  ex_info->valid = (1 << buflen) - 1;
  ex_info->insn_bytes = buf;

  *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
  return 0;
}

/* Utility to print an insn.
   BUF is the base part of the insn, target byte order, BUFLEN bytes long.
   The result is the size of the insn in bytes or zero for an unknown insn
   or -1 if an error occurs fetching data (memory_error_func will have
   been called).  */

static int
print_insn (CGEN_CPU_DESC cd,
	    bfd_vma pc,
	    disassemble_info *info,
	    bfd_byte *buf,
	    unsigned int buflen)
{
  CGEN_INSN_INT insn_value;
  const CGEN_INSN_LIST *insn_list;
  CGEN_EXTRACT_INFO ex_info;
  int basesize;

  /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
  basesize = cd->base_insn_bitsize < buflen * 8 ?
                                     cd->base_insn_bitsize : buflen * 8;
  insn_value = cgen_get_insn_value (cd, buf, basesize);


  /* Fill in ex_info fields like read_insn would.  Don't actually call
     read_insn, since the incoming buffer is already read (and possibly
     modified a la m32r).  */
  ex_info.valid = (1 << buflen) - 1;
  ex_info.dis_info = info;
  ex_info.insn_bytes = buf;

  /* The instructions are stored in hash lists.
     Pick the first one and keep trying until we find the right one.  */

  insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
  while (insn_list != NULL)
    {
      const CGEN_INSN *insn = insn_list->insn;
      CGEN_FIELDS fields;
      int length;
      unsigned long insn_value_cropped;

#ifdef CGEN_VALIDATE_INSN_SUPPORTED
      /* Not needed as insn shouldn't be in hash lists if not supported.  */
      /* Supported by this cpu?  */
      if (! xstormy16_cgen_insn_supported (cd, insn))
        {
          insn_list = CGEN_DIS_NEXT_INSN (insn_list);
	  continue;
        }
#endif

      /* Basic bit mask must be correct.  */
      /* ??? May wish to allow target to defer this check until the extract
	 handler.  */

      /* Base size may exceed this instruction's size.  Extract the
         relevant part from the buffer. */
      if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
	  (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
	insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
					   info->endian == BFD_ENDIAN_BIG);
      else
	insn_value_cropped = insn_value;

      if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
	  == CGEN_INSN_BASE_VALUE (insn))
	{
	  /* Printing is handled in two passes.  The first pass parses the
	     machine insn and extracts the fields.  The second pass prints
	     them.  */

	  /* Make sure the entire insn is loaded into insn_value, if it
	     can fit.  */
	  if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
	      (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
	    {
	      unsigned long full_insn_value;
	      int rc = read_insn (cd, pc, info, buf,
				  CGEN_INSN_BITSIZE (insn) / 8,
				  & ex_info, & full_insn_value);
	      if (rc != 0)
		return rc;
	      length = CGEN_EXTRACT_FN (cd, insn)
		(cd, insn, &ex_info, full_insn_value, &fields, pc);
	    }
	  else
	    length = CGEN_EXTRACT_FN (cd, insn)
	      (cd, insn, &ex_info, insn_value_cropped, &fields, pc);

	  /* Length < 0 -> error.  */
	  if (length < 0)
	    return length;
	  if (length > 0)
	    {
	      CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
	      /* Length is in bits, result is in bytes.  */
	      return length / 8;
	    }
	}

      insn_list = CGEN_DIS_NEXT_INSN (insn_list);
    }

  return 0;
}

/* Default value for CGEN_PRINT_INSN.
   The result is the size of the insn in bytes or zero for an unknown insn
   or -1 if an error occured fetching bytes.  */

#ifndef CGEN_PRINT_INSN
#define CGEN_PRINT_INSN default_print_insn
#endif

static int
default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
{
  bfd_byte buf[CGEN_MAX_INSN_SIZE];
  int buflen;
  int status;

  /* Attempt to read the base part of the insn.  */
  buflen = cd->base_insn_bitsize / 8;
  status = (*info->read_memory_func) (pc, buf, buflen, info);

  /* Try again with the minimum part, if min < base.  */
  if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
    {
      buflen = cd->min_insn_bitsize / 8;
      status = (*info->read_memory_func) (pc, buf, buflen, info);
    }

  if (status != 0)
    {
      (*info->memory_error_func) (status, pc, info);
      return -1;
    }

  return print_insn (cd, pc, info, buf, buflen);
}

/* Main entry point.
   Print one instruction from PC on INFO->STREAM.
   Return the size of the instruction (in bytes).  */

typedef struct cpu_desc_list
{
  struct cpu_desc_list *next;
  CGEN_BITSET *isa;
  int mach;
  int endian;
  CGEN_CPU_DESC cd;
} cpu_desc_list;

int
print_insn_xstormy16 (bfd_vma pc, disassemble_info *info)
{
  static cpu_desc_list *cd_list = 0;
  cpu_desc_list *cl = 0;
  static CGEN_CPU_DESC cd = 0;
  static CGEN_BITSET *prev_isa;
  static int prev_mach;
  static int prev_endian;
  int length;
  CGEN_BITSET *isa;
  int mach;
  int endian = (info->endian == BFD_ENDIAN_BIG
		? CGEN_ENDIAN_BIG
		: CGEN_ENDIAN_LITTLE);
  enum bfd_architecture arch;

  /* ??? gdb will set mach but leave the architecture as "unknown" */
#ifndef CGEN_BFD_ARCH
#define CGEN_BFD_ARCH bfd_arch_xstormy16
#endif
  arch = info->arch;
  if (arch == bfd_arch_unknown)
    arch = CGEN_BFD_ARCH;

  /* There's no standard way to compute the machine or isa number
     so we leave it to the target.  */
#ifdef CGEN_COMPUTE_MACH
  mach = CGEN_COMPUTE_MACH (info);
#else
  mach = info->mach;
#endif

#ifdef CGEN_COMPUTE_ISA
  {
    static CGEN_BITSET *permanent_isa;

    if (!permanent_isa)
      permanent_isa = cgen_bitset_create (MAX_ISAS);
    isa = permanent_isa;
    cgen_bitset_clear (isa);
    cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
  }
#else
  isa = info->insn_sets;
#endif

  /* If we've switched cpu's, try to find a handle we've used before */
  if (cd
      && (cgen_bitset_compare (isa, prev_isa) != 0
	  || mach != prev_mach
	  || endian != prev_endian))
    {
      cd = 0;
      for (cl = cd_list; cl; cl = cl->next)
	{
	  if (cgen_bitset_compare (cl->isa, isa) == 0 &&
	      cl->mach == mach &&
	      cl->endian == endian)
	    {
	      cd = cl->cd;
 	      prev_isa = cd->isas;
	      break;
	    }
	}
    }

  /* If we haven't initialized yet, initialize the opcode table.  */
  if (! cd)
    {
      const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
      const char *mach_name;

      if (!arch_type)
	abort ();
      mach_name = arch_type->printable_name;

      prev_isa = cgen_bitset_copy (isa);
      prev_mach = mach;
      prev_endian = endian;
      cd = xstormy16_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
				 CGEN_CPU_OPEN_BFDMACH, mach_name,
				 CGEN_CPU_OPEN_ENDIAN, prev_endian,
				 CGEN_CPU_OPEN_END);
      if (!cd)
	abort ();

      /* Save this away for future reference.  */
      cl = xmalloc (sizeof (struct cpu_desc_list));
      cl->cd = cd;
      cl->isa = prev_isa;
      cl->mach = mach;
      cl->endian = endian;
      cl->next = cd_list;
      cd_list = cl;

      xstormy16_cgen_init_dis (cd);
    }

  /* We try to have as much common code as possible.
     But at this point some targets need to take over.  */
  /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
     but if not possible try to move this hook elsewhere rather than
     have two hooks.  */
  length = CGEN_PRINT_INSN (cd, pc, info);
  if (length > 0)
    return length;
  if (length < 0)
    return -1;

  (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
  return cd->default_insn_bitsize / 8;
}
Commit	Line	Data
93fbbb04 GK	1	/* Disassembler interface for targets using CGEN. -- C --
	2	CGEN: Cpu tools GENerator
	3
47b0e7ad NC	4	THIS FILE IS MACHINE GENERATED WITH CGEN.
47b0e7ad NC	5	- the resultant file is machine generated, cgen-dis.in isn't
93fbbb04	6
6f2750fe	7	Copyright (C) 1996-2016 Free Software Foundation, Inc.
93fbbb04	8
9b201bb5	9	This file is part of libopcodes.
93fbbb04	10
9b201bb5	11	This library is free software; you can redistribute it and/or modify
47b0e7ad	12	it under the terms of the GNU General Public License as published by
9b201bb5	13	the Free Software Foundation; either version 3, or (at your option)
47b0e7ad	14	any later version.
93fbbb04	15
9b201bb5 NC	16	It is distributed in the hope that it will be useful, but WITHOUT
	17	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	18	or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	19	License for more details.
93fbbb04	20
47b0e7ad NC	21	You should have received a copy of the GNU General Public License
	22	along with this program; if not, write to the Free Software Foundation, Inc.,
	23	51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
93fbbb04 GK	24
	25	/* ??? Eventually more and more of this stuff can go to cpu-independent files.
	26	Keep that in mind. */
	27
	28	#include "sysdep.h"
	29	#include <stdio.h>
	30	#include "ansidecl.h"
	31	#include "dis-asm.h"
	32	#include "bfd.h"
	33	#include "symcat.h"
98f70fc4	34	#include "libiberty.h"
93fbbb04 GK	35	#include "xstormy16-desc.h"
	36	#include "xstormy16-opc.h"
	37	#include "opintl.h"
	38
	39	/* Default text to print if an instruction isn't recognized. */
	40	#define UNKNOWN_INSN_MSG _("unknown")
	41
	42	static void print_normal
ffead7ae	43	(CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
93fbbb04	44	static void print_address
bf143b25	45	(CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
93fbbb04	46	static void print_keyword
bf143b25	47	(CGEN_CPU_DESC, void , CGEN_KEYWORD , long, unsigned int) ATTRIBUTE_UNUSED;
93fbbb04	48	static void print_insn_normal
ffead7ae	49	(CGEN_CPU_DESC, void , const CGEN_INSN , CGEN_FIELDS *, bfd_vma, int);
93fbbb04	50	static int print_insn
33b71eeb	51	(CGEN_CPU_DESC, bfd_vma, disassemble_info , bfd_byte , unsigned);
93fbbb04	52	static int default_print_insn
bf143b25	53	(CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
93fbbb04	54	static int read_insn
33b71eeb	55	(CGEN_CPU_DESC, bfd_vma, disassemble_info , bfd_byte , int, CGEN_EXTRACT_INFO *,
ffead7ae	56	unsigned long *);
93fbbb04	57	\f
47b0e7ad	58	/* -- disassembler routines inserted here. */
93fbbb04 GK	59
	60
	61	void xstormy16_cgen_print_operand
47b0e7ad	62	(CGEN_CPU_DESC, int, PTR, CGEN_FIELDS , void const , bfd_vma, int);
93fbbb04 GK	63
	64	/* Main entry point for printing operands.
	65	XINFO is a `void ' and not a `disassemble_info ' to not put a requirement
	66	of dis-asm.h on cgen.h.
	67
	68	This function is basically just a big switch statement. Earlier versions
	69	used tables to look up the function to use, but
	70	- if the table contains both assembler and disassembler functions then
	71	the disassembler contains much of the assembler and vice-versa,
	72	- there's a lot of inlining possibilities as things grow,
	73	- using a switch statement avoids the function call overhead.
	74
	75	This function could be moved into `print_insn_normal', but keeping it
	76	separate makes clear the interface between `print_insn_normal' and each of
	77	the handlers. */
	78
	79	void
47b0e7ad NC	80	xstormy16_cgen_print_operand (CGEN_CPU_DESC cd,
	81	int opindex,
	82	void * xinfo,
	83	CGEN_FIELDS *fields,
	84	void const *attrs ATTRIBUTE_UNUSED,
	85	bfd_vma pc,
	86	int length)
93fbbb04	87	{
47b0e7ad	88	disassemble_info info = (disassemble_info ) xinfo;
93fbbb04 GK	89
	90	switch (opindex)
	91	{
	92	case XSTORMY16_OPERAND_RB :
1951c6f7	93	print_keyword (cd, info, & xstormy16_cgen_opval_gr_Rb_names, fields->f_Rb, 0);
93fbbb04 GK	94	break;
93fbbb04 GK	95	case XSTORMY16_OPERAND_RBJ :
1951c6f7	96	print_keyword (cd, info, & xstormy16_cgen_opval_gr_Rb_names, fields->f_Rbj, 0);
93fbbb04 GK	97	break;
	98	case XSTORMY16_OPERAND_RD :
	99	print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rd, 0);
	100	break;
	101	case XSTORMY16_OPERAND_RDM :
	102	print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rdm, 0);
	103	break;
	104	case XSTORMY16_OPERAND_RM :
	105	print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rm, 0);
	106	break;
	107	case XSTORMY16_OPERAND_RS :
	108	print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rs, 0);
	109	break;
	110	case XSTORMY16_OPERAND_ABS24 :
	111	print_normal (cd, info, fields->f_abs24, 0\|(1<<CGEN_OPERAND_ABS_ADDR)\|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
	112	break;
	113	case XSTORMY16_OPERAND_BCOND2 :
	114	print_keyword (cd, info, & xstormy16_cgen_opval_h_branchcond, fields->f_op2, 0);
	115	break;
	116	case XSTORMY16_OPERAND_BCOND5 :
	117	print_keyword (cd, info, & xstormy16_cgen_opval_h_branchcond, fields->f_op5, 0);
	118	break;
	119	case XSTORMY16_OPERAND_HMEM8 :
	120	print_normal (cd, info, fields->f_hmem8, 0\|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
	121	break;
	122	case XSTORMY16_OPERAND_IMM12 :
	123	print_normal (cd, info, fields->f_imm12, 0\|(1<<CGEN_OPERAND_SIGNED), pc, length);
	124	break;
	125	case XSTORMY16_OPERAND_IMM16 :
	126	print_normal (cd, info, fields->f_imm16, 0\|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
	127	break;
	128	case XSTORMY16_OPERAND_IMM2 :
	129	print_normal (cd, info, fields->f_imm2, 0, pc, length);
	130	break;
	131	case XSTORMY16_OPERAND_IMM3 :
	132	print_normal (cd, info, fields->f_imm3, 0, pc, length);
	133	break;
	134	case XSTORMY16_OPERAND_IMM3B :
	135	print_normal (cd, info, fields->f_imm3b, 0, pc, length);
	136	break;
	137	case XSTORMY16_OPERAND_IMM4 :
	138	print_normal (cd, info, fields->f_imm4, 0, pc, length);
	139	break;
	140	case XSTORMY16_OPERAND_IMM8 :
	141	print_normal (cd, info, fields->f_imm8, 0, pc, length);
	142	break;
	143	case XSTORMY16_OPERAND_IMM8SMALL :
	144	print_normal (cd, info, fields->f_imm8, 0, pc, length);
	145	break;
	146	case XSTORMY16_OPERAND_LMEM8 :
	147	print_normal (cd, info, fields->f_lmem8, 0\|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
	148	break;
	149	case XSTORMY16_OPERAND_REL12 :
	150	print_normal (cd, info, fields->f_rel12, 0\|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
	151	break;
	152	case XSTORMY16_OPERAND_REL12A :
	153	print_normal (cd, info, fields->f_rel12a, 0\|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
	154	break;
	155	case XSTORMY16_OPERAND_REL8_2 :
	156	print_normal (cd, info, fields->f_rel8_2, 0\|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
	157	break;
	158	case XSTORMY16_OPERAND_REL8_4 :
	159	print_normal (cd, info, fields->f_rel8_4, 0\|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
	160	break;
161	case XSTORMY16_OPERAND_WS2 :
162	print_keyword (cd, info, & xstormy16_cgen_opval_h_wordsize, fields->f_op2m, 0);
163	break;
164
165	default :
166	/* xgettext:c-format */
167	fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
168	opindex);
169	abort ();
170	}
171	}
172
43e65147	173	cgen_print_fn * const xstormy16_cgen_print_handlers[] =
93fbbb04 GK	174	{
	175	print_insn_normal,
	176	};
	177
	178
	179	void
47b0e7ad	180	xstormy16_cgen_init_dis (CGEN_CPU_DESC cd)
93fbbb04 GK	181	{
	182	xstormy16_cgen_init_opcode_table (cd);
	183	xstormy16_cgen_init_ibld_table (cd);
	184	cd->print_handlers = & xstormy16_cgen_print_handlers[0];
	185	cd->print_operand = xstormy16_cgen_print_operand;
	186	}
	187
	188	\f
	189	/* Default print handler. */
	190
	191	static void
ffead7ae MM	192	print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	193	void *dis_info,
	194	long value,
	195	unsigned int attrs,
	196	bfd_vma pc ATTRIBUTE_UNUSED,
	197	int length ATTRIBUTE_UNUSED)
93fbbb04 GK	198	{
	199	disassemble_info info = (disassemble_info ) dis_info;
	200
93fbbb04 GK	201	/* Print the operand as directed by the attributes. */
	202	if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
	203	; /* nothing to do */
	204	else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
	205	(*info->fprintf_func) (info->stream, "%ld", value);
	206	else
	207	(*info->fprintf_func) (info->stream, "0x%lx", value);
	208	}
	209
	210	/* Default address handler. */
	211
	212	static void
ffead7ae MM	213	print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	214	void *dis_info,
	215	bfd_vma value,
	216	unsigned int attrs,
	217	bfd_vma pc ATTRIBUTE_UNUSED,
	218	int length ATTRIBUTE_UNUSED)
93fbbb04 GK	219	{
	220	disassemble_info info = (disassemble_info ) dis_info;
	221
93fbbb04 GK	222	/* Print the operand as directed by the attributes. */
93fbbb04 GK	223	if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
47b0e7ad	224	; /* Nothing to do. */
93fbbb04 GK	225	else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
	226	(*info->print_address_func) (value, info);
	227	else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
	228	(*info->print_address_func) (value, info);
	229	else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
	230	(*info->fprintf_func) (info->stream, "%ld", (long) value);
	231	else
	232	(*info->fprintf_func) (info->stream, "0x%lx", (long) value);
	233	}
	234
	235	/* Keyword print handler. */
	236
	237	static void
ffead7ae MM	238	print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	239	void *dis_info,
	240	CGEN_KEYWORD *keyword_table,
	241	long value,
	242	unsigned int attrs ATTRIBUTE_UNUSED)
93fbbb04 GK	243	{
	244	disassemble_info info = (disassemble_info ) dis_info;
	245	const CGEN_KEYWORD_ENTRY *ke;
	246
	247	ke = cgen_keyword_lookup_value (keyword_table, value);
	248	if (ke != NULL)
	249	(*info->fprintf_func) (info->stream, "%s", ke->name);
	250	else
	251	(*info->fprintf_func) (info->stream, "???");
	252	}
	253	\f
	254	/* Default insn printer.
	255
ffead7ae	256	DIS_INFO is defined as `void *' so the disassembler needn't know anything
93fbbb04 GK	257	about disassemble_info. */
	258
	259	static void
ffead7ae MM	260	print_insn_normal (CGEN_CPU_DESC cd,
	261	void *dis_info,
	262	const CGEN_INSN *insn,
	263	CGEN_FIELDS *fields,
	264	bfd_vma pc,
	265	int length)
93fbbb04 GK	266	{
	267	const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
	268	disassemble_info info = (disassemble_info ) dis_info;
	269	const CGEN_SYNTAX_CHAR_TYPE *syn;
	270
	271	CGEN_INIT_PRINT (cd);
	272
	273	for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
	274	{
	275	if (CGEN_SYNTAX_MNEMONIC_P (*syn))
	276	{
	277	(*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
	278	continue;
	279	}
	280	if (CGEN_SYNTAX_CHAR_P (*syn))
	281	{
	282	(info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (syn));
	283	continue;
	284	}
	285
	286	/* We have an operand. */
	287	xstormy16_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
	288	fields, CGEN_INSN_ATTRS (insn), pc, length);
	289	}
	290	}
	291	\f
	292	/* Subroutine of print_insn. Reads an insn into the given buffers and updates
	293	the extract info.
	294	Returns 0 if all is well, non-zero otherwise. */
	295
	296	static int
ffead7ae MM	297	read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	298	bfd_vma pc,
	299	disassemble_info *info,
33b71eeb	300	bfd_byte *buf,
ffead7ae MM	301	int buflen,
	302	CGEN_EXTRACT_INFO *ex_info,
	303	unsigned long *insn_value)
93fbbb04 GK	304	{
93fbbb04 GK	305	int status = (*info->read_memory_func) (pc, buf, buflen, info);
47b0e7ad	306
93fbbb04 GK	307	if (status != 0)
	308	{
	309	(*info->memory_error_func) (status, pc, info);
	310	return -1;
	311	}
	312
	313	ex_info->dis_info = info;
	314	ex_info->valid = (1 << buflen) - 1;
	315	ex_info->insn_bytes = buf;
	316
	317	insn_value = bfd_get_bits (buf, buflen 8, info->endian == BFD_ENDIAN_BIG);
	318	return 0;
	319	}
	320
	321	/* Utility to print an insn.
	322	BUF is the base part of the insn, target byte order, BUFLEN bytes long.
	323	The result is the size of the insn in bytes or zero for an unknown insn
	324	or -1 if an error occurs fetching data (memory_error_func will have
	325	been called). */
	326
	327	static int
ffead7ae MM	328	print_insn (CGEN_CPU_DESC cd,
	329	bfd_vma pc,
	330	disassemble_info *info,
33b71eeb	331	bfd_byte *buf,
ffead7ae	332	unsigned int buflen)
93fbbb04 GK	333	{
	334	CGEN_INSN_INT insn_value;
	335	const CGEN_INSN_LIST *insn_list;
	336	CGEN_EXTRACT_INFO ex_info;
1951c6f7	337	int basesize;
93fbbb04 GK	338
93fbbb04 GK	339	/* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
1951c6f7 MG	340	basesize = cd->base_insn_bitsize < buflen * 8 ?
	341	cd->base_insn_bitsize : buflen * 8;
	342	insn_value = cgen_get_insn_value (cd, buf, basesize);
	343
93fbbb04 GK	344
	345	/* Fill in ex_info fields like read_insn would. Don't actually call
	346	read_insn, since the incoming buffer is already read (and possibly
	347	modified a la m32r). */
	348	ex_info.valid = (1 << buflen) - 1;
	349	ex_info.dis_info = info;
	350	ex_info.insn_bytes = buf;
	351
	352	/* The instructions are stored in hash lists.
	353	Pick the first one and keep trying until we find the right one. */
	354
33b71eeb	355	insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
93fbbb04 GK	356	while (insn_list != NULL)
	357	{
	358	const CGEN_INSN *insn = insn_list->insn;
	359	CGEN_FIELDS fields;
	360	int length;
	361	unsigned long insn_value_cropped;
	362
43e65147	363	#ifdef CGEN_VALIDATE_INSN_SUPPORTED
93fbbb04 GK	364	/* Not needed as insn shouldn't be in hash lists if not supported. */
	365	/* Supported by this cpu? */
	366	if (! xstormy16_cgen_insn_supported (cd, insn))
	367	{
	368	insn_list = CGEN_DIS_NEXT_INSN (insn_list);
	369	continue;
	370	}
	371	#endif
	372
	373	/* Basic bit mask must be correct. */
	374	/* ??? May wish to allow target to defer this check until the extract
	375	handler. */
	376
	377	/* Base size may exceed this instruction's size. Extract the
	378	relevant part from the buffer. */
	379	if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
	380	(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
43e65147	381	insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
93fbbb04 GK	382	info->endian == BFD_ENDIAN_BIG);
	383	else
	384	insn_value_cropped = insn_value;
	385
	386	if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
	387	== CGEN_INSN_BASE_VALUE (insn))
	388	{
	389	/* Printing is handled in two passes. The first pass parses the
	390	machine insn and extracts the fields. The second pass prints
	391	them. */
	392
	393	/* Make sure the entire insn is loaded into insn_value, if it
	394	can fit. */
	395	if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
	396	(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
	397	{
	398	unsigned long full_insn_value;
	399	int rc = read_insn (cd, pc, info, buf,
	400	CGEN_INSN_BITSIZE (insn) / 8,
	401	& ex_info, & full_insn_value);
	402	if (rc != 0)
	403	return rc;
	404	length = CGEN_EXTRACT_FN (cd, insn)
	405	(cd, insn, &ex_info, full_insn_value, &fields, pc);
	406	}
	407	else
	408	length = CGEN_EXTRACT_FN (cd, insn)
	409	(cd, insn, &ex_info, insn_value_cropped, &fields, pc);
	410
47b0e7ad	411	/* Length < 0 -> error. */
93fbbb04 GK	412	if (length < 0)
	413	return length;
	414	if (length > 0)
	415	{
	416	CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
47b0e7ad	417	/* Length is in bits, result is in bytes. */
93fbbb04 GK	418	return length / 8;
	419	}
	420	}
	421
	422	insn_list = CGEN_DIS_NEXT_INSN (insn_list);
	423	}
	424
	425	return 0;
	426	}
	427
	428	/* Default value for CGEN_PRINT_INSN.
	429	The result is the size of the insn in bytes or zero for an unknown insn
	430	or -1 if an error occured fetching bytes. */
	431
	432	#ifndef CGEN_PRINT_INSN
	433	#define CGEN_PRINT_INSN default_print_insn
	434	#endif
	435
	436	static int
ffead7ae	437	default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
93fbbb04	438	{
33b71eeb	439	bfd_byte buf[CGEN_MAX_INSN_SIZE];
93fbbb04 GK	440	int buflen;
	441	int status;
	442
	443	/* Attempt to read the base part of the insn. */
	444	buflen = cd->base_insn_bitsize / 8;
	445	status = (*info->read_memory_func) (pc, buf, buflen, info);
	446
	447	/* Try again with the minimum part, if min < base. */
	448	if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
	449	{
	450	buflen = cd->min_insn_bitsize / 8;
	451	status = (*info->read_memory_func) (pc, buf, buflen, info);
	452	}
	453
	454	if (status != 0)
	455	{
	456	(*info->memory_error_func) (status, pc, info);
	457	return -1;
	458	}
	459
	460	return print_insn (cd, pc, info, buf, buflen);
	461	}
	462
	463	/* Main entry point.
	464	Print one instruction from PC on INFO->STREAM.
	465	Return the size of the instruction (in bytes). */
	466
47b0e7ad NC	467	typedef struct cpu_desc_list
47b0e7ad NC	468	{
a978a3e5	469	struct cpu_desc_list *next;
fb53f5a8	470	CGEN_BITSET *isa;
a978a3e5 NC	471	int mach;
	472	int endian;
	473	CGEN_CPU_DESC cd;
	474	} cpu_desc_list;
	475
93fbbb04	476	int
ffead7ae	477	print_insn_xstormy16 (bfd_vma pc, disassemble_info *info)
93fbbb04	478	{
a978a3e5 NC	479	static cpu_desc_list *cd_list = 0;
a978a3e5 NC	480	cpu_desc_list *cl = 0;
93fbbb04	481	static CGEN_CPU_DESC cd = 0;
fb53f5a8	482	static CGEN_BITSET *prev_isa;
93fbbb04 GK	483	static int prev_mach;
	484	static int prev_endian;
	485	int length;
fb53f5a8 DB	486	CGEN_BITSET *isa;
fb53f5a8 DB	487	int mach;
93fbbb04 GK	488	int endian = (info->endian == BFD_ENDIAN_BIG
	489	? CGEN_ENDIAN_BIG
	490	: CGEN_ENDIAN_LITTLE);
	491	enum bfd_architecture arch;
	492
	493	/* ??? gdb will set mach but leave the architecture as "unknown" */
	494	#ifndef CGEN_BFD_ARCH
	495	#define CGEN_BFD_ARCH bfd_arch_xstormy16
	496	#endif
	497	arch = info->arch;
	498	if (arch == bfd_arch_unknown)
	499	arch = CGEN_BFD_ARCH;
43e65147	500
93fbbb04 GK	501	/* There's no standard way to compute the machine or isa number
	502	so we leave it to the target. */
	503	#ifdef CGEN_COMPUTE_MACH
	504	mach = CGEN_COMPUTE_MACH (info);
	505	#else
	506	mach = info->mach;
	507	#endif
	508
	509	#ifdef CGEN_COMPUTE_ISA
fb53f5a8 DB	510	{
	511	static CGEN_BITSET *permanent_isa;
	512
	513	if (!permanent_isa)
	514	permanent_isa = cgen_bitset_create (MAX_ISAS);
	515	isa = permanent_isa;
	516	cgen_bitset_clear (isa);
	517	cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
	518	}
93fbbb04	519	#else
a978a3e5	520	isa = info->insn_sets;
93fbbb04 GK	521	#endif
93fbbb04 GK	522
a978a3e5	523	/* If we've switched cpu's, try to find a handle we've used before */
93fbbb04	524	if (cd
fb53f5a8	525	&& (cgen_bitset_compare (isa, prev_isa) != 0
93fbbb04 GK	526	\|\| mach != prev_mach
	527	\|\| endian != prev_endian))
	528	{
93fbbb04	529	cd = 0;
a978a3e5 NC	530	for (cl = cd_list; cl; cl = cl->next)
a978a3e5 NC	531	{
fb53f5a8	532	if (cgen_bitset_compare (cl->isa, isa) == 0 &&
a978a3e5 NC	533	cl->mach == mach &&
	534	cl->endian == endian)
	535	{
	536	cd = cl->cd;
fb53f5a8	537	prev_isa = cd->isas;
a978a3e5 NC	538	break;
	539	}
	540	}
43e65147	541	}
93fbbb04 GK	542
	543	/* If we haven't initialized yet, initialize the opcode table. */
	544	if (! cd)
	545	{
	546	const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
	547	const char *mach_name;
	548
	549	if (!arch_type)
	550	abort ();
	551	mach_name = arch_type->printable_name;
	552
fb53f5a8	553	prev_isa = cgen_bitset_copy (isa);
93fbbb04 GK	554	prev_mach = mach;
	555	prev_endian = endian;
	556	cd = xstormy16_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
	557	CGEN_CPU_OPEN_BFDMACH, mach_name,
	558	CGEN_CPU_OPEN_ENDIAN, prev_endian,
	559	CGEN_CPU_OPEN_END);
	560	if (!cd)
	561	abort ();
a978a3e5	562
47b0e7ad	563	/* Save this away for future reference. */
a978a3e5 NC	564	cl = xmalloc (sizeof (struct cpu_desc_list));
a978a3e5 NC	565	cl->cd = cd;
fb53f5a8	566	cl->isa = prev_isa;
a978a3e5 NC	567	cl->mach = mach;
	568	cl->endian = endian;
	569	cl->next = cd_list;
	570	cd_list = cl;
	571
93fbbb04 GK	572	xstormy16_cgen_init_dis (cd);
	573	}
	574
	575	/* We try to have as much common code as possible.
	576	But at this point some targets need to take over. */
	577	/* ??? Some targets may need a hook elsewhere. Try to avoid this,
	578	but if not possible try to move this hook elsewhere rather than
	579	have two hooks. */
	580	length = CGEN_PRINT_INSN (cd, pc, info);
	581	if (length > 0)
	582	return length;
	583	if (length < 0)
	584	return -1;
	585
	586	(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
	587	return cd->default_insn_bitsize / 8;
	588	}