[deliverable/binutils-gdb.git] / sim / arm / armemu.h

/*  armemu.h -- ARMulator emulation macros:  ARM6 Instruction Emulator.
    Copyright (C) 1994 Advanced RISC Machines Ltd.
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 3 of the License, or
    (at your option) any later version.
 
    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, see <http://www.gnu.org/licenses/>. */

extern ARMword isize;
extern int trace;
extern int disas;
extern int trace_funcs;
extern void print_insn (ARMword);

/* Condition code values.  */
#define EQ 0
#define NE 1
#define CS 2
#define CC 3
#define MI 4
#define PL 5
#define VS 6
#define VC 7
#define HI 8
#define LS 9
#define GE 10
#define LT 11
#define GT 12
#define LE 13
#define AL 14
#define NV 15

/* Shift Opcodes.  */
#define LSL 0
#define LSR 1
#define ASR 2
#define ROR 3

/* Macros to twiddle the status flags and mode.  */
#define NBIT ((unsigned)1L << 31)
#define ZBIT (1L << 30)
#define CBIT (1L << 29)
#define VBIT (1L << 28)
#define SBIT (1L << 27)
#define GE0 (1L << 16)
#define GE1 (1L << 17)
#define GE2 (1L << 18)
#define GE3 (1L << 19)
#define IBIT (1L << 7)
#define FBIT (1L << 6)
#define IFBITS (3L << 6)
#define R15IBIT (1L << 27)
#define R15FBIT (1L << 26)
#define R15IFBITS (3L << 26)

#define POS(i) ( (~(i)) >> 31 )
#define NEG(i) ( (i) >> 31 )

#ifdef MODET			/* Thumb support.  */
/* ??? This bit is actually in the low order bit of the PC in the hardware.
   It isn't clear if the simulator needs to model that or not.  */
#define TBIT (1L << 5)
#define TFLAG state->TFlag
#define SETT state->TFlag = 1
#define CLEART state->TFlag = 0
#define ASSIGNT(res) state->TFlag = res
#define INSN_SIZE (TFLAG ? 2 : 4)
#else
#define INSN_SIZE 4
#endif

#define NFLAG state->NFlag
#define SETN state->NFlag = 1
#define CLEARN state->NFlag = 0
#define ASSIGNN(res) state->NFlag = res

#define ZFLAG state->ZFlag
#define SETZ state->ZFlag = 1
#define CLEARZ state->ZFlag = 0
#define ASSIGNZ(res) state->ZFlag = res

#define CFLAG state->CFlag
#define SETC state->CFlag = 1
#define CLEARC state->CFlag = 0
#define ASSIGNC(res) state->CFlag = res

#define VFLAG state->VFlag
#define SETV state->VFlag = 1
#define CLEARV state->VFlag = 0
#define ASSIGNV(res) state->VFlag = res

#define SFLAG state->SFlag
#define SETS state->SFlag = 1
#define CLEARS state->SFlag = 0
#define ASSIGNS(res) state->SFlag = res

#define IFLAG (state->IFFlags >> 1)
#define FFLAG (state->IFFlags & 1)
#define IFFLAGS state->IFFlags
#define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3)
#define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ;

#define PSR_FBITS (0xff000000L)
#define PSR_SBITS (0x00ff0000L)
#define PSR_XBITS (0x0000ff00L)
#define PSR_CBITS (0x000000ffL)

#if defined MODE32 || defined MODET
#define CCBITS (0xf8000000L)
#else
#define CCBITS (0xf0000000L)
#endif

#define INTBITS (0xc0L)

#if defined MODET && defined MODE32
#define PCBITS (0xffffffffL)
#else
#define PCBITS (0xfffffffcL)
#endif

#define MODEBITS (0x1fL)
#define R15INTBITS (3L << 26)

#if defined MODET && defined MODE32
#define R15PCBITS (0x03ffffffL)
#else
#define R15PCBITS (0x03fffffcL)
#endif

#define R15PCMODEBITS (0x03ffffffL)
#define R15MODEBITS (0x3L)

#ifdef MODE32
#define PCMASK PCBITS
#define PCWRAP(pc) (pc)
#else
#define PCMASK R15PCBITS
#define PCWRAP(pc) ((pc) & R15PCBITS)
#endif

#define PC (state->Reg[15] & PCMASK)
#define R15CCINTMODE (state->Reg[15] & (CCBITS | R15INTBITS | R15MODEBITS))
#define R15INT (state->Reg[15] & R15INTBITS)
#define R15INTPC (state->Reg[15] & (R15INTBITS | R15PCBITS))
#define R15INTPCMODE (state->Reg[15] & (R15INTBITS | R15PCBITS | R15MODEBITS))
#define R15INTMODE (state->Reg[15] & (R15INTBITS | R15MODEBITS))
#define R15PC (state->Reg[15] & R15PCBITS)
#define R15PCMODE (state->Reg[15] & (R15PCBITS | R15MODEBITS))
#define R15MODE (state->Reg[15] & R15MODEBITS)

#define ECC ((NFLAG << 31) | (ZFLAG << 30) | (CFLAG << 29) | (VFLAG << 28) | (SFLAG << 27))
#define EINT (IFFLAGS << 6)
#define ER15INT (IFFLAGS << 26)
#define EMODE (state->Mode)

#ifdef MODET
#define CPSR (ECC | EINT | EMODE | (TFLAG << 5))
#else
#define CPSR (ECC | EINT | EMODE)
#endif

#ifdef MODE32
#define PATCHR15
#else
#define PATCHR15 state->Reg[15] = ECC | ER15INT | EMODE | R15PC
#endif

#define GETSPSR(bank) (ARMul_GetSPSR (state, EMODE))
#define SETPSR_F(d,s) d = ((d) & ~PSR_FBITS) | ((s) & PSR_FBITS)
#define SETPSR_S(d,s) d = ((d) & ~PSR_SBITS) | ((s) & PSR_SBITS)
#define SETPSR_X(d,s) d = ((d) & ~PSR_XBITS) | ((s) & PSR_XBITS)
#define SETPSR_C(d,s) d = ((d) & ~PSR_CBITS) | ((s) & PSR_CBITS)

#define SETR15PSR(s) 								\
  do										\
    {										\
      if (state->Mode == USER26MODE)						\
        {									\
          state->Reg[15] = ((s) & CCBITS) | R15PC | ER15INT | EMODE;		\
          ASSIGNN ((state->Reg[15] & NBIT) != 0);				\
          ASSIGNZ ((state->Reg[15] & ZBIT) != 0);				\
          ASSIGNC ((state->Reg[15] & CBIT) != 0);				\
          ASSIGNV ((state->Reg[15] & VBIT) != 0);				\
        }									\
      else									\
        {									\
          state->Reg[15] = R15PC | ((s) & (CCBITS | R15INTBITS | R15MODEBITS));	\
          ARMul_R15Altered (state);						\
       }									\
    }										\
  while (0)
     
#define SETABORT(i, m, d)						\
  do									\
    { 									\
      int SETABORT_mode = (m);						\
									\
      ARMul_SetSPSR (state, SETABORT_mode, ARMul_GetCPSR (state));	\
      ARMul_SetCPSR (state, ((ARMul_GetCPSR (state) & ~(EMODE | TBIT))	\
			     | (i) | SETABORT_mode));			\
      state->Reg[14] = temp - (d);					\
    }									\
  while (0)

#ifndef MODE32
#define VECTORS 0x20
#define LEGALADDR 0x03ffffff
#define VECTORACCESS(address) (address < VECTORS && ARMul_MODE26BIT && state->prog32Sig)
#define ADDREXCEPT(address)   (address > LEGALADDR && !state->data32Sig)
#endif

#define INTERNALABORT(address)			\
  do						\
    {						\
      if (address < VECTORS)			\
	state->Aborted = ARMul_DataAbortV;	\
      else					\
	state->Aborted = ARMul_AddrExceptnV;	\
    }						\
  while (0)

#ifdef MODE32
#define TAKEABORT ARMul_Abort (state, ARMul_DataAbortV)
#else
#define TAKEABORT 					\
  do							\
    {							\
      if (state->Aborted == ARMul_AddrExceptnV) 	\
	ARMul_Abort (state, ARMul_AddrExceptnV); 	\
      else 						\
	ARMul_Abort (state, ARMul_DataAbortV);		\
    }							\
  while (0)
#endif

#define CPTAKEABORT					\
  do							\
    {							\
      if (!state->Aborted)				\
	ARMul_Abort (state, ARMul_UndefinedInstrV); 	\
      else if (state->Aborted == ARMul_AddrExceptnV) 	\
	ARMul_Abort (state, ARMul_AddrExceptnV); 	\
      else 						\
	ARMul_Abort (state, ARMul_DataAbortV);		\
    }							\
  while (0);


/* Different ways to start the next instruction.  */
#define SEQ           0
#define NONSEQ        1
#define PCINCEDSEQ    2
#define PCINCEDNONSEQ 3
#define PRIMEPIPE     4
#define RESUME        8

#define NORMALCYCLE state->NextInstr = 0
#define BUSUSEDN    state->NextInstr |= 1  /* The next fetch will be an N cycle.  */
#define BUSUSEDINCPCS						\
  do								\
    {								\
      if (! state->is_v4)					\
        {							\
	  /* A standard PC inc and an S cycle.  */		\
	  state->Reg[15] += isize;				\
	  state->NextInstr = (state->NextInstr & 0xff) | 2;	\
	}							\
    }								\
  while (0)

#define BUSUSEDINCPCN					\
  do							\
    {							\
      if (state->is_v4)					\
	BUSUSEDN;					\
      else						\
	{						\
	  /* A standard PC inc and an N cycle.  */	\
	  state->Reg[15] += isize;			\
	  state->NextInstr |= 3;			\
	}						\
    }							\
  while (0)

#define INCPC 			\
  do				\
    {				\
      /* A standard PC inc.  */	\
      state->Reg[15] += isize;	\
      state->NextInstr |= 2;	\
    }				\
  while (0)

#define FLUSHPIPE state->NextInstr |= PRIMEPIPE

/* Cycle based emulation.  */

#define OUTPUTCP(i,a,b)
#define NCYCLE
#define SCYCLE
#define ICYCLE
#define CCYCLE
#define NEXTCYCLE(c)

/* Macros to extract parts of instructions.  */
#define DESTReg (BITS (12, 15))
#define LHSReg  (BITS (16, 19))
#define RHSReg  (BITS ( 0,  3))

#define DEST (state->Reg[DESTReg])

#ifdef MODE32
#ifdef MODET
#define LHS ((LHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC): (state->Reg[LHSReg]))
#else
#define LHS (state->Reg[LHSReg])
#endif
#else
#define LHS ((LHSReg == 15) ? R15PC : (state->Reg[LHSReg]))
#endif

#define MULDESTReg (BITS (16, 19))
#define MULLHSReg  (BITS ( 0,  3))
#define MULRHSReg  (BITS ( 8, 11))
#define MULACCReg  (BITS (12, 15))

#define DPImmRHS (ARMul_ImmedTable[BITS(0, 11)])
#define DPSImmRHS temp = BITS(0,11) ; \
                  rhs = ARMul_ImmedTable[temp] ; \
                  if (temp > 255) /* There was a shift.  */ \
                     ASSIGNC (rhs >> 31) ;

#ifdef MODE32
#define DPRegRHS  ((BITS (4,11) == 0) ? state->Reg[RHSReg] \
                                      : GetDPRegRHS (state, instr))
#define DPSRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \
                                      : GetDPSRegRHS (state, instr))
#else
#define DPRegRHS  ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
                                       : GetDPRegRHS (state, instr))
#define DPSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
                                       : GetDPSRegRHS (state, instr))
#endif

#define LSBase state->Reg[LHSReg]
#define LSImmRHS (BITS(0,11))

#ifdef MODE32
#define LSRegRHS ((BITS (4, 11) == 0) ? state->Reg[RHSReg] \
                                      : GetLSRegRHS (state, instr))
#else
#define LSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
                                      : GetLSRegRHS (state, instr))
#endif

#define LSMNumRegs ((ARMword) ARMul_BitList[BITS (0, 7)] + \
                    (ARMword) ARMul_BitList[BITS (8, 15)] )
#define LSMBaseFirst ((LHSReg == 0 && BIT (0)) || \
                      (BIT (LHSReg) && BITS (0, LHSReg - 1) == 0))

#define SWAPSRC (state->Reg[RHSReg])

#define LSCOff (BITS (0, 7) << 2)
#define CPNum   BITS (8, 11)

/* Determine if access to coprocessor CP is permitted.
   The XScale has a register in CP15 which controls access to CP0 - CP13.  */
#define CP_ACCESS_ALLOWED(STATE, CP)			\
    (   ((CP) >= 14)					\
     || (! (STATE)->is_XScale)				\
     || (read_cp15_reg (15, 0, 1) & (1 << (CP))))

/* Macro to rotate n right by b bits.  */
#define ROTATER(n, b) (((n) >> (b)) | ((n) << (32 - (b))))

/* Macros to store results of instructions.  */
#define WRITEDEST(d)				\
  do						\
    {						\
      if (DESTReg == 15) 			\
	WriteR15 (state, d); 			\
      else 					\
	DEST = d;				\
    }						\
  while (0)

#define WRITESDEST(d)				\
  do						\
    {						\
      if (DESTReg == 15)			\
	WriteSR15 (state, d);			\
      else					\
	{					\
	  DEST = d;				\
	  ARMul_NegZero (state, d);		\
	}					\
    }						\
  while (0)

#define WRITEDESTB(d)				\
  do						\
    {						\
      if (DESTReg == 15)			\
	WriteR15Load (state, d);		\
      else					\
	DEST = d;				\
    }						\
  while (0)

#define BYTETOBUS(data) ((data & 0xff) | \
                        ((data & 0xff) << 8) | \
                        ((data & 0xff) << 16) | \
                        ((data & 0xff) << 24))

#define BUSTOBYTE(address, data)				\
  do								\
    {								\
      if (state->bigendSig) 					\
	temp = (data >> (((address ^ 3) & 3) << 3)) & 0xff;	\
      else							\
	temp = (data >> ((address & 3) << 3)) & 0xff;		\
    }								\
  while (0)

#define LOADMULT(instr,   address, wb)  LoadMult   (state, instr, address, wb)
#define LOADSMULT(instr,  address, wb)  LoadSMult  (state, instr, address, wb)
#define STOREMULT(instr,  address, wb)  StoreMult  (state, instr, address, wb)
#define STORESMULT(instr, address, wb)  StoreSMult (state, instr, address, wb)

#define POSBRANCH ((instr & 0x7fffff) << 2)
#define NEGBRANCH ((0xff000000 |(instr & 0xffffff)) << 2)


/* Values for Emulate.  */
#define STOP            0	/* stop */
#define CHANGEMODE      1	/* change mode */
#define ONCE            2	/* execute just one interation */
#define RUN             3	/* continuous execution */

/* Stuff that is shared across modes.  */
extern unsigned ARMul_MultTable[];	/* Number of I cycles for a mult.  */
extern ARMword  ARMul_ImmedTable[];	/* Immediate DP LHS values.  */
extern char     ARMul_BitList[];	/* Number of bits in a byte table.  */

#define EVENTLISTSIZE 1024L

/* Thumb support.  */
typedef enum
{
  t_undefined,		/* Undefined Thumb instruction.  */
  t_decoded,		/* Instruction decoded to ARM equivalent.  */
  t_branch		/* Thumb branch (already processed).  */
}
tdstate;

#define t_resolved t_branch

/* Macros to scrutinize instructions.  The dummy do loop is to keep the compiler
   happy when the statement is used in an otherwise empty else statement.  */
#define UNDEF_Test		do { ; } while (0)
#define UNDEF_Shift		do { ; } while (0)
#define UNDEF_MSRPC		do { ; } while (0)
#define UNDEF_MRSPC		do { ; } while (0)
#define UNDEF_MULPCDest		do { ; } while (0)
#define UNDEF_MULDestEQOp1	do { ; } while (0)
#define UNDEF_LSRBPC		do { ; } while (0)
#define UNDEF_LSRBaseEQOffWb	do { ; } while (0)
#define UNDEF_LSRBaseEQDestWb	do { ; } while (0)
#define UNDEF_LSRPCBaseWb	do { ; } while (0)
#define UNDEF_LSRPCOffWb	do { ; } while (0)
#define UNDEF_LSMNoRegs		do { ; } while (0)
#define UNDEF_LSMPCBase		do { ; } while (0)
#define UNDEF_LSMUserBankWb	do { ; } while (0)
#define UNDEF_LSMBaseInListWb	do { ; } while (0)
#define UNDEF_SWPPC		do { ; } while (0)
#define UNDEF_CoProHS		do { ; } while (0)
#define UNDEF_MCRPC		do { ; } while (0)
#define UNDEF_LSCPCBaseWb	do { ; } while (0)
#define UNDEF_UndefNotBounced	do { ; } while (0)
#define UNDEF_ShortInt		do { ; } while (0)
#define UNDEF_IllegalMode	do { ; } while (0)
#define UNDEF_Prog32SigChange	do { ; } while (0)
#define UNDEF_Data32SigChange	do { ; } while (0)

/* Prototypes for exported functions.  */
extern unsigned ARMul_NthReg        (ARMword, unsigned);
extern int      AddOverflow         (ARMword, ARMword, ARMword);
extern int      SubOverflow         (ARMword, ARMword, ARMword);
extern ARMword  ARMul_Emulate26     (ARMul_State *);
extern ARMword  ARMul_Emulate32     (ARMul_State *);
extern unsigned IntPending          (ARMul_State *);
extern void     ARMul_CPSRAltered   (ARMul_State *);
extern void     ARMul_R15Altered    (ARMul_State *);
extern ARMword  ARMul_GetPC         (ARMul_State *);
extern ARMword  ARMul_GetNextPC     (ARMul_State *);
extern ARMword  ARMul_GetR15        (ARMul_State *);
extern ARMword  ARMul_GetCPSR       (ARMul_State *);
extern void     ARMul_EnvokeEvent   (ARMul_State *);
extern unsigned long ARMul_Time     (ARMul_State *);
extern void     ARMul_NegZero       (ARMul_State *, ARMword);
extern void     ARMul_SetPC         (ARMul_State *, ARMword);
extern void     ARMul_SetR15        (ARMul_State *, ARMword);
extern void     ARMul_SetCPSR       (ARMul_State *, ARMword);
extern ARMword  ARMul_GetSPSR       (ARMul_State *, ARMword);
extern void     ARMul_Abort26       (ARMul_State *, ARMword);
extern void     ARMul_Abort32       (ARMul_State *, ARMword);
extern ARMword  ARMul_MRC           (ARMul_State *, ARMword);
extern void     ARMul_CDP           (ARMul_State *, ARMword);
extern void     ARMul_LDC           (ARMul_State *, ARMword, ARMword);
extern void     ARMul_STC           (ARMul_State *, ARMword, ARMword);
extern void     ARMul_MCR           (ARMul_State *, ARMword, ARMword);
extern void     ARMul_SetSPSR       (ARMul_State *, ARMword, ARMword);
extern ARMword  ARMul_SwitchMode    (ARMul_State *, ARMword, ARMword);
extern ARMword  ARMul_Align         (ARMul_State *, ARMword, ARMword);
extern ARMword  ARMul_SwitchMode    (ARMul_State *, ARMword, ARMword);
extern void     ARMul_MSRCpsr       (ARMul_State *, ARMword, ARMword);
extern void     ARMul_SubOverflow   (ARMul_State *, ARMword, ARMword, ARMword);
extern void     ARMul_AddOverflow   (ARMul_State *, ARMword, ARMword, ARMword);
extern void     ARMul_SubCarry      (ARMul_State *, ARMword, ARMword, ARMword);
extern void     ARMul_AddCarry      (ARMul_State *, ARMword, ARMword, ARMword);
extern tdstate  ARMul_ThumbDecode   (ARMul_State *, ARMword, ARMword, ARMword *);
extern ARMword  ARMul_GetReg        (ARMul_State *, unsigned, unsigned);
extern void     ARMul_SetReg        (ARMul_State *, unsigned, unsigned, ARMword);
extern void     ARMul_ScheduleEvent (ARMul_State *, unsigned long, unsigned (*) (ARMul_State *));
/* Coprocessor support functions.  */
extern unsigned ARMul_CoProInit     (ARMul_State *);
extern void     ARMul_CoProExit     (ARMul_State *);
extern void     ARMul_CoProAttach   (ARMul_State *, unsigned, ARMul_CPInits *, ARMul_CPExits *,
				     ARMul_LDCs *, ARMul_STCs *, ARMul_MRCs *, ARMul_MCRs *,
				     ARMul_CDPs *, ARMul_CPReads *, ARMul_CPWrites *);
extern void     ARMul_CoProDetach   (ARMul_State *, unsigned);
extern ARMword  read_cp15_reg       (unsigned, unsigned, unsigned);

extern unsigned DSPLDC4 (ARMul_State *, unsigned, ARMword, ARMword);
extern unsigned DSPMCR4 (ARMul_State *, unsigned, ARMword, ARMword);
extern unsigned DSPMRC4 (ARMul_State *, unsigned, ARMword, ARMword *);
extern unsigned	DSPSTC4 (ARMul_State *, unsigned, ARMword, ARMword *);
extern unsigned	DSPCDP4 (ARMul_State *, unsigned, ARMword);
extern unsigned DSPMCR5 (ARMul_State *, unsigned, ARMword, ARMword);
extern unsigned DSPMRC5 (ARMul_State *, unsigned, ARMword, ARMword *);
extern unsigned DSPLDC5 (ARMul_State *, unsigned, ARMword, ARMword);
extern unsigned	DSPSTC5 (ARMul_State *, unsigned, ARMword, ARMword *);
extern unsigned	DSPCDP5 (ARMul_State *, unsigned, ARMword);
extern unsigned DSPMCR6 (ARMul_State *, unsigned, ARMword, ARMword);
extern unsigned DSPMRC6 (ARMul_State *, unsigned, ARMword, ARMword *);
extern unsigned	DSPCDP6 (ARMul_State *, unsigned, ARMword);
Commit	Line	Data
c906108c SS	1	/* armemu.h -- ARMulator emulation macros: ARM6 Instruction Emulator.
	2	Copyright (C) 1994 Advanced RISC Machines Ltd.
	3
	4	This program is free software; you can redistribute it and/or modify
	5	it under the terms of the GNU General Public License as published by
3fd725ef	6	the Free Software Foundation; either version 3 of the License, or
c906108c SS	7	(at your option) any later version.
	8
	9	This program is distributed in the hope that it will be useful,
	10	but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	GNU General Public License for more details.
	13
	14	You should have received a copy of the GNU General Public License
51b318de	15	along with this program; if not, see <http://www.gnu.org/licenses/>. */
c906108c SS	16
c906108c SS	17	extern ARMword isize;
8d052926 NC	18	extern int trace;
	19	extern int disas;
	20	extern int trace_funcs;
	21	extern void print_insn (ARMword);
c906108c	22
ff44f8e3	23	/* Condition code values. */
c906108c SS	24	#define EQ 0
	25	#define NE 1
	26	#define CS 2
	27	#define CC 3
	28	#define MI 4
	29	#define PL 5
	30	#define VS 6
	31	#define VC 7
	32	#define HI 8
	33	#define LS 9
	34	#define GE 10
	35	#define LT 11
	36	#define GT 12
	37	#define LE 13
	38	#define AL 14
	39	#define NV 15
	40
ff44f8e3	41	/* Shift Opcodes. */
c906108c SS	42	#define LSL 0
	43	#define LSR 1
	44	#define ASR 2
	45	#define ROR 3
	46
ff44f8e3	47	/* Macros to twiddle the status flags and mode. */
c906108c SS	48	#define NBIT ((unsigned)1L << 31)
	49	#define ZBIT (1L << 30)
	50	#define CBIT (1L << 29)
	51	#define VBIT (1L << 28)
f1129fb8	52	#define SBIT (1L << 27)
8d052926 NC	53	#define GE0 (1L << 16)
	54	#define GE1 (1L << 17)
	55	#define GE2 (1L << 18)
	56	#define GE3 (1L << 19)
c906108c SS	57	#define IBIT (1L << 7)
	58	#define FBIT (1L << 6)
	59	#define IFBITS (3L << 6)
	60	#define R15IBIT (1L << 27)
	61	#define R15FBIT (1L << 26)
	62	#define R15IFBITS (3L << 26)
	63
	64	#define POS(i) ( (~(i)) >> 31 )
	65	#define NEG(i) ( (i) >> 31 )
	66
ff44f8e3	67	#ifdef MODET /* Thumb support. */
c906108c SS	68	/* ??? This bit is actually in the low order bit of the PC in the hardware.
	69	It isn't clear if the simulator needs to model that or not. */
	70	#define TBIT (1L << 5)
	71	#define TFLAG state->TFlag
	72	#define SETT state->TFlag = 1
	73	#define CLEART state->TFlag = 0
	74	#define ASSIGNT(res) state->TFlag = res
e063aa3b AO	75	#define INSN_SIZE (TFLAG ? 2 : 4)
	76	#else
	77	#define INSN_SIZE 4
c906108c SS	78	#endif
	79
	80	#define NFLAG state->NFlag
	81	#define SETN state->NFlag = 1
	82	#define CLEARN state->NFlag = 0
	83	#define ASSIGNN(res) state->NFlag = res
	84
	85	#define ZFLAG state->ZFlag
	86	#define SETZ state->ZFlag = 1
	87	#define CLEARZ state->ZFlag = 0
	88	#define ASSIGNZ(res) state->ZFlag = res
	89
	90	#define CFLAG state->CFlag
	91	#define SETC state->CFlag = 1
	92	#define CLEARC state->CFlag = 0
	93	#define ASSIGNC(res) state->CFlag = res
	94
	95	#define VFLAG state->VFlag
	96	#define SETV state->VFlag = 1
	97	#define CLEARV state->VFlag = 0
	98	#define ASSIGNV(res) state->VFlag = res
	99
f1129fb8 NC	100	#define SFLAG state->SFlag
	101	#define SETS state->SFlag = 1
	102	#define CLEARS state->SFlag = 0
	103	#define ASSIGNS(res) state->SFlag = res
f743149e	104
c906108c SS	105	#define IFLAG (state->IFFlags >> 1)
	106	#define FFLAG (state->IFFlags & 1)
	107	#define IFFLAGS state->IFFlags
	108	#define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3)
	109	#define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ;
	110
4ef2594f AO	111	#define PSR_FBITS (0xff000000L)
	112	#define PSR_SBITS (0x00ff0000L)
	113	#define PSR_XBITS (0x0000ff00L)
	114	#define PSR_CBITS (0x000000ffL)
	115
f1129fb8 NC	116	#if defined MODE32 \|\| defined MODET
	117	#define CCBITS (0xf8000000L)
	118	#else
c906108c	119	#define CCBITS (0xf0000000L)
f1129fb8 NC	120	#endif
f1129fb8 NC	121
c906108c SS	122	#define INTBITS (0xc0L)
	123
	124	#if defined MODET && defined MODE32
	125	#define PCBITS (0xffffffffL)
	126	#else
	127	#define PCBITS (0xfffffffcL)
	128	#endif
	129
	130	#define MODEBITS (0x1fL)
	131	#define R15INTBITS (3L << 26)
	132
	133	#if defined MODET && defined MODE32
	134	#define R15PCBITS (0x03ffffffL)
	135	#else
	136	#define R15PCBITS (0x03fffffcL)
	137	#endif
	138
	139	#define R15PCMODEBITS (0x03ffffffL)
	140	#define R15MODEBITS (0x3L)
	141
	142	#ifdef MODE32
	143	#define PCMASK PCBITS
	144	#define PCWRAP(pc) (pc)
	145	#else
	146	#define PCMASK R15PCBITS
	147	#define PCWRAP(pc) ((pc) & R15PCBITS)
	148	#endif
	149
	150	#define PC (state->Reg[15] & PCMASK)
	151	#define R15CCINTMODE (state->Reg[15] & (CCBITS \| R15INTBITS \| R15MODEBITS))
	152	#define R15INT (state->Reg[15] & R15INTBITS)
	153	#define R15INTPC (state->Reg[15] & (R15INTBITS \| R15PCBITS))
	154	#define R15INTPCMODE (state->Reg[15] & (R15INTBITS \| R15PCBITS \| R15MODEBITS))
	155	#define R15INTMODE (state->Reg[15] & (R15INTBITS \| R15MODEBITS))
	156	#define R15PC (state->Reg[15] & R15PCBITS)
	157	#define R15PCMODE (state->Reg[15] & (R15PCBITS \| R15MODEBITS))
	158	#define R15MODE (state->Reg[15] & R15MODEBITS)
	159
f1129fb8	160	#define ECC ((NFLAG << 31) \| (ZFLAG << 30) \| (CFLAG << 29) \| (VFLAG << 28) \| (SFLAG << 27))
c906108c SS	161	#define EINT (IFFLAGS << 6)
	162	#define ER15INT (IFFLAGS << 26)
	163	#define EMODE (state->Mode)
	164
	165	#ifdef MODET
	166	#define CPSR (ECC \| EINT \| EMODE \| (TFLAG << 5))
	167	#else
	168	#define CPSR (ECC \| EINT \| EMODE)
	169	#endif
	170
	171	#ifdef MODE32
	172	#define PATCHR15
	173	#else
	174	#define PATCHR15 state->Reg[15] = ECC \| ER15INT \| EMODE \| R15PC
	175	#endif
	176
cf52c765	177	#define GETSPSR(bank) (ARMul_GetSPSR (state, EMODE))
4ef2594f AO	178	#define SETPSR_F(d,s) d = ((d) & ~PSR_FBITS) \| ((s) & PSR_FBITS)
	179	#define SETPSR_S(d,s) d = ((d) & ~PSR_SBITS) \| ((s) & PSR_SBITS)
	180	#define SETPSR_X(d,s) d = ((d) & ~PSR_XBITS) \| ((s) & PSR_XBITS)
	181	#define SETPSR_C(d,s) d = ((d) & ~PSR_CBITS) \| ((s) & PSR_CBITS)
ff44f8e3 NC	182
	183	#define SETR15PSR(s) \
	184	do \
	185	{ \
	186	if (state->Mode == USER26MODE) \
	187	{ \
	188	state->Reg[15] = ((s) & CCBITS) \| R15PC \| ER15INT \| EMODE; \
	189	ASSIGNN ((state->Reg[15] & NBIT) != 0); \
	190	ASSIGNZ ((state->Reg[15] & ZBIT) != 0); \
	191	ASSIGNC ((state->Reg[15] & CBIT) != 0); \
	192	ASSIGNV ((state->Reg[15] & VBIT) != 0); \
	193	} \
	194	else \
	195	{ \
	196	state->Reg[15] = R15PC \| ((s) & (CCBITS \| R15INTBITS \| R15MODEBITS)); \
	197	ARMul_R15Altered (state); \
	198	} \
	199	} \
	200	while (0)
	201
	202	#define SETABORT(i, m, d) \
	203	do \
	204	{ \
	205	int SETABORT_mode = (m); \
	206	\
	207	ARMul_SetSPSR (state, SETABORT_mode, ARMul_GetCPSR (state)); \
	208	ARMul_SetCPSR (state, ((ARMul_GetCPSR (state) & ~(EMODE \| TBIT)) \
	209	\| (i) \| SETABORT_mode)); \
	210	state->Reg[14] = temp - (d); \
	211	} \
	212	while (0)
c906108c SS	213
	214	#ifndef MODE32
	215	#define VECTORS 0x20
	216	#define LEGALADDR 0x03ffffff
	217	#define VECTORACCESS(address) (address < VECTORS && ARMul_MODE26BIT && state->prog32Sig)
ff44f8e3	218	#define ADDREXCEPT(address) (address > LEGALADDR && !state->data32Sig)
c906108c SS	219	#endif
c906108c SS	220
ff44f8e3 NC	221	#define INTERNALABORT(address) \
	222	do \
	223	{ \
	224	if (address < VECTORS) \
	225	state->Aborted = ARMul_DataAbortV; \
	226	else \
	227	state->Aborted = ARMul_AddrExceptnV; \
	228	} \
	229	while (0)
c906108c SS	230
c906108c SS	231	#ifdef MODE32
ff44f8e3	232	#define TAKEABORT ARMul_Abort (state, ARMul_DataAbortV)
c906108c	233	#else
ff44f8e3 NC	234	#define TAKEABORT \
	235	do \
	236	{ \
	237	if (state->Aborted == ARMul_AddrExceptnV) \
	238	ARMul_Abort (state, ARMul_AddrExceptnV); \
	239	else \
	240	ARMul_Abort (state, ARMul_DataAbortV); \
	241	} \
	242	while (0)
c906108c	243	#endif
c906108c	244
ff44f8e3 NC	245	#define CPTAKEABORT \
	246	do \
	247	{ \
	248	if (!state->Aborted) \
	249	ARMul_Abort (state, ARMul_UndefinedInstrV); \
	250	else if (state->Aborted == ARMul_AddrExceptnV) \
	251	ARMul_Abort (state, ARMul_AddrExceptnV); \
	252	else \
	253	ARMul_Abort (state, ARMul_DataAbortV); \
	254	} \
	255	while (0);
	256
	257
	258	/* Different ways to start the next instruction. */
	259	#define SEQ 0
	260	#define NONSEQ 1
	261	#define PCINCEDSEQ 2
c906108c	262	#define PCINCEDNONSEQ 3
ff44f8e3 NC	263	#define PRIMEPIPE 4
ff44f8e3 NC	264	#define RESUME 8
c906108c SS	265
c906108c SS	266	#define NORMALCYCLE state->NextInstr = 0
3943c96b	267	#define BUSUSEDN state->NextInstr \|= 1 /* The next fetch will be an N cycle. */
ff44f8e3 NC	268	#define BUSUSEDINCPCS \
	269	do \
	270	{ \
	271	if (! state->is_v4) \
	272	{ \
	273	/* A standard PC inc and an S cycle. */ \
	274	state->Reg[15] += isize; \
	275	state->NextInstr = (state->NextInstr & 0xff) \| 2; \
	276	} \
	277	} \
3943c96b	278	while (0)
ff44f8e3 NC	279
	280	#define BUSUSEDINCPCN \
	281	do \
	282	{ \
	283	if (state->is_v4) \
	284	BUSUSEDN; \
	285	else \
	286	{ \
	287	/* A standard PC inc and an N cycle. */ \
	288	state->Reg[15] += isize; \
	289	state->NextInstr \|= 3; \
	290	} \
	291	} \
3943c96b	292	while (0)
ff44f8e3 NC	293
	294	#define INCPC \
	295	do \
	296	{ \
	297	/* A standard PC inc. */ \
	298	state->Reg[15] += isize; \
	299	state->NextInstr \|= 2; \
	300	} \
	301	while (0)
	302
c906108c SS	303	#define FLUSHPIPE state->NextInstr \|= PRIMEPIPE
c906108c SS	304
ff44f8e3	305	/* Cycle based emulation. */
c906108c SS	306
	307	#define OUTPUTCP(i,a,b)
	308	#define NCYCLE
	309	#define SCYCLE
	310	#define ICYCLE
	311	#define CCYCLE
	312	#define NEXTCYCLE(c)
	313
ff44f8e3	314	/* Macros to extract parts of instructions. */
57165fb4 NC	315	#define DESTReg (BITS (12, 15))
	316	#define LHSReg (BITS (16, 19))
	317	#define RHSReg (BITS ( 0, 3))
c906108c SS	318
	319	#define DEST (state->Reg[DESTReg])
	320
	321	#ifdef MODE32
	322	#ifdef MODET
	323	#define LHS ((LHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC): (state->Reg[LHSReg]))
	324	#else
	325	#define LHS (state->Reg[LHSReg])
	326	#endif
	327	#else
ff44f8e3	328	#define LHS ((LHSReg == 15) ? R15PC : (state->Reg[LHSReg]))
c906108c SS	329	#endif
c906108c SS	330
ff44f8e3 NC	331	#define MULDESTReg (BITS (16, 19))
	332	#define MULLHSReg (BITS ( 0, 3))
	333	#define MULRHSReg (BITS ( 8, 11))
	334	#define MULACCReg (BITS (12, 15))
c906108c	335
ff44f8e3	336	#define DPImmRHS (ARMul_ImmedTable[BITS(0, 11)])
c906108c SS	337	#define DPSImmRHS temp = BITS(0,11) ; \
c906108c SS	338	rhs = ARMul_ImmedTable[temp] ; \
ff44f8e3 NC	339	if (temp > 255) /* There was a shift. */ \
ff44f8e3 NC	340	ASSIGNC (rhs >> 31) ;
c906108c SS	341
c906108c SS	342	#ifdef MODE32
ff44f8e3 NC	343	#define DPRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \
	344	: GetDPRegRHS (state, instr))
	345	#define DPSRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \
	346	: GetDPSRegRHS (state, instr))
c906108c	347	#else
ff44f8e3 NC	348	#define DPRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
	349	: GetDPRegRHS (state, instr))
	350	#define DPSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
	351	: GetDPSRegRHS (state, instr))
c906108c SS	352	#endif
	353
	354	#define LSBase state->Reg[LHSReg]
	355	#define LSImmRHS (BITS(0,11))
	356
	357	#ifdef MODE32
ff44f8e3 NC	358	#define LSRegRHS ((BITS (4, 11) == 0) ? state->Reg[RHSReg] \
ff44f8e3 NC	359	: GetLSRegRHS (state, instr))
c906108c	360	#else
ff44f8e3 NC	361	#define LSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
ff44f8e3 NC	362	: GetLSRegRHS (state, instr))
c906108c SS	363	#endif
c906108c SS	364
ff44f8e3 NC	365	#define LSMNumRegs ((ARMword) ARMul_BitList[BITS (0, 7)] + \
	366	(ARMword) ARMul_BitList[BITS (8, 15)] )
	367	#define LSMBaseFirst ((LHSReg == 0 && BIT (0)) \|\| \
	368	(BIT (LHSReg) && BITS (0, LHSReg - 1) == 0))
c906108c SS	369
	370	#define SWAPSRC (state->Reg[RHSReg])
	371
ff44f8e3 NC	372	#define LSCOff (BITS (0, 7) << 2)
ff44f8e3 NC	373	#define CPNum BITS (8, 11)
c906108c	374
ff44f8e3 NC	375	/* Determine if access to coprocessor CP is permitted.
ff44f8e3 NC	376	The XScale has a register in CP15 which controls access to CP0 - CP13. */
57165fb4 NC	377	#define CP_ACCESS_ALLOWED(STATE, CP) \
	378	( ((CP) >= 14) \
	379	\|\| (! (STATE)->is_XScale) \
ff44f8e3	380	\|\| (read_cp15_reg (15, 0, 1) & (1 << (CP))))
c906108c	381
ff44f8e3 NC	382	/* Macro to rotate n right by b bits. */
ff44f8e3 NC	383	#define ROTATER(n, b) (((n) >> (b)) \| ((n) << (32 - (b))))
c906108c	384
ff44f8e3	385	/* Macros to store results of instructions. */
57165fb4 NC	386	#define WRITEDEST(d) \
	387	do \
	388	{ \
	389	if (DESTReg == 15) \
	390	WriteR15 (state, d); \
	391	else \
	392	DEST = d; \
	393	} \
	394	while (0)
	395
	396	#define WRITESDEST(d) \
	397	do \
	398	{ \
	399	if (DESTReg == 15) \
	400	WriteSR15 (state, d); \
	401	else \
	402	{ \
	403	DEST = d; \
	404	ARMul_NegZero (state, d); \
	405	} \
	406	} \
	407	while (0)
	408
	409	#define WRITEDESTB(d) \
	410	do \
	411	{ \
	412	if (DESTReg == 15) \
b9366cf3	413	WriteR15Load (state, d); \
57165fb4 NC	414	else \
	415	DEST = d; \
	416	} \
	417	while (0)
892c6b9d	418
c906108c SS	419	#define BYTETOBUS(data) ((data & 0xff) \| \
	420	((data & 0xff) << 8) \| \
	421	((data & 0xff) << 16) \| \
	422	((data & 0xff) << 24))
ff44f8e3	423
57165fb4 NC	424	#define BUSTOBYTE(address, data) \
	425	do \
	426	{ \
	427	if (state->bigendSig) \
	428	temp = (data >> (((address ^ 3) & 3) << 3)) & 0xff; \
	429	else \
	430	temp = (data >> ((address & 3) << 3)) & 0xff; \
	431	} \
	432	while (0)
c906108c	433
ff44f8e3 NC	434	#define LOADMULT(instr, address, wb) LoadMult (state, instr, address, wb)
	435	#define LOADSMULT(instr, address, wb) LoadSMult (state, instr, address, wb)
	436	#define STOREMULT(instr, address, wb) StoreMult (state, instr, address, wb)
	437	#define STORESMULT(instr, address, wb) StoreSMult (state, instr, address, wb)
c906108c SS	438
c906108c SS	439	#define POSBRANCH ((instr & 0x7fffff) << 2)
179ae6ea NC	440	#define NEGBRANCH ((0xff000000 \|(instr & 0xffffff)) << 2)
179ae6ea NC	441
c906108c	442
ff44f8e3	443	/* Values for Emulate. */
dfcd3bfb JM	444	#define STOP 0 /* stop */
	445	#define CHANGEMODE 1 /* change mode */
	446	#define ONCE 2 /* execute just one interation */
	447	#define RUN 3 /* continuous execution */
c906108c	448
ff44f8e3 NC	449	/* Stuff that is shared across modes. */
	450	extern unsigned ARMul_MultTable[]; /* Number of I cycles for a mult. */
	451	extern ARMword ARMul_ImmedTable[]; /* Immediate DP LHS values. */
	452	extern char ARMul_BitList[]; /* Number of bits in a byte table. */
c906108c	453
ff44f8e3	454	#define EVENTLISTSIZE 1024L
c906108c	455
ff44f8e3	456	/* Thumb support. */
dfcd3bfb JM	457	typedef enum
dfcd3bfb JM	458	{
ff44f8e3 NC	459	t_undefined, /* Undefined Thumb instruction. */
	460	t_decoded, /* Instruction decoded to ARM equivalent. */
	461	t_branch /* Thumb branch (already processed). */
dfcd3bfb JM	462	}
dfcd3bfb JM	463	tdstate;
c906108c	464
73cb0348 NC	465	#define t_resolved t_branch
73cb0348 NC	466
58b991b1 MF	467	/* Macros to scrutinize instructions. The dummy do loop is to keep the compiler
	468	happy when the statement is used in an otherwise empty else statement. */
	469	#define UNDEF_Test do { ; } while (0)
	470	#define UNDEF_Shift do { ; } while (0)
	471	#define UNDEF_MSRPC do { ; } while (0)
	472	#define UNDEF_MRSPC do { ; } while (0)
	473	#define UNDEF_MULPCDest do { ; } while (0)
	474	#define UNDEF_MULDestEQOp1 do { ; } while (0)
	475	#define UNDEF_LSRBPC do { ; } while (0)
	476	#define UNDEF_LSRBaseEQOffWb do { ; } while (0)
	477	#define UNDEF_LSRBaseEQDestWb do { ; } while (0)
	478	#define UNDEF_LSRPCBaseWb do { ; } while (0)
	479	#define UNDEF_LSRPCOffWb do { ; } while (0)
	480	#define UNDEF_LSMNoRegs do { ; } while (0)
	481	#define UNDEF_LSMPCBase do { ; } while (0)
	482	#define UNDEF_LSMUserBankWb do { ; } while (0)
	483	#define UNDEF_LSMBaseInListWb do { ; } while (0)
	484	#define UNDEF_SWPPC do { ; } while (0)
	485	#define UNDEF_CoProHS do { ; } while (0)
	486	#define UNDEF_MCRPC do { ; } while (0)
	487	#define UNDEF_LSCPCBaseWb do { ; } while (0)
	488	#define UNDEF_UndefNotBounced do { ; } while (0)
	489	#define UNDEF_ShortInt do { ; } while (0)
	490	#define UNDEF_IllegalMode do { ; } while (0)
	491	#define UNDEF_Prog32SigChange do { ; } while (0)
	492	#define UNDEF_Data32SigChange do { ; } while (0)
f1129fb8	493
ff44f8e3 NC	494	/* Prototypes for exported functions. */
	495	extern unsigned ARMul_NthReg (ARMword, unsigned);
	496	extern int AddOverflow (ARMword, ARMword, ARMword);
	497	extern int SubOverflow (ARMword, ARMword, ARMword);
	498	extern ARMword ARMul_Emulate26 (ARMul_State *);
	499	extern ARMword ARMul_Emulate32 (ARMul_State *);
	500	extern unsigned IntPending (ARMul_State *);
	501	extern void ARMul_CPSRAltered (ARMul_State *);
	502	extern void ARMul_R15Altered (ARMul_State *);
	503	extern ARMword ARMul_GetPC (ARMul_State *);
	504	extern ARMword ARMul_GetNextPC (ARMul_State *);
	505	extern ARMword ARMul_GetR15 (ARMul_State *);
	506	extern ARMword ARMul_GetCPSR (ARMul_State *);
	507	extern void ARMul_EnvokeEvent (ARMul_State *);
	508	extern unsigned long ARMul_Time (ARMul_State *);
	509	extern void ARMul_NegZero (ARMul_State *, ARMword);
	510	extern void ARMul_SetPC (ARMul_State *, ARMword);
	511	extern void ARMul_SetR15 (ARMul_State *, ARMword);
	512	extern void ARMul_SetCPSR (ARMul_State *, ARMword);
	513	extern ARMword ARMul_GetSPSR (ARMul_State *, ARMword);
	514	extern void ARMul_Abort26 (ARMul_State *, ARMword);
	515	extern void ARMul_Abort32 (ARMul_State *, ARMword);
	516	extern ARMword ARMul_MRC (ARMul_State *, ARMword);
	517	extern void ARMul_CDP (ARMul_State *, ARMword);
	518	extern void ARMul_LDC (ARMul_State *, ARMword, ARMword);
	519	extern void ARMul_STC (ARMul_State *, ARMword, ARMword);
	520	extern void ARMul_MCR (ARMul_State *, ARMword, ARMword);
	521	extern void ARMul_SetSPSR (ARMul_State *, ARMword, ARMword);
	522	extern ARMword ARMul_SwitchMode (ARMul_State *, ARMword, ARMword);
	523	extern ARMword ARMul_Align (ARMul_State *, ARMword, ARMword);
	524	extern ARMword ARMul_SwitchMode (ARMul_State *, ARMword, ARMword);
	525	extern void ARMul_MSRCpsr (ARMul_State *, ARMword, ARMword);
	526	extern void ARMul_SubOverflow (ARMul_State *, ARMword, ARMword, ARMword);
	527	extern void ARMul_AddOverflow (ARMul_State *, ARMword, ARMword, ARMword);
	528	extern void ARMul_SubCarry (ARMul_State *, ARMword, ARMword, ARMword);
	529	extern void ARMul_AddCarry (ARMul_State *, ARMword, ARMword, ARMword);
	530	extern tdstate ARMul_ThumbDecode (ARMul_State , ARMword, ARMword, ARMword );
	531	extern ARMword ARMul_GetReg (ARMul_State *, unsigned, unsigned);
	532	extern void ARMul_SetReg (ARMul_State *, unsigned, unsigned, ARMword);
	533	extern void ARMul_ScheduleEvent (ARMul_State , unsigned long, unsigned () (ARMul_State *));
f1129fb8	534	/* Coprocessor support functions. */
ff44f8e3 NC	535	extern unsigned ARMul_CoProInit (ARMul_State *);
	536	extern void ARMul_CoProExit (ARMul_State *);
	537	extern void ARMul_CoProAttach (ARMul_State , unsigned, ARMul_CPInits , ARMul_CPExits *,
	538	ARMul_LDCs , ARMul_STCs , ARMul_MRCs , ARMul_MCRs ,
	539	ARMul_CDPs , ARMul_CPReads , ARMul_CPWrites *);
	540	extern void ARMul_CoProDetach (ARMul_State *, unsigned);
	541	extern ARMword read_cp15_reg (unsigned, unsigned, unsigned);
	542
f603c8fe NC	543	extern unsigned DSPLDC4 (ARMul_State *, unsigned, ARMword, ARMword);
	544	extern unsigned DSPMCR4 (ARMul_State *, unsigned, ARMword, ARMword);
	545	extern unsigned DSPMRC4 (ARMul_State , unsigned, ARMword, ARMword );
	546	extern unsigned DSPSTC4 (ARMul_State , unsigned, ARMword, ARMword );
	547	extern unsigned DSPCDP4 (ARMul_State *, unsigned, ARMword);
	548	extern unsigned DSPMCR5 (ARMul_State *, unsigned, ARMword, ARMword);
	549	extern unsigned DSPMRC5 (ARMul_State , unsigned, ARMword, ARMword );
	550	extern unsigned DSPLDC5 (ARMul_State *, unsigned, ARMword, ARMword);
	551	extern unsigned DSPSTC5 (ARMul_State , unsigned, ARMword, ARMword );
	552	extern unsigned DSPCDP5 (ARMul_State *, unsigned, ARMword);
	553	extern unsigned DSPMCR6 (ARMul_State *, unsigned, ARMword, ARMword);
	554	extern unsigned DSPMRC6 (ARMul_State , unsigned, ARMword, ARMword );
	555	extern unsigned DSPCDP6 (ARMul_State *, unsigned, ARMword);