[deliverable/binutils-gdb.git] / sim / arm / armvirt.c

/*  armvirt.c -- ARMulator virtual memory interace:  ARM6 Instruction Emulator.
    Copyright (C) 1994 Advanced RISC Machines Ltd.

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 3 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program; if not, see <http://www.gnu.org/licenses/>. */

/* This file contains a complete ARMulator memory model, modelling a
   "virtual memory" system. A much simpler model can be found in armfast.c,
   and that model goes faster too, but has a fixed amount of memory. This
   model's memory has 64K pages, allocated on demand from a 64K entry page
   table. The routines PutWord and GetWord implement this. Pages are never
   freed as they might be needed again. A single area of memory may be
   defined to generate aborts.  */

#include "armos.h"
#include "armdefs.h"
#include "ansidecl.h"

#ifdef VALIDATE			/* for running the validate suite */
#define TUBE 48 * 1024 * 1024	/* write a char on the screen */
#define ABORTS 1
#endif

/* #define ABORTS */

#ifdef ABORTS			/* the memory system will abort */
/* For the old test suite Abort between 32 Kbytes and 32 Mbytes
   For the new test suite Abort between 8 Mbytes and 26 Mbytes */
/* #define LOWABORT 32 * 1024
#define HIGHABORT 32 * 1024 * 1024 */
#define LOWABORT 8 * 1024 * 1024
#define HIGHABORT 26 * 1024 * 1024

#endif

#define NUMPAGES 64 * 1024
#define PAGESIZE 64 * 1024
#define PAGEBITS 16
#define OFFSETBITS 0xffff

int SWI_vector_installed = FALSE;

/***************************************************************************\
*        Get a Word from Virtual Memory, maybe allocating the page          *
\***************************************************************************/

static ARMword
GetWord (ARMul_State * state, ARMword address, int check)
{
  ARMword page;
  ARMword offset;
  ARMword **pagetable;
  ARMword *pageptr;

  if (check && state->is_XScale)
    XScale_check_memacc (state, &address, 0);

  page = address >> PAGEBITS;
  offset = (address & OFFSETBITS) >> 2;
  pagetable = (ARMword **) state->MemDataPtr;
  pageptr = *(pagetable + page);

  if (pageptr == NULL)
    {
      pageptr = (ARMword *) malloc (PAGESIZE);

      if (pageptr == NULL)
	{
	  perror ("ARMulator can't allocate VM page");
	  exit (12);
	}

      *(pagetable + page) = pageptr;
    }

  return *(pageptr + offset);
}

/***************************************************************************\
*        Put a Word into Virtual Memory, maybe allocating the page          *
\***************************************************************************/

static void
PutWord (ARMul_State * state, ARMword address, ARMword data, int check)
{
  ARMword page;
  ARMword offset;
  ARMword **pagetable;
  ARMword *pageptr;

  if (check && state->is_XScale)
    XScale_check_memacc (state, &address, 1);

  page = address >> PAGEBITS;
  offset = (address & OFFSETBITS) >> 2;
  pagetable = (ARMword **) state->MemDataPtr;
  pageptr = *(pagetable + page);

  if (pageptr == NULL)
    {
      pageptr = (ARMword *) malloc (PAGESIZE);
      if (pageptr == NULL)
	{
	  perror ("ARMulator can't allocate VM page");
	  exit (13);
	}

      *(pagetable + page) = pageptr;
    }

  if (address == 0x8)
    SWI_vector_installed = TRUE;

  *(pageptr + offset) = data;
}

/***************************************************************************\
*                      Initialise the memory interface                      *
\***************************************************************************/

unsigned
ARMul_MemoryInit (ARMul_State * state, unsigned long initmemsize)
{
  ARMword **pagetable;
  unsigned page;

  if (initmemsize)
    state->MemSize = initmemsize;

  pagetable = (ARMword **) malloc (sizeof (ARMword *) * NUMPAGES);

  if (pagetable == NULL)
    return FALSE;

  for (page = 0; page < NUMPAGES; page++)
    *(pagetable + page) = NULL;

  state->MemDataPtr = (unsigned char *) pagetable;

  ARMul_ConsolePrint (state, ", 4 Gb memory");

  return TRUE;
}

/***************************************************************************\
*                         Remove the memory interface                       *
\***************************************************************************/

void
ARMul_MemoryExit (ARMul_State * state)
{
  ARMword page;
  ARMword **pagetable;
  ARMword *pageptr;

  pagetable = (ARMword **) state->MemDataPtr;
  for (page = 0; page < NUMPAGES; page++)
    {
      pageptr = *(pagetable + page);
      if (pageptr != NULL)
	free ((char *) pageptr);
    }
  free ((char *) pagetable);
  return;
}

/***************************************************************************\
*                   ReLoad Instruction                                     *
\***************************************************************************/

ARMword
ARMul_ReLoadInstr (ARMul_State * state, ARMword address, ARMword isize)
{
#ifdef ABORTS
  if (address >= LOWABORT && address < HIGHABORT)
    {
      ARMul_PREFETCHABORT (address);
      return ARMul_ABORTWORD;
    }
  else
    {
      ARMul_CLEARABORT;
    }
#endif

  if ((isize == 2) && (address & 0x2))
    {
      /* We return the next two halfwords: */
      ARMword lo = GetWord (state, address, FALSE);
      ARMword hi = GetWord (state, address + 4, FALSE);

      if (state->bigendSig == HIGH)
	return (lo << 16) | (hi >> 16);
      else
	return ((hi & 0xFFFF) << 16) | (lo >> 16);
    }

  return GetWord (state, address, TRUE);
}

/***************************************************************************\
*                   Load Instruction, Sequential Cycle                      *
\***************************************************************************/

ARMword ARMul_LoadInstrS (ARMul_State * state, ARMword address, ARMword isize)
{
  state->NumScycles++;

  return ARMul_ReLoadInstr (state, address, isize);
}

/***************************************************************************\
*                 Load Instruction, Non Sequential Cycle                    *
\***************************************************************************/

ARMword ARMul_LoadInstrN (ARMul_State * state, ARMword address, ARMword isize)
{
  state->NumNcycles++;

  return ARMul_ReLoadInstr (state, address, isize);
}

/***************************************************************************\
*                      Read Word (but don't tell anyone!)                   *
\***************************************************************************/

ARMword ARMul_ReadWord (ARMul_State * state, ARMword address)
{
#ifdef ABORTS
  if (address >= LOWABORT && address < HIGHABORT)
    {
      ARMul_DATAABORT (address);
      return ARMul_ABORTWORD;
    }
  else
    {
      ARMul_CLEARABORT;
    }
#endif

  return GetWord (state, address, TRUE);
}

/***************************************************************************\
*                        Load Word, Sequential Cycle                        *
\***************************************************************************/

ARMword ARMul_LoadWordS (ARMul_State * state, ARMword address)
{
  state->NumScycles++;

  return ARMul_ReadWord (state, address);
}

/***************************************************************************\
*                      Load Word, Non Sequential Cycle                      *
\***************************************************************************/

ARMword ARMul_LoadWordN (ARMul_State * state, ARMword address)
{
  state->NumNcycles++;

  return ARMul_ReadWord (state, address);
}

/***************************************************************************\
*                     Load Halfword, (Non Sequential Cycle)                 *
\***************************************************************************/

ARMword ARMul_LoadHalfWord (ARMul_State * state, ARMword address)
{
  ARMword temp, offset;

  state->NumNcycles++;

  temp = ARMul_ReadWord (state, address);
  offset = (((ARMword) state->bigendSig * 2) ^ (address & 2)) << 3;	/* bit offset into the word */

  return (temp >> offset) & 0xffff;
}

/***************************************************************************\
*                      Read Byte (but don't tell anyone!)                   *
\***************************************************************************/

ARMword ARMul_ReadByte (ARMul_State * state, ARMword address)
{
  ARMword temp, offset;

  temp = ARMul_ReadWord (state, address);
  offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3;	/* bit offset into the word */

  return (temp >> offset & 0xffL);
}

/***************************************************************************\
*                     Load Byte, (Non Sequential Cycle)                     *
\***************************************************************************/

ARMword ARMul_LoadByte (ARMul_State * state, ARMword address)
{
  state->NumNcycles++;

  return ARMul_ReadByte (state, address);
}

/***************************************************************************\
*                     Write Word (but don't tell anyone!)                   *
\***************************************************************************/

void
ARMul_WriteWord (ARMul_State * state, ARMword address, ARMword data)
{
#ifdef ABORTS
  if (address >= LOWABORT && address < HIGHABORT)
    {
      ARMul_DATAABORT (address);
      return;
    }
  else
    {
      ARMul_CLEARABORT;
    }
#endif

  PutWord (state, address, data, TRUE);
}

/***************************************************************************\
*                       Store Word, Sequential Cycle                        *
\***************************************************************************/

void
ARMul_StoreWordS (ARMul_State * state, ARMword address, ARMword data)
{
  state->NumScycles++;

  ARMul_WriteWord (state, address, data);
}

/***************************************************************************\
*                       Store Word, Non Sequential Cycle                        *
\***************************************************************************/

void
ARMul_StoreWordN (ARMul_State * state, ARMword address, ARMword data)
{
  state->NumNcycles++;

  ARMul_WriteWord (state, address, data);
}

/***************************************************************************\
*                    Store HalfWord, (Non Sequential Cycle)                 *
\***************************************************************************/

void
ARMul_StoreHalfWord (ARMul_State * state, ARMword address, ARMword data)
{
  ARMword temp, offset;

  state->NumNcycles++;

#ifdef VALIDATE
  if (address == TUBE)
    {
      if (data == 4)
	state->Emulate = FALSE;
      else
	(void) putc ((char) data, stderr);	/* Write Char */
      return;
    }
#endif

  temp = ARMul_ReadWord (state, address);
  offset = (((ARMword) state->bigendSig * 2) ^ (address & 2)) << 3;	/* bit offset into the word */

  PutWord (state, address,
	   (temp & ~(0xffffL << offset)) | ((data & 0xffffL) << offset),
	   TRUE);
}

/***************************************************************************\
*                     Write Byte (but don't tell anyone!)                   *
\***************************************************************************/

void
ARMul_WriteByte (ARMul_State * state, ARMword address, ARMword data)
{
  ARMword temp, offset;

  temp = ARMul_ReadWord (state, address);
  offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3;	/* bit offset into the word */

  PutWord (state, address,
	   (temp & ~(0xffL << offset)) | ((data & 0xffL) << offset),
	   TRUE);
}

/***************************************************************************\
*                    Store Byte, (Non Sequential Cycle)                     *
\***************************************************************************/

void
ARMul_StoreByte (ARMul_State * state, ARMword address, ARMword data)
{
  state->NumNcycles++;

#ifdef VALIDATE
  if (address == TUBE)
    {
      if (data == 4)
	state->Emulate = FALSE;
      else
	(void) putc ((char) data, stderr);	/* Write Char */
      return;
    }
#endif

  ARMul_WriteByte (state, address, data);
}

/***************************************************************************\
*                   Swap Word, (Two Non Sequential Cycles)                  *
\***************************************************************************/

ARMword ARMul_SwapWord (ARMul_State * state, ARMword address, ARMword data)
{
  ARMword temp;

  state->NumNcycles++;

  temp = ARMul_ReadWord (state, address);

  state->NumNcycles++;

  PutWord (state, address, data, TRUE);

  return temp;
}

/***************************************************************************\
*                   Swap Byte, (Two Non Sequential Cycles)                  *
\***************************************************************************/

ARMword ARMul_SwapByte (ARMul_State * state, ARMword address, ARMword data)
{
  ARMword temp;

  temp = ARMul_LoadByte (state, address);
  ARMul_StoreByte (state, address, data);

  return temp;
}

/***************************************************************************\
*                             Count I Cycles                                *
\***************************************************************************/

void
ARMul_Icycles (ARMul_State * state, unsigned number, ARMword address ATTRIBUTE_UNUSED)
{
  state->NumIcycles += number;
  ARMul_CLEARABORT;
}

/***************************************************************************\
*                             Count C Cycles                                *
\***************************************************************************/

void
ARMul_Ccycles (ARMul_State * state, unsigned number, ARMword address ATTRIBUTE_UNUSED)
{
  state->NumCcycles += number;
  ARMul_CLEARABORT;
}


/* Read a byte.  Do not check for alignment or access errors.  */

ARMword
ARMul_SafeReadByte (ARMul_State * state, ARMword address)
{
  ARMword temp, offset;

  temp = GetWord (state, address, FALSE);
  offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3;

  return (temp >> offset & 0xffL);
}

void
ARMul_SafeWriteByte (ARMul_State * state, ARMword address, ARMword data)
{
  ARMword temp, offset;

  temp = GetWord (state, address, FALSE);
  offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3;

  PutWord (state, address,
	   (temp & ~(0xffL << offset)) | ((data & 0xffL) << offset),
	   FALSE);
}
Commit	Line	Data
c906108c SS	1	/* armvirt.c -- ARMulator virtual memory interace: ARM6 Instruction Emulator.
c906108c SS	2	Copyright (C) 1994 Advanced RISC Machines Ltd.
454de2ee	3
c906108c SS	4	This program is free software; you can redistribute it and/or modify
c906108c SS	5	it under the terms of the GNU General Public License as published by
3fd725ef	6	the Free Software Foundation; either version 3 of the License, or
c906108c	7	(at your option) any later version.
454de2ee	8
c906108c SS	9	This program is distributed in the hope that it will be useful,
	10	but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	GNU General Public License for more details.
454de2ee	13
c906108c	14	You should have received a copy of the GNU General Public License
51b318de	15	along with this program; if not, see <http://www.gnu.org/licenses/>. */
c906108c SS	16
c906108c SS	17	/* This file contains a complete ARMulator memory model, modelling a
454de2ee NC	18	"virtual memory" system. A much simpler model can be found in armfast.c,
	19	and that model goes faster too, but has a fixed amount of memory. This
	20	model's memory has 64K pages, allocated on demand from a 64K entry page
	21	table. The routines PutWord and GetWord implement this. Pages are never
	22	freed as they might be needed again. A single area of memory may be
	23	defined to generate aborts. */
c906108c	24
917bca4f	25	#include "armos.h"
c906108c	26	#include "armdefs.h"
6d358e86	27	#include "ansidecl.h"
c906108c	28
dfcd3bfb JM	29	#ifdef VALIDATE /* for running the validate suite */
dfcd3bfb JM	30	#define TUBE 48 * 1024 * 1024 /* write a char on the screen */
c906108c SS	31	#define ABORTS 1
	32	#endif
	33
ae3c7619	34	/* #define ABORTS */
c906108c	35
dfcd3bfb	36	#ifdef ABORTS /* the memory system will abort */
c906108c SS	37	/* For the old test suite Abort between 32 Kbytes and 32 Mbytes
	38	For the new test suite Abort between 8 Mbytes and 26 Mbytes */
	39	/* #define LOWABORT 32 * 1024
	40	#define HIGHABORT 32 * 1024 * 1024 */
	41	#define LOWABORT 8 * 1024 * 1024
	42	#define HIGHABORT 26 * 1024 * 1024
	43
	44	#endif
	45
	46	#define NUMPAGES 64 * 1024
	47	#define PAGESIZE 64 * 1024
	48	#define PAGEBITS 16
	49	#define OFFSETBITS 0xffff
	50
88694af3 NC	51	int SWI_vector_installed = FALSE;
88694af3 NC	52
c906108c SS	53	/***************************************************************************\
	54	* Get a Word from Virtual Memory, maybe allocating the page *
	55	\***************************************************************************/
	56
	57	static ARMword
917bca4f	58	GetWord (ARMul_State * state, ARMword address, int check)
c906108c	59	{
dfcd3bfb JM	60	ARMword page;
	61	ARMword offset;
	62	ARMword **pagetable;
	63	ARMword *pageptr;
c906108c	64
c88931b0	65	if (check && state->is_XScale)
10b57fcb	66	XScale_check_memacc (state, &address, 0);
c3ae2f98	67
dfcd3bfb JM	68	page = address >> PAGEBITS;
dfcd3bfb JM	69	offset = (address & OFFSETBITS) >> 2;
c906108c	70	pagetable = (ARMword **) state->MemDataPtr;
dfcd3bfb JM	71	pageptr = *(pagetable + page);
dfcd3bfb JM	72
c906108c SS	73	if (pageptr == NULL)
	74	{
	75	pageptr = (ARMword *) malloc (PAGESIZE);
dfcd3bfb	76
c906108c SS	77	if (pageptr == NULL)
	78	{
	79	perror ("ARMulator can't allocate VM page");
	80	exit (12);
	81	}
dfcd3bfb	82
c906108c SS	83	*(pagetable + page) = pageptr;
c906108c SS	84	}
dfcd3bfb	85
c906108c SS	86	return *(pageptr + offset);
	87	}
	88
	89	/***************************************************************************\
	90	* Put a Word into Virtual Memory, maybe allocating the page *
	91	\***************************************************************************/
	92
	93	static void
917bca4f	94	PutWord (ARMul_State * state, ARMword address, ARMword data, int check)
c906108c	95	{
dfcd3bfb JM	96	ARMword page;
	97	ARMword offset;
	98	ARMword **pagetable;
	99	ARMword *pageptr;
	100
c88931b0	101	if (check && state->is_XScale)
10b57fcb	102	XScale_check_memacc (state, &address, 1);
c3ae2f98	103
dfcd3bfb JM	104	page = address >> PAGEBITS;
	105	offset = (address & OFFSETBITS) >> 2;
	106	pagetable = (ARMword **) state->MemDataPtr;
	107	pageptr = *(pagetable + page);
	108
c906108c SS	109	if (pageptr == NULL)
	110	{
	111	pageptr = (ARMword *) malloc (PAGESIZE);
	112	if (pageptr == NULL)
	113	{
	114	perror ("ARMulator can't allocate VM page");
dfcd3bfb	115	exit (13);
c906108c	116	}
dfcd3bfb	117
c906108c SS	118	*(pagetable + page) = pageptr;
c906108c SS	119	}
dfcd3bfb	120
88694af3 NC	121	if (address == 0x8)
	122	SWI_vector_installed = TRUE;
	123
c906108c SS	124	*(pageptr + offset) = data;
	125	}
	126
	127	/***************************************************************************\
	128	* Initialise the memory interface *
	129	\***************************************************************************/
	130
	131	unsigned
	132	ARMul_MemoryInit (ARMul_State * state, unsigned long initmemsize)
	133	{
dfcd3bfb JM	134	ARMword **pagetable;
dfcd3bfb JM	135	unsigned page;
c906108c SS	136
	137	if (initmemsize)
	138	state->MemSize = initmemsize;
dfcd3bfb	139
c4793bac	140	pagetable = (ARMword *) malloc (sizeof (ARMword ) * NUMPAGES);
dfcd3bfb	141
c906108c SS	142	if (pagetable == NULL)
c906108c SS	143	return FALSE;
dfcd3bfb JM	144
dfcd3bfb JM	145	for (page = 0; page < NUMPAGES; page++)
c906108c	146	*(pagetable + page) = NULL;
dfcd3bfb JM	147
dfcd3bfb JM	148	state->MemDataPtr = (unsigned char *) pagetable;
c906108c SS	149
c906108c SS	150	ARMul_ConsolePrint (state, ", 4 Gb memory");
dfcd3bfb JM	151
dfcd3bfb JM	152	return TRUE;
c906108c SS	153	}
	154
	155	/***************************************************************************\
	156	* Remove the memory interface *
	157	\***************************************************************************/
	158
	159	void
	160	ARMul_MemoryExit (ARMul_State * state)
	161	{
dfcd3bfb JM	162	ARMword page;
	163	ARMword **pagetable;
	164	ARMword *pageptr;
c906108c	165
dfcd3bfb JM	166	pagetable = (ARMword **) state->MemDataPtr;
dfcd3bfb JM	167	for (page = 0; page < NUMPAGES; page++)
c906108c SS	168	{
	169	pageptr = *(pagetable + page);
	170	if (pageptr != NULL)
dfcd3bfb	171	free ((char *) pageptr);
c906108c	172	}
dfcd3bfb	173	free ((char *) pagetable);
c906108c SS	174	return;
	175	}
	176
	177	/***************************************************************************\
	178	* ReLoad Instruction *
	179	\***************************************************************************/
	180
	181	ARMword
	182	ARMul_ReLoadInstr (ARMul_State * state, ARMword address, ARMword isize)
	183	{
	184	#ifdef ABORTS
dfcd3bfb	185	if (address >= LOWABORT && address < HIGHABORT)
c906108c SS	186	{
	187	ARMul_PREFETCHABORT (address);
	188	return ARMul_ABORTWORD;
	189	}
dfcd3bfb JM	190	else
	191	{
	192	ARMul_CLEARABORT;
	193	}
c906108c SS	194	#endif
c906108c SS	195
dfcd3bfb JM	196	if ((isize == 2) && (address & 0x2))
	197	{
	198	/* We return the next two halfwords: */
3cf84db9 NC	199	ARMword lo = GetWord (state, address, FALSE);
3cf84db9 NC	200	ARMword hi = GetWord (state, address + 4, FALSE);
c906108c	201
dfcd3bfb JM	202	if (state->bigendSig == HIGH)
	203	return (lo << 16) \| (hi >> 16);
	204	else
	205	return ((hi & 0xFFFF) << 16) \| (lo >> 16);
	206	}
c906108c	207
917bca4f	208	return GetWord (state, address, TRUE);
c906108c SS	209	}
	210
	211	/***************************************************************************\
	212	* Load Instruction, Sequential Cycle *
	213	\***************************************************************************/
	214
dfcd3bfb	215	ARMword ARMul_LoadInstrS (ARMul_State * state, ARMword address, ARMword isize)
c906108c	216	{
dfcd3bfb	217	state->NumScycles++;
c906108c	218
c906108c SS	219	return ARMul_ReLoadInstr (state, address, isize);
	220	}
	221
	222	/***************************************************************************\
	223	* Load Instruction, Non Sequential Cycle *
	224	\***************************************************************************/
	225
dfcd3bfb	226	ARMword ARMul_LoadInstrN (ARMul_State * state, ARMword address, ARMword isize)
c906108c	227	{
dfcd3bfb	228	state->NumNcycles++;
c906108c SS	229
	230	return ARMul_ReLoadInstr (state, address, isize);
	231	}
	232
	233	/***************************************************************************\
	234	* Read Word (but don't tell anyone!) *
	235	\***************************************************************************/
	236
dfcd3bfb	237	ARMword ARMul_ReadWord (ARMul_State * state, ARMword address)
c906108c SS	238	{
	239	#ifdef ABORTS
	240	if (address >= LOWABORT && address < HIGHABORT)
	241	{
	242	ARMul_DATAABORT (address);
	243	return ARMul_ABORTWORD;
	244	}
	245	else
	246	{
	247	ARMul_CLEARABORT;
	248	}
	249	#endif
	250
917bca4f	251	return GetWord (state, address, TRUE);
c906108c SS	252	}
	253
	254	/***************************************************************************\
	255	* Load Word, Sequential Cycle *
	256	\***************************************************************************/
	257
dfcd3bfb	258	ARMword ARMul_LoadWordS (ARMul_State * state, ARMword address)
c906108c	259	{
dfcd3bfb	260	state->NumScycles++;
c906108c SS	261
	262	return ARMul_ReadWord (state, address);
	263	}
	264
	265	/***************************************************************************\
	266	* Load Word, Non Sequential Cycle *
	267	\***************************************************************************/
	268
dfcd3bfb	269	ARMword ARMul_LoadWordN (ARMul_State * state, ARMword address)
c906108c	270	{
dfcd3bfb JM	271	state->NumNcycles++;
dfcd3bfb JM	272
c906108c SS	273	return ARMul_ReadWord (state, address);
	274	}
	275
	276	/***************************************************************************\
	277	* Load Halfword, (Non Sequential Cycle) *
	278	\***************************************************************************/
	279
dfcd3bfb	280	ARMword ARMul_LoadHalfWord (ARMul_State * state, ARMword address)
c906108c SS	281	{
	282	ARMword temp, offset;
	283
dfcd3bfb	284	state->NumNcycles++;
c906108c	285
dfcd3bfb JM	286	temp = ARMul_ReadWord (state, address);
dfcd3bfb JM	287	offset = (((ARMword) state->bigendSig * 2) ^ (address & 2)) << 3; /* bit offset into the word */
c906108c SS	288
	289	return (temp >> offset) & 0xffff;
	290	}
	291
	292	/***************************************************************************\
	293	* Read Byte (but don't tell anyone!) *
	294	\***************************************************************************/
	295
dfcd3bfb	296	ARMword ARMul_ReadByte (ARMul_State * state, ARMword address)
c906108c SS	297	{
	298	ARMword temp, offset;
	299
dfcd3bfb JM	300	temp = ARMul_ReadWord (state, address);
dfcd3bfb JM	301	offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3; /* bit offset into the word */
c906108c	302
dfcd3bfb	303	return (temp >> offset & 0xffL);
c906108c SS	304	}
	305
	306	/***************************************************************************\
	307	* Load Byte, (Non Sequential Cycle) *
	308	\***************************************************************************/
	309
dfcd3bfb	310	ARMword ARMul_LoadByte (ARMul_State * state, ARMword address)
c906108c	311	{
dfcd3bfb	312	state->NumNcycles++;
c906108c SS	313
	314	return ARMul_ReadByte (state, address);
	315	}
	316
	317	/***************************************************************************\
	318	* Write Word (but don't tell anyone!) *
	319	\***************************************************************************/
	320
	321	void
	322	ARMul_WriteWord (ARMul_State * state, ARMword address, ARMword data)
	323	{
	324	#ifdef ABORTS
	325	if (address >= LOWABORT && address < HIGHABORT)
	326	{
	327	ARMul_DATAABORT (address);
	328	return;
	329	}
	330	else
	331	{
	332	ARMul_CLEARABORT;
	333	}
	334	#endif
	335
917bca4f	336	PutWord (state, address, data, TRUE);
c906108c SS	337	}
	338
	339	/***************************************************************************\
	340	* Store Word, Sequential Cycle *
	341	\***************************************************************************/
	342
	343	void
	344	ARMul_StoreWordS (ARMul_State * state, ARMword address, ARMword data)
	345	{
dfcd3bfb	346	state->NumScycles++;
c906108c SS	347
	348	ARMul_WriteWord (state, address, data);
	349	}
	350
	351	/***************************************************************************\
	352	* Store Word, Non Sequential Cycle *
	353	\***************************************************************************/
	354
	355	void
	356	ARMul_StoreWordN (ARMul_State * state, ARMword address, ARMword data)
	357	{
dfcd3bfb	358	state->NumNcycles++;
c906108c SS	359
	360	ARMul_WriteWord (state, address, data);
	361	}
	362
	363	/***************************************************************************\
	364	* Store HalfWord, (Non Sequential Cycle) *
	365	\***************************************************************************/
	366
	367	void
	368	ARMul_StoreHalfWord (ARMul_State * state, ARMword address, ARMword data)
	369	{
	370	ARMword temp, offset;
	371
dfcd3bfb JM	372	state->NumNcycles++;
dfcd3bfb JM	373
c906108c SS	374	#ifdef VALIDATE
	375	if (address == TUBE)
	376	{
	377	if (data == 4)
	378	state->Emulate = FALSE;
	379	else
dfcd3bfb	380	(void) putc ((char) data, stderr); /* Write Char */
c906108c SS	381	return;
	382	}
	383	#endif
	384
dfcd3bfb JM	385	temp = ARMul_ReadWord (state, address);
	386	offset = (((ARMword) state->bigendSig * 2) ^ (address & 2)) << 3; /* bit offset into the word */
	387
	388	PutWord (state, address,
917bca4f NC	389	(temp & ~(0xffffL << offset)) \| ((data & 0xffffL) << offset),
917bca4f NC	390	TRUE);
c906108c SS	391	}
	392
	393	/***************************************************************************\
	394	* Write Byte (but don't tell anyone!) *
	395	\***************************************************************************/
	396
	397	void
	398	ARMul_WriteByte (ARMul_State * state, ARMword address, ARMword data)
	399	{
	400	ARMword temp, offset;
	401
dfcd3bfb JM	402	temp = ARMul_ReadWord (state, address);
	403	offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3; /* bit offset into the word */
	404
	405	PutWord (state, address,
917bca4f NC	406	(temp & ~(0xffL << offset)) \| ((data & 0xffL) << offset),
917bca4f NC	407	TRUE);
c906108c SS	408	}
	409
	410	/***************************************************************************\
	411	* Store Byte, (Non Sequential Cycle) *
	412	\***************************************************************************/
	413
	414	void
	415	ARMul_StoreByte (ARMul_State * state, ARMword address, ARMword data)
	416	{
dfcd3bfb	417	state->NumNcycles++;
c906108c SS	418
	419	#ifdef VALIDATE
	420	if (address == TUBE)
	421	{
	422	if (data == 4)
	423	state->Emulate = FALSE;
	424	else
dfcd3bfb	425	(void) putc ((char) data, stderr); /* Write Char */
c906108c SS	426	return;
	427	}
	428	#endif
	429
	430	ARMul_WriteByte (state, address, data);
	431	}
	432
	433	/***************************************************************************\
	434	* Swap Word, (Two Non Sequential Cycles) *
	435	\***************************************************************************/
	436
dfcd3bfb	437	ARMword ARMul_SwapWord (ARMul_State * state, ARMword address, ARMword data)
c906108c SS	438	{
	439	ARMword temp;
	440
dfcd3bfb	441	state->NumNcycles++;
c906108c SS	442
c906108c SS	443	temp = ARMul_ReadWord (state, address);
dfcd3bfb JM	444
	445	state->NumNcycles++;
	446
917bca4f	447	PutWord (state, address, data, TRUE);
dfcd3bfb	448
c906108c SS	449	return temp;
	450	}
	451
	452	/***************************************************************************\
	453	* Swap Byte, (Two Non Sequential Cycles) *
	454	\***************************************************************************/
	455
dfcd3bfb	456	ARMword ARMul_SwapByte (ARMul_State * state, ARMword address, ARMword data)
c906108c SS	457	{
	458	ARMword temp;
	459
	460	temp = ARMul_LoadByte (state, address);
	461	ARMul_StoreByte (state, address, data);
dfcd3bfb	462
c906108c SS	463	return temp;
	464	}
	465
	466	/***************************************************************************\
	467	* Count I Cycles *
	468	\***************************************************************************/
	469
	470	void
6d358e86	471	ARMul_Icycles (ARMul_State * state, unsigned number, ARMword address ATTRIBUTE_UNUSED)
c906108c SS	472	{
	473	state->NumIcycles += number;
	474	ARMul_CLEARABORT;
	475	}
	476
	477	/***************************************************************************\
	478	* Count C Cycles *
	479	\***************************************************************************/
	480
	481	void
6d358e86	482	ARMul_Ccycles (ARMul_State * state, unsigned number, ARMword address ATTRIBUTE_UNUSED)
c906108c SS	483	{
	484	state->NumCcycles += number;
	485	ARMul_CLEARABORT;
	486	}
917bca4f NC	487
	488
	489	/* Read a byte. Do not check for alignment or access errors. */
	490
	491	ARMword
	492	ARMul_SafeReadByte (ARMul_State * state, ARMword address)
	493	{
	494	ARMword temp, offset;
	495
	496	temp = GetWord (state, address, FALSE);
	497	offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3;
	498
	499	return (temp >> offset & 0xffL);
	500	}
	501
	502	void
	503	ARMul_SafeWriteByte (ARMul_State * state, ARMword address, ARMword data)
	504	{
	505	ARMword temp, offset;
	506
	507	temp = GetWord (state, address, FALSE);
	508	offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3;
	509
	510	PutWord (state, address,
	511	(temp & ~(0xffL << offset)) \| ((data & 0xffL) << offset),
	512	FALSE);
	513	}