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[deliverable/binutils-gdb.git] / sim / cr16 / simops.c
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fee8ec00 1/* Simulation code for the CR16 processor.
88b9d363 2 Copyright (C) 2008-2022 Free Software Foundation, Inc.
fee8ec00
SR		 3 Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com>
4
5 This file is part of GDB, the GNU debugger.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
dc3cf14f 9 the Free Software Foundation; either version 3, or (at your option)
fee8ec00
SR		 10 any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
537e4bb9
SR		 17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
fee8ec00 19
6df01ab8
MF		 20/* This must come before any other includes. */
21#include "defs.h"
fee8ec00
SR		 22
23#include <signal.h>
24#include <errno.h>
25#include <sys/types.h>
26#include <sys/stat.h>
27#ifdef HAVE_UNISTD_H
28#include <unistd.h>
29#endif
fee8ec00 30#include <string.h>
5aedb83b 31#include <time.h>
5aedb83b 32#include <sys/time.h>
fee8ec00 33
247ac9ee 34#include "sim-main.h"
1fef66b0 35#include "sim-signal.h"
fee8ec00
SR		 36#include "simops.h"
37#include "targ-vals.h"
38
5aedb83b
MF		 39#ifdef TARGET_SYS_utime
40#include <utime.h>
41#endif
42#ifdef TARGET_SYS_wait
43#include <sys/wait.h>
44#endif
fee8ec00 45
0ef7f981
MF		 46#define EXCEPTION(sig) sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, sig)
47
fee8ec00
SR		 48enum op_types {
49 OP_VOID,
50 OP_CONSTANT3,
fee8ec00 51 OP_UCONSTANT3,
fee8ec00 52 OP_CONSTANT4,
fee8ec00 53 OP_CONSTANT4_1,
fee8ec00 54 OP_CONSTANT5,
fee8ec00 55 OP_CONSTANT6,
fee8ec00 56 OP_CONSTANT16,
fee8ec00 57 OP_UCONSTANT16,
fee8ec00 58 OP_CONSTANT20,
fee8ec00 59 OP_UCONSTANT20,
fee8ec00 60 OP_CONSTANT32,
fee8ec00 61 OP_UCONSTANT32,
fee8ec00
SR		 62 OP_MEMREF,
63 OP_MEMREF2,
64 OP_MEMREF3,
65
66 OP_DISP5,
fee8ec00 67 OP_DISP17,
fee8ec00 68 OP_DISP25,
fee8ec00 69 OP_DISPE9,
fee8ec00
SR		 70 //OP_ABS20,
71 OP_ABS20_OUTPUT,
72 //OP_ABS24,
73 OP_ABS24_OUTPUT,
74
75 OP_R_BASE_DISPS16,
fee8ec00 76 OP_R_BASE_DISP20,
fee8ec00 77 OP_R_BASE_DISPS20,
fee8ec00 78 OP_R_BASE_DISPE20,
fee8ec00
SR		 79
80 OP_RP_BASE_DISPE0,
fee8ec00 81 OP_RP_BASE_DISP4,
fee8ec00 82 OP_RP_BASE_DISPE4,
fee8ec00 83 OP_RP_BASE_DISP14,
fee8ec00 84 OP_RP_BASE_DISP16,
fee8ec00 85 OP_RP_BASE_DISP20,
fee8ec00 86 OP_RP_BASE_DISPS20,
fee8ec00 87 OP_RP_BASE_DISPE20,
fee8ec00
SR		 88
89 OP_R_INDEX7_ABS20,
fee8ec00 90 OP_R_INDEX8_ABS20,
fee8ec00
SR		 91
92 OP_RP_INDEX_DISP0,
fee8ec00 93 OP_RP_INDEX_DISP14,
fee8ec00 94 OP_RP_INDEX_DISP20,
fee8ec00 95 OP_RP_INDEX_DISPS20,
fee8ec00
SR		 96
97 OP_REG,
fee8ec00 98 OP_REGP,
fee8ec00 99 OP_PROC_REG,
fee8ec00 100 OP_PROC_REGP,
fee8ec00 101 OP_COND,
537e4bb9 102 OP_RA
fee8ec00
SR		 103};
104
105
106enum {
107 PSR_MASK = (PSR_I_BIT
108 | PSR_P_BIT
109 | PSR_E_BIT
110 | PSR_N_BIT
111 | PSR_Z_BIT
112 | PSR_F_BIT
113 | PSR_U_BIT
114 | PSR_L_BIT
115 | PSR_T_BIT
116 | PSR_C_BIT),
117 /* The following bits in the PSR _can't_ be set by instructions such
118 as mvtc. */
119 PSR_HW_MASK = (PSR_MASK)
120};
121
122/* cond Code Condition True State
123 * EQ Equal Z flag is 1
124 * NE Not Equal Z flag is 0
125 * CS Carry Set C flag is 1
126 * CC Carry Clear C flag is 0
127 * HI Higher L flag is 1
128 * LS Lower or Same L flag is 0
129 * GT Greater Than N flag is 1
130 * LE Less Than or Equal To N flag is 0
131 * FS Flag Set F flag is 1
132 * FC Flag Clear F flag is 0
133 * LO Lower Z and L flags are 0
134 * HS Higher or Same Z or L flag is 1
135 * LT Less Than Z and N flags are 0
136 * GE Greater Than or Equal To Z or N flag is 1. */
137
5aedb83b 138static int cond_stat(int cc)
fee8ec00
SR		 139{
140 switch (cc)
141 {
142 case 0: return PSR_Z; break;
143 case 1: return !PSR_Z; break;
144 case 2: return PSR_C; break;
145 case 3: return !PSR_C; break;
146 case 4: return PSR_L; break;
147 case 5: return !PSR_L; break;
148 case 6: return PSR_N; break;
149 case 7: return !PSR_N; break;
150 case 8: return PSR_F; break;
151 case 9: return !PSR_F; break;
152 case 10: return !PSR_Z && !PSR_L; break;
153 case 11: return PSR_Z || PSR_L; break;
154 case 12: return !PSR_Z && !PSR_N; break;
155 case 13: return PSR_Z || PSR_N; break;
156 case 14: return 1; break; /*ALWAYS. */
157 default:
158 // case NEVER: return false; break;
159 //case NO_COND_CODE:
160 //panic("Shouldn't have NO_COND_CODE in an actual instruction!");
161 return 0; break;
162 }
163 return 0;
164}
165
166
167creg_t
267b3b8e 168move_to_cr (SIM_DESC sd, SIM_CPU *cpu, int cr, creg_t mask, creg_t val, int psw_hw_p)
fee8ec00
SR		 169{
170 /* A MASK bit is set when the corresponding bit in the CR should
171 be left alone. */
172 /* This assumes that (VAL & MASK) == 0. */
173 switch (cr)
174 {
175 case PSR_CR:
176 if (psw_hw_p)
177 val &= PSR_HW_MASK;
178#if 0
179 else
180 val &= PSR_MASK;
9db36cf8
MF		 181 sim_io_printf
182 (sd,
fee8ec00 183 "ERROR at PC 0x%x: ST can only be set when FX is set.\n", PC);
0ef7f981 184 EXCEPTION (SIM_SIGILL);
fee8ec00
SR		 185#endif
186 /* keep an up-to-date psw around for tracing. */
187 State.trace.psw = (State.trace.psw & mask) | val;
188 break;
189 default:
190 break;
191 }
192 /* only issue an update if the register is being changed. */
193 if ((State.cregs[cr] & ~mask) != val)
194 SLOT_PEND_MASK (State.cregs[cr], mask, val);
537e4bb9 195
fee8ec00
SR		 196 return val;
197}
198
199#ifdef DEBUG
267b3b8e
MF		 200static void trace_input_func (SIM_DESC sd,
201 const char *name,
bdca5ee4
TT		 202 enum op_types in1,
203 enum op_types in2,
204 enum op_types in3);
fee8ec00 205
267b3b8e 206#define trace_input(name, in1, in2, in3) do { if (cr16_debug) trace_input_func (sd, name, in1, in2, in3); } while (0)
fee8ec00
SR		 207
208#ifndef SIZE_INSTRUCTION
209#define SIZE_INSTRUCTION 8
210#endif
211
212#ifndef SIZE_OPERANDS
213#define SIZE_OPERANDS 18
214#endif
215
216#ifndef SIZE_VALUES
217#define SIZE_VALUES 13
218#endif
219
220#ifndef SIZE_LOCATION
221#define SIZE_LOCATION 20
222#endif
223
224#ifndef SIZE_PC
225#define SIZE_PC 4
226#endif
227
228#ifndef SIZE_LINE_NUMBER
229#define SIZE_LINE_NUMBER 2
230#endif
231
232static void
267b3b8e 233trace_input_func (SIM_DESC sd, const char *name, enum op_types in1, enum op_types in2, enum op_types in3)
fee8ec00
SR		 234{
235 char *comma;
236 enum op_types in[3];
237 int i;
238 char buf[1024];
239 char *p;
240 long tmp;
241 char *type;
242 const char *filename;
243 const char *functionname;
244 unsigned int linenumber;
245 bfd_vma byte_pc;
246
247 if ((cr16_debug & DEBUG_TRACE) == 0)
248 return;
249
250 switch (State.ins_type)
251 {
252 default:
253 case INS_UNKNOWN: type = " ?"; break;
254 }
255
256 if ((cr16_debug & DEBUG_LINE_NUMBER) == 0)
9db36cf8 257 sim_io_printf (sd,
fee8ec00
SR		 258 "0x%.*x %s: %-*s ",
259 SIZE_PC, (unsigned)PC,
260 type,
261 SIZE_INSTRUCTION, name);
262
263 else
264 {
265 buf[0] = '\0';
247ac9ee 266 byte_pc = PC;
267b3b8e
MF		 267 if (STATE_TEXT_SECTION (sd)
268 && byte_pc >= STATE_TEXT_START (sd)
269 && byte_pc < STATE_TEXT_END (sd))
fee8ec00
SR		 270 {
271 filename = (const char *)0;
272 functionname = (const char *)0;
273 linenumber = 0;
267b3b8e
MF		 274 if (bfd_find_nearest_line (STATE_PROG_BFD (sd),
275 STATE_TEXT_SECTION (sd),
247ac9ee 276 (struct bfd_symbol **)0,
267b3b8e 277 byte_pc - STATE_TEXT_START (sd),
fee8ec00
SR		 278 &filename, &functionname, &linenumber))
279 {
280 p = buf;
281 if (linenumber)
282 {
283 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
284 p += strlen (p);
285 }
286 else
287 {
288 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
289 p += SIZE_LINE_NUMBER+2;
290 }
291
292 if (functionname)
293 {
294 sprintf (p, "%s ", functionname);
295 p += strlen (p);
296 }
297 else if (filename)
298 {
299 char *q = strrchr (filename, '/');
300 sprintf (p, "%s ", (q) ? q+1 : filename);
301 p += strlen (p);
302 }
303
304 if (*p == ' ')
305 *p = '\0';
306 }
307 }
308
9db36cf8 309 sim_io_printf (sd,
fee8ec00
SR		 310 "0x%.*x %s: %-*.*s %-*s ",
311 SIZE_PC, (unsigned)PC,
312 type,
313 SIZE_LOCATION, SIZE_LOCATION, buf,
314 SIZE_INSTRUCTION, name);
315 }
316
317 in[0] = in1;
318 in[1] = in2;
319 in[2] = in3;
320 comma = "";
321 p = buf;
322 for (i = 0; i < 3; i++)
323 {
324 switch (in[i])
325 {
326 case OP_VOID:
327 break;
328
329 case OP_REG:
fee8ec00 330 case OP_REGP:
fee8ec00
SR		 331 sprintf (p, "%sr%d", comma, OP[i]);
332 p += strlen (p);
333 comma = ",";
334 break;
335
336 case OP_PROC_REG:
fee8ec00
SR		 337 sprintf (p, "%scr%d", comma, OP[i]);
338 p += strlen (p);
339 comma = ",";
340 break;
341
342 case OP_CONSTANT16:
343 sprintf (p, "%s%d", comma, OP[i]);
344 p += strlen (p);
345 comma = ",";
346 break;
347
348 case OP_CONSTANT4:
349 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
350 p += strlen (p);
351 comma = ",";
352 break;
353
354 case OP_CONSTANT3:
355 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
356 p += strlen (p);
357 comma = ",";
358 break;
359
360 case OP_MEMREF:
361 sprintf (p, "%s@r%d", comma, OP[i]);
362 p += strlen (p);
363 comma = ",";
364 break;
365
366 case OP_MEMREF2:
367 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
368 p += strlen (p);
369 comma = ",";
370 break;
371
372 case OP_MEMREF3:
373 sprintf (p, "%s@%d", comma, OP[i]);
374 p += strlen (p);
375 comma = ",";
376 break;
377 }
378 }
379
380 if ((cr16_debug & DEBUG_VALUES) == 0)
381 {
382 *p++ = '\n';
383 *p = '\0';
9db36cf8 384 sim_io_printf (sd, "%s", buf);
fee8ec00
SR		 385 }
386 else
387 {
388 *p = '\0';
9db36cf8 389 sim_io_printf (sd, "%-*s", SIZE_OPERANDS, buf);
fee8ec00
SR		 390
391 p = buf;
392 for (i = 0; i < 3; i++)
393 {
394 buf[0] = '\0';
395 switch (in[i])
396 {
397 case OP_VOID:
9db36cf8 398 sim_io_printf (sd, "%*s", SIZE_VALUES, "");
fee8ec00
SR		 399 break;
400
fee8ec00 401 case OP_REG:
9db36cf8 402 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
fee8ec00
SR		 403 (uint16) GPR (OP[i]));
404 break;
405
406 case OP_REGP:
407 tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
9db36cf8 408 sim_io_printf (sd, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
fee8ec00
SR		 409 break;
410
411 case OP_PROC_REG:
9db36cf8 412 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
fee8ec00
SR		 413 (uint16) CREG (OP[i]));
414 break;
415
416 case OP_CONSTANT16:
9db36cf8 417 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
fee8ec00
SR		 418 (uint16)OP[i]);
419 break;
420
421 case OP_CONSTANT4:
9db36cf8 422 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
fee8ec00
SR		 423 (uint16)SEXT4(OP[i]));
424 break;
425
426 case OP_CONSTANT3:
9db36cf8 427 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
fee8ec00
SR		 428 (uint16)SEXT3(OP[i]));
429 break;
430
431 case OP_MEMREF2:
9db36cf8 432 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
fee8ec00 433 (uint16)OP[i]);
9db36cf8 434 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
fee8ec00
SR		 435 (uint16)GPR (OP[i + 1]));
436 i++;
437 break;
438 }
439 }
440 }
441
9db36cf8 442 sim_io_flush_stdout (sd);
fee8ec00
SR		 443}
444
445static void
267b3b8e 446do_trace_output_flush (SIM_DESC sd)
fee8ec00 447{
9db36cf8 448 sim_io_flush_stdout (sd);
fee8ec00
SR		 449}
450
451static void
267b3b8e 452do_trace_output_finish (SIM_DESC sd)
fee8ec00 453{
9db36cf8 454 sim_io_printf (sd,
fee8ec00
SR		 455 " F0=%d F1=%d C=%d\n",
456 (State.trace.psw & PSR_F_BIT) != 0,
457 (State.trace.psw & PSR_F_BIT) != 0,
458 (State.trace.psw & PSR_C_BIT) != 0);
9db36cf8 459 sim_io_flush_stdout (sd);
fee8ec00
SR		 460}
461
5aedb83b 462#if 0
fee8ec00 463static void
267b3b8e 464trace_output_40 (SIM_DESC sd, uint64 val)
fee8ec00
SR		 465{
466 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
467 {
9db36cf8 468 sim_io_printf (sd,
fee8ec00
SR		 469 " :: %*s0x%.2x%.8lx",
470 SIZE_VALUES - 12,
471 "",
472 ((int)(val >> 32) & 0xff),
473 ((unsigned long) val) & 0xffffffff);
474 do_trace_output_finish ();
475 }
476}
5aedb83b 477#endif
fee8ec00
SR		 478
479static void
267b3b8e 480trace_output_32 (SIM_DESC sd, uint32 val)
fee8ec00
SR		 481{
482 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
483 {
9db36cf8 484 sim_io_printf (sd,
fee8ec00
SR		 485 " :: %*s0x%.8x",
486 SIZE_VALUES - 10,
487 "",
488 (int) val);
267b3b8e 489 do_trace_output_finish (sd);
fee8ec00
SR		 490 }
491}
492
493static void
267b3b8e 494trace_output_16 (SIM_DESC sd, uint16 val)
fee8ec00
SR		 495{
496 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
497 {
9db36cf8 498 sim_io_printf (sd,
fee8ec00
SR		 499 " :: %*s0x%.4x",
500 SIZE_VALUES - 6,
501 "",
502 (int) val);
267b3b8e 503 do_trace_output_finish (sd);
fee8ec00
SR		 504 }
505}
506
507static void
267b3b8e 508trace_output_void (SIM_DESC sd)
fee8ec00
SR		 509{
510 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
511 {
9db36cf8 512 sim_io_printf (sd, "\n");
267b3b8e 513 do_trace_output_flush (sd);
fee8ec00
SR		 514 }
515}
516
517static void
267b3b8e 518trace_output_flag (SIM_DESC sd)
fee8ec00
SR		 519{
520 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
521 {
9db36cf8 522 sim_io_printf (sd,
fee8ec00
SR		 523 " :: %*s",
524 SIZE_VALUES,
525 "");
267b3b8e 526 do_trace_output_finish (sd);
fee8ec00
SR		 527 }
528}
529
530
531
532
533#else
534#define trace_input(NAME, IN1, IN2, IN3)
535#define trace_output(RESULT)
536#endif
537
538/* addub. */
539void
267b3b8e 540OP_2C_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 541{
542 uint8 tmp;
543 uint8 a = OP[0] & 0xff;
544 uint16 b = (GPR (OP[1])) & 0xff;
545 trace_input ("addub", OP_CONSTANT4_1, OP_REG, OP_VOID);
546 tmp = (a + b) & 0xff;
547 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 548 trace_output_16 (sd, tmp);
fee8ec00
SR		 549}
550
551/* addub. */
552void
267b3b8e 553OP_2CB_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 554{
555 uint16 tmp;
556 uint8 a = ((OP[0]) & 0xff), b = (GPR (OP[1])) & 0xff;
557 trace_input ("addub", OP_CONSTANT16, OP_REG, OP_VOID);
558 tmp = (a + b) & 0xff;
559 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 560 trace_output_16 (sd, tmp);
fee8ec00
SR		 561}
562
563/* addub. */
564void
267b3b8e 565OP_2D_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 566{
567 uint8 a = (GPR (OP[0])) & 0xff;
568 uint8 b = (GPR (OP[1])) & 0xff;
569 uint16 tmp = (a + b) & 0xff;
570 trace_input ("addub", OP_REG, OP_REG, OP_VOID);
571 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 572 trace_output_16 (sd, tmp);
fee8ec00
SR		 573}
574
575/* adduw. */
576void
267b3b8e 577OP_2E_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 578{
579 uint16 a = OP[0];
580 uint16 b = GPR (OP[1]);
581 uint16 tmp = (a + b);
582 trace_input ("adduw", OP_CONSTANT4_1, OP_REG, OP_VOID);
583 SET_GPR (OP[1], tmp);
267b3b8e 584 trace_output_16 (sd, tmp);
fee8ec00
SR		 585}
586
587/* adduw. */
588void
267b3b8e 589OP_2EB_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 590{
591 uint16 a = OP[0];
592 uint16 b = GPR (OP[1]);
593 uint16 tmp = (a + b);
594 trace_input ("adduw", OP_CONSTANT16, OP_REG, OP_VOID);
595 SET_GPR (OP[1], tmp);
267b3b8e 596 trace_output_16 (sd, tmp);
fee8ec00
SR		 597}
598
599/* adduw. */
600void
267b3b8e 601OP_2F_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 602{
603 uint16 a = GPR (OP[0]);
604 uint16 b = GPR (OP[1]);
605 uint16 tmp = (a + b);
606 trace_input ("adduw", OP_REG, OP_REG, OP_VOID);
607 SET_GPR (OP[1], tmp);
267b3b8e 608 trace_output_16 (sd, tmp);
fee8ec00
SR		 609}
610
611/* addb. */
612void
267b3b8e 613OP_30_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 614{
615 uint8 a = OP[0];
616 uint8 b = (GPR (OP[1]) & 0xff);
fee8ec00 617 uint16 tmp = (a + b) & 0xff;
5aedb83b 618 trace_input ("addb", OP_CONSTANT4_1, OP_REG, OP_VOID);
fee8ec00
SR		 619 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
620 SET_PSR_C (tmp > 0xFF);
621 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
267b3b8e 622 trace_output_16 (sd, tmp);
fee8ec00
SR		 623}
624
625/* addb. */
626void
267b3b8e 627OP_30B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 628{
629 uint8 a = (OP[0]) & 0xff;
630 uint8 b = (GPR (OP[1]) & 0xff);
fee8ec00 631 uint16 tmp = (a + b) & 0xff;
5aedb83b 632 trace_input ("addb", OP_CONSTANT16, OP_REG, OP_VOID);
fee8ec00
SR		 633 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
634 SET_PSR_C (tmp > 0xFF);
635 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
267b3b8e 636 trace_output_16 (sd, tmp);
fee8ec00
SR		 637}
638
639/* addb. */
640void
267b3b8e 641OP_31_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 642{
643 uint8 a = (GPR (OP[0]) & 0xff);
644 uint8 b = (GPR (OP[1]) & 0xff);
fee8ec00 645 uint16 tmp = (a + b) & 0xff;
5aedb83b 646 trace_input ("addb", OP_REG, OP_REG, OP_VOID);
fee8ec00
SR		 647 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
648 SET_PSR_C (tmp > 0xFF);
649 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
267b3b8e 650 trace_output_16 (sd, tmp);
fee8ec00
SR		 651}
652
653/* addw. */
654void
267b3b8e 655OP_32_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 656{
657 int16 a = OP[0];
658 uint16 tmp, b = GPR (OP[1]);
fee8ec00 659 tmp = (a + b);
5aedb83b 660 trace_input ("addw", OP_CONSTANT4_1, OP_REG, OP_VOID);
fee8ec00
SR		 661 SET_GPR (OP[1], tmp);
662 SET_PSR_C (tmp > 0xFFFF);
663 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
267b3b8e 664 trace_output_16 (sd, tmp);
fee8ec00
SR		 665}
666
667/* addw. */
668void
267b3b8e 669OP_32B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 670{
671 int16 a = OP[0];
672 uint16 tmp, b = GPR (OP[1]);
673 tmp = (a + b);
674 trace_input ("addw", OP_CONSTANT16, OP_REG, OP_VOID);
675 SET_GPR (OP[1], tmp);
676 SET_PSR_C (tmp > 0xFFFF);
677 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
267b3b8e 678 trace_output_16 (sd, tmp);
fee8ec00
SR		 679}
680
681/* addw. */
682void
267b3b8e 683OP_33_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 684{
685 uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
686 trace_input ("addw", OP_REG, OP_REG, OP_VOID);
687 tmp = (a + b);
688 SET_GPR (OP[1], tmp);
689 SET_PSR_C (tmp > 0xFFFF);
690 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
267b3b8e 691 trace_output_16 (sd, tmp);
fee8ec00
SR		 692}
693
694/* addcb. */
695void
267b3b8e 696OP_34_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 697{
698 uint8 tmp, a = OP[0] & 0xff, b = (GPR (OP[1])) & 0xff;
699 trace_input ("addcb", OP_CONSTANT4_1, OP_REG, OP_REG);
700 tmp = (a + b + PSR_C) & 0xff;
701 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
702 SET_PSR_C (tmp > 0xFF);
703 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
267b3b8e 704 trace_output_16 (sd, tmp);
fee8ec00
SR		 705}
706
707/* addcb. */
708void
267b3b8e 709OP_34B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 710{
711 int8 a = OP[0] & 0xff;
712 uint8 b = (GPR (OP[1])) & 0xff;
fee8ec00 713 uint8 tmp = (a + b + PSR_C) & 0xff;
5aedb83b 714 trace_input ("addcb", OP_CONSTANT16, OP_REG, OP_VOID);
fee8ec00
SR		 715 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
716 SET_PSR_C (tmp > 0xFF);
717 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
267b3b8e 718 trace_output_16 (sd, tmp);
fee8ec00
SR		 719}
720
721/* addcb. */
722void
267b3b8e 723OP_35_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 724{
725 uint8 a = (GPR (OP[0])) & 0xff;
726 uint8 b = (GPR (OP[1])) & 0xff;
fee8ec00 727 uint8 tmp = (a + b + PSR_C) & 0xff;
5aedb83b 728 trace_input ("addcb", OP_REG, OP_REG, OP_VOID);
fee8ec00
SR		 729 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
730 SET_PSR_C (tmp > 0xFF);
731 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
267b3b8e 732 trace_output_16 (sd, tmp);
fee8ec00
SR		 733}
734
735/* addcw. */
736void
267b3b8e 737OP_36_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 738{
739 uint16 a = OP[0];
740 uint16 b = GPR (OP[1]);
fee8ec00 741 uint16 tmp = (a + b + PSR_C);
5aedb83b 742 trace_input ("addcw", OP_CONSTANT4_1, OP_REG, OP_VOID);
fee8ec00
SR		 743 SET_GPR (OP[1], tmp);
744 SET_PSR_C (tmp > 0xFFFF);
745 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
267b3b8e 746 trace_output_16 (sd, tmp);
fee8ec00
SR		 747}
748
749/* addcw. */
750void
267b3b8e 751OP_36B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 752{
753 int16 a = OP[0];
754 uint16 b = GPR (OP[1]);
fee8ec00 755 uint16 tmp = (a + b + PSR_C);
5aedb83b 756 trace_input ("addcw", OP_CONSTANT16, OP_REG, OP_VOID);
fee8ec00
SR		 757 SET_GPR (OP[1], tmp);
758 SET_PSR_C (tmp > 0xFFFF);
759 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
267b3b8e 760 trace_output_16 (sd, tmp);
fee8ec00
SR		 761}
762
763/* addcw. */
764void
267b3b8e 765OP_37_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 766{
767 uint16 a = GPR (OP[1]);
768 uint16 b = GPR (OP[1]);
fee8ec00 769 uint16 tmp = (a + b + PSR_C);
5aedb83b 770 trace_input ("addcw", OP_REG, OP_REG, OP_VOID);
fee8ec00
SR		 771 SET_GPR (OP[1], tmp);
772 SET_PSR_C (tmp > 0xFFFF);
773 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
267b3b8e 774 trace_output_16 (sd, tmp);
fee8ec00
SR		 775}
776
777/* addd. */
778void
267b3b8e 779OP_60_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 780{
781 int16 a = (OP[0]);
782 uint32 b = GPR32 (OP[1]);
fee8ec00 783 uint32 tmp = (a + b);
5aedb83b 784 trace_input ("addd", OP_CONSTANT4_1, OP_REGP, OP_VOID);
fee8ec00
SR		 785 SET_GPR32 (OP[1], tmp);
786 SET_PSR_C (tmp > 0xFFFFFFFF);
787 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
267b3b8e 788 trace_output_32 (sd, tmp);
fee8ec00
SR		 789}
790
791/* addd. */
792void
267b3b8e 793OP_60B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 794{
795 int32 a = (SEXT16(OP[0]));
796 uint32 b = GPR32 (OP[1]);
fee8ec00 797 uint32 tmp = (a + b);
5aedb83b 798 trace_input ("addd", OP_CONSTANT16, OP_REGP, OP_VOID);
fee8ec00
SR		 799 SET_GPR32 (OP[1], tmp);
800 SET_PSR_C (tmp > 0xFFFFFFFF);
801 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
267b3b8e 802 trace_output_32 (sd, tmp);
fee8ec00
SR		 803}
804
805/* addd. */
806void
267b3b8e 807OP_61_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 808{
809 uint32 a = GPR32 (OP[0]);
810 uint32 b = GPR32 (OP[1]);
fee8ec00 811 uint32 tmp = (a + b);
5aedb83b 812 trace_input ("addd", OP_REGP, OP_REGP, OP_VOID);
fee8ec00 813 SET_GPR32 (OP[1], tmp);
267b3b8e 814 trace_output_32 (sd, tmp);
fee8ec00
SR		 815 SET_PSR_C (tmp > 0xFFFFFFFF);
816 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
817}
818
819/* addd. */
820void
267b3b8e 821OP_4_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 822{
823 uint32 a = OP[0];
824 uint32 b = GPR32 (OP[1]);
825 uint32 tmp;
826 trace_input ("addd", OP_CONSTANT20, OP_REGP, OP_VOID);
827 tmp = (a + b);
828 SET_GPR32 (OP[1], tmp);
829 SET_PSR_C (tmp > 0xFFFFFFFF);
830 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
267b3b8e 831 trace_output_32 (sd, tmp);
fee8ec00
SR		 832}
833
834/* addd. */
835void
267b3b8e 836OP_2_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 837{
838 int32 a = OP[0];
839 uint32 b = GPR32 (OP[1]);
840 uint32 tmp;
841 trace_input ("addd", OP_CONSTANT32, OP_REGP, OP_VOID);
842 tmp = (a + b);
843 SET_GPR32 (OP[1], tmp);
844 SET_PSR_C (tmp > 0xFFFFFFFF);
845 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
267b3b8e 846 trace_output_32 (sd, tmp);
fee8ec00
SR		 847}
848
849/* andb. */
850void
267b3b8e 851OP_20_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 852{
853 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
854 trace_input ("andb", OP_CONSTANT4, OP_REG, OP_VOID);
855 tmp = a & b;
856 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 857 trace_output_16 (sd, tmp);
fee8ec00
SR		 858}
859
860/* andb. */
861void
267b3b8e 862OP_20B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 863{
864 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
865 trace_input ("andb", OP_CONSTANT16, OP_REG, OP_VOID);
866 tmp = a & b;
867 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 868 trace_output_16 (sd, tmp);
fee8ec00
SR		 869}
870
871/* andb. */
872void
267b3b8e 873OP_21_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 874{
875 uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
876 trace_input ("andb", OP_REG, OP_REG, OP_VOID);
877 tmp = a & b;
878 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 879 trace_output_16 (sd, tmp);
fee8ec00
SR		 880}
881
882/* andw. */
883void
267b3b8e 884OP_22_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 885{
886 uint16 tmp, a = OP[0], b = GPR (OP[1]);
887 trace_input ("andw", OP_CONSTANT4, OP_REG, OP_VOID);
888 tmp = a & b;
889 SET_GPR (OP[1], tmp);
267b3b8e 890 trace_output_16 (sd, tmp);
fee8ec00
SR		 891}
892
893/* andw. */
894void
267b3b8e 895OP_22B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 896{
897 uint16 tmp, a = OP[0], b = GPR (OP[1]);
898 trace_input ("andw", OP_CONSTANT16, OP_REG, OP_VOID);
899 tmp = a & b;
900 SET_GPR (OP[1], tmp);
267b3b8e 901 trace_output_16 (sd, tmp);
fee8ec00
SR		 902}
903
904/* andw. */
905void
267b3b8e 906OP_23_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 907{
908 uint16 tmp, a = GPR (OP[0]), b = GPR (OP[1]);
909 trace_input ("andw", OP_REG, OP_REG, OP_VOID);
910 tmp = a & b;
911 SET_GPR (OP[1], tmp);
267b3b8e 912 trace_output_16 (sd, tmp);
fee8ec00
SR		 913}
914
915/* andd. */
916void
267b3b8e 917OP_4_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 918{
919 uint32 tmp, a = OP[0], b = GPR32 (OP[1]);
920 trace_input ("andd", OP_CONSTANT32, OP_REGP, OP_VOID);
921 tmp = a & b;
922 SET_GPR32 (OP[1], tmp);
267b3b8e 923 trace_output_32 (sd, tmp);
fee8ec00
SR		 924}
925
926/* andd. */
927void
267b3b8e 928OP_14B_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 929{
930 uint32 tmp, a = (GPR32 (OP[0])), b = (GPR32 (OP[1]));
931 trace_input ("andd", OP_REGP, OP_REGP, OP_VOID);
932 tmp = a & b;
933 SET_GPR32 (OP[1], tmp);
267b3b8e 934 trace_output_32 (sd, tmp);
fee8ec00
SR		 935}
936
937/* ord. */
938void
267b3b8e 939OP_5_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 940{
941 uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]);
942 trace_input ("ord", OP_CONSTANT32, OP_REG, OP_VOID);
943 tmp = a | b;
944 SET_GPR32 (OP[1], tmp);
267b3b8e 945 trace_output_32 (sd, tmp);
fee8ec00
SR		 946}
947
948/* ord. */
949void
267b3b8e 950OP_149_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 951{
952 uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
953 trace_input ("ord", OP_REGP, OP_REGP, OP_VOID);
954 tmp = a | b;
955 SET_GPR32 (OP[1], tmp);
267b3b8e 956 trace_output_32 (sd, tmp);
fee8ec00
SR		 957}
958
959/* xord. */
960void
267b3b8e 961OP_6_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 962{
963 uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]);
964 trace_input ("xord", OP_CONSTANT32, OP_REG, OP_VOID);
965 tmp = a ^ b;
966 SET_GPR32 (OP[1], tmp);
267b3b8e 967 trace_output_32 (sd, tmp);
fee8ec00
SR		 968}
969
970/* xord. */
971void
267b3b8e 972OP_14A_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 973{
974 uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
975 trace_input ("xord", OP_REGP, OP_REGP, OP_VOID);
976 tmp = a ^ b;
977 SET_GPR32 (OP[1], tmp);
267b3b8e 978 trace_output_32 (sd, tmp);
fee8ec00
SR		 979}
980
981
982/* b. */
983void
267b3b8e 984OP_1_4 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 985{
5aedb83b 986 uint32 tmp = 0, cc = cond_stat (OP[0]);
fee8ec00
SR		 987 trace_input ("b", OP_CONSTANT4, OP_DISPE9, OP_VOID);
988 if (cc)
989 {
990 if (sign_flag)
991 tmp = (PC - (OP[1]));
992 else
993 tmp = (PC + (OP[1]));
994 /* If the resulting PC value is less than 0x00_0000 or greater
995 than 0xFF_FFFF, this instruction causes an IAD trap.*/
996
997 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
998 {
267b3b8e 999 trace_output_void (sd);
0ef7f981 1000 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 1001 }
1002 else
1003 JMP (tmp);
1004 }
1005 sign_flag = 0; /* Reset sign_flag. */
267b3b8e 1006 trace_output_32 (sd, tmp);
fee8ec00
SR		 1007}
1008
1009/* b. */
1010void
267b3b8e 1011OP_18_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1012{
5aedb83b 1013 uint32 tmp = 0, cc = cond_stat (OP[0]);
fee8ec00
SR		 1014 trace_input ("b", OP_CONSTANT4, OP_DISP17, OP_VOID);
1015 if (cc)
1016 {
1017 if (sign_flag)
1018 tmp = (PC - OP[1]);
1019 else
1020 tmp = (PC + OP[1]);
1021 /* If the resulting PC value is less than 0x00_0000 or greater
1022 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1023
1024 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1025 {
267b3b8e 1026 trace_output_void (sd);
0ef7f981 1027 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 1028 }
1029 else
1030 JMP (tmp);
1031 }
1032 sign_flag = 0; /* Reset sign_flag. */
267b3b8e 1033 trace_output_32 (sd, tmp);
fee8ec00
SR		 1034}
1035
1036/* b. */
1037void
267b3b8e 1038OP_10_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1039{
5aedb83b 1040 uint32 tmp = 0, cc = cond_stat (OP[0]);
fee8ec00
SR		 1041 trace_input ("b", OP_CONSTANT4, OP_DISP25, OP_VOID);
1042 if (cc)
1043 {
1044 if (sign_flag)
1045 tmp = (PC - (OP[1]));
1046 else
1047 tmp = (PC + (OP[1]));
1048 /* If the resulting PC value is less than 0x00_0000 or greater
1049 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1050
1051 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1052 {
267b3b8e 1053 trace_output_void (sd);
0ef7f981 1054 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 1055 }
1056 else
1057 JMP (tmp);
1058 }
1059 sign_flag = 0; /* Reset sign_flag. */
267b3b8e 1060 trace_output_32 (sd, tmp);
fee8ec00
SR		 1061}
1062
1063/* bal. */
1064void
267b3b8e 1065OP_C0_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1066{
1067 uint32 tmp;
1068 trace_input ("bal", OP_REG, OP_DISP17, OP_VOID);
1069 tmp = ((PC + 4) >> 1); /* Store PC in RA register. */
1070 SET_GPR32 (14, tmp);
1071 if (sign_flag)
1072 tmp = (PC - (OP[1]));
1073 else
1074 tmp = (PC + (OP[1]));
1075
1076 /* If the resulting PC value is less than 0x00_0000 or greater
1077 than 0xFF_FFFF, this instruction causes an IAD trap. */
1078
1079 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1080 {
267b3b8e 1081 trace_output_void (sd);
0ef7f981 1082 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 1083 }
1084 else
1085 JMP (tmp);
1086 sign_flag = 0; /* Reset sign_flag. */
267b3b8e 1087 trace_output_32 (sd, tmp);
fee8ec00
SR		 1088}
1089
1090
1091/* bal. */
1092void
267b3b8e 1093OP_102_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1094{
1095 uint32 tmp;
1096 trace_input ("bal", OP_REGP, OP_DISP25, OP_VOID);
1097 tmp = (((PC) + 4) >> 1); /* Store PC in reg pair. */
1098 SET_GPR32 (OP[0], tmp);
1099 if (sign_flag)
1100 tmp = ((PC) - (OP[1]));
1101 else
1102 tmp = ((PC) + (OP[1]));
1103 /* If the resulting PC value is less than 0x00_0000 or greater
1104 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1105
1106 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1107 {
267b3b8e 1108 trace_output_void (sd);
0ef7f981 1109 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 1110 }
1111 else
1112 JMP (tmp);
1113 sign_flag = 0; /* Reset sign_flag. */
267b3b8e 1114 trace_output_32 (sd, tmp);
fee8ec00
SR		 1115}
1116
1117/* jal. */
1118void
267b3b8e 1119OP_148_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1120{
1121 uint32 tmp;
1122 trace_input ("jal", OP_REGP, OP_REGP, OP_VOID);
1123 SET_GPR32 (OP[0], (((PC) + 4) >> 1)); /* Store next PC in RA */
1124 tmp = GPR32 (OP[1]);
1125 tmp = SEXT24(tmp << 1);
1126 /* If the resulting PC value is less than 0x00_0000 or greater
1127 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1128
1129 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
1130 {
267b3b8e 1131 trace_output_void (sd);
0ef7f981 1132 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 1133 }
1134 else
1135 JMP (tmp);
1136
267b3b8e 1137 trace_output_32 (sd, tmp);
fee8ec00
SR		 1138}
1139
1140
1141/* jal. */
1142void
267b3b8e 1143OP_D_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1144{
1145 uint32 tmp;
1146 trace_input ("jal", OP_REGP, OP_VOID, OP_VOID);
1147 SET_GPR32 (14, (((PC) + 2) >> 1)); /* Store next PC in RA */
1148 tmp = GPR32 (OP[0]);
1149 tmp = SEXT24(tmp << 1);
1150 /* If the resulting PC value is less than 0x00_0000 or greater
1151 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1152
1153 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
1154 {
267b3b8e 1155 trace_output_void (sd);
0ef7f981 1156 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 1157 }
1158 else
1159 JMP (tmp);
1160
267b3b8e 1161 trace_output_32 (sd, tmp);
fee8ec00
SR		 1162}
1163
1164
1165/* beq0b. */
1166void
267b3b8e 1167OP_C_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1168{
1169 uint32 addr;
1170 uint8 a = (GPR (OP[0]) & 0xFF);
1171 trace_input ("beq0b", OP_REG, OP_DISP5, OP_VOID);
1172 addr = OP[1];
1173 if (a == 0)
1174 {
1175 if (sign_flag)
1176 addr = (PC - OP[1]);
1177 else
1178 addr = (PC + OP[1]);
1179
1180 JMP (addr);
1181 }
1182 sign_flag = 0; /* Reset sign_flag. */
267b3b8e 1183 trace_output_void (sd);
fee8ec00
SR		 1184}
1185
1186/* bne0b. */
1187void
267b3b8e 1188OP_D_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1189{
1190 uint32 addr;
1191 uint8 a = (GPR (OP[0]) & 0xFF);
1192 trace_input ("bne0b", OP_REG, OP_DISP5, OP_VOID);
1193 addr = OP[1];
1194 if (a != 0)
1195 {
1196 if (sign_flag)
1197 addr = (PC - OP[1]);
1198 else
1199 addr = (PC + OP[1]);
1200
1201 JMP (addr);
1202 }
1203 sign_flag = 0; /* Reset sign_flag. */
267b3b8e 1204 trace_output_void (sd);
fee8ec00
SR		 1205}
1206
1207/* beq0w. */
1208void
267b3b8e 1209OP_E_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1210{
1211 uint32 addr;
1212 uint16 a = GPR (OP[0]);
1213 trace_input ("beq0w", OP_REG, OP_DISP5, OP_VOID);
1214 addr = OP[1];
1215 if (a == 0)
1216 {
1217 if (sign_flag)
1218 addr = (PC - OP[1]);
1219 else
1220 addr = (PC + OP[1]);
1221
1222 JMP (addr);
1223 }
1224 sign_flag = 0; /* Reset sign_flag. */
267b3b8e 1225 trace_output_void (sd);
fee8ec00
SR		 1226}
1227
1228/* bne0w. */
1229void
267b3b8e 1230OP_F_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1231{
1232 uint32 addr;
1233 uint16 a = GPR (OP[0]);
1234 trace_input ("bne0w", OP_REG, OP_DISP5, OP_VOID);
1235 addr = OP[1];
1236 if (a != 0)
1237 {
1238 if (sign_flag)
1239 addr = (PC - OP[1]);
1240 else
1241 addr = (PC + OP[1]);
1242
1243 JMP (addr);
1244 }
1245 sign_flag = 0; /* Reset sign_flag. */
267b3b8e 1246 trace_output_void (sd);
fee8ec00
SR		 1247}
1248
1249
1250/* jeq. */
1251void
267b3b8e 1252OP_A0_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1253{
5aedb83b 1254 uint32 tmp = 0;
fee8ec00
SR		 1255 trace_input ("jeq", OP_REGP, OP_VOID, OP_VOID);
1256 if ((PSR_Z) == 1)
1257 {
1258 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */
1259 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */
1260 }
267b3b8e 1261 trace_output_32 (sd, tmp);
fee8ec00
SR		 1262}
1263
1264/* jne. */
1265void
267b3b8e 1266OP_A1_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1267{
5aedb83b 1268 uint32 tmp = 0;
fee8ec00
SR		 1269 trace_input ("jne", OP_REGP, OP_VOID, OP_VOID);
1270 if ((PSR_Z) == 0)
1271 {
1272 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */
1273 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */
1274 }
267b3b8e 1275 trace_output_32 (sd, tmp);
fee8ec00
SR		 1276}
1277
1278/* jcs. */
1279void
267b3b8e 1280OP_A2_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1281{
5aedb83b 1282 uint32 tmp = 0;
fee8ec00
SR		 1283 trace_input ("jcs", OP_REGP, OP_VOID, OP_VOID);
1284 if ((PSR_C) == 1)
1285 {
1286 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1287 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1288 }
267b3b8e 1289 trace_output_32 (sd, tmp);
fee8ec00
SR		 1290}
1291
1292/* jcc. */
1293void
267b3b8e 1294OP_A3_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1295{
5aedb83b 1296 uint32 tmp = 0;
fee8ec00
SR		 1297 trace_input ("jcc", OP_REGP, OP_VOID, OP_VOID);
1298 if ((PSR_C) == 0)
1299 {
1300 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1301 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1302 }
267b3b8e 1303 trace_output_32 (sd, tmp);
fee8ec00
SR		 1304}
1305
1306/* jhi. */
1307void
267b3b8e 1308OP_A4_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1309{
5aedb83b 1310 uint32 tmp = 0;
fee8ec00
SR		 1311 trace_input ("jhi", OP_REGP, OP_VOID, OP_VOID);
1312 if ((PSR_L) == 1)
1313 {
1314 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1315 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1316 }
267b3b8e 1317 trace_output_32 (sd, tmp);
fee8ec00
SR		 1318}
1319
1320/* jls. */
1321void
267b3b8e 1322OP_A5_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1323{
5aedb83b 1324 uint32 tmp = 0;
fee8ec00
SR		 1325 trace_input ("jls", OP_REGP, OP_VOID, OP_VOID);
1326 if ((PSR_L) == 0)
1327 {
1328 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1329 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1330 }
267b3b8e 1331 trace_output_32 (sd, tmp);
fee8ec00
SR		 1332}
1333
1334/* jgt. */
1335void
267b3b8e 1336OP_A6_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1337{
5aedb83b 1338 uint32 tmp = 0;
fee8ec00
SR		 1339 trace_input ("jgt", OP_REGP, OP_VOID, OP_VOID);
1340 if ((PSR_N) == 1)
1341 {
1342 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1343 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1344 }
267b3b8e 1345 trace_output_32 (sd, tmp);
fee8ec00
SR		 1346}
1347
1348/* jle. */
1349void
267b3b8e 1350OP_A7_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1351{
5aedb83b 1352 uint32 tmp = 0;
fee8ec00
SR		 1353 trace_input ("jle", OP_REGP, OP_VOID, OP_VOID);
1354 if ((PSR_N) == 0)
1355 {
1356 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1357 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1358 }
267b3b8e 1359 trace_output_32 (sd, tmp);
fee8ec00
SR		 1360}
1361
1362
1363/* jfs. */
1364void
267b3b8e 1365OP_A8_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1366{
5aedb83b 1367 uint32 tmp = 0;
fee8ec00
SR		 1368 trace_input ("jfs", OP_REGP, OP_VOID, OP_VOID);
1369 if ((PSR_F) == 1)
1370 {
1371 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1372 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1373 }
267b3b8e 1374 trace_output_32 (sd, tmp);
fee8ec00
SR		 1375}
1376
1377/* jfc. */
1378void
267b3b8e 1379OP_A9_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1380{
5aedb83b 1381 uint32 tmp = 0;
fee8ec00
SR		 1382 trace_input ("jfc", OP_REGP, OP_VOID, OP_VOID);
1383 if ((PSR_F) == 0)
1384 {
1385 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1386 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1387 }
267b3b8e 1388 trace_output_32 (sd, tmp);
fee8ec00
SR		 1389}
1390
1391/* jlo. */
1392void
267b3b8e 1393OP_AA_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1394{
5aedb83b 1395 uint32 tmp = 0;
fee8ec00
SR		 1396 trace_input ("jlo", OP_REGP, OP_VOID, OP_VOID);
1397 if (((PSR_Z) == 0) & ((PSR_L) == 0))
1398 {
1399 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1400 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1401 }
267b3b8e 1402 trace_output_32 (sd, tmp);
fee8ec00
SR		 1403}
1404
1405/* jhs. */
1406void
267b3b8e 1407OP_AB_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1408{
5aedb83b 1409 uint32 tmp = 0;
fee8ec00
SR		 1410 trace_input ("jhs", OP_REGP, OP_VOID, OP_VOID);
1411 if (((PSR_Z) == 1) | ((PSR_L) == 1))
1412 {
1413 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1414 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1415 }
267b3b8e 1416 trace_output_32 (sd, tmp);
fee8ec00
SR		 1417}
1418
1419/* jlt. */
1420void
267b3b8e 1421OP_AC_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1422{
5aedb83b 1423 uint32 tmp = 0;
fee8ec00
SR		 1424 trace_input ("jlt", OP_REGP, OP_VOID, OP_VOID);
1425 if (((PSR_Z) == 0) & ((PSR_N) == 0))
1426 {
1427 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1428 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1429 }
267b3b8e 1430 trace_output_32 (sd, tmp);
fee8ec00
SR		 1431}
1432
1433/* jge. */
1434void
267b3b8e 1435OP_AD_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 1436{
5aedb83b 1437 uint32 tmp = 0;
fee8ec00
SR		 1438 trace_input ("jge", OP_REGP, OP_VOID, OP_VOID);
1439 if (((PSR_Z) == 1) | ((PSR_N) == 1))
1440 {
1441 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1442 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1443 }
267b3b8e 1444 trace_output_32 (sd, tmp);
fee8ec00
SR		 1445}
1446
1447/* jump. */
1448void
267b3b8e 1449OP_AE_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1450{
1451 uint32 tmp;
1452 trace_input ("jump", OP_REGP, OP_VOID, OP_VOID);
1453 tmp = GPR32 (OP[0]) /*& 0x3fffff*/; /* Use only 0 - 22 bits */
1454 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
267b3b8e 1455 trace_output_32 (sd, tmp);
fee8ec00
SR		 1456}
1457
1458/* jusr. */
1459void
267b3b8e 1460OP_AF_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1461{
1462 uint32 tmp;
1463 trace_input ("jusr", OP_REGP, OP_VOID, OP_VOID);
1464 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1465 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1466 SET_PSR_U(1);
267b3b8e 1467 trace_output_32 (sd, tmp);
fee8ec00
SR		 1468}
1469
1470/* seq. */
1471void
267b3b8e 1472OP_80_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1473{
1474 trace_input ("seq", OP_REG, OP_VOID, OP_VOID);
1475 if ((PSR_Z) == 1)
1476 SET_GPR (OP[0], 1);
1477 else
1478 SET_GPR (OP[0], 0);
267b3b8e 1479 trace_output_void (sd);
fee8ec00
SR		 1480}
1481/* sne. */
1482void
267b3b8e 1483OP_81_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1484{
1485 trace_input ("sne", OP_REG, OP_VOID, OP_VOID);
1486 if ((PSR_Z) == 0)
1487 SET_GPR (OP[0], 1);
1488 else
1489 SET_GPR (OP[0], 0);
267b3b8e 1490 trace_output_void (sd);
fee8ec00
SR		 1491}
1492
1493/* scs. */
1494void
267b3b8e 1495OP_82_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1496{
1497 trace_input ("scs", OP_REG, OP_VOID, OP_VOID);
1498 if ((PSR_C) == 1)
1499 SET_GPR (OP[0], 1);
1500 else
1501 SET_GPR (OP[0], 0);
267b3b8e 1502 trace_output_void (sd);
fee8ec00
SR		 1503}
1504
1505/* scc. */
1506void
267b3b8e 1507OP_83_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1508{
1509 trace_input ("scc", OP_REG, OP_VOID, OP_VOID);
1510 if ((PSR_C) == 0)
1511 SET_GPR (OP[0], 1);
1512 else
1513 SET_GPR (OP[0], 0);
267b3b8e 1514 trace_output_void (sd);
fee8ec00
SR		 1515}
1516
1517/* shi. */
1518void
267b3b8e 1519OP_84_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1520{
1521 trace_input ("shi", OP_REG, OP_VOID, OP_VOID);
1522 if ((PSR_L) == 1)
1523 SET_GPR (OP[0], 1);
1524 else
1525 SET_GPR (OP[0], 0);
267b3b8e 1526 trace_output_void (sd);
fee8ec00
SR		 1527}
1528
1529/* sls. */
1530void
267b3b8e 1531OP_85_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1532{
1533 trace_input ("sls", OP_REG, OP_VOID, OP_VOID);
1534 if ((PSR_L) == 0)
1535 SET_GPR (OP[0], 1);
1536 else
1537 SET_GPR (OP[0], 0);
267b3b8e 1538 trace_output_void (sd);
fee8ec00
SR		 1539}
1540
1541/* sgt. */
1542void
267b3b8e 1543OP_86_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1544{
1545 trace_input ("sgt", OP_REG, OP_VOID, OP_VOID);
1546 if ((PSR_N) == 1)
1547 SET_GPR (OP[0], 1);
1548 else
1549 SET_GPR (OP[0], 0);
267b3b8e 1550 trace_output_void (sd);
fee8ec00
SR		 1551}
1552
1553/* sle. */
1554void
267b3b8e 1555OP_87_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1556{
1557 trace_input ("sle", OP_REG, OP_VOID, OP_VOID);
1558 if ((PSR_N) == 0)
1559 SET_GPR (OP[0], 1);
1560 else
1561 SET_GPR (OP[0], 0);
267b3b8e 1562 trace_output_void (sd);
fee8ec00
SR		 1563}
1564
1565/* sfs. */
1566void
267b3b8e 1567OP_88_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1568{
1569 trace_input ("sfs", OP_REG, OP_VOID, OP_VOID);
1570 if ((PSR_F) == 1)
1571 SET_GPR (OP[0], 1);
1572 else
1573 SET_GPR (OP[0], 0);
267b3b8e 1574 trace_output_void (sd);
fee8ec00
SR		 1575}
1576
1577/* sfc. */
1578void
267b3b8e 1579OP_89_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1580{
1581 trace_input ("sfc", OP_REG, OP_VOID, OP_VOID);
1582 if ((PSR_F) == 0)
1583 SET_GPR (OP[0], 1);
1584 else
1585 SET_GPR (OP[0], 0);
267b3b8e 1586 trace_output_void (sd);
fee8ec00
SR		 1587}
1588
1589
1590/* slo. */
1591void
267b3b8e 1592OP_8A_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1593{
1594 trace_input ("slo", OP_REG, OP_VOID, OP_VOID);
1595 if (((PSR_Z) == 0) & ((PSR_L) == 0))
1596 SET_GPR (OP[0], 1);
1597 else
1598 SET_GPR (OP[0], 0);
267b3b8e 1599 trace_output_void (sd);
fee8ec00
SR		 1600}
1601
1602/* shs. */
1603void
267b3b8e 1604OP_8B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1605{
1606 trace_input ("shs", OP_REG, OP_VOID, OP_VOID);
1607 if ( ((PSR_Z) == 1) | ((PSR_L) == 1))
1608 SET_GPR (OP[0], 1);
1609 else
1610 SET_GPR (OP[0], 0);
267b3b8e 1611 trace_output_void (sd);
fee8ec00
SR		 1612}
1613
1614/* slt. */
1615void
267b3b8e 1616OP_8C_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1617{
1618 trace_input ("slt", OP_REG, OP_VOID, OP_VOID);
1619 if (((PSR_Z) == 0) & ((PSR_N) == 0))
1620 SET_GPR (OP[0], 1);
1621 else
1622 SET_GPR (OP[0], 0);
267b3b8e 1623 trace_output_void (sd);
fee8ec00
SR		 1624}
1625
1626/* sge. */
1627void
267b3b8e 1628OP_8D_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1629{
1630 trace_input ("sge", OP_REG, OP_VOID, OP_VOID);
1631 if (((PSR_Z) == 1) | ((PSR_N) == 1))
1632 SET_GPR (OP[0], 1);
1633 else
1634 SET_GPR (OP[0], 0);
267b3b8e 1635 trace_output_void (sd);
fee8ec00
SR		 1636}
1637
1638/* cbitb. */
1639void
267b3b8e 1640OP_D7_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1641{
1642 uint8 a = OP[0] & 0xff;
1643 uint32 addr = OP[1], tmp;
1644 trace_input ("cbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1645 tmp = RB (addr);
1646 SET_PSR_F (tmp & (1 << a));
1647 tmp = tmp & ~(1 << a);
1648 SB (addr, tmp);
267b3b8e 1649 trace_output_32 (sd, tmp);
fee8ec00
SR		 1650}
1651
1652/* cbitb. */
1653void
267b3b8e 1654OP_107_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1655{
1656 uint8 a = OP[0] & 0xff;
1657 uint32 addr = OP[1], tmp;
1658 trace_input ("cbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1659 tmp = RB (addr);
1660 SET_PSR_F (tmp & (1 << a));
1661 tmp = tmp & ~(1 << a);
1662 SB (addr, tmp);
267b3b8e 1663 trace_output_32 (sd, tmp);
fee8ec00
SR		 1664}
1665
1666/* cbitb. */
1667void
267b3b8e 1668OP_68_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1669{
1670 uint8 a = (OP[0]) & 0xff;
1671 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1672 trace_input ("cbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
1673 tmp = RB (addr);
1674 SET_PSR_F (tmp & (1 << a));
1675 tmp = tmp & ~(1 << a);
1676 SB (addr, tmp);
267b3b8e 1677 trace_output_32 (sd, addr);
fee8ec00
SR		 1678}
1679
1680/* cbitb. */
1681void
267b3b8e 1682OP_1AA_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1683{
1684 uint8 a = (OP[0]) & 0xff;
1685 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1686 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1687 tmp = RB (addr);
1688 SET_PSR_F (tmp & (1 << a));
1689 tmp = tmp & ~(1 << a);
1690 SB (addr, tmp);
267b3b8e 1691 trace_output_32 (sd, addr);
fee8ec00
SR		 1692}
1693
1694/* cbitb. */
1695void
267b3b8e 1696OP_104_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1697{
1698 uint8 a = (OP[0]) & 0xff;
1699 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1700 trace_input ("cbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1701 tmp = RB (addr);
1702 SET_PSR_F (tmp & (1 << a));
1703 tmp = tmp & ~(1 << a);
1704 SB (addr, tmp);
267b3b8e 1705 trace_output_32 (sd, addr);
fee8ec00
SR		 1706}
1707
1708/* cbitb. */
1709void
267b3b8e 1710OP_D4_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1711{
1712 uint8 a = (OP[0]) & 0xff;
1713 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1714 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1715 tmp = RB (addr);
1716 SET_PSR_F (tmp & (1 << a));
1717 tmp = tmp & ~(1 << a);
1718 SB (addr, tmp);
267b3b8e 1719 trace_output_32 (sd, addr);
fee8ec00
SR		 1720}
1721
1722/* cbitb. */
1723void
267b3b8e 1724OP_D6_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1725{
1726 uint8 a = (OP[0]) & 0xff;
1727 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1728 trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
1729 tmp = RB (addr);
1730 SET_PSR_F (tmp & (1 << a));
1731 tmp = tmp & ~(1 << a);
1732 SB (addr, tmp);
267b3b8e 1733 trace_output_32 (sd, addr);
fee8ec00
SR		 1734
1735}
1736
1737/* cbitb. */
1738void
267b3b8e 1739OP_105_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1740{
1741 uint8 a = (OP[0]) & 0xff;
1742 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1743 trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
1744 tmp = RB (addr);
1745 SET_PSR_F (tmp & (1 << a));
1746 tmp = tmp & ~(1 << a);
1747 SB (addr, tmp);
267b3b8e 1748 trace_output_32 (sd, addr);
fee8ec00
SR		 1749}
1750
1751/* cbitb. */
1752void
267b3b8e 1753OP_106_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1754{
1755 uint8 a = (OP[0]) & 0xff;
1756 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1757 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
1758 tmp = RB (addr);
1759 SET_PSR_F (tmp & (1 << a));
1760 tmp = tmp & ~(1 << a);
1761 SB (addr, tmp);
267b3b8e 1762 trace_output_32 (sd, addr);
fee8ec00
SR		 1763}
1764
1765
1766/* cbitw. */
1767void
267b3b8e 1768OP_6F_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1769{
1770 uint16 a = OP[0];
1771 uint32 addr = OP[1], tmp;
1772 trace_input ("cbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1773 tmp = RW (addr);
1774 SET_PSR_F (tmp & (1 << a));
1775 tmp = tmp & ~(1 << a);
1776 SW (addr, tmp);
267b3b8e 1777 trace_output_32 (sd, tmp);
fee8ec00
SR		 1778}
1779
1780/* cbitw. */
1781void
267b3b8e 1782OP_117_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1783{
1784 uint16 a = OP[0];
1785 uint32 addr = OP[1], tmp;
1786 trace_input ("cbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1787 tmp = RW (addr);
1788 SET_PSR_F (tmp & (1 << a));
1789 tmp = tmp & ~(1 << a);
1790 SW (addr, tmp);
267b3b8e 1791 trace_output_32 (sd, tmp);
fee8ec00
SR		 1792}
1793
1794/* cbitw. */
1795void
267b3b8e 1796OP_36_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1797{
1798 uint32 addr;
1799 uint16 a = (OP[0]), tmp;
1800 trace_input ("cbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
1801
1802 if (OP[1] == 0)
1803 addr = (GPR32 (12)) + OP[2];
1804 else
1805 addr = (GPR32 (13)) + OP[2];
1806
1807 tmp = RW (addr);
1808 SET_PSR_F (tmp & (1 << a));
1809 tmp = tmp & ~(1 << a);
1810 SW (addr, tmp);
267b3b8e 1811 trace_output_32 (sd, addr);
fee8ec00
SR		 1812
1813}
1814
1815/* cbitw. */
1816void
267b3b8e 1817OP_1AB_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1818{
1819 uint16 a = (OP[0]);
1820 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1821 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1822 tmp = RW (addr);
1823 SET_PSR_F (tmp & (1 << a));
1824 tmp = tmp & ~(1 << a);
1825 SW (addr, tmp);
267b3b8e 1826 trace_output_32 (sd, addr);
fee8ec00
SR		 1827}
1828
1829/* cbitw. */
1830void
267b3b8e 1831OP_114_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1832{
1833 uint16 a = (OP[0]);
1834 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1835 trace_input ("cbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1836 tmp = RW (addr);
1837 SET_PSR_F (tmp & (1 << a));
1838 tmp = tmp & ~(1 << a);
1839 SW (addr, tmp);
267b3b8e 1840 trace_output_32 (sd, addr);
fee8ec00
SR		 1841}
1842
1843
1844/* cbitw. */
1845void
267b3b8e 1846OP_6E_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1847{
1848 uint16 a = (OP[0]);
1849 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1850 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1851 tmp = RW (addr);
1852 SET_PSR_F (tmp & (1 << a));
1853 tmp = tmp & ~(1 << a);
1854 SW (addr, tmp);
267b3b8e 1855 trace_output_32 (sd, addr);
fee8ec00
SR		 1856}
1857
1858/* cbitw. */
1859void
267b3b8e 1860OP_69_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1861{
1862 uint16 a = (OP[0]);
1863 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1864 trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
1865 tmp = RW (addr);
1866 SET_PSR_F (tmp & (1 << a));
1867 tmp = tmp & ~(1 << a);
1868 SW (addr, tmp);
267b3b8e 1869 trace_output_32 (sd, addr);
fee8ec00
SR		 1870}
1871
1872
1873/* cbitw. */
1874void
267b3b8e 1875OP_115_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1876{
1877 uint16 a = (OP[0]);
1878 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1879 trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
1880 tmp = RW (addr);
1881 SET_PSR_F (tmp & (1 << a));
1882 tmp = tmp & ~(1 << a);
1883 SW (addr, tmp);
267b3b8e 1884 trace_output_32 (sd, addr);
fee8ec00
SR		 1885}
1886
1887/* cbitw. */
1888void
267b3b8e 1889OP_116_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1890{
1891 uint16 a = (OP[0]);
1892 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1893 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
1894 tmp = RW (addr);
1895 SET_PSR_F (tmp & (1 << a));
1896 tmp = tmp & ~(1 << a);
1897 SW (addr, tmp);
267b3b8e 1898 trace_output_32 (sd, addr);
fee8ec00
SR		 1899}
1900
1901/* sbitb. */
1902void
267b3b8e 1903OP_E7_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1904{
1905 uint8 a = OP[0] & 0xff;
1906 uint32 addr = OP[1], tmp;
1907 trace_input ("sbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1908 tmp = RB (addr);
1909 SET_PSR_F (tmp & (1 << a));
1910 tmp = tmp | (1 << a);
1911 SB (addr, tmp);
267b3b8e 1912 trace_output_32 (sd, tmp);
fee8ec00
SR		 1913}
1914
1915/* sbitb. */
1916void
267b3b8e 1917OP_10B_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1918{
1919 uint8 a = OP[0] & 0xff;
1920 uint32 addr = OP[1], tmp;
1921 trace_input ("sbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1922 tmp = RB (addr);
1923 SET_PSR_F (tmp & (1 << a));
1924 tmp = tmp | (1 << a);
1925 SB (addr, tmp);
267b3b8e 1926 trace_output_32 (sd, tmp);
fee8ec00
SR		 1927}
1928
1929/* sbitb. */
1930void
267b3b8e 1931OP_70_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1932{
1933 uint8 a = OP[0] & 0xff;
1934 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1935 trace_input ("sbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
1936 tmp = RB (addr);
1937 SET_PSR_F (tmp & (1 << a));
1938 tmp = tmp | (1 << a);
1939 SB (addr, tmp);
267b3b8e 1940 trace_output_32 (sd, tmp);
fee8ec00
SR		 1941}
1942
1943/* sbitb. */
1944void
267b3b8e 1945OP_1CA_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1946{
1947 uint8 a = OP[0] & 0xff;
1948 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1949 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1950 tmp = RB (addr);
1951 SET_PSR_F (tmp & (1 << a));
1952 tmp = tmp | (1 << a);
1953 SB (addr, tmp);
267b3b8e 1954 trace_output_32 (sd, tmp);
fee8ec00
SR		 1955}
1956
1957/* sbitb. */
1958void
267b3b8e 1959OP_108_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1960{
1961 uint8 a = OP[0] & 0xff;
1962 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1963 trace_input ("sbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1964 tmp = RB (addr);
1965 SET_PSR_F (tmp & (1 << a));
1966 tmp = tmp | (1 << a);
1967 SB (addr, tmp);
267b3b8e 1968 trace_output_32 (sd, tmp);
fee8ec00
SR		 1969}
1970
1971
1972/* sbitb. */
1973void
267b3b8e 1974OP_E4_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1975{
1976 uint8 a = OP[0] & 0xff;
1977 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1978 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1979 tmp = RB (addr);
1980 SET_PSR_F (tmp & (1 << a));
1981 tmp = tmp | (1 << a);
1982 SB (addr, tmp);
267b3b8e 1983 trace_output_32 (sd, tmp);
fee8ec00
SR		 1984}
1985
1986/* sbitb. */
1987void
267b3b8e 1988OP_E6_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 1989{
1990 uint8 a = OP[0] & 0xff;
1991 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1992 trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
1993 tmp = RB (addr);
1994 SET_PSR_F (tmp & (1 << a));
1995 tmp = tmp | (1 << a);
1996 SB (addr, tmp);
267b3b8e 1997 trace_output_32 (sd, tmp);
fee8ec00
SR		 1998}
1999
2000
2001/* sbitb. */
2002void
267b3b8e 2003OP_109_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2004{
2005 uint8 a = OP[0] & 0xff;
2006 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2007 trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2008 tmp = RB (addr);
2009 SET_PSR_F (tmp & (1 << a));
2010 tmp = tmp | (1 << a);
2011 SB (addr, tmp);
267b3b8e 2012 trace_output_32 (sd, tmp);
fee8ec00
SR		 2013}
2014
2015
2016/* sbitb. */
2017void
267b3b8e 2018OP_10A_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2019{
2020 uint8 a = OP[0] & 0xff;
2021 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2022 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2023 tmp = RB (addr);
2024 SET_PSR_F (tmp & (1 << a));
2025 tmp = tmp | (1 << a);
2026 SB (addr, tmp);
267b3b8e 2027 trace_output_32 (sd, tmp);
fee8ec00
SR		 2028}
2029
2030
2031/* sbitw. */
2032void
267b3b8e 2033OP_77_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2034{
2035 uint16 a = OP[0];
2036 uint32 addr = OP[1], tmp;
2037 trace_input ("sbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2038 tmp = RW (addr);
2039 SET_PSR_F (tmp & (1 << a));
2040 tmp = tmp | (1 << a);
2041 SW (addr, tmp);
267b3b8e 2042 trace_output_32 (sd, tmp);
fee8ec00
SR		 2043}
2044
2045/* sbitw. */
2046void
267b3b8e 2047OP_11B_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2048{
2049 uint16 a = OP[0];
2050 uint32 addr = OP[1], tmp;
2051 trace_input ("sbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2052 tmp = RW (addr);
2053 SET_PSR_F (tmp & (1 << a));
2054 tmp = tmp | (1 << a);
2055 SW (addr, tmp);
267b3b8e 2056 trace_output_32 (sd, tmp);
fee8ec00
SR		 2057}
2058
2059/* sbitw. */
2060void
267b3b8e 2061OP_3A_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2062{
2063 uint32 addr;
2064 uint16 a = (OP[0]), tmp;
2065 trace_input ("sbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
2066
2067 if (OP[1] == 0)
2068 addr = (GPR32 (12)) + OP[2];
2069 else
2070 addr = (GPR32 (13)) + OP[2];
2071
2072 tmp = RW (addr);
2073 SET_PSR_F (tmp & (1 << a));
2074 tmp = tmp | (1 << a);
2075 SW (addr, tmp);
267b3b8e 2076 trace_output_32 (sd, addr);
fee8ec00
SR		 2077}
2078
2079/* sbitw. */
2080void
267b3b8e 2081OP_1CB_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2082{
2083 uint16 a = (OP[0]);
2084 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2085 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2086 tmp = RW (addr);
2087 SET_PSR_F (tmp & (1 << a));
2088 tmp = tmp | (1 << a);
2089 SW (addr, tmp);
267b3b8e 2090 trace_output_32 (sd, addr);
fee8ec00
SR		 2091}
2092
2093/* sbitw. */
2094void
267b3b8e 2095OP_118_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2096{
2097 uint16 a = (OP[0]);
2098 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2099 trace_input ("sbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2100 tmp = RW (addr);
2101 SET_PSR_F (tmp & (1 << a));
2102 tmp = tmp | (1 << a);
2103 SW (addr, tmp);
267b3b8e 2104 trace_output_32 (sd, addr);
fee8ec00
SR		 2105}
2106
2107/* sbitw. */
2108void
267b3b8e 2109OP_76_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2110{
2111 uint16 a = (OP[0]);
2112 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2113 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2114 tmp = RW (addr);
2115 SET_PSR_F (tmp & (1 << a));
2116 tmp = tmp | (1 << a);
2117 SW (addr, tmp);
267b3b8e 2118 trace_output_32 (sd, addr);
fee8ec00
SR		 2119}
2120
2121/* sbitw. */
2122void
267b3b8e 2123OP_71_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2124{
2125 uint16 a = (OP[0]);
2126 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2127 trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2128 tmp = RW (addr);
2129 SET_PSR_F (tmp & (1 << a));
2130 tmp = tmp | (1 << a);
2131 SW (addr, tmp);
267b3b8e 2132 trace_output_32 (sd, addr);
fee8ec00
SR		 2133}
2134
2135/* sbitw. */
2136void
267b3b8e 2137OP_119_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2138{
2139 uint16 a = (OP[0]);
2140 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2141 trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2142 tmp = RW (addr);
2143 SET_PSR_F (tmp & (1 << a));
2144 tmp = tmp | (1 << a);
2145 SW (addr, tmp);
267b3b8e 2146 trace_output_32 (sd, addr);
fee8ec00
SR		 2147}
2148
2149/* sbitw. */
2150void
267b3b8e 2151OP_11A_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2152{
2153 uint16 a = (OP[0]);
2154 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2155 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2156 tmp = RW (addr);
2157 SET_PSR_F (tmp & (1 << a));
2158 tmp = tmp | (1 << a);
2159 SW (addr, tmp);
267b3b8e 2160 trace_output_32 (sd, addr);
fee8ec00
SR		 2161}
2162
2163
2164/* tbitb. */
2165void
267b3b8e 2166OP_F7_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2167{
2168 uint8 a = OP[0] & 0xff;
2169 uint32 addr = OP[1], tmp;
2170 trace_input ("tbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2171 tmp = RB (addr);
2172 SET_PSR_F (tmp & (1 << a));
267b3b8e 2173 trace_output_32 (sd, tmp);
fee8ec00
SR		 2174}
2175
2176/* tbitb. */
2177void
267b3b8e 2178OP_10F_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2179{
2180 uint8 a = OP[0] & 0xff;
2181 uint32 addr = OP[1], tmp;
2182 trace_input ("tbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2183 tmp = RB (addr);
2184 SET_PSR_F (tmp & (1 << a));
267b3b8e 2185 trace_output_32 (sd, tmp);
fee8ec00
SR		 2186}
2187
2188/* tbitb. */
2189void
267b3b8e 2190OP_78_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2191{
2192 uint8 a = (OP[0]) & 0xff;
2193 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2194 trace_input ("tbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
2195 tmp = RB (addr);
2196 SET_PSR_F (tmp & (1 << a));
267b3b8e 2197 trace_output_32 (sd, addr);
fee8ec00
SR		 2198}
2199
2200/* tbitb. */
2201void
267b3b8e 2202OP_1EA_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2203{
2204 uint8 a = (OP[0]) & 0xff;
2205 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2206 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2207 tmp = RB (addr);
2208 SET_PSR_F (tmp & (1 << a));
267b3b8e 2209 trace_output_32 (sd, addr);
fee8ec00
SR		 2210}
2211
2212/* tbitb. */
2213void
267b3b8e 2214OP_10C_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2215{
2216 uint8 a = (OP[0]) & 0xff;
2217 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2218 trace_input ("tbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2219 tmp = RB (addr);
2220 SET_PSR_F (tmp & (1 << a));
267b3b8e 2221 trace_output_32 (sd, addr);
fee8ec00
SR		 2222}
2223
2224/* tbitb. */
2225void
267b3b8e 2226OP_F4_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2227{
2228 uint8 a = (OP[0]) & 0xff;
2229 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2230 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2231 tmp = RB (addr);
2232 SET_PSR_F (tmp & (1 << a));
267b3b8e 2233 trace_output_32 (sd, addr);
fee8ec00
SR		 2234}
2235
2236/* tbitb. */
2237void
267b3b8e 2238OP_F6_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2239{
2240 uint8 a = (OP[0]) & 0xff;
2241 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2242 trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2243 tmp = RB (addr);
2244 SET_PSR_F (tmp & (1 << a));
267b3b8e 2245 trace_output_32 (sd, addr);
fee8ec00
SR		 2246}
2247
2248/* tbitb. */
2249void
267b3b8e 2250OP_10D_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2251{
2252 uint8 a = (OP[0]) & 0xff;
2253 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2254 trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2255 tmp = RB (addr);
2256 SET_PSR_F (tmp & (1 << a));
267b3b8e 2257 trace_output_32 (sd, addr);
fee8ec00
SR		 2258}
2259
2260/* tbitb. */
2261void
267b3b8e 2262OP_10E_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2263{
2264 uint8 a = (OP[0]) & 0xff;
2265 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2266 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2267 tmp = RB (addr);
2268 SET_PSR_F (tmp & (1 << a));
267b3b8e 2269 trace_output_32 (sd, addr);
fee8ec00
SR		 2270}
2271
2272
2273/* tbitw. */
2274void
267b3b8e 2275OP_7F_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2276{
2277 uint16 a = OP[0];
2278 uint32 addr = OP[1], tmp;
2279 trace_input ("tbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2280 tmp = RW (addr);
2281 SET_PSR_F (tmp & (1 << a));
267b3b8e 2282 trace_output_32 (sd, tmp);
fee8ec00
SR		 2283}
2284
2285/* tbitw. */
2286void
267b3b8e 2287OP_11F_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2288{
2289 uint16 a = OP[0];
2290 uint32 addr = OP[1], tmp;
2291 trace_input ("tbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2292 tmp = RW (addr);
2293 SET_PSR_F (tmp & (1 << a));
267b3b8e 2294 trace_output_32 (sd, tmp);
fee8ec00
SR		 2295}
2296
2297
2298/* tbitw. */
2299void
267b3b8e 2300OP_3E_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2301{
2302 uint32 addr;
2303 uint16 a = (OP[0]), tmp;
2304 trace_input ("tbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
2305
2306 if (OP[1] == 0)
2307 addr = (GPR32 (12)) + OP[2];
2308 else
2309 addr = (GPR32 (13)) + OP[2];
2310
2311 tmp = RW (addr);
2312 SET_PSR_F (tmp & (1 << a));
267b3b8e 2313 trace_output_32 (sd, addr);
fee8ec00
SR		 2314}
2315
2316/* tbitw. */
2317void
267b3b8e 2318OP_1EB_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2319{
2320 uint16 a = (OP[0]);
2321 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2322 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2323 tmp = RW (addr);
2324 SET_PSR_F (tmp & (1 << a));
267b3b8e 2325 trace_output_32 (sd, addr);
fee8ec00
SR		 2326}
2327
2328/* tbitw. */
2329void
267b3b8e 2330OP_11C_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2331{
2332 uint16 a = (OP[0]);
2333 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2334 trace_input ("tbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2335 tmp = RW (addr);
2336 SET_PSR_F (tmp & (1 << a));
267b3b8e 2337 trace_output_32 (sd, addr);
fee8ec00
SR		 2338}
2339
2340/* tbitw. */
2341void
267b3b8e 2342OP_7E_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2343{
2344 uint16 a = (OP[0]);
2345 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2346 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2347 tmp = RW (addr);
2348 SET_PSR_F (tmp & (1 << a));
267b3b8e 2349 trace_output_32 (sd, addr);
fee8ec00
SR		 2350}
2351
2352/* tbitw. */
2353void
267b3b8e 2354OP_79_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2355{
2356 uint16 a = (OP[0]);
2357 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2358 trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2359 tmp = RW (addr);
2360 SET_PSR_F (tmp & (1 << a));
267b3b8e 2361 trace_output_32 (sd, addr);
fee8ec00
SR		 2362}
2363
2364/* tbitw. */
2365void
267b3b8e 2366OP_11D_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2367{
2368 uint16 a = (OP[0]);
2369 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2370 trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2371 tmp = RW (addr);
2372 SET_PSR_F (tmp & (1 << a));
267b3b8e 2373 trace_output_32 (sd, addr);
fee8ec00
SR		 2374}
2375
2376
2377/* tbitw. */
2378void
267b3b8e 2379OP_11E_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2380{
2381 uint16 a = (OP[0]);
2382 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2383 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2384 tmp = RW (addr);
2385 SET_PSR_F (tmp & (1 << a));
267b3b8e 2386 trace_output_32 (sd, addr);
fee8ec00
SR		 2387}
2388
2389
2390/* tbit. */
2391void
267b3b8e 2392OP_6_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2393{
2394 uint16 a = OP[0];
537e4bb9 2395 uint16 b = (GPR (OP[1]));
fee8ec00 2396 trace_input ("tbit", OP_CONSTANT4, OP_REG, OP_VOID);
537e4bb9 2397 SET_PSR_F (b & (1 << a));
267b3b8e 2398 trace_output_16 (sd, b);
fee8ec00
SR		 2399}
2400
2401/* tbit. */
2402void
267b3b8e 2403OP_7_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2404{
2405 uint16 a = GPR (OP[0]);
537e4bb9 2406 uint16 b = (GPR (OP[1]));
fee8ec00 2407 trace_input ("tbit", OP_REG, OP_REG, OP_VOID);
537e4bb9 2408 SET_PSR_F (b & (1 << a));
267b3b8e 2409 trace_output_16 (sd, b);
fee8ec00
SR		 2410}
2411
2412
2413/* cmpb. */
2414void
267b3b8e 2415OP_50_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2416{
2417 uint8 a = (OP[0]) & 0xFF;
2418 uint8 b = (GPR (OP[1])) & 0xFF;
2419 trace_input ("cmpb", OP_CONSTANT4, OP_REG, OP_VOID);
2420 SET_PSR_Z (a == b);
2421 SET_PSR_N ((int8)a > (int8)b);
2422 SET_PSR_L (a > b);
267b3b8e 2423 trace_output_flag (sd);
fee8ec00
SR		 2424}
2425
2426/* cmpb. */
2427void
267b3b8e 2428OP_50B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2429{
2430 uint8 a = (OP[0]) & 0xFF;
2431 uint8 b = (GPR (OP[1])) & 0xFF;
2432 trace_input ("cmpb", OP_CONSTANT16, OP_REG, OP_VOID);
2433 SET_PSR_Z (a == b);
2434 SET_PSR_N ((int8)a > (int8)b);
2435 SET_PSR_L (a > b);
267b3b8e 2436 trace_output_flag (sd);
fee8ec00
SR		 2437}
2438
2439/* cmpb. */
2440void
267b3b8e 2441OP_51_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2442{
2443 uint8 a = (GPR (OP[0])) & 0xFF;
2444 uint8 b = (GPR (OP[1])) & 0xFF;
2445 trace_input ("cmpb", OP_REG, OP_REG, OP_VOID);
2446 SET_PSR_Z (a == b);
2447 SET_PSR_N ((int8)a > (int8)b);
2448 SET_PSR_L (a > b);
267b3b8e 2449 trace_output_flag (sd);
fee8ec00
SR		 2450}
2451
2452/* cmpw. */
2453void
267b3b8e 2454OP_52_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2455{
2456 uint16 a = (OP[0]);
2457 uint16 b = GPR (OP[1]);
2458 trace_input ("cmpw", OP_CONSTANT4, OP_REG, OP_VOID);
2459 SET_PSR_Z (a == b);
2460 SET_PSR_N ((int16)a > (int16)b);
2461 SET_PSR_L (a > b);
267b3b8e 2462 trace_output_flag (sd);
fee8ec00
SR		 2463}
2464
2465/* cmpw. */
2466void
267b3b8e 2467OP_52B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2468{
2469 uint16 a = (OP[0]);
2470 uint16 b = GPR (OP[1]);
2471 trace_input ("cmpw", OP_CONSTANT16, OP_REG, OP_VOID);
2472 SET_PSR_Z (a == b);
2473 SET_PSR_N ((int16)a > (int16)b);
2474 SET_PSR_L (a > b);
267b3b8e 2475 trace_output_flag (sd);
fee8ec00
SR		 2476}
2477
2478/* cmpw. */
2479void
267b3b8e 2480OP_53_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2481{
2482 uint16 a = GPR (OP[0]) ;
2483 uint16 b = GPR (OP[1]) ;
2484 trace_input ("cmpw", OP_REG, OP_REG, OP_VOID);
2485 SET_PSR_Z (a == b);
2486 SET_PSR_N ((int16)a > (int16)b);
2487 SET_PSR_L (a > b);
267b3b8e 2488 trace_output_flag (sd);
fee8ec00
SR		 2489}
2490
2491/* cmpd. */
2492void
267b3b8e 2493OP_56_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2494{
2495 uint32 a = (OP[0]);
2496 uint32 b = GPR32 (OP[1]);
2497 trace_input ("cmpd", OP_CONSTANT4, OP_REGP, OP_VOID);
2498 SET_PSR_Z (a == b);
2499 SET_PSR_N ((int32)a > (int32)b);
2500 SET_PSR_L (a > b);
267b3b8e 2501 trace_output_flag (sd);
fee8ec00
SR		 2502}
2503
2504/* cmpd. */
2505void
267b3b8e 2506OP_56B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2507{
2508 uint32 a = (SEXT16(OP[0]));
2509 uint32 b = GPR32 (OP[1]);
2510 trace_input ("cmpd", OP_CONSTANT16, OP_REGP, OP_VOID);
2511 SET_PSR_Z (a == b);
2512 SET_PSR_N ((int32)a > (int32)b);
2513 SET_PSR_L (a > b);
267b3b8e 2514 trace_output_flag (sd);
fee8ec00
SR		 2515}
2516
2517/* cmpd. */
2518void
267b3b8e 2519OP_57_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2520{
2521 uint32 a = GPR32 (OP[0]) ;
2522 uint32 b = GPR32 (OP[1]) ;
2523 trace_input ("cmpd", OP_REGP, OP_REGP, OP_VOID);
2524 SET_PSR_Z (a == b);
2525 SET_PSR_N ((int32)a > (int32)b);
2526 SET_PSR_L (a > b);
267b3b8e 2527 trace_output_flag (sd);
fee8ec00
SR		 2528}
2529
2530/* cmpd. */
2531void
267b3b8e 2532OP_9_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2533{
2534 uint32 a = (OP[0]);
2535 uint32 b = GPR32 (OP[1]);
2536 trace_input ("cmpd", OP_CONSTANT32, OP_REGP, OP_VOID);
2537 SET_PSR_Z (a == b);
2538 SET_PSR_N ((int32)a > (int32)b);
2539 SET_PSR_L (a > b);
267b3b8e 2540 trace_output_flag (sd);
fee8ec00
SR		 2541}
2542
2543
2544/* movb. */
2545void
267b3b8e 2546OP_58_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2547{
2548 uint8 tmp = OP[0] & 0xFF;
fee8ec00 2549 uint16 a = (GPR (OP[1])) & 0xFF00;
5aedb83b 2550 trace_input ("movb", OP_CONSTANT4, OP_REG, OP_VOID);
fee8ec00 2551 SET_GPR (OP[1], (a | tmp));
267b3b8e 2552 trace_output_16 (sd, tmp);
fee8ec00
SR		 2553}
2554
2555/* movb. */
2556void
267b3b8e 2557OP_58B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2558{
2559 uint8 tmp = OP[0] & 0xFF;
fee8ec00 2560 uint16 a = (GPR (OP[1])) & 0xFF00;
5aedb83b 2561 trace_input ("movb", OP_CONSTANT16, OP_REG, OP_VOID);
fee8ec00 2562 SET_GPR (OP[1], (a | tmp));
267b3b8e 2563 trace_output_16 (sd, tmp);
fee8ec00
SR		 2564}
2565
2566/* movb. */
2567void
267b3b8e 2568OP_59_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2569{
2570 uint8 tmp = (GPR (OP[0])) & 0xFF;
fee8ec00 2571 uint16 a = (GPR (OP[1])) & 0xFF00;
5aedb83b 2572 trace_input ("movb", OP_REG, OP_REG, OP_VOID);
fee8ec00 2573 SET_GPR (OP[1], (a | tmp));
267b3b8e 2574 trace_output_16 (sd, tmp);
fee8ec00
SR		 2575}
2576
2577/* movw. */
2578void
267b3b8e 2579OP_5A_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2580{
2581 uint16 tmp = OP[0];
2582 trace_input ("movw", OP_CONSTANT4_1, OP_REG, OP_VOID);
2583 SET_GPR (OP[1], (tmp & 0xffff));
267b3b8e 2584 trace_output_16 (sd, tmp);
fee8ec00
SR		 2585}
2586
2587/* movw. */
2588void
267b3b8e 2589OP_5AB_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2590{
2591 int16 tmp = OP[0];
2592 trace_input ("movw", OP_CONSTANT16, OP_REG, OP_VOID);
2593 SET_GPR (OP[1], (tmp & 0xffff));
267b3b8e 2594 trace_output_16 (sd, tmp);
fee8ec00
SR		 2595}
2596
2597/* movw. */
2598void
267b3b8e 2599OP_5B_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2600{
2601 uint16 tmp = GPR (OP[0]);
fee8ec00 2602 uint32 a = GPR32 (OP[1]);
5aedb83b 2603 trace_input ("movw", OP_REG, OP_REGP, OP_VOID);
fee8ec00
SR		 2604 a = (a & 0xffff0000) | tmp;
2605 SET_GPR32 (OP[1], a);
267b3b8e 2606 trace_output_16 (sd, tmp);
fee8ec00
SR		 2607}
2608
2609/* movxb. */
2610void
267b3b8e 2611OP_5C_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2612{
2613 uint8 tmp = (GPR (OP[0])) & 0xFF;
2614 trace_input ("movxb", OP_REG, OP_REG, OP_VOID);
2615 SET_GPR (OP[1], ((SEXT8(tmp)) & 0xffff));
267b3b8e 2616 trace_output_16 (sd, tmp);
fee8ec00
SR		 2617}
2618
2619/* movzb. */
2620void
267b3b8e 2621OP_5D_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2622{
2623 uint8 tmp = (GPR (OP[0])) & 0xFF;
2624 trace_input ("movzb", OP_REG, OP_REG, OP_VOID);
2625 SET_GPR (OP[1], tmp);
267b3b8e 2626 trace_output_16 (sd, tmp);
fee8ec00
SR		 2627}
2628
2629/* movxw. */
2630void
267b3b8e 2631OP_5E_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2632{
2633 uint16 tmp = GPR (OP[0]);
2634 trace_input ("movxw", OP_REG, OP_REGP, OP_VOID);
2635 SET_GPR32 (OP[1], SEXT16(tmp));
267b3b8e 2636 trace_output_16 (sd, tmp);
fee8ec00
SR		 2637}
2638
2639/* movzw. */
2640void
267b3b8e 2641OP_5F_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2642{
2643 uint16 tmp = GPR (OP[0]);
2644 trace_input ("movzw", OP_REG, OP_REGP, OP_VOID);
2645 SET_GPR32 (OP[1], (tmp & 0x0000FFFF));
267b3b8e 2646 trace_output_16 (sd, tmp);
fee8ec00
SR		 2647}
2648
2649/* movd. */
2650void
267b3b8e 2651OP_54_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2652{
2653 int32 tmp = OP[0];
2654 trace_input ("movd", OP_CONSTANT4, OP_REGP, OP_VOID);
2655 SET_GPR32 (OP[1], tmp);
267b3b8e 2656 trace_output_32 (sd, tmp);
fee8ec00
SR		 2657}
2658
2659/* movd. */
2660void
267b3b8e 2661OP_54B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2662{
2663 int32 tmp = SEXT16(OP[0]);
2664 trace_input ("movd", OP_CONSTANT16, OP_REGP, OP_VOID);
2665 SET_GPR32 (OP[1], tmp);
267b3b8e 2666 trace_output_32 (sd, tmp);
fee8ec00
SR		 2667}
2668
2669/* movd. */
2670void
267b3b8e 2671OP_55_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2672{
2673 uint32 tmp = GPR32 (OP[0]);
2674 trace_input ("movd", OP_REGP, OP_REGP, OP_VOID);
2675 SET_GPR32 (OP[1], tmp);
267b3b8e 2676 trace_output_32 (sd, tmp);
fee8ec00
SR		 2677}
2678
2679/* movd. */
2680void
267b3b8e 2681OP_5_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2682{
2683 uint32 tmp = OP[0];
2684 trace_input ("movd", OP_CONSTANT20, OP_REGP, OP_VOID);
2685 SET_GPR32 (OP[1], tmp);
267b3b8e 2686 trace_output_32 (sd, tmp);
fee8ec00
SR		 2687}
2688
2689/* movd. */
2690void
267b3b8e 2691OP_7_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2692{
2693 int32 tmp = OP[0];
2694 trace_input ("movd", OP_CONSTANT32, OP_REGP, OP_VOID);
2695 SET_GPR32 (OP[1], tmp);
267b3b8e 2696 trace_output_32 (sd, tmp);
fee8ec00
SR		 2697}
2698
2699/* loadm. */
2700void
267b3b8e 2701OP_14_D (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2702{
2703 uint32 addr = GPR (0);
2704 uint16 count = OP[0], reg = 2, tmp;
2705 trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID);
2706 if ((addr & 1))
2707 {
267b3b8e 2708 trace_output_void (sd);
0ef7f981 2709 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 2710 }
2711
2712 while (count)
2713 {
2714 tmp = RW (addr);
2715 SET_GPR (reg, tmp);
2716 addr +=2;
2717 --count;
2718 reg++;
2719 if (reg == 6) reg = 8;
2720 };
2721
2722 SET_GPR (0, addr);
267b3b8e 2723 trace_output_void (sd);
fee8ec00
SR		 2724}
2725
2726
2727/* loadmp. */
2728void
267b3b8e 2729OP_15_D (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2730{
2731 uint32 addr = GPR32 (0);
2732 uint16 count = OP[0], reg = 2, tmp;
2733 trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID);
2734 if ((addr & 1))
2735 {
267b3b8e 2736 trace_output_void (sd);
0ef7f981 2737 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 2738 }
2739
2740 while (count)
2741 {
2742 tmp = RW (addr);
2743 SET_GPR (reg, tmp);
2744 addr +=2;
2745 --count;
2746 reg++;
2747 if (reg == 6) reg = 8;
2748 };
2749
2750 SET_GPR32 (0, addr);
267b3b8e 2751 trace_output_void (sd);
fee8ec00
SR		 2752}
2753
2754
2755/* loadb. */
2756void
267b3b8e 2757OP_88_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2758{
2759 /* loadb ABS20, REG
2760 * ADDR = zext24(abs20) | remap (ie 0xF00000)
2761 * REG = [ADDR]
2762 * NOTE: remap is
2763 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
2764 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
2765 * by the core to 16M-64k to 16M. */
2766
2767 uint16 tmp, a = (GPR (OP[1])) & 0xFF00;
2768 uint32 addr = OP[0];
2769 trace_input ("loadb", OP_ABS20, OP_REG, OP_VOID);
2770 if (addr > 0xEFFFF) addr |= 0xF00000;
2771 tmp = (RB (addr));
2772 SET_GPR (OP[1], (a | tmp));
267b3b8e 2773 trace_output_16 (sd, tmp);
fee8ec00
SR		 2774}
2775
2776/* loadb. */
2777void
267b3b8e 2778OP_127_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2779{
2780 /* loadb ABS24, REG
2781 * ADDR = abs24
2782 * REGR = [ADDR]. */
2783
2784 uint16 tmp, a = (GPR (OP[1])) & 0xFF00;
2785 uint32 addr = OP[0];
2786 trace_input ("loadb", OP_ABS24, OP_REG, OP_VOID);
2787 tmp = (RB (addr));
2788 SET_GPR (OP[1], (a | tmp));
267b3b8e 2789 trace_output_16 (sd, tmp);
fee8ec00
SR		 2790}
2791
2792/* loadb. */
2793void
267b3b8e 2794OP_45_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2795{
2796 /* loadb [Rindex]ABS20 REG
2797 * ADDR = Rindex + zext24(disp20)
2798 * REGR = [ADDR]. */
2799
2800 uint32 addr;
2801 uint16 tmp, a = (GPR (OP[2])) & 0xFF00;
2802 trace_input ("loadb", OP_R_INDEX8_ABS20, OP_REG, OP_VOID);
2803
2804 if (OP[0] == 0)
2805 addr = (GPR32 (12)) + OP[1];
2806 else
2807 addr = (GPR32 (13)) + OP[1];
2808
2809 tmp = (RB (addr));
2810 SET_GPR (OP[2], (a | tmp));
267b3b8e 2811 trace_output_16 (sd, tmp);
fee8ec00
SR		 2812}
2813
2814
2815/* loadb. */
2816void
267b3b8e 2817OP_B_4 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2818{
2819 /* loadb DIPS4(REGP) REG
2820 * ADDR = RPBASE + zext24(DISP4)
2821 * REG = [ADDR]. */
2822 uint16 tmp, a = (GPR (OP[2])) & 0xFF00;
2823 uint32 addr = (GPR32 (OP[1])) + OP[0];
2824 trace_input ("loadb", OP_RP_BASE_DISP4, OP_REG, OP_VOID);
2825 tmp = (RB (addr));
2826 SET_GPR (OP[2], (a | tmp));
267b3b8e 2827 trace_output_16 (sd, tmp);
fee8ec00
SR		 2828}
2829
2830/* loadb. */
2831void
267b3b8e 2832OP_BE_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2833{
2834 /* loadb [Rindex]disp0(RPbasex) REG
2835 * ADDR = Rpbasex + Rindex
2836 * REGR = [ADDR] */
2837
2838 uint32 addr;
2839 uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
2840 trace_input ("loadb", OP_RP_INDEX_DISP0, OP_REG, OP_VOID);
2841
2842 addr = (GPR32 (OP[2])) + OP[1];
2843
2844 if (OP[0] == 0)
2845 addr = (GPR32 (12)) + addr;
2846 else
2847 addr = (GPR32 (13)) + addr;
2848
2849 tmp = (RB (addr));
2850 SET_GPR (OP[3], (a | tmp));
267b3b8e 2851 trace_output_16 (sd, tmp);
fee8ec00
SR		 2852}
2853
2854/* loadb. */
2855void
267b3b8e 2856OP_219_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2857{
2858 /* loadb [Rindex]disp14(RPbasex) REG
2859 * ADDR = Rpbasex + Rindex + zext24(disp14)
2860 * REGR = [ADDR] */
2861
2862 uint32 addr;
2863 uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
2864
2865 addr = (GPR32 (OP[2])) + OP[1];
2866
2867 if (OP[0] == 0)
2868 addr = (GPR32 (12)) + addr;
2869 else
2870 addr = (GPR32 (13)) + addr;
2871
2872 trace_input ("loadb", OP_RP_INDEX_DISP14, OP_REG, OP_VOID);
2873 tmp = (RB (addr));
2874 SET_GPR (OP[3], (a | tmp));
267b3b8e 2875 trace_output_16 (sd, tmp);
fee8ec00
SR		 2876}
2877
2878
2879/* loadb. */
2880void
267b3b8e 2881OP_184_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2882{
2883 /* loadb DISPE20(REG) REG
2884 * zext24(Rbase) + zext24(dispe20)
2885 * REG = [ADDR] */
2886
2887 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2888 uint32 addr = OP[0] + (GPR (OP[1]));
2889 trace_input ("loadb", OP_R_BASE_DISPE20, OP_REG, OP_VOID);
2890 tmp = (RB (addr));
2891 SET_GPR (OP[2], (a | tmp));
267b3b8e 2892 trace_output_16 (sd, tmp);
fee8ec00
SR		 2893}
2894
2895/* loadb. */
2896void
267b3b8e 2897OP_124_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2898{
2899 /* loadb DISP20(REG) REG
2900 * ADDR = zext24(Rbase) + zext24(disp20)
2901 * REG = [ADDR] */
2902
2903 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2904 uint32 addr = OP[0] + (GPR (OP[1]));
2905 trace_input ("loadb", OP_R_BASE_DISP20, OP_REG, OP_VOID);
2906 tmp = (RB (addr));
2907 SET_GPR (OP[2], (a | tmp));
267b3b8e 2908 trace_output_16 (sd, tmp);
fee8ec00
SR		 2909}
2910
2911/* loadb. */
2912void
267b3b8e 2913OP_BF_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2914{
2915 /* loadb disp16(REGP) REG
2916 * ADDR = RPbase + zext24(disp16)
2917 * REGR = [ADDR] */
2918
2919 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2920 uint32 addr = (GPR32 (OP[1])) + OP[0];
2921 trace_input ("loadb", OP_RP_BASE_DISP16, OP_REG, OP_VOID);
2922 tmp = (RB (addr));
2923 SET_GPR (OP[2], (a | tmp));
267b3b8e 2924 trace_output_16 (sd, tmp);
fee8ec00
SR		 2925}
2926
2927/* loadb. */
2928void
267b3b8e 2929OP_125_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2930{
2931 /* loadb disp20(REGP) REG
2932 * ADDR = RPbase + zext24(disp20)
2933 * REGR = [ADDR] */
2934 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2935 uint32 addr = (GPR32 (OP[1])) + OP[0];
2936 trace_input ("loadb", OP_RP_BASE_DISP20, OP_REG, OP_VOID);
2937 tmp = (RB (addr));
2938 SET_GPR (OP[2], (a | tmp));
267b3b8e 2939 trace_output_16 (sd, tmp);
fee8ec00
SR		 2940}
2941
2942
2943/* loadb. */
2944void
267b3b8e 2945OP_185_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2946{
2947 /* loadb -disp20(REGP) REG
2948 * ADDR = RPbase + zext24(-disp20)
2949 * REGR = [ADDR] */
2950 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2951 uint32 addr = (GPR32 (OP[1])) + OP[1];
2952 trace_input ("loadb", OP_RP_BASE_DISPE20, OP_REG, OP_VOID);
2953 tmp = (RB (addr));
2954 SET_GPR (OP[2], (a | tmp));
267b3b8e 2955 trace_output_16 (sd, tmp);
fee8ec00
SR		 2956}
2957
2958/* loadb. */
2959void
267b3b8e 2960OP_126_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2961{
2962 /* loadb [Rindex]disp20(RPbasexb) REG
2963 * ADDR = RPbasex + Rindex + zext24(disp20)
2964 * REGR = [ADDR] */
2965
2966 uint32 addr;
2967 uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
2968 trace_input ("loadb", OP_RP_INDEX_DISP20, OP_REG, OP_VOID);
2969
2970 addr = (GPR32 (OP[2])) + OP[1];
2971
2972 if (OP[0] == 0)
2973 addr = (GPR32 (12)) + addr;
2974 else
2975 addr = (GPR32 (13)) + addr;
2976
2977 tmp = (RB (addr));
2978 SET_GPR (OP[3], (a | tmp));
267b3b8e 2979 trace_output_16 (sd, tmp);
fee8ec00
SR		 2980}
2981
2982
2983/* loadw. */
2984void
267b3b8e 2985OP_89_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 2986{
2987 /* loadw ABS20, REG
2988 * ADDR = zext24(abs20) | remap
2989 * REGR = [ADDR]
2990 * NOTE: remap is
2991 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
2992 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
2993 * by the core to 16M-64k to 16M. */
2994
2995 uint16 tmp;
2996 uint32 addr = OP[0];
2997 trace_input ("loadw", OP_ABS20, OP_REG, OP_VOID);
2998 if (addr > 0xEFFFF) addr |= 0xF00000;
2999 tmp = (RW (addr));
3000 SET_GPR (OP[1], tmp);
267b3b8e 3001 trace_output_16 (sd, tmp);
fee8ec00
SR		 3002}
3003
3004
3005/* loadw. */
3006void
267b3b8e 3007OP_12F_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3008{
3009 /* loadw ABS24, REG
3010 * ADDR = abs24
3011 * REGR = [ADDR] */
3012 uint16 tmp;
3013 uint32 addr = OP[0];
3014 trace_input ("loadw", OP_ABS24, OP_REG, OP_VOID);
3015 tmp = (RW (addr));
3016 SET_GPR (OP[1], tmp);
267b3b8e 3017 trace_output_16 (sd, tmp);
fee8ec00
SR		 3018}
3019
3020/* loadw. */
3021void
267b3b8e 3022OP_47_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3023{
3024 /* loadw [Rindex]ABS20 REG
3025 * ADDR = Rindex + zext24(disp20)
3026 * REGR = [ADDR] */
3027
3028 uint32 addr;
3029 uint16 tmp;
3030 trace_input ("loadw", OP_R_INDEX8_ABS20, OP_REG, OP_VOID);
3031
3032 if (OP[0] == 0)
3033 addr = (GPR32 (12)) + OP[1];
3034 else
3035 addr = (GPR32 (13)) + OP[1];
3036
3037 tmp = (RW (addr));
3038 SET_GPR (OP[2], tmp);
267b3b8e 3039 trace_output_16 (sd, tmp);
fee8ec00
SR		 3040}
3041
3042
3043/* loadw. */
3044void
267b3b8e 3045OP_9_4 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3046{
3047 /* loadw DIPS4(REGP) REGP
3048 * ADDR = RPBASE + zext24(DISP4)
3049 * REGP = [ADDR]. */
3050 uint16 tmp;
3051 uint32 addr, a;
3052 trace_input ("loadw", OP_RP_BASE_DISP4, OP_REG, OP_VOID);
3053 addr = (GPR32 (OP[1])) + OP[0];
3054 tmp = (RW (addr));
3055 if (OP[2] > 11)
3056 {
3057 a = (GPR32 (OP[2])) & 0xffff0000;
3058 SET_GPR32 (OP[2], (a | tmp));
3059 }
3060 else
3061 SET_GPR (OP[2], tmp);
3062
267b3b8e 3063 trace_output_16 (sd, tmp);
fee8ec00
SR		 3064}
3065
3066
3067/* loadw. */
3068void
267b3b8e 3069OP_9E_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3070{
3071 /* loadw [Rindex]disp0(RPbasex) REG
3072 * ADDR = Rpbasex + Rindex
3073 * REGR = [ADDR] */
3074
3075 uint32 addr;
3076 uint16 tmp;
3077 trace_input ("loadw", OP_RP_INDEX_DISP0, OP_REG, OP_VOID);
3078
3079 addr = (GPR32 (OP[2])) + OP[1];
3080
3081 if (OP[0] == 0)
3082 addr = (GPR32 (12)) + addr;
3083 else
3084 addr = (GPR32 (13)) + addr;
3085
3086 tmp = RW (addr);
3087 SET_GPR (OP[3], tmp);
267b3b8e 3088 trace_output_16 (sd, tmp);
fee8ec00
SR		 3089}
3090
3091
3092/* loadw. */
3093void
267b3b8e 3094OP_21B_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3095{
3096 /* loadw [Rindex]disp14(RPbasex) REG
3097 * ADDR = Rpbasex + Rindex + zext24(disp14)
3098 * REGR = [ADDR] */
3099
3100 uint32 addr;
3101 uint16 tmp;
3102 trace_input ("loadw", OP_RP_INDEX_DISP14, OP_REG, OP_VOID);
3103 addr = (GPR32 (OP[2])) + OP[1];
3104
3105 if (OP[0] == 0)
3106 addr = (GPR32 (12)) + addr;
3107 else
3108 addr = (GPR32 (13)) + addr;
3109
3110 tmp = (RW (addr));
3111 SET_GPR (OP[3], tmp);
267b3b8e 3112 trace_output_16 (sd, tmp);
fee8ec00
SR		 3113}
3114
3115/* loadw. */
3116void
267b3b8e 3117OP_18C_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3118{
3119 /* loadw dispe20(REG) REGP
3120 * REGP = [DISPE20+[REG]] */
3121
3122 uint16 tmp;
3123 uint32 addr, a;
3124 trace_input ("loadw", OP_R_BASE_DISPE20, OP_REGP, OP_VOID);
3125 addr = OP[0] + (GPR (OP[1]));
3126 tmp = (RW (addr));
3127 if (OP[2] > 11)
3128 {
3129 a = (GPR32 (OP[2])) & 0xffff0000;
3130 SET_GPR32 (OP[2], (a | tmp));
3131 }
3132 else
3133 SET_GPR (OP[2], tmp);
3134
267b3b8e 3135 trace_output_16 (sd, tmp);
fee8ec00
SR		 3136}
3137
3138
3139/* loadw. */
3140void
267b3b8e 3141OP_12C_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3142{
3143 /* loadw DISP20(REG) REGP
3144 * ADDR = zext24(Rbase) + zext24(disp20)
3145 * REGP = [ADDR] */
3146
3147 uint16 tmp;
3148 uint32 addr, a;
3149 trace_input ("loadw", OP_R_BASE_DISP20, OP_REGP, OP_VOID);
3150 addr = OP[0] + (GPR (OP[1]));
3151 tmp = (RW (addr));
3152 if (OP[2] > 11)
3153 {
3154 a = (GPR32 (OP[2])) & 0xffff0000;
3155 SET_GPR32 (OP[2], (a | tmp));
3156 }
3157 else
3158 SET_GPR (OP[2], tmp);
3159
267b3b8e 3160 trace_output_16 (sd, tmp);
fee8ec00
SR		 3161}
3162
3163/* loadw. */
3164void
267b3b8e 3165OP_9F_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3166{
3167 /* loadw disp16(REGP) REGP
3168 * ADDR = RPbase + zext24(disp16)
3169 * REGP = [ADDR] */
3170 uint16 tmp;
3171 uint32 addr, a;
3172 trace_input ("loadw", OP_RP_BASE_DISP16, OP_REGP, OP_VOID);
3173 addr = (GPR32 (OP[1])) + OP[0];
3174 tmp = (RW (addr));
3175 if (OP[2] > 11)
3176 {
3177 a = (GPR32 (OP[2])) & 0xffff0000;
3178 SET_GPR32 (OP[2], (a | tmp));
3179 }
3180 else
3181 SET_GPR (OP[2], tmp);
3182
267b3b8e 3183 trace_output_16 (sd, tmp);
fee8ec00
SR		 3184}
3185
3186/* loadw. */
3187void
267b3b8e 3188OP_12D_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3189{
3190 /* loadw disp20(REGP) REGP
3191 * ADDR = RPbase + zext24(disp20)
3192 * REGP = [ADDR] */
3193 uint16 tmp;
3194 uint32 addr, a;
3195 trace_input ("loadw", OP_RP_BASE_DISP20, OP_REG, OP_VOID);
3196 addr = (GPR32 (OP[1])) + OP[0];
3197 tmp = (RW (addr));
3198 if (OP[2] > 11)
3199 {
3200 a = (GPR32 (OP[2])) & 0xffff0000;
3201 SET_GPR32 (OP[2], (a | tmp));
3202 }
3203 else
3204 SET_GPR (OP[2], tmp);
3205
267b3b8e 3206 trace_output_16 (sd, tmp);
fee8ec00
SR		 3207}
3208
3209/* loadw. */
3210void
267b3b8e 3211OP_18D_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3212{
3213 /* loadw -disp20(REGP) REG
3214 * ADDR = RPbase + zext24(-disp20)
3215 * REGR = [ADDR] */
3216
3217 uint16 tmp;
3218 uint32 addr, a;
3219 trace_input ("loadw", OP_RP_BASE_DISPE20, OP_REG, OP_VOID);
3220 addr = (GPR32 (OP[1])) + OP[0];
3221 tmp = (RB (addr));
3222 if (OP[2] > 11)
3223 {
3224 a = (GPR32 (OP[2])) & 0xffff0000;
3225 SET_GPR32 (OP[2], (a | tmp));
3226 }
3227 else
3228 SET_GPR (OP[2], tmp);
3229
267b3b8e 3230 trace_output_16 (sd, tmp);
fee8ec00
SR		 3231}
3232
3233
3234/* loadw. */
3235void
267b3b8e 3236OP_12E_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3237{
3238 /* loadw [Rindex]disp20(RPbasexb) REG
3239 * ADDR = RPbasex + Rindex + zext24(disp20)
3240 * REGR = [ADDR] */
3241
3242 uint32 addr;
3243 uint16 tmp;
3244 trace_input ("loadw", OP_RP_INDEX_DISP20, OP_REG, OP_VOID);
3245
3246 if (OP[0] == 0)
3247 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3248 else
3249 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3250
3251 tmp = (RW (addr));
3252 SET_GPR (OP[3], tmp);
267b3b8e 3253 trace_output_16 (sd, tmp);
fee8ec00
SR		 3254}
3255
3256
3257/* loadd. */
3258void
267b3b8e 3259OP_87_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3260{
3261 /* loadd ABS20, REGP
3262 * ADDR = zext24(abs20) | remap
3263 * REGP = [ADDR]
3264 * NOTE: remap is
3265 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3266 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3267 * by the core to 16M-64k to 16M. */
3268
3269 uint32 addr, tmp;
3270 addr = OP[0];
3271 trace_input ("loadd", OP_ABS20, OP_REGP, OP_VOID);
3272 if (addr > 0xEFFFF) addr |= 0xF00000;
3273 tmp = RLW (addr);
3274 tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff);
3275 SET_GPR32 (OP[1], tmp);
267b3b8e 3276 trace_output_32 (sd, tmp);
fee8ec00
SR		 3277}
3278
3279/* loadd. */
3280void
267b3b8e 3281OP_12B_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3282{
3283 /* loadd ABS24, REGP
3284 * ADDR = abs24
3285 * REGP = [ADDR] */
3286
3287 uint32 addr = OP[0];
3288 uint32 tmp;
3289 trace_input ("loadd", OP_ABS24, OP_REGP, OP_VOID);
3290 tmp = RLW (addr);
3291 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3292 SET_GPR32 (OP[1],tmp);
267b3b8e 3293 trace_output_32 (sd, tmp);
fee8ec00
SR		 3294}
3295
3296
3297/* loadd. */
3298void
267b3b8e 3299OP_46_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3300{
3301 /* loadd [Rindex]ABS20 REGP
3302 * ADDR = Rindex + zext24(disp20)
3303 * REGP = [ADDR] */
3304
3305 uint32 addr, tmp;
3306 trace_input ("loadd", OP_R_INDEX8_ABS20, OP_REGP, OP_VOID);
3307
3308 if (OP[0] == 0)
3309 addr = (GPR32 (12)) + OP[1];
3310 else
3311 addr = (GPR32 (13)) + OP[1];
3312
3313 tmp = RLW (addr);
3314 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3315 SET_GPR32 (OP[2], tmp);
267b3b8e 3316 trace_output_32 (sd, tmp);
fee8ec00
SR		 3317}
3318
3319
3320/* loadd. */
3321void
267b3b8e 3322OP_A_4 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3323{
3324 /* loadd dips4(regp) REGP
3325 * ADDR = Rpbase + zext24(disp4)
3326 * REGP = [ADDR] */
3327
3328 uint32 tmp, addr = (GPR32 (OP[1])) + OP[0];
3329 trace_input ("loadd", OP_RP_BASE_DISP4, OP_REGP, OP_VOID);
3330 tmp = RLW (addr);
3331 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3332 SET_GPR32 (OP[2], tmp);
267b3b8e 3333 trace_output_32 (sd, tmp);
fee8ec00
SR		 3334}
3335
3336
3337/* loadd. */
3338void
267b3b8e 3339OP_AE_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3340{
3341 /* loadd [Rindex]disp0(RPbasex) REGP
3342 * ADDR = Rpbasex + Rindex
3343 * REGP = [ADDR] */
3344
3345 uint32 addr, tmp;
3346 trace_input ("loadd", OP_RP_INDEX_DISP0, OP_REGP, OP_VOID);
3347
3348 if (OP[0] == 0)
3349 addr = (GPR32 (12)) + (GPR32 (OP[2])) + OP[1];
3350 else
3351 addr = (GPR32 (13)) + (GPR32 (OP[2])) + OP[1];
3352
3353 tmp = RLW (addr);
3354 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3355 SET_GPR32 (OP[3], tmp);
267b3b8e 3356 trace_output_32 (sd, tmp);
fee8ec00
SR		 3357}
3358
3359
3360/* loadd. */
3361void
267b3b8e 3362OP_21A_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3363{
3364 /* loadd [Rindex]disp14(RPbasex) REGP
3365 * ADDR = Rpbasex + Rindex + zext24(disp14)
3366 * REGR = [ADDR] */
3367
3368 uint32 addr, tmp;
3369 trace_input ("loadd", OP_RP_INDEX_DISP14, OP_REGP, OP_VOID);
3370
3371 if (OP[0] == 0)
3372 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3373 else
3374 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3375
3376 tmp = RLW (addr);
3377 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3378 SET_GPR (OP[3],tmp);
267b3b8e 3379 trace_output_32 (sd, tmp);
fee8ec00
SR		 3380}
3381
3382
3383/* loadd. */
3384void
267b3b8e 3385OP_188_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3386{
3387 /* loadd dispe20(REG) REG
3388 * zext24(Rbase) + zext24(dispe20)
3389 * REG = [ADDR] */
3390
3391 uint32 tmp, addr = OP[0] + (GPR (OP[1]));
3392 trace_input ("loadd", OP_R_BASE_DISPE20, OP_REGP, OP_VOID);
3393 tmp = RLW (addr);
3394 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3395 SET_GPR32 (OP[2], tmp);
267b3b8e 3396 trace_output_32 (sd, tmp);
fee8ec00
SR		 3397}
3398
3399
3400/* loadd. */
3401void
267b3b8e 3402OP_128_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3403{
3404 /* loadd DISP20(REG) REG
3405 * ADDR = zext24(Rbase) + zext24(disp20)
3406 * REG = [ADDR] */
3407
3408 uint32 tmp, addr = OP[0] + (GPR (OP[1]));
3409 trace_input ("loadd", OP_R_BASE_DISP20, OP_REGP, OP_VOID);
3410 tmp = RLW (addr);
3411 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3412 SET_GPR32 (OP[2], tmp);
267b3b8e 3413 trace_output_32 (sd, tmp);
fee8ec00
SR		 3414}
3415
3416/* loadd. */
3417void
267b3b8e 3418OP_AF_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3419{
3420 /* loadd disp16(REGP) REGP
3421 * ADDR = RPbase + zext24(disp16)
3422 * REGR = [ADDR] */
3423 uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
3424 trace_input ("loadd", OP_RP_BASE_DISP16, OP_REGP, OP_VOID);
3425 tmp = RLW (addr);
3426 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3427 SET_GPR32 (OP[2], tmp);
267b3b8e 3428 trace_output_32 (sd, tmp);
fee8ec00
SR		 3429}
3430
3431
3432/* loadd. */
3433void
267b3b8e 3434OP_129_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3435{
3436 /* loadd disp20(REGP) REGP
3437 * ADDR = RPbase + zext24(disp20)
3438 * REGP = [ADDR] */
3439 uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
3440 trace_input ("loadd", OP_RP_BASE_DISP20, OP_REGP, OP_VOID);
3441 tmp = RLW (addr);
3442 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3443 SET_GPR32 (OP[2], tmp);
267b3b8e 3444 trace_output_32 (sd, tmp);
fee8ec00
SR		 3445}
3446
3447/* loadd. */
3448void
267b3b8e 3449OP_189_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3450{
3451 /* loadd -disp20(REGP) REGP
3452 * ADDR = RPbase + zext24(-disp20)
3453 * REGP = [ADDR] */
3454
3455 uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
3456 trace_input ("loadd", OP_RP_BASE_DISPE20, OP_REGP, OP_VOID);
3457 tmp = RLW (addr);
3458 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3459 SET_GPR32 (OP[2], tmp);
267b3b8e 3460 trace_output_32 (sd, tmp);
fee8ec00
SR		 3461}
3462
3463/* loadd. */
3464void
267b3b8e 3465OP_12A_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3466{
3467 /* loadd [Rindex]disp20(RPbasexb) REGP
3468 * ADDR = RPbasex + Rindex + zext24(disp20)
3469 * REGP = [ADDR] */
3470
3471 uint32 addr, tmp;
3472 trace_input ("loadd", OP_RP_INDEX_DISP20, OP_REGP, OP_VOID);
3473
3474 if (OP[0] == 0)
3475 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3476 else
3477 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3478
3479 tmp = RLW (addr);
3480 tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff);
3481 SET_GPR32 (OP[3], tmp);
267b3b8e 3482 trace_output_32 (sd, tmp);
fee8ec00
SR		 3483}
3484
3485
3486/* storb. */
3487void
267b3b8e 3488OP_C8_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3489{
3490 /* storb REG, ABS20
3491 * ADDR = zext24(abs20) | remap
3492 * [ADDR] = REGR
3493 * NOTE: remap is
3494 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3495 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3496 * by the core to 16M-64k to 16M. */
3497
3498 uint8 a = ((GPR (OP[0])) & 0xff);
3499 uint32 addr = OP[1];
3500 trace_input ("storb", OP_REG, OP_ABS20_OUTPUT, OP_VOID);
3501 SB (addr, a);
267b3b8e 3502 trace_output_32 (sd, addr);
fee8ec00
SR		 3503}
3504
3505/* storb. */
3506void
267b3b8e 3507OP_137_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3508{
3509 /* storb REG, ABS24
3510 * ADDR = abs24
3511 * [ADDR] = REGR. */
3512
3513 uint8 a = ((GPR (OP[0])) & 0xff);
3514 uint32 addr = OP[1];
3515 trace_input ("storb", OP_REG, OP_ABS24_OUTPUT, OP_VOID);
3516 SB (addr, a);
267b3b8e 3517 trace_output_32 (sd, addr);
fee8ec00
SR		 3518}
3519
3520/* storb. */
3521void
267b3b8e 3522OP_65_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3523{
3524 /* storb REG, [Rindex]ABS20
3525 * ADDR = Rindex + zext24(disp20)
3526 * [ADDR] = REGR */
3527
3528 uint32 addr;
3529 uint8 a = ((GPR (OP[0])) & 0xff);
3530 trace_input ("storb", OP_REG, OP_R_INDEX8_ABS20, OP_VOID);
3531
3532 if (OP[1] == 0)
3533 addr = (GPR32 (12)) + OP[2];
3534 else
3535 addr = (GPR32 (13)) + OP[2];
3536
3537 SB (addr, a);
267b3b8e 3538 trace_output_32 (sd, addr);
fee8ec00
SR		 3539}
3540
3541/* storb. */
3542void
267b3b8e 3543OP_F_4 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3544{
3545 /* storb REG, DIPS4(REGP)
3546 * ADDR = RPBASE + zext24(DISP4)
3547 * [ADDR] = REG. */
3548
3549 uint16 a = ((GPR (OP[0])) & 0xff);
5aedb83b 3550 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 3551 trace_input ("storb", OP_REG, OP_RP_BASE_DISPE4, OP_VOID);
fee8ec00 3552 SB (addr, a);
267b3b8e 3553 trace_output_32 (sd, addr);
fee8ec00
SR		 3554}
3555
3556/* storb. */
3557void
267b3b8e 3558OP_FE_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3559{
3560 /* storb [Rindex]disp0(RPbasex) REG
3561 * ADDR = Rpbasex + Rindex
3562 * [ADDR] = REGR */
3563
3564 uint32 addr;
3565 uint8 a = ((GPR (OP[0])) & 0xff);
3566 trace_input ("storb", OP_REG, OP_RP_INDEX_DISP0, OP_VOID);
3567
3568 if (OP[1] == 0)
3569 addr = (GPR32 (12)) + (GPR32 (OP[3])) + OP[2];
3570 else
3571 addr = (GPR32 (13)) + (GPR32 (OP[3])) + OP[2];
3572
3573 SB (addr, a);
267b3b8e 3574 trace_output_32 (sd, addr);
fee8ec00
SR		 3575}
3576
3577/* storb. */
3578void
267b3b8e 3579OP_319_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3580{
3581 /* storb REG, [Rindex]disp14(RPbasex)
3582 * ADDR = Rpbasex + Rindex + zext24(disp14)
3583 * [ADDR] = REGR */
3584
3585 uint8 a = ((GPR (OP[0])) & 0xff);
fee8ec00 3586 uint32 addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3587 trace_input ("storb", OP_REG, OP_RP_INDEX_DISP14, OP_VOID);
fee8ec00 3588 SB (addr, a);
267b3b8e 3589 trace_output_32 (sd, addr);
fee8ec00
SR		 3590}
3591
3592/* storb. */
3593void
267b3b8e 3594OP_194_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3595{
3596 /* storb REG, DISPE20(REG)
3597 * zext24(Rbase) + zext24(dispe20)
3598 * [ADDR] = REG */
3599
3600 uint8 a = ((GPR (OP[0])) & 0xff);
fee8ec00 3601 uint32 addr = OP[1] + (GPR (OP[2]));
5aedb83b 3602 trace_input ("storb", OP_REG, OP_R_BASE_DISPE20, OP_VOID);
fee8ec00 3603 SB (addr, a);
267b3b8e 3604 trace_output_32 (sd, addr);
fee8ec00
SR		 3605}
3606
3607/* storb. */
3608void
267b3b8e 3609OP_134_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3610{
3611 /* storb REG, DISP20(REG)
3612 * ADDR = zext24(Rbase) + zext24(disp20)
3613 * [ADDR] = REG */
3614
3615 uint8 a = (GPR (OP[0]) & 0xff);
5aedb83b 3616 uint32 addr = OP[1] + (GPR (OP[2]));
fee8ec00 3617 trace_input ("storb", OP_REG, OP_R_BASE_DISPS20, OP_VOID);
fee8ec00 3618 SB (addr, a);
267b3b8e 3619 trace_output_32 (sd, addr);
fee8ec00
SR		 3620}
3621
3622/* storb. */
3623void
267b3b8e 3624OP_FF_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3625{
3626 /* storb REG, disp16(REGP)
3627 * ADDR = RPbase + zext24(disp16)
3628 * [ADDR] = REGP */
3629
3630 uint8 a = ((GPR (OP[0])) & 0xff);
fee8ec00 3631 uint32 addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3632 trace_input ("storb", OP_REG, OP_RP_BASE_DISP16, OP_VOID);
fee8ec00 3633 SB (addr, a);
267b3b8e 3634 trace_output_32 (sd, addr);
fee8ec00
SR		 3635}
3636
3637/* storb. */
3638void
267b3b8e 3639OP_135_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3640{
3641 /* storb REG, disp20(REGP)
3642 * ADDR = RPbase + zext24(disp20)
3643 * [ADDR] = REGP */
3644
3645 uint8 a = ((GPR (OP[0])) & 0xff);
fee8ec00 3646 uint32 addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3647 trace_input ("storb", OP_REG, OP_RP_BASE_DISPS20, OP_VOID);
fee8ec00 3648 SB (addr, a);
267b3b8e 3649 trace_output_32 (sd, addr);
fee8ec00
SR		 3650}
3651
3652/* storb. */
3653void
267b3b8e 3654OP_195_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3655{
3656 /* storb REG, -disp20(REGP)
3657 * ADDR = RPbase + zext24(-disp20)
3658 * [ADDR] = REGP */
3659
3660 uint8 a = (GPR (OP[0]) & 0xff);
fee8ec00 3661 uint32 addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3662 trace_input ("storb", OP_REG, OP_RP_BASE_DISPE20, OP_VOID);
fee8ec00 3663 SB (addr, a);
267b3b8e 3664 trace_output_32 (sd, addr);
fee8ec00
SR		 3665}
3666
3667/* storb. */
3668void
267b3b8e 3669OP_136_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3670{
3671 /* storb REG, [Rindex]disp20(RPbase)
3672 * ADDR = RPbasex + Rindex + zext24(disp20)
3673 * [ADDR] = REGP */
3674
3675 uint8 a = (GPR (OP[0])) & 0xff;
fee8ec00 3676 uint32 addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3677 trace_input ("storb", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID);
fee8ec00 3678 SB (addr, a);
267b3b8e 3679 trace_output_32 (sd, addr);
fee8ec00
SR		 3680}
3681
3682/* STR_IMM instructions. */
3683/* storb . */
3684void
267b3b8e 3685OP_81_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3686{
3687 uint8 a = (OP[0]) & 0xff;
fee8ec00 3688 uint32 addr = OP[1];
5aedb83b 3689 trace_input ("storb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
fee8ec00 3690 SB (addr, a);
267b3b8e 3691 trace_output_32 (sd, addr);
fee8ec00
SR		 3692}
3693
3694/* storb. */
3695void
267b3b8e 3696OP_123_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3697{
3698 uint8 a = (OP[0]) & 0xff;
fee8ec00 3699 uint32 addr = OP[1];
5aedb83b 3700 trace_input ("storb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
fee8ec00 3701 SB (addr, a);
267b3b8e 3702 trace_output_32 (sd, addr);
fee8ec00
SR		 3703}
3704
3705/* storb. */
3706void
267b3b8e 3707OP_42_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3708{
3709 uint32 addr;
3710 uint8 a = (OP[0]) & 0xff;
3711 trace_input ("storb", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
3712
3713 if (OP[1] == 0)
3714 addr = (GPR32 (12)) + OP[2];
3715 else
3716 addr = (GPR32 (13)) + OP[2];
3717
3718 SB (addr, a);
267b3b8e 3719 trace_output_32 (sd, addr);
fee8ec00
SR		 3720}
3721
3722/* storb. */
3723void
267b3b8e 3724OP_218_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3725{
3726 uint8 a = (OP[0]) & 0xff;
fee8ec00 3727 uint32 addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3728 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID);
fee8ec00 3729 SB (addr, a);
267b3b8e 3730 trace_output_32 (sd, addr);
fee8ec00
SR		 3731}
3732
3733/* storb. */
3734void
267b3b8e 3735OP_82_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3736{
3737 uint8 a = (OP[0]) & 0xff;
fee8ec00 3738 uint32 addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3739 trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
fee8ec00 3740 SB (addr, a);
267b3b8e 3741 trace_output_32 (sd, addr);
fee8ec00
SR		 3742}
3743
3744/* storb. */
3745void
267b3b8e 3746OP_120_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3747{
3748 uint8 a = (OP[0]) & 0xff;
fee8ec00 3749 uint32 addr = (GPR (OP[2])) + OP[1];
5aedb83b 3750 trace_input ("storb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
fee8ec00 3751 SB (addr, a);
267b3b8e 3752 trace_output_32 (sd, addr);
fee8ec00
SR		 3753}
3754
3755/* storb. */
3756void
267b3b8e 3757OP_83_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3758{
3759 uint8 a = (OP[0]) & 0xff;
fee8ec00 3760 uint32 addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3761 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
fee8ec00 3762 SB (addr, a);
267b3b8e 3763 trace_output_32 (sd, addr);
fee8ec00
SR		 3764}
3765
3766/* storb. */
3767void
267b3b8e 3768OP_121_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3769{
3770 uint8 a = (OP[0]) & 0xff;
fee8ec00 3771 uint32 addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3772 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
fee8ec00 3773 SB (addr, a);
267b3b8e 3774 trace_output_32 (sd, addr);
fee8ec00
SR		 3775}
3776
3777/* storb. */
3778void
267b3b8e 3779OP_122_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3780{
3781 uint8 a = (OP[0]) & 0xff;
fee8ec00 3782 uint32 addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3783 trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
fee8ec00 3784 SB (addr, a);
267b3b8e 3785 trace_output_32 (sd, addr);
fee8ec00
SR		 3786}
3787/* endif for STR_IMM. */
3788
3789/* storw . */
3790void
267b3b8e 3791OP_C9_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3792{
3793 uint16 a = GPR (OP[0]);
fee8ec00 3794 uint32 addr = OP[1];
5aedb83b 3795 trace_input ("storw", OP_REG, OP_ABS20_OUTPUT, OP_VOID);
fee8ec00 3796 SW (addr, a);
267b3b8e 3797 trace_output_32 (sd, addr);
fee8ec00
SR		 3798}
3799
3800/* storw. */
3801void
267b3b8e 3802OP_13F_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3803{
3804 uint16 a = GPR (OP[0]);
fee8ec00 3805 uint32 addr = OP[1];
5aedb83b 3806 trace_input ("storw", OP_REG, OP_ABS24_OUTPUT, OP_VOID);
fee8ec00 3807 SW (addr, a);
267b3b8e 3808 trace_output_32 (sd, addr);
fee8ec00
SR		 3809}
3810
3811/* storw. */
3812void
267b3b8e 3813OP_67_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3814{
3815 uint32 addr;
3816 uint16 a = GPR (OP[0]);
3817 trace_input ("storw", OP_REG, OP_R_INDEX8_ABS20, OP_VOID);
3818
3819 if (OP[1] == 0)
3820 addr = (GPR32 (12)) + OP[2];
3821 else
3822 addr = (GPR32 (13)) + OP[2];
3823
3824 SW (addr, a);
267b3b8e 3825 trace_output_32 (sd, addr);
fee8ec00
SR		 3826}
3827
3828
3829/* storw. */
3830void
267b3b8e 3831OP_D_4 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3832{
3833 uint16 a = (GPR (OP[0]));
5aedb83b 3834 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 3835 trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID);
fee8ec00 3836 SW (addr, a);
267b3b8e 3837 trace_output_32 (sd, addr);
fee8ec00
SR		 3838}
3839
3840/* storw. */
3841void
267b3b8e 3842OP_DE_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3843{
3844 uint16 a = GPR (OP[0]);
fee8ec00 3845 uint32 addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3846 trace_input ("storw", OP_REG, OP_RP_INDEX_DISP0, OP_VOID);
fee8ec00 3847 SW (addr, a);
267b3b8e 3848 trace_output_32 (sd, addr);
fee8ec00
SR		 3849}
3850
3851/* storw. */
3852void
267b3b8e 3853OP_31B_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3854{
3855 uint16 a = GPR (OP[0]);
fee8ec00 3856 uint32 addr = (GPR32 (OP[2])) + OP[1];
5aedb83b 3857 trace_input ("storw", OP_REG, OP_RP_INDEX_DISP14, OP_VOID);
fee8ec00 3858 SW (addr, a);
267b3b8e 3859 trace_output_32 (sd, addr);
fee8ec00
SR		 3860}
3861
3862/* storw. */
3863void
267b3b8e 3864OP_19C_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3865{
3866 uint16 a = (GPR (OP[0]));
5aedb83b 3867 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 3868 trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID);
fee8ec00 3869 SW (addr, a);
267b3b8e 3870 trace_output_32 (sd, addr);
fee8ec00
SR		 3871}
3872
3873/* storw. */
3874void
267b3b8e 3875OP_13C_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3876{
3877 uint16 a = (GPR (OP[0]));
5aedb83b 3878 uint32 addr = (GPR (OP[2])) + OP[1];
fee8ec00 3879 trace_input ("storw", OP_REG, OP_R_BASE_DISPS20, OP_VOID);
fee8ec00 3880 SW (addr, a);
267b3b8e 3881 trace_output_32 (sd, addr);
fee8ec00
SR		 3882}
3883
3884/* storw. */
3885void
267b3b8e 3886OP_DF_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3887{
3888 uint16 a = (GPR (OP[0]));
5aedb83b 3889 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 3890 trace_input ("storw", OP_REG, OP_RP_BASE_DISP16, OP_VOID);
fee8ec00 3891 SW (addr, a);
267b3b8e 3892 trace_output_32 (sd, addr);
fee8ec00
SR		 3893}
3894
3895/* storw. */
3896void
267b3b8e 3897OP_13D_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3898{
3899 uint16 a = (GPR (OP[0]));
5aedb83b 3900 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 3901 trace_input ("storw", OP_REG, OP_RP_BASE_DISPS20, OP_VOID);
fee8ec00 3902 SW (addr, a);
267b3b8e 3903 trace_output_32 (sd, addr);
fee8ec00
SR		 3904}
3905
3906/* storw. */
3907void
267b3b8e 3908OP_19D_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3909{
3910 uint16 a = (GPR (OP[0]));
5aedb83b 3911 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 3912 trace_input ("storw", OP_REG, OP_RP_BASE_DISPE20, OP_VOID);
fee8ec00 3913 SW (addr, a);
267b3b8e 3914 trace_output_32 (sd, addr);
fee8ec00
SR		 3915}
3916
3917/* storw. */
3918void
267b3b8e 3919OP_13E_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3920{
3921 uint16 a = (GPR (OP[0]));
5aedb83b 3922 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 3923 trace_input ("storw", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID);
fee8ec00 3924 SW (addr, a);
267b3b8e 3925 trace_output_32 (sd, addr);
fee8ec00
SR		 3926}
3927
3928/* STORE-w IMM instruction *****/
3929/* storw . */
3930void
267b3b8e 3931OP_C1_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3932{
3933 uint16 a = OP[0];
5aedb83b 3934 uint32 addr = OP[1];
fee8ec00 3935 trace_input ("storw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
fee8ec00 3936 SW (addr, a);
267b3b8e 3937 trace_output_32 (sd, addr);
fee8ec00
SR		 3938}
3939
3940/* storw. */
3941void
267b3b8e 3942OP_133_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3943{
3944 uint16 a = OP[0];
5aedb83b 3945 uint32 addr = OP[1];
fee8ec00 3946 trace_input ("storw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
fee8ec00 3947 SW (addr, a);
267b3b8e 3948 trace_output_32 (sd, addr);
fee8ec00
SR		 3949}
3950
3951/* storw. */
3952void
267b3b8e 3953OP_62_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3954{
3955 uint32 addr;
3956 uint16 a = OP[0];
3957 trace_input ("storw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
3958
3959 if (OP[1] == 0)
3960 addr = (GPR32 (12)) + OP[2];
3961 else
3962 addr = (GPR32 (13)) + OP[2];
3963
3964 SW (addr, a);
267b3b8e 3965 trace_output_32 (sd, addr);
fee8ec00
SR		 3966}
3967
3968/* storw. */
3969void
267b3b8e 3970OP_318_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3971{
3972 uint16 a = OP[0];
5aedb83b 3973 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 3974 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID);
fee8ec00 3975 SW (addr, a);
267b3b8e 3976 trace_output_32 (sd, addr);
fee8ec00
SR		 3977}
3978
3979/* storw. */
3980void
267b3b8e 3981OP_C2_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3982{
3983 uint16 a = OP[0];
5aedb83b 3984 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 3985 trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
fee8ec00 3986 SW (addr, a);
267b3b8e 3987 trace_output_32 (sd, addr);
fee8ec00
SR		 3988}
3989
3990/* storw. */
3991void
267b3b8e 3992OP_130_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 3993{
3994 uint16 a = OP[0];
5aedb83b 3995 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 3996 trace_input ("storw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
fee8ec00 3997 SW (addr, a);
267b3b8e 3998 trace_output_32 (sd, addr);
fee8ec00
SR		 3999}
4000
4001/* storw. */
4002void
267b3b8e 4003OP_C3_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4004{
4005 uint16 a = OP[0];
5aedb83b 4006 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4007 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
fee8ec00 4008 SW (addr, a);
267b3b8e 4009 trace_output_32 (sd, addr);
fee8ec00
SR		 4010}
4011
4012
4013/* storw. */
4014void
267b3b8e 4015OP_131_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4016{
4017 uint16 a = OP[0];
5aedb83b 4018 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4019 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
fee8ec00 4020 SW (addr, a);
267b3b8e 4021 trace_output_32 (sd, addr);
fee8ec00
SR		 4022}
4023
4024/* storw. */
4025void
267b3b8e 4026OP_132_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4027{
4028 uint16 a = OP[0];
5aedb83b 4029 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4030 trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
fee8ec00 4031 SW (addr, a);
267b3b8e 4032 trace_output_32 (sd, addr);
fee8ec00
SR		 4033}
4034
4035
4036/* stord. */
4037void
267b3b8e 4038OP_C7_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4039{
4040 uint32 a = GPR32 (OP[0]);
5aedb83b 4041 uint32 addr = OP[1];
fee8ec00 4042 trace_input ("stord", OP_REGP, OP_ABS20_OUTPUT, OP_VOID);
fee8ec00 4043 SLW (addr, a);
267b3b8e 4044 trace_output_32 (sd, addr);
fee8ec00
SR		 4045}
4046
4047/* stord. */
4048void
267b3b8e 4049OP_13B_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4050{
4051 uint32 a = GPR32 (OP[0]);
5aedb83b 4052 uint32 addr = OP[1];
fee8ec00 4053 trace_input ("stord", OP_REGP, OP_ABS24_OUTPUT, OP_VOID);
fee8ec00 4054 SLW (addr, a);
267b3b8e 4055 trace_output_32 (sd, addr);
fee8ec00
SR		 4056}
4057
4058/* stord. */
4059void
267b3b8e 4060OP_66_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4061{
4062 uint32 addr, a = GPR32 (OP[0]);
4063 trace_input ("stord", OP_REGP, OP_R_INDEX8_ABS20, OP_VOID);
4064
4065 if (OP[1] == 0)
4066 addr = (GPR32 (12)) + OP[2];
4067 else
4068 addr = (GPR32 (13)) + OP[2];
4069
4070 SLW (addr, a);
267b3b8e 4071 trace_output_32 (sd, addr);
fee8ec00
SR		 4072}
4073
4074/* stord. */
4075void
267b3b8e 4076OP_E_4 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4077{
4078 uint32 a = GPR32 (OP[0]);
5aedb83b 4079 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4080 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID);
fee8ec00 4081 SLW (addr, a);
267b3b8e 4082 trace_output_32 (sd, addr);
fee8ec00
SR		 4083}
4084
4085/* stord. */
4086void
267b3b8e 4087OP_EE_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4088{
4089 uint32 a = GPR32 (OP[0]);
5aedb83b 4090 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4091 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP0, OP_VOID);
fee8ec00 4092 SLW (addr, a);
267b3b8e 4093 trace_output_32 (sd, addr);
fee8ec00
SR		 4094}
4095
4096/* stord. */
4097void
267b3b8e 4098OP_31A_A (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4099{
4100 uint32 a = GPR32 (OP[0]);
5aedb83b 4101 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4102 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP14, OP_VOID);
fee8ec00 4103 SLW (addr, a);
267b3b8e 4104 trace_output_32 (sd, addr);
fee8ec00
SR		 4105}
4106
4107/* stord. */
4108void
267b3b8e 4109OP_198_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4110{
4111 uint32 a = GPR32 (OP[0]);
5aedb83b 4112 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4113 trace_input ("stord", OP_REGP, OP_R_BASE_DISPE20, OP_VOID);
fee8ec00 4114 SLW (addr, a);
267b3b8e 4115 trace_output_32 (sd, addr);
fee8ec00
SR		 4116}
4117
4118/* stord. */
4119void
267b3b8e 4120OP_138_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4121{
4122 uint32 a = GPR32 (OP[0]);
5aedb83b 4123 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4124 trace_input ("stord", OP_REGP, OP_R_BASE_DISPS20, OP_VOID);
fee8ec00 4125 SLW (addr, a);
267b3b8e 4126 trace_output_32 (sd, addr);
fee8ec00
SR		 4127}
4128
4129/* stord. */
4130void
267b3b8e 4131OP_EF_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4132{
4133 uint32 a = GPR32 (OP[0]);
5aedb83b 4134 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4135 trace_input ("stord", OP_REGP, OP_RP_BASE_DISP16, OP_VOID);
fee8ec00 4136 SLW (addr, a);
267b3b8e 4137 trace_output_32 (sd, addr);
fee8ec00
SR		 4138}
4139
4140/* stord. */
4141void
267b3b8e 4142OP_139_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4143{
4144 uint32 a = GPR32 (OP[0]);
5aedb83b 4145 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4146 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPS20, OP_VOID);
fee8ec00 4147 SLW (addr, a);
267b3b8e 4148 trace_output_32 (sd, addr);
fee8ec00
SR		 4149}
4150
4151/* stord. */
4152void
267b3b8e 4153OP_199_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4154{
4155 uint32 a = GPR32 (OP[0]);
5aedb83b 4156 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4157 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID);
fee8ec00 4158 SLW (addr, a);
267b3b8e 4159 trace_output_32 (sd, addr);
fee8ec00
SR		 4160}
4161
4162/* stord. */
4163void
267b3b8e 4164OP_13A_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4165{
4166 uint32 a = GPR32 (OP[0]);
5aedb83b 4167 uint32 addr = (GPR32 (OP[2])) + OP[1];
fee8ec00 4168 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISPS20, OP_VOID);
fee8ec00 4169 SLW (addr, a);
267b3b8e 4170 trace_output_32 (sd, addr);
fee8ec00
SR		 4171}
4172
4173/* macqu. */
4174void
267b3b8e 4175OP_14D_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4176{
4177 int32 tmp;
4178 int16 src1, src2;
4179 trace_input ("macuw", OP_REG, OP_REG, OP_REGP);
4180 src1 = GPR (OP[0]);
4181 src2 = GPR (OP[1]);
4182 tmp = src1 * src2;
4183 /*REVISIT FOR SATURATION and Q FORMAT. */
4184 SET_GPR32 (OP[2], tmp);
267b3b8e 4185 trace_output_32 (sd, tmp);
fee8ec00
SR		 4186}
4187
4188/* macuw. */
4189void
267b3b8e 4190OP_14E_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4191{
4192 uint32 tmp;
4193 uint16 src1, src2;
4194 trace_input ("macuw", OP_REG, OP_REG, OP_REGP);
4195 src1 = GPR (OP[0]);
4196 src2 = GPR (OP[1]);
4197 tmp = src1 * src2;
4198 /*REVISIT FOR SATURATION. */
4199 SET_GPR32 (OP[2], tmp);
267b3b8e 4200 trace_output_32 (sd, tmp);
fee8ec00
SR		 4201}
4202
4203/* macsw. */
4204void
267b3b8e 4205OP_14F_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4206{
4207 int32 tmp;
4208 int16 src1, src2;
4209 trace_input ("macsw", OP_REG, OP_REG, OP_REGP);
4210 src1 = GPR (OP[0]);
4211 src2 = GPR (OP[1]);
4212 tmp = src1 * src2;
4213 /*REVISIT FOR SATURATION. */
4214 SET_GPR32 (OP[2], tmp);
267b3b8e 4215 trace_output_32 (sd, tmp);
fee8ec00
SR		 4216}
4217
4218
4219/* mulb. */
4220void
267b3b8e 4221OP_64_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4222{
4223 int16 tmp;
4224 int8 a = (OP[0]) & 0xff;
4225 int8 b = (GPR (OP[1])) & 0xff;
4226 trace_input ("mulb", OP_CONSTANT4_1, OP_REG, OP_VOID);
4227 tmp = (a * b) & 0xff;
4228 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 4229 trace_output_16 (sd, tmp);
fee8ec00
SR		 4230}
4231
4232/* mulb. */
4233void
267b3b8e 4234OP_64B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4235{
4236 int16 tmp;
4237 int8 a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
4238 trace_input ("mulb", OP_CONSTANT4, OP_REG, OP_VOID);
4239 tmp = (a * b) & 0xff;
4240 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 4241 trace_output_16 (sd, tmp);
fee8ec00
SR		 4242}
4243
4244
4245/* mulb. */
4246void
267b3b8e 4247OP_65_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4248{
4249 int16 tmp;
4250 int8 a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
4251 trace_input ("mulb", OP_REG, OP_REG, OP_VOID);
4252 tmp = (a * b) & 0xff;
4253 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 4254 trace_output_16 (sd, tmp);
fee8ec00
SR		 4255}
4256
4257
4258/* mulw. */
4259void
267b3b8e 4260OP_66_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4261{
4262 int32 tmp;
4263 uint16 a = OP[0];
4264 int16 b = (GPR (OP[1]));
4265 trace_input ("mulw", OP_CONSTANT4_1, OP_REG, OP_VOID);
4266 tmp = (a * b) & 0xffff;
4267 SET_GPR (OP[1], tmp);
267b3b8e 4268 trace_output_32 (sd, tmp);
fee8ec00
SR		 4269}
4270
4271/* mulw. */
4272void
267b3b8e 4273OP_66B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4274{
4275 int32 tmp;
4276 int16 a = OP[0], b = (GPR (OP[1]));
4277 trace_input ("mulw", OP_CONSTANT4, OP_REG, OP_VOID);
4278 tmp = (a * b) & 0xffff;
4279 SET_GPR (OP[1], tmp);
267b3b8e 4280 trace_output_32 (sd, tmp);
fee8ec00
SR		 4281}
4282
4283
4284/* mulw. */
4285void
267b3b8e 4286OP_67_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4287{
4288 int32 tmp;
4289 int16 a = (GPR (OP[0])), b = (GPR (OP[1]));
4290 trace_input ("mulw", OP_REG, OP_REG, OP_VOID);
4291 tmp = (a * b) & 0xffff;
4292 SET_GPR (OP[1], tmp);
267b3b8e 4293 trace_output_32 (sd, tmp);
fee8ec00
SR		 4294}
4295
4296
4297/* mulsb. */
4298void
267b3b8e 4299OP_B_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4300{
4301 int16 tmp;
4302 int8 a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
4303 trace_input ("mulsb", OP_REG, OP_REG, OP_VOID);
4304 tmp = a * b;
4305 SET_GPR (OP[1], tmp);
267b3b8e 4306 trace_output_32 (sd, tmp);
fee8ec00
SR		 4307}
4308
4309/* mulsw. */
4310void
267b3b8e 4311OP_62_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4312{
537e4bb9
SR		 4313 int32 tmp;
4314 int16 a = (GPR (OP[0])), b = (GPR (OP[1]));
fee8ec00
SR		 4315 trace_input ("mulsw", OP_REG, OP_REGP, OP_VOID);
4316 tmp = a * b;
4317 SET_GPR32 (OP[1], tmp);
267b3b8e 4318 trace_output_32 (sd, tmp);
fee8ec00
SR		 4319}
4320
4321/* muluw. */
4322void
267b3b8e 4323OP_63_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 4324{
537e4bb9
SR		 4325 uint32 tmp;
4326 uint16 a = (GPR (OP[0])), b = (GPR (OP[1]));
fee8ec00
SR		 4327 trace_input ("muluw", OP_REG, OP_REGP, OP_VOID);
4328 tmp = a * b;
4329 SET_GPR32 (OP[1], tmp);
267b3b8e 4330 trace_output_32 (sd, tmp);
fee8ec00
SR		 4331}
4332
4333
4334/* nop. */
4335void
267b3b8e 4336OP_2C00_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4337{
4338 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
4339
4340#if 0
fee8ec00
SR		 4341 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
4342 switch (State.ins_type)
4343 {
4344 default:
4345 ins_type_counters[ (int)INS_UNKNOWN ]++;
4346 break;
4347
4348 }
0ef7f981 4349 EXCEPTION (SIM_SIGTRAP);
fee8ec00 4350#endif
267b3b8e 4351 trace_output_void (sd);
fee8ec00
SR		 4352}
4353
4354
4355/* orb. */
4356void
267b3b8e 4357OP_24_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4358{
4359 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
4360 trace_input ("orb", OP_CONSTANT4, OP_REG, OP_VOID);
4361 tmp = a | b;
4362 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
267b3b8e 4363 trace_output_16 (sd, tmp);
fee8ec00
SR		 4364}
4365
4366/* orb. */
4367void
267b3b8e 4368OP_24B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4369{
4370 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
4371 trace_input ("orb", OP_CONSTANT16, OP_REG, OP_VOID);
4372 tmp = a | b;
4373 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
267b3b8e 4374 trace_output_16 (sd, tmp);
fee8ec00
SR		 4375}
4376
4377/* orb. */
4378void
267b3b8e 4379OP_25_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4380{
4381 uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
4382 trace_input ("orb", OP_REG, OP_REG, OP_VOID);
4383 tmp = a | b;
4384 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
267b3b8e 4385 trace_output_16 (sd, tmp);
fee8ec00
SR		 4386}
4387
4388/* orw. */
4389void
267b3b8e 4390OP_26_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4391{
4392 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
4393 trace_input ("orw", OP_CONSTANT4, OP_REG, OP_VOID);
4394 tmp = a | b;
4395 SET_GPR (OP[1], tmp);
267b3b8e 4396 trace_output_16 (sd, tmp);
fee8ec00
SR		 4397}
4398
4399
4400/* orw. */
4401void
267b3b8e 4402OP_26B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4403{
4404 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
4405 trace_input ("orw", OP_CONSTANT16, OP_REG, OP_VOID);
4406 tmp = a | b;
4407 SET_GPR (OP[1], tmp);
267b3b8e 4408 trace_output_16 (sd, tmp);
fee8ec00
SR		 4409}
4410
4411/* orw. */
4412void
267b3b8e 4413OP_27_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4414{
4415 uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
4416 trace_input ("orw", OP_REG, OP_REG, OP_VOID);
4417 tmp = a | b;
4418 SET_GPR (OP[1], tmp);
267b3b8e 4419 trace_output_16 (sd, tmp);
fee8ec00
SR		 4420}
4421
4422
4423/* lshb. */
4424void
267b3b8e 4425OP_13_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4426{
4427 uint16 a = OP[0];
4428 uint16 tmp, b = (GPR (OP[1])) & 0xFF;
4429 trace_input ("lshb", OP_CONSTANT4, OP_REG, OP_VOID);
4430 /* A positive count specifies a shift to the left;
4431 * A negative count specifies a shift to the right. */
4432 if (sign_flag)
4433 tmp = b >> a;
4434 else
4435 tmp = b << a;
4436
4437 sign_flag = 0; /* Reset sign_flag. */
4438
4439 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
267b3b8e 4440 trace_output_16 (sd, tmp);
fee8ec00
SR		 4441}
4442
4443/* lshb. */
4444void
267b3b8e 4445OP_44_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4446{
4447 uint16 a = (GPR (OP[0])) & 0xff;
4448 uint16 tmp, b = (GPR (OP[1])) & 0xFF;
4449 trace_input ("lshb", OP_REG, OP_REG, OP_VOID);
4450 if (a & ((long)1 << 3))
4451 {
4452 sign_flag = 1;
4453 a = ~(a) + 1;
4454 }
4455 a = (unsigned int) (a & 0x7);
4456
4457 /* A positive count specifies a shift to the left;
4458 * A negative count specifies a shift to the right. */
4459 if (sign_flag)
4460 tmp = b >> a;
4461 else
4462 tmp = b << a;
4463
4464 sign_flag = 0; /* Reset sign_flag. */
4465 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
267b3b8e 4466 trace_output_16 (sd, tmp);
fee8ec00
SR		 4467}
4468
4469/* lshw. */
4470void
267b3b8e 4471OP_46_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4472{
4473 uint16 tmp, b = GPR (OP[1]);
4474 int16 a = GPR (OP[0]);
4475 trace_input ("lshw", OP_REG, OP_REG, OP_VOID);
4476 if (a & ((long)1 << 4))
4477 {
4478 sign_flag = 1;
4479 a = ~(a) + 1;
4480 }
4481 a = (unsigned int) (a & 0xf);
4482
4483 /* A positive count specifies a shift to the left;
4484 * A negative count specifies a shift to the right. */
4485 if (sign_flag)
4486 tmp = b >> a;
4487 else
4488 tmp = b << a;
4489
4490 sign_flag = 0; /* Reset sign_flag. */
4491 SET_GPR (OP[1], (tmp & 0xffff));
267b3b8e 4492 trace_output_16 (sd, tmp);
fee8ec00
SR		 4493}
4494
4495/* lshw. */
4496void
267b3b8e 4497OP_49_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4498{
4499 uint16 tmp, b = GPR (OP[1]);
4500 uint16 a = OP[0];
4501 trace_input ("lshw", OP_CONSTANT5, OP_REG, OP_VOID);
4502 /* A positive count specifies a shift to the left;
4503 * A negative count specifies a shift to the right. */
4504 if (sign_flag)
4505 tmp = b >> a;
4506 else
4507 tmp = b << a;
4508
4509 sign_flag = 0; /* Reset sign_flag. */
4510 SET_GPR (OP[1], (tmp & 0xffff));
267b3b8e 4511 trace_output_16 (sd, tmp);
fee8ec00
SR		 4512}
4513
4514/* lshd. */
4515void
267b3b8e 4516OP_25_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4517{
4518 uint32 tmp, b = GPR32 (OP[1]);
4519 uint16 a = OP[0];
4520 trace_input ("lshd", OP_CONSTANT6, OP_REGP, OP_VOID);
4521 /* A positive count specifies a shift to the left;
4522 * A negative count specifies a shift to the right. */
4523 if (sign_flag)
4524 tmp = b >> a;
4525 else
4526 tmp = b << a;
4527
4528 sign_flag = 0; /* Reset sign flag. */
4529
4530 SET_GPR32 (OP[1], tmp);
267b3b8e 4531 trace_output_32 (sd, tmp);
fee8ec00
SR		 4532}
4533
4534/* lshd. */
4535void
267b3b8e 4536OP_47_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4537{
4538 uint32 tmp, b = GPR32 (OP[1]);
4539 uint16 a = GPR (OP[0]);
4540 trace_input ("lshd", OP_REG, OP_REGP, OP_VOID);
4541 if (a & ((long)1 << 5))
4542 {
4543 sign_flag = 1;
4544 a = ~(a) + 1;
4545 }
4546 a = (unsigned int) (a & 0x1f);
4547 /* A positive count specifies a shift to the left;
4548 * A negative count specifies a shift to the right. */
4549 if (sign_flag)
4550 tmp = b >> a;
4551 else
4552 tmp = b << a;
4553
4554 sign_flag = 0; /* Reset sign flag. */
4555
4556 SET_GPR32 (OP[1], tmp);
267b3b8e 4557 trace_output_32 (sd, tmp);
fee8ec00
SR		 4558}
4559
4560/* ashub. */
4561void
267b3b8e 4562OP_80_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4563{
4564 uint16 a = OP[0];
4565 int8 tmp, b = (GPR (OP[1])) & 0xFF;
4566 trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID);
4567 /* A positive count specifies a shift to the left;
4568 * A negative count specifies a shift to the right. */
4569 if (sign_flag)
4570 tmp = b >> a;
4571 else
4572 tmp = b << a;
4573
4574 sign_flag = 0; /* Reset sign flag. */
4575
4576 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xff00)));
267b3b8e 4577 trace_output_16 (sd, tmp);
fee8ec00
SR		 4578}
4579
4580/* ashub. */
4581void
267b3b8e 4582OP_81_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4583{
4584 uint16 a = OP[0];
4585 int8 tmp, b = (GPR (OP[1])) & 0xFF;
4586 trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID);
4587 /* A positive count specifies a shift to the left;
4588 * A negative count specifies a shift to the right. */
4589 if (sign_flag)
4590 tmp = b >> a;
4591 else
4592 tmp = b << a;
4593
4594 sign_flag = 0; /* Reset sign flag. */
4595
4596 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
267b3b8e 4597 trace_output_16 (sd, tmp);
fee8ec00
SR		 4598}
4599
4600
4601/* ashub. */
4602void
267b3b8e 4603OP_41_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4604{
4605 int16 a = (GPR (OP[0]));
4606 int8 tmp, b = (GPR (OP[1])) & 0xFF;
4607 trace_input ("ashub", OP_REG, OP_REG, OP_VOID);
4608
4609 if (a & ((long)1 << 3))
4610 {
4611 sign_flag = 1;
4612 a = ~(a) + 1;
4613 }
4614 a = (unsigned int) (a & 0x7);
4615
4616 /* A positive count specifies a shift to the left;
4617 * A negative count specifies a shift to the right. */
4618 if (sign_flag)
4619 tmp = b >> a;
4620 else
4621 tmp = b << a;
4622
4623 sign_flag = 0; /* Reset sign flag. */
4624
4625 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
267b3b8e 4626 trace_output_16 (sd, tmp);
fee8ec00
SR		 4627}
4628
4629
4630/* ashuw. */
4631void
267b3b8e 4632OP_42_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4633{
4634 int16 tmp, b = GPR (OP[1]);
4635 uint16 a = OP[0];
4636 trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID);
4637 /* A positive count specifies a shift to the left;
4638 * A negative count specifies a shift to the right. */
4639 if (sign_flag)
4640 tmp = b >> a;
4641 else
4642 tmp = b << a;
4643
4644 sign_flag = 0; /* Reset sign flag. */
4645
4646 SET_GPR (OP[1], (tmp & 0xffff));
267b3b8e 4647 trace_output_16 (sd, tmp);
fee8ec00
SR		 4648}
4649
4650/* ashuw. */
4651void
267b3b8e 4652OP_43_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4653{
4654 int16 tmp, b = GPR (OP[1]);
4655 uint16 a = OP[0];
4656 trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID);
4657 /* A positive count specifies a shift to the left;
4658 * A negative count specifies a shift to the right. */
4659 if (sign_flag)
4660 tmp = b >> a;
4661 else
4662 tmp = b << a;
4663
4664 sign_flag = 0; /* Reset sign flag. */
4665 SET_GPR (OP[1], (tmp & 0xffff));
267b3b8e 4666 trace_output_16 (sd, tmp);
fee8ec00
SR		 4667}
4668
4669/* ashuw. */
4670void
267b3b8e 4671OP_45_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4672{
4673 int16 tmp;
4674 int16 a = GPR (OP[0]), b = GPR (OP[1]);
4675 trace_input ("ashuw", OP_REG, OP_REG, OP_VOID);
4676
4677 if (a & ((long)1 << 4))
4678 {
4679 sign_flag = 1;
4680 a = ~(a) + 1;
4681 }
4682 a = (unsigned int) (a & 0xf);
4683 /* A positive count specifies a shift to the left;
4684 * A negative count specifies a shift to the right. */
4685
4686 if (sign_flag)
4687 tmp = b >> a;
4688 else
4689 tmp = b << a;
4690
4691 sign_flag = 0; /* Reset sign flag. */
4692 SET_GPR (OP[1], (tmp & 0xffff));
267b3b8e 4693 trace_output_16 (sd, tmp);
fee8ec00
SR		 4694}
4695
4696/* ashud. */
4697void
267b3b8e 4698OP_26_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4699{
4700 int32 tmp,b = GPR32 (OP[1]);
4701 uint32 a = OP[0];
4702 trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID);
4703 /* A positive count specifies a shift to the left;
4704 * A negative count specifies a shift to the right. */
4705 if (sign_flag)
4706 tmp = b >> a;
4707 else
4708 tmp = b << a;
4709
4710 sign_flag = 0; /* Reset sign flag. */
4711 SET_GPR32 (OP[1], tmp);
267b3b8e 4712 trace_output_32 (sd, tmp);
fee8ec00
SR		 4713}
4714
4715/* ashud. */
4716void
267b3b8e 4717OP_27_7 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4718{
4719 int32 tmp;
4720 int32 a = OP[0], b = GPR32 (OP[1]);
4721 trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID);
4722 /* A positive count specifies a shift to the left;
4723 * A negative count specifies a shift to the right. */
4724 if (sign_flag)
4725 tmp = b >> a;
4726 else
4727 tmp = b << a;
4728
4729 sign_flag = 0; /* Reset sign flag. */
4730 SET_GPR32 (OP[1], tmp);
267b3b8e 4731 trace_output_32 (sd, tmp);
fee8ec00
SR		 4732}
4733
4734/* ashud. */
4735void
267b3b8e 4736OP_48_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4737{
4738 int32 tmp;
4739 int32 a = GPR32 (OP[0]), b = GPR32 (OP[1]);
4740 trace_input ("ashud", OP_REGP, OP_REGP, OP_VOID);
4741
4742 if (a & ((long)1 << 5))
4743 {
4744 sign_flag = 1;
4745 a = ~(a) + 1;
4746 }
4747 a = (unsigned int) (a & 0x1f);
4748 /* A positive count specifies a shift to the left;
4749 * A negative count specifies a shift to the right. */
4750 if (sign_flag)
4751 tmp = b >> a;
4752 else
4753 tmp = b << a;
4754
4755 sign_flag = 0; /* Reset sign flag. */
4756 SET_GPR32 (OP[1], tmp);
267b3b8e 4757 trace_output_32 (sd, tmp);
fee8ec00
SR		 4758}
4759
4760
4761/* storm. */
4762void
267b3b8e 4763OP_16_D (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4764{
4765 uint32 addr = GPR (1);
4766 uint16 count = OP[0], reg = 2;
4767 trace_input ("storm", OP_CONSTANT4, OP_VOID, OP_VOID);
4768 if ((addr & 1))
4769 {
267b3b8e 4770 trace_output_void (sd);
0ef7f981 4771 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 4772 }
4773
4774 while (count)
4775 {
4776 SW (addr, (GPR (reg)));
4777 addr +=2;
4778 --count;
4779 reg++;
4780 if (reg == 6) reg = 8;
4781 };
4782
4783 SET_GPR (1, addr);
4784
267b3b8e 4785 trace_output_void (sd);
fee8ec00
SR		 4786}
4787
4788
4789/* stormp. */
4790void
267b3b8e 4791OP_17_D (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4792{
4793 uint32 addr = GPR32 (6);
4794 uint16 count = OP[0], reg = 2;
4795 trace_input ("stormp", OP_CONSTANT4, OP_VOID, OP_VOID);
4796 if ((addr & 1))
4797 {
267b3b8e 4798 trace_output_void (sd);
0ef7f981 4799 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 4800 }
4801
4802 while (count)
4803 {
4804 SW (addr, (GPR (reg)));
4805 addr +=2;
4806 --count;
4807 reg++;
4808 if (reg == 6) reg = 8;
4809 };
4810
4811 SET_GPR32 (6, addr);
267b3b8e 4812 trace_output_void (sd);
fee8ec00
SR		 4813}
4814
4815/* subb. */
4816void
267b3b8e 4817OP_38_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4818{
4819 uint8 a = OP[0];
4820 uint8 b = (GPR (OP[1])) & 0xff;
4821 uint16 tmp = (~a + 1 + b) & 0xff;
4822 trace_input ("subb", OP_CONSTANT4, OP_REG, OP_VOID);
4823 /* see ../common/sim-alu.h for a more extensive discussion on how to
4824 compute the carry/overflow bits. */
4825 SET_PSR_C (tmp > 0xff);
4826 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4827 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 4828 trace_output_16 (sd, tmp);
fee8ec00
SR		 4829}
4830
4831/* subb. */
4832void
267b3b8e 4833OP_38B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4834{
4835 uint8 a = OP[0] & 0xFF;
4836 uint8 b = (GPR (OP[1])) & 0xFF;
4837 uint16 tmp = (~a + 1 + b) & 0xFF;
4838 trace_input ("subb", OP_CONSTANT16, OP_REG, OP_VOID);
4839 /* see ../common/sim-alu.h for a more extensive discussion on how to
4840 compute the carry/overflow bits. */
4841 SET_PSR_C (tmp > 0xff);
4842 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4843 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 4844 trace_output_16 (sd, tmp);
fee8ec00
SR		 4845}
4846
4847/* subb. */
4848void
267b3b8e 4849OP_39_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4850{
4851 uint8 a = (GPR (OP[0])) & 0xFF;
4852 uint8 b = (GPR (OP[1])) & 0xFF;
4853 uint16 tmp = (~a + 1 + b) & 0xff;
4854 trace_input ("subb", OP_REG, OP_REG, OP_VOID);
4855 /* see ../common/sim-alu.h for a more extensive discussion on how to
4856 compute the carry/overflow bits. */
4857 SET_PSR_C (tmp > 0xff);
4858 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4859 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 4860 trace_output_16 (sd, tmp);
fee8ec00
SR		 4861}
4862
4863/* subw. */
4864void
267b3b8e 4865OP_3A_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4866{
4867 uint16 a = OP[0];
4868 uint16 b = GPR (OP[1]);
4869 uint16 tmp = (~a + 1 + b);
4870 trace_input ("subw", OP_CONSTANT4, OP_REG, OP_VOID);
4871 /* see ../common/sim-alu.h for a more extensive discussion on how to
4872 compute the carry/overflow bits. */
4873 SET_PSR_C (tmp > 0xffff);
4874 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4875 SET_GPR (OP[1], tmp);
267b3b8e 4876 trace_output_16 (sd, tmp);
fee8ec00
SR		 4877}
4878
4879/* subw. */
4880void
267b3b8e 4881OP_3AB_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4882{
4883 uint16 a = OP[0];
4884 uint16 b = GPR (OP[1]);
4885 uint32 tmp = (~a + 1 + b);
4886 trace_input ("subw", OP_CONSTANT16, OP_REG, OP_VOID);
4887 /* see ../common/sim-alu.h for a more extensive discussion on how to
4888 compute the carry/overflow bits. */
4889 SET_PSR_C (tmp > 0xffff);
4890 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4891 SET_GPR (OP[1], tmp & 0xffff);
267b3b8e 4892 trace_output_16 (sd, tmp);
fee8ec00
SR		 4893}
4894
4895/* subw. */
4896void
267b3b8e 4897OP_3B_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4898{
4899 uint16 a = GPR (OP[0]);
4900 uint16 b = GPR (OP[1]);
4901 uint32 tmp = (~a + 1 + b);
4902 trace_input ("subw", OP_REG, OP_REG, OP_VOID);
4903 /* see ../common/sim-alu.h for a more extensive discussion on how to
4904 compute the carry/overflow bits. */
4905 SET_PSR_C (tmp > 0xffff);
4906 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4907 SET_GPR (OP[1], tmp & 0xffff);
267b3b8e 4908 trace_output_16 (sd, tmp);
fee8ec00
SR		 4909}
4910
4911/* subcb. */
4912void
267b3b8e 4913OP_3C_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4914{
4915 uint8 a = OP[0];
4916 uint8 b = (GPR (OP[1])) & 0xff;
4917 //uint16 tmp1 = a + 1;
4918 uint16 tmp1 = a + (PSR_C);
4919 uint16 tmp = (~tmp1 + 1 + b);
4920 trace_input ("subcb", OP_CONSTANT4, OP_REG, OP_VOID);
4921 /* see ../common/sim-alu.h for a more extensive discussion on how to
4922 compute the carry/overflow bits. */
4923 SET_PSR_C (tmp > 0xff);
4924 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4925 SET_GPR (OP[1], tmp);
267b3b8e 4926 trace_output_16 (sd, tmp);
fee8ec00
SR		 4927}
4928
4929/* subcb. */
4930void
267b3b8e 4931OP_3CB_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4932{
4933 uint16 a = OP[0];
4934 uint16 b = (GPR (OP[1])) & 0xff;
4935 //uint16 tmp1 = a + 1;
4936 uint16 tmp1 = a + (PSR_C);
4937 uint16 tmp = (~tmp1 + 1 + b);
4938 trace_input ("subcb", OP_CONSTANT16, OP_REG, OP_VOID);
4939 /* see ../common/sim-alu.h for a more extensive discussion on how to
4940 compute the carry/overflow bits. */
4941 SET_PSR_C (tmp > 0xff);
4942 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4943 SET_GPR (OP[1], tmp);
267b3b8e 4944 trace_output_16 (sd, tmp);
fee8ec00
SR		 4945}
4946
4947/* subcb. */
4948void
267b3b8e 4949OP_3D_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4950{
4951 uint16 a = (GPR (OP[0])) & 0xff;
4952 uint16 b = (GPR (OP[1])) & 0xff;
4953 uint16 tmp1 = a + (PSR_C);
4954 uint16 tmp = (~tmp1 + 1 + b);
4955 trace_input ("subcb", OP_REG, OP_REG, OP_VOID);
4956 /* see ../common/sim-alu.h for a more extensive discussion on how to
4957 compute the carry/overflow bits. */
4958 SET_PSR_C (tmp > 0xff);
4959 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4960 SET_GPR (OP[1], tmp);
267b3b8e 4961 trace_output_16 (sd, tmp);
fee8ec00
SR		 4962}
4963
4964/* subcw. */
4965void
267b3b8e 4966OP_3E_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4967{
4968 uint16 a = OP[0], b = (GPR (OP[1]));
4969 uint16 tmp1 = a + (PSR_C);
4970 uint16 tmp = (~tmp1 + 1 + b);
4971 trace_input ("subcw", OP_CONSTANT4, OP_REG, OP_VOID);
4972 /* see ../common/sim-alu.h for a more extensive discussion on how to
4973 compute the carry/overflow bits. */
4974 SET_PSR_C (tmp > 0xffff);
4975 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4976 SET_GPR (OP[1], tmp);
267b3b8e 4977 trace_output_16 (sd, tmp);
fee8ec00
SR		 4978}
4979
4980/* subcw. */
4981void
267b3b8e 4982OP_3EB_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 4983{
4984 int16 a = OP[0];
4985 uint16 b = GPR (OP[1]);
4986 uint16 tmp1 = a + (PSR_C);
4987 uint16 tmp = (~tmp1 + 1 + b);
4988 trace_input ("subcw", OP_CONSTANT16, OP_REG, OP_VOID);
4989 /* see ../common/sim-alu.h for a more extensive discussion on how to
4990 compute the carry/overflow bits. */
4991 SET_PSR_C (tmp > 0xffff);
4992 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4993 SET_GPR (OP[1], tmp);
267b3b8e 4994 trace_output_16 (sd, tmp);
fee8ec00
SR		 4995}
4996
4997/* subcw. */
4998void
267b3b8e 4999OP_3F_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5000{
5001 uint16 a = (GPR (OP[0])), b = (GPR (OP[1]));
5002 uint16 tmp1 = a + (PSR_C);
5003 uint16 tmp = (~tmp1 + 1 + b);
5004 trace_input ("subcw", OP_REG, OP_REG, OP_VOID);
5005 /* see ../common/sim-alu.h for a more extensive discussion on how to
5006 compute the carry/overflow bits. */
5007 SET_PSR_C (tmp > 0xffff);
5008 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
5009 SET_GPR (OP[1], tmp);
267b3b8e 5010 trace_output_16 (sd, tmp);
fee8ec00
SR		 5011}
5012
5013/* subd. */
5014void
267b3b8e 5015OP_3_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5016{
5017 int32 a = OP[0];
5018 uint32 b = GPR32 (OP[1]);
5019 uint32 tmp = (~a + 1 + b);
5020 trace_input ("subd", OP_CONSTANT32, OP_REGP, OP_VOID);
5021 /* see ../common/sim-alu.h for a more extensive discussion on how to
5022 compute the carry/overflow bits. */
5023 SET_PSR_C (tmp > 0xffffffff);
5024 SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) &&
5025 ((b & 0x80000000) != (tmp & 0x80000000)));
5026 SET_GPR32 (OP[1], tmp);
267b3b8e 5027 trace_output_32 (sd, tmp);
fee8ec00
SR		 5028}
5029
5030/* subd. */
5031void
267b3b8e 5032OP_14C_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5033{
5034 uint32 a = GPR32 (OP[0]);
5035 uint32 b = GPR32 (OP[1]);
5036 uint32 tmp = (~a + 1 + b);
5037 trace_input ("subd", OP_REGP, OP_REGP, OP_VOID);
5038 /* see ../common/sim-alu.h for a more extensive discussion on how to
5039 compute the carry/overflow bits. */
5040 SET_PSR_C (tmp > 0xffffffff);
5041 SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) &&
5042 ((b & 0x80000000) != (tmp & 0x80000000)));
5043 SET_GPR32 (OP[1], tmp);
267b3b8e 5044 trace_output_32 (sd, tmp);
fee8ec00
SR		 5045}
5046
5047/* excp. */
5048void
267b3b8e 5049OP_C_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00 5050{
9db36cf8 5051 host_callback *cb = STATE_CALLBACK (sd);
5a06d7c4
MF		 5052 uint32 tmp;
5053 uint16 a;
fee8ec00
SR		 5054 trace_input ("excp", OP_CONSTANT4, OP_VOID, OP_VOID);
5055 switch (OP[0])
5056 {
5057 default:
5058#if (DEBUG & DEBUG_TRAP) == 0
5059 {
5060#if 0
5061 uint16 vec = OP[0] + TRAP_VECTOR_START;
5062 SET_BPC (PC + 1);
5063 SET_BPSR (PSR);
5064 SET_PSR (PSR & PSR_SM_BIT);
5065 JMP (vec);
5066 break;
5067#endif
5068 }
5069#else /* if debugging use trap to print registers */
5070 {
5071 int i;
5072 static int first_time = 1;
5073
5074 if (first_time)
5075 {
5076 first_time = 0;
9db36cf8 5077 sim_io_printf (sd, "Trap # PC ");
fee8ec00 5078 for (i = 0; i < 16; i++)
9db36cf8
MF		 5079 sim_io_printf (sd, " %sr%d", (i > 9) ? "" : " ", i);
5080 sim_io_printf (sd, " a0 a1 f0 f1 c\n");
fee8ec00
SR		 5081 }
5082
9db36cf8 5083 sim_io_printf (sd, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
fee8ec00
SR		 5084
5085 for (i = 0; i < 16; i++)
9db36cf8 5086 sim_io_printf (sd, " %.4x", (int) GPR (i));
fee8ec00
SR		 5087
5088 for (i = 0; i < 2; i++)
9db36cf8 5089 sim_io_printf (sd, " %.2x%.8lx",
fee8ec00
SR		 5090 ((int)(ACC (i) >> 32) & 0xff),
5091 ((unsigned long) ACC (i)) & 0xffffffff);
5092
9db36cf8 5093 sim_io_printf (sd, " %d %d %d\n",
fee8ec00 5094 PSR_F != 0, PSR_F != 0, PSR_C != 0);
9db36cf8 5095 sim_io_flush_stdout (sd);
fee8ec00
SR		 5096 break;
5097 }
5098#endif
5099 case 8: /* new system call trap */
5100 /* Trap 8 is used for simulating low-level I/O */
5101 {
5102 unsigned32 result = 0;
5103 errno = 0;
5104
5105/* Registers passed to trap 0. */
5106
5107#define FUNC GPR (0) /* function number. */
5108#define PARM1 GPR (2) /* optional parm 1. */
5109#define PARM2 GPR (3) /* optional parm 2. */
5110#define PARM3 GPR (4) /* optional parm 3. */
5111#define PARM4 GPR (5) /* optional parm 4. */
5112
5113/* Registers set by trap 0 */
5114
5115#define RETVAL(X) do { result = (0xffff & (X));SET_GPR (0, result);} while (0)
5116#define RETVAL32(X) do { result = (X); SET_GPR32 (0, result);} while (0)
5117#define RETERR(X) SET_GPR (4, (X)) /* return error code. */
5118
5119/* Turn a pointer in a register into a pointer into real memory. */
5120
761e171a 5121#define MEMPTR(x) sim_core_trans_addr (sd, cpu, read_map, x)
fee8ec00
SR		 5122
5123 switch (FUNC)
5124 {
5125#if !defined(__GO32__) && !defined(_WIN32)
9220438c 5126#ifdef TARGET_SYS_fork
fee8ec00
SR		 5127 case TARGET_SYS_fork:
5128 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
5129 RETVAL (fork ());
267b3b8e 5130 trace_output_16 (sd, result);
fee8ec00 5131 break;
9220438c 5132#endif
fee8ec00
SR		 5133
5134#define getpid() 47
5135 case TARGET_SYS_getpid:
5136 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
5137 RETVAL (getpid ());
267b3b8e 5138 trace_output_16 (sd, result);
fee8ec00
SR		 5139 break;
5140
5141 case TARGET_SYS_kill:
5142 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
5143 if (PARM1 == getpid ())
5144 {
267b3b8e 5145 trace_output_void (sd);
0ef7f981 5146 EXCEPTION (PARM2);
fee8ec00
SR		 5147 }
5148 else
5149 {
5150 int os_sig = -1;
5151 switch (PARM2)
5152 {
5153#ifdef SIGHUP
5154 case 1: os_sig = SIGHUP; break;
5155#endif
5156#ifdef SIGINT
5157 case 2: os_sig = SIGINT; break;
5158#endif
5159#ifdef SIGQUIT
5160 case 3: os_sig = SIGQUIT; break;
5161#endif
5162#ifdef SIGILL
5163 case 4: os_sig = SIGILL; break;
5164#endif
5165#ifdef SIGTRAP
5166 case 5: os_sig = SIGTRAP; break;
5167#endif
5168#ifdef SIGABRT
5169 case 6: os_sig = SIGABRT; break;
5170#elif defined(SIGIOT)
5171 case 6: os_sig = SIGIOT; break;
5172#endif
5173#ifdef SIGEMT
5174 case 7: os_sig = SIGEMT; break;
5175#endif
5176#ifdef SIGFPE
5177 case 8: os_sig = SIGFPE; break;
5178#endif
5179#ifdef SIGKILL
5180 case 9: os_sig = SIGKILL; break;
5181#endif
5182#ifdef SIGBUS
5183 case 10: os_sig = SIGBUS; break;
5184#endif
5185#ifdef SIGSEGV
5186 case 11: os_sig = SIGSEGV; break;
5187#endif
5188#ifdef SIGSYS
5189 case 12: os_sig = SIGSYS; break;
5190#endif
5191#ifdef SIGPIPE
5192 case 13: os_sig = SIGPIPE; break;
5193#endif
5194#ifdef SIGALRM
5195 case 14: os_sig = SIGALRM; break;
5196#endif
5197#ifdef SIGTERM
5198 case 15: os_sig = SIGTERM; break;
5199#endif
5200#ifdef SIGURG
5201 case 16: os_sig = SIGURG; break;
5202#endif
5203#ifdef SIGSTOP
5204 case 17: os_sig = SIGSTOP; break;
5205#endif
5206#ifdef SIGTSTP
5207 case 18: os_sig = SIGTSTP; break;
5208#endif
5209#ifdef SIGCONT
5210 case 19: os_sig = SIGCONT; break;
5211#endif
5212#ifdef SIGCHLD
5213 case 20: os_sig = SIGCHLD; break;
5214#elif defined(SIGCLD)
5215 case 20: os_sig = SIGCLD; break;
5216#endif
5217#ifdef SIGTTIN
5218 case 21: os_sig = SIGTTIN; break;
5219#endif
5220#ifdef SIGTTOU
5221 case 22: os_sig = SIGTTOU; break;
5222#endif
5223#ifdef SIGIO
5224 case 23: os_sig = SIGIO; break;
5225#elif defined (SIGPOLL)
5226 case 23: os_sig = SIGPOLL; break;
5227#endif
5228#ifdef SIGXCPU
5229 case 24: os_sig = SIGXCPU; break;
5230#endif
5231#ifdef SIGXFSZ
5232 case 25: os_sig = SIGXFSZ; break;
5233#endif
5234#ifdef SIGVTALRM
5235 case 26: os_sig = SIGVTALRM; break;
5236#endif
5237#ifdef SIGPROF
5238 case 27: os_sig = SIGPROF; break;
5239#endif
5240#ifdef SIGWINCH
5241 case 28: os_sig = SIGWINCH; break;
5242#endif
5243#ifdef SIGLOST
5244 case 29: os_sig = SIGLOST; break;
5245#endif
5246#ifdef SIGUSR1
5247 case 30: os_sig = SIGUSR1; break;
5248#endif
5249#ifdef SIGUSR2
5250 case 31: os_sig = SIGUSR2; break;
5251#endif
5252 }
5253
5254 if (os_sig == -1)
5255 {
267b3b8e 5256 trace_output_void (sd);
9db36cf8
MF		 5257 sim_io_printf (sd, "Unknown signal %d\n", PARM2);
5258 sim_io_flush_stdout (sd);
0ef7f981 5259 EXCEPTION (SIM_SIGILL);
fee8ec00
SR		 5260 }
5261 else
5262 {
5263 RETVAL (kill (PARM1, PARM2));
267b3b8e 5264 trace_output_16 (sd, result);
fee8ec00
SR		 5265 }
5266 }
5267 break;
5268
9220438c 5269#ifdef TARGET_SYS_execve
fee8ec00
SR		 5270 case TARGET_SYS_execve:
5271 trace_input ("<execve>", OP_VOID, OP_VOID, OP_VOID);
5272 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2<<16|PARM3),
5273 (char **)MEMPTR (PARM4)));
267b3b8e 5274 trace_output_16 (sd, result);
fee8ec00 5275 break;
9220438c 5276#endif
fee8ec00
SR		 5277
5278#ifdef TARGET_SYS_execv
5279 case TARGET_SYS_execv:
5280 trace_input ("<execv>", OP_VOID, OP_VOID, OP_VOID);
5281 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
267b3b8e 5282 trace_output_16 (sd, result);
fee8ec00
SR		 5283 break;
5284#endif
5285
9220438c 5286#ifdef TARGET_SYS_pipe
fee8ec00
SR		 5287 case TARGET_SYS_pipe:
5288 {
5289 reg_t buf;
5290 int host_fd[2];
5291
5292 trace_input ("<pipe>", OP_VOID, OP_VOID, OP_VOID);
5293 buf = PARM1;
5294 RETVAL (pipe (host_fd));
5295 SW (buf, host_fd[0]);
5296 buf += sizeof(uint16);
5297 SW (buf, host_fd[1]);
267b3b8e 5298 trace_output_16 (sd, result);
fee8ec00
SR		 5299 }
5300 break;
9220438c 5301#endif
fee8ec00
SR		 5302
5303#ifdef TARGET_SYS_wait
5304 case TARGET_SYS_wait:
5305 {
5306 int status;
5307 trace_input ("<wait>", OP_REG, OP_VOID, OP_VOID);
5308 RETVAL (wait (&status));
5309 if (PARM1)
5310 SW (PARM1, status);
267b3b8e 5311 trace_output_16 (sd, result);
fee8ec00
SR		 5312 }
5313 break;
5314#endif
5315#else
5316 case TARGET_SYS_getpid:
5317 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
5318 RETVAL (1);
267b3b8e 5319 trace_output_16 (sd, result);
fee8ec00
SR		 5320 break;
5321
5322 case TARGET_SYS_kill:
5323 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
267b3b8e 5324 trace_output_void (sd);
0ef7f981 5325 EXCEPTION (PARM2);
fee8ec00
SR		 5326 break;
5327#endif
5328
5329 case TARGET_SYS_read:
5330 trace_input ("<read>", OP_REG, OP_MEMREF, OP_REG);
9db36cf8
MF		 5331 RETVAL (cb->read (cb, PARM1,
5332 MEMPTR (((unsigned long)PARM3 << 16)
5333 | ((unsigned long)PARM2)), PARM4));
267b3b8e 5334 trace_output_16 (sd, result);
fee8ec00
SR		 5335 break;
5336
5337 case TARGET_SYS_write:
5338 trace_input ("<write>", OP_REG, OP_MEMREF, OP_REG);
9db36cf8
MF		 5339 RETVAL ((int)cb->write (cb, PARM1,
5340 MEMPTR (((unsigned long)PARM3 << 16)
5341 | PARM2), PARM4));
267b3b8e 5342 trace_output_16 (sd, result);
fee8ec00
SR		 5343 break;
5344
5345 case TARGET_SYS_lseek:
5346 trace_input ("<lseek>", OP_REG, OP_REGP, OP_REG);
9db36cf8
MF		 5347 RETVAL32 (cb->lseek (cb, PARM1, ((((long) PARM3) << 16) | PARM2),
5348 PARM4));
267b3b8e 5349 trace_output_32 (sd, result);
fee8ec00
SR		 5350 break;
5351
5352 case TARGET_SYS_close:
5353 trace_input ("<close>", OP_REG, OP_VOID, OP_VOID);
9db36cf8 5354 RETVAL (cb->close (cb, PARM1));
267b3b8e 5355 trace_output_16 (sd, result);
fee8ec00
SR		 5356 break;
5357
5358 case TARGET_SYS_open:
5359 trace_input ("<open>", OP_MEMREF, OP_REG, OP_VOID);
9db36cf8
MF		 5360 RETVAL32 (cb->open (cb, MEMPTR ((((unsigned long)PARM2) << 16)
5361 | PARM1), PARM3));
267b3b8e 5362 trace_output_32 (sd, result);
fee8ec00
SR		 5363 break;
5364
9220438c 5365#ifdef TARGET_SYS_rename
fee8ec00
SR		 5366 case TARGET_SYS_rename:
5367 trace_input ("<rename>", OP_MEMREF, OP_MEMREF, OP_VOID);
9db36cf8
MF		 5368 RETVAL (cb->rename (cb, MEMPTR ((((unsigned long)PARM2) << 16) | PARM1),
5369 MEMPTR ((((unsigned long)PARM4) << 16) | PARM3)));
267b3b8e 5370 trace_output_16 (sd, result);
fee8ec00 5371 break;
9220438c 5372#endif
fee8ec00
SR		 5373
5374 case 0x408: /* REVISIT: Added a dummy getenv call. */
5375 trace_input ("<getenv>", OP_MEMREF, OP_MEMREF, OP_VOID);
5aedb83b 5376 RETVAL32 (0);
267b3b8e 5377 trace_output_32 (sd, result);
fee8ec00
SR		 5378 break;
5379
5380 case TARGET_SYS_exit:
5381 trace_input ("<exit>", OP_VOID, OP_VOID, OP_VOID);
267b3b8e 5382 trace_output_void (sd);
0ef7f981 5383 sim_engine_halt (sd, cpu, NULL, PC, sim_exited, GPR (2));
fee8ec00
SR		 5384 break;
5385
5386 case TARGET_SYS_unlink:
5387 trace_input ("<unlink>", OP_MEMREF, OP_VOID, OP_VOID);
9db36cf8 5388 RETVAL (cb->unlink (cb, MEMPTR (((unsigned long)PARM2 << 16) | PARM1)));
267b3b8e 5389 trace_output_16 (sd, result);
fee8ec00
SR		 5390 break;
5391
5392
5393#ifdef TARGET_SYS_stat
5394 case TARGET_SYS_stat:
5395 trace_input ("<stat>", OP_VOID, OP_VOID, OP_VOID);
5396 /* stat system call. */
5397 {
5398 struct stat host_stat;
5399 reg_t buf;
5400
5401 RETVAL (stat (MEMPTR ((((unsigned long)PARM2) << 16)|PARM1), &host_stat));
5402
5403 buf = PARM2;
5404
5405 /* The hard-coded offsets and sizes were determined by using
5406 * the CR16 compiler on a test program that used struct stat.
5407 */
5408 SW (buf, host_stat.st_dev);
5409 SW (buf+2, host_stat.st_ino);
5410 SW (buf+4, host_stat.st_mode);
5411 SW (buf+6, host_stat.st_nlink);
5412 SW (buf+8, host_stat.st_uid);
5413 SW (buf+10, host_stat.st_gid);
5414 SW (buf+12, host_stat.st_rdev);
5415 SLW (buf+16, host_stat.st_size);
5416 SLW (buf+20, host_stat.st_atime);
5417 SLW (buf+28, host_stat.st_mtime);
5418 SLW (buf+36, host_stat.st_ctime);
5419 }
267b3b8e 5420 trace_output_16 (sd, result);
fee8ec00
SR		 5421 break;
5422#endif
5423
9220438c 5424#ifdef TARGET_SYS_chown
fee8ec00
SR		 5425 case TARGET_SYS_chown:
5426 trace_input ("<chown>", OP_VOID, OP_VOID, OP_VOID);
5427 RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
267b3b8e 5428 trace_output_16 (sd, result);
fee8ec00 5429 break;
9220438c 5430#endif
fee8ec00
SR		 5431
5432 case TARGET_SYS_chmod:
5433 trace_input ("<chmod>", OP_VOID, OP_VOID, OP_VOID);
5434 RETVAL (chmod (MEMPTR (PARM1), PARM2));
267b3b8e 5435 trace_output_16 (sd, result);
fee8ec00
SR		 5436 break;
5437
5438#ifdef TARGET_SYS_utime
5439 case TARGET_SYS_utime:
5440 trace_input ("<utime>", OP_REG, OP_REG, OP_REG);
5441 /* Cast the second argument to void *, to avoid type mismatch
5442 if a prototype is present. */
5443 RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
267b3b8e 5444 trace_output_16 (sd, result);
fee8ec00
SR		 5445 break;
5446#endif
5447
5448#ifdef TARGET_SYS_time
5449 case TARGET_SYS_time:
5450 trace_input ("<time>", OP_VOID, OP_VOID, OP_REG);
5451 RETVAL32 (time (NULL));
267b3b8e 5452 trace_output_32 (sd, result);
fee8ec00
SR		 5453 break;
5454#endif
5455
5456 default:
5a06d7c4
MF		 5457 a = OP[0];
5458 switch (a)
5459 {
5460 case TRAP_BREAKPOINT:
5a06d7c4
MF		 5461 tmp = (PC);
5462 JMP(tmp);
267b3b8e 5463 trace_output_void (sd);
0ef7f981 5464 EXCEPTION (SIM_SIGTRAP);
5a06d7c4
MF		 5465 break;
5466 case SIGTRAP: /* supervisor call ? */
267b3b8e 5467 trace_output_void (sd);
0ef7f981 5468 sim_engine_halt (sd, cpu, NULL, PC, sim_exited, GPR (2));
5a06d7c4
MF		 5469 break;
5470 default:
9db36cf8 5471 cb->error (cb, "Unknown syscall %d", FUNC);
5a06d7c4
MF		 5472 break;
5473 }
fee8ec00 5474 }
fee8ec00 5475 if ((uint16) result == (uint16) -1)
9db36cf8 5476 RETERR (cb->get_errno (cb));
fee8ec00
SR		 5477 else
5478 RETERR (0);
5479 break;
5480 }
5481 }
5482}
5483
5484
5485/* push. */
5486void
267b3b8e 5487OP_3_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5488{
5489 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5490 uint32 tmp, sp_addr = (GPR32 (15)) - (a * 2) - 4, is_regp = 0;
5491 trace_input ("push", OP_CONSTANT3, OP_REG, OP_REG);
5492
5493 for (; i < a; ++i)
5494 {
5495 if ((b+i) <= 11)
5496 {
5497 SW (sp_addr, (GPR (b+i)));
5498 sp_addr +=2;
5499 }
5500 else
5501 {
5502 if (is_regp == 0)
5503 tmp = (GPR32 (b+i));
5504 else
5505 tmp = (GPR32 (b+i-1));
5506
5507 if ((a-i) > 1)
5508 {
5509 SLW (sp_addr, tmp);
5510 sp_addr +=4;
5511 }
5512 else
5513 {
5514 SW (sp_addr, tmp);
5515 sp_addr +=2;
5516 }
5517 ++i;
5518 is_regp = 1;
5519 }
5520 }
5521
5522 sp_addr +=4;
5523
5524 /* Store RA address. */
5525 tmp = (GPR32 (14));
5526 SLW(sp_addr,tmp);
5527
5528 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5529 SET_GPR32 (15, sp_addr); /* Update SP address. */
5530
267b3b8e 5531 trace_output_void (sd);
fee8ec00
SR		 5532}
5533
5534/* push. */
5535void
267b3b8e 5536OP_1_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5537{
5538 uint32 sp_addr, tmp, is_regp = 0;
5539 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5540 trace_input ("push", OP_CONSTANT3, OP_REG, OP_VOID);
5541
5542 if (c == 1)
5543 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5544 else
5545 sp_addr = (GPR32 (15)) - (a * 2);
5546
5547 for (; i < a; ++i)
5548 {
5549 if ((b+i) <= 11)
5550 {
5551 SW (sp_addr, (GPR (b+i)));
5552 sp_addr +=2;
5553 }
5554 else
5555 {
5556 if (is_regp == 0)
5557 tmp = (GPR32 (b+i));
5558 else
5559 tmp = (GPR32 (b+i-1));
5560
5561 if ((a-i) > 1)
5562 {
5563 SLW (sp_addr, tmp);
5564 sp_addr +=4;
5565 }
5566 else
5567 {
5568 SW (sp_addr, tmp);
5569 sp_addr +=2;
5570 }
5571 ++i;
5572 is_regp = 1;
5573 }
5574 }
5575
5576 if (c == 1)
5577 {
5578 /* Store RA address. */
5579 tmp = (GPR32 (14));
5580 SLW(sp_addr,tmp);
5581 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5582 }
5583 else
5584 sp_addr = (GPR32 (15)) - (a * 2);
5585
5586 SET_GPR32 (15, sp_addr); /* Update SP address. */
5587
267b3b8e 5588 trace_output_void (sd);
fee8ec00
SR		 5589}
5590
5591
5592/* push. */
5593void
267b3b8e 5594OP_11E_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5595{
5596 uint32 sp_addr = (GPR32 (15)), tmp;
5597 trace_input ("push", OP_VOID, OP_VOID, OP_VOID);
5598 tmp = (GPR32 (14));
5599 SLW(sp_addr-4,tmp); /* Store RA address. */
5600 SET_GPR32 (15, (sp_addr - 4)); /* Update SP address. */
267b3b8e 5601 trace_output_void (sd);
fee8ec00
SR		 5602}
5603
5604
5605/* pop. */
5606void
267b3b8e 5607OP_5_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5608{
5609 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5610 uint32 tmp, sp_addr = (GPR32 (15)), is_regp = 0;;
5611 trace_input ("pop", OP_CONSTANT3, OP_REG, OP_REG);
5612
5613 for (; i < a; ++i)
5614 {
5615 if ((b+i) <= 11)
5616 {
5617 SET_GPR ((b+i), RW(sp_addr));
5618 sp_addr +=2;
5619 }
5620 else
5621 {
5622 if ((a-i) > 1)
5623 {
5624 tmp = RLW(sp_addr);
5625 sp_addr +=4;
5626 }
5627 else
5628 {
5629 tmp = RW(sp_addr);
5630 sp_addr +=2;
5631
5632 if (is_regp == 0)
5633 tmp = (tmp << 16) | (GPR32 (b+i));
5634 else
5635 tmp = (tmp << 16) | (GPR32 (b+i-1));
5636 }
5637
5638 if (is_regp == 0)
5639 SET_GPR32 ((b+i), (((tmp & 0xffff) << 16)
5640 | ((tmp >> 16) & 0xffff)));
5641 else
5642 SET_GPR32 ((b+i-1), (((tmp & 0xffff) << 16)
5643 | ((tmp >> 16) & 0xffff)));
5644
5645 ++i;
5646 is_regp = 1;
5647 }
5648 }
5649
5650 tmp = RLW(sp_addr); /* store RA also. */
5651 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5652
5653 SET_GPR32 (15, (sp_addr + 4)); /* Update SP address. */
5654
267b3b8e 5655 trace_output_void (sd);
fee8ec00
SR		 5656}
5657
5658/* pop. */
5659void
267b3b8e 5660OP_2_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5661{
5662 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5663 uint32 tmp, sp_addr = (GPR32 (15)), is_regp = 0;
5664 trace_input ("pop", OP_CONSTANT3, OP_REG, OP_VOID);
5665
5666 for (; i < a; ++i)
5667 {
5668 if ((b+i) <= 11)
5669 {
5670 SET_GPR ((b+i), RW(sp_addr));
5671 sp_addr +=2;
5672 }
5673 else
5674 {
5675 if ((a-i) > 1)
5676 {
5677 tmp = RLW(sp_addr);
5678 sp_addr +=4;
5679 }
5680 else
5681 {
5682 tmp = RW(sp_addr);
5683 sp_addr +=2;
5684
5685 if (is_regp == 0)
5686 tmp = ((tmp << 16) & 0xffffffff) | (GPR32 (b+i));
5687 else
5688 tmp = ((tmp << 16) & 0xffffffff) | (GPR32 (b+i-1));
5689 }
5690
5691 if (is_regp == 0)
5692 SET_GPR32 ((b+i), (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5693 else
5694 SET_GPR32 ((b+i-1), (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5695 ++i;
5696 is_regp = 1;
5697 }
5698 }
5699
5700 if (c == 1)
5701 {
5702 tmp = RLW(sp_addr); /* Store RA Reg. */
5703 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5704 sp_addr +=4;
5705 }
5706
5707 SET_GPR32 (15, sp_addr); /* Update SP address. */
5708
267b3b8e 5709 trace_output_void (sd);
fee8ec00
SR		 5710}
5711
5712/* pop. */
5713void
267b3b8e 5714OP_21E_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5715{
5716 uint32 sp_addr = GPR32 (15);
5717 uint32 tmp;
5718 trace_input ("pop", OP_VOID, OP_VOID, OP_VOID);
5719
5720 tmp = RLW(sp_addr);
5721 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5722 SET_GPR32 (15, (sp_addr+4)); /* Update SP address. */
5723
267b3b8e 5724 trace_output_void (sd);
fee8ec00
SR		 5725}
5726
5727/* popret. */
5728void
267b3b8e 5729OP_7_9 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5730{
5731 uint16 a = OP[0], b = OP[1];
5732 trace_input ("popret", OP_CONSTANT3, OP_REG, OP_REG);
267b3b8e 5733 OP_5_9 (sd, cpu);
fee8ec00
SR		 5734 JMP(((GPR32(14)) << 1) & 0xffffff);
5735
267b3b8e 5736 trace_output_void (sd);
fee8ec00
SR		 5737}
5738
5739/* popret. */
5740void
267b3b8e 5741OP_3_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5742{
5743 uint16 a = OP[0], b = OP[1];
5744 trace_input ("popret", OP_CONSTANT3, OP_REG, OP_VOID);
267b3b8e 5745 OP_2_8 (sd, cpu);
fee8ec00
SR		 5746 JMP(((GPR32(14)) << 1) & 0xffffff);
5747
267b3b8e 5748 trace_output_void (sd);
fee8ec00
SR		 5749}
5750
5751/* popret. */
5752void
267b3b8e 5753OP_31E_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5754{
5755 uint32 tmp;
5756 trace_input ("popret", OP_VOID, OP_VOID, OP_VOID);
267b3b8e 5757 OP_21E_10 (sd, cpu);
fee8ec00
SR		 5758 tmp = (((GPR32(14)) << 1) & 0xffffff);
5759 /* If the resulting PC value is less than 0x00_0000 or greater
5760 than 0xFF_FFFF, this instruction causes an IAD trap.*/
5761
5762 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
5763 {
267b3b8e 5764 trace_output_void (sd);
0ef7f981 5765 EXCEPTION (SIM_SIGBUS);
fee8ec00
SR		 5766 }
5767 else
5768 JMP (tmp);
5769
267b3b8e 5770 trace_output_32 (sd, tmp);
fee8ec00
SR		 5771}
5772
5773
5774/* cinv[i]. */
5775void
267b3b8e 5776OP_A_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5777{
5778 trace_input ("cinv[i]", OP_VOID, OP_VOID, OP_VOID);
5779 SET_PSR_I (1);
267b3b8e 5780 trace_output_void (sd);
fee8ec00
SR		 5781}
5782
5783/* cinv[i,u]. */
5784void
267b3b8e 5785OP_B_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5786{
5787 trace_input ("cinv[i,u]", OP_VOID, OP_VOID, OP_VOID);
5788 SET_PSR_I (1);
267b3b8e 5789 trace_output_void (sd);
fee8ec00
SR		 5790}
5791
5792/* cinv[d]. */
5793void
267b3b8e 5794OP_C_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5795{
5796 trace_input ("cinv[d]", OP_VOID, OP_VOID, OP_VOID);
5797 SET_PSR_I (1);
267b3b8e 5798 trace_output_void (sd);
fee8ec00
SR		 5799}
5800
5801/* cinv[d,u]. */
5802void
267b3b8e 5803OP_D_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5804{
5805 trace_input ("cinv[i,u]", OP_VOID, OP_VOID, OP_VOID);
5806 SET_PSR_I (1);
267b3b8e 5807 trace_output_void (sd);
fee8ec00
SR		 5808}
5809
5810/* cinv[d,i]. */
5811void
267b3b8e 5812OP_E_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5813{
5814 trace_input ("cinv[d,i]", OP_VOID, OP_VOID, OP_VOID);
5815 SET_PSR_I (1);
267b3b8e 5816 trace_output_void (sd);
fee8ec00
SR		 5817}
5818
5819/* cinv[d,i,u]. */
5820void
267b3b8e 5821OP_F_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5822{
5823 trace_input ("cinv[d,i,u]", OP_VOID, OP_VOID, OP_VOID);
5824 SET_PSR_I (1);
267b3b8e 5825 trace_output_void (sd);
fee8ec00
SR		 5826}
5827
5828/* retx. */
5829void
267b3b8e 5830OP_3_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5831{
5832 trace_input ("retx", OP_VOID, OP_VOID, OP_VOID);
5833 SET_PSR_I (1);
267b3b8e 5834 trace_output_void (sd);
fee8ec00
SR		 5835}
5836
5837/* di. */
5838void
267b3b8e 5839OP_4_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5840{
5841 trace_input ("di", OP_VOID, OP_VOID, OP_VOID);
5842 SET_PSR_I (1);
267b3b8e 5843 trace_output_void (sd);
fee8ec00
SR		 5844}
5845
5846/* ei. */
5847void
267b3b8e 5848OP_5_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5849{
5850 trace_input ("ei", OP_VOID, OP_VOID, OP_VOID);
5851 SET_PSR_I (1);
267b3b8e 5852 trace_output_void (sd);
fee8ec00
SR		 5853}
5854
5855/* wait. */
5856void
267b3b8e 5857OP_6_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5858{
5859 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
267b3b8e 5860 trace_output_void (sd);
0ef7f981 5861 EXCEPTION (SIM_SIGTRAP);
fee8ec00
SR		 5862}
5863
5864/* ewait. */
5865void
267b3b8e 5866OP_7_10 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5867{
5868 trace_input ("ewait", OP_VOID, OP_VOID, OP_VOID);
5869 SET_PSR_I (1);
267b3b8e 5870 trace_output_void (sd);
fee8ec00
SR		 5871}
5872
5873/* xorb. */
5874void
267b3b8e 5875OP_28_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5876{
5877 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
5878 trace_input ("xorb", OP_CONSTANT4, OP_REG, OP_VOID);
5879 tmp = a ^ b;
5880 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 5881 trace_output_16 (sd, tmp);
fee8ec00
SR		 5882}
5883
5884/* xorb. */
5885void
267b3b8e 5886OP_28B_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5887{
5888 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
5889 trace_input ("xorb", OP_CONSTANT16, OP_REG, OP_VOID);
5890 tmp = a ^ b;
5891 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 5892 trace_output_16 (sd, tmp);
fee8ec00
SR		 5893}
5894
5895/* xorb. */
5896void
267b3b8e 5897OP_29_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5898{
5899 uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
5900 trace_input ("xorb", OP_REG, OP_REG, OP_VOID);
5901 tmp = a ^ b;
5902 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
267b3b8e 5903 trace_output_16 (sd, tmp);
fee8ec00
SR		 5904}
5905
5906/* xorw. */
5907void
267b3b8e 5908OP_2A_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5909{
5910 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
5911 trace_input ("xorw", OP_CONSTANT4, OP_REG, OP_VOID);
5912 tmp = a ^ b;
5913 SET_GPR (OP[1], tmp);
267b3b8e 5914 trace_output_16 (sd, tmp);
fee8ec00
SR		 5915}
5916
5917/* xorw. */
5918void
267b3b8e 5919OP_2AB_C (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5920{
5921 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
5922 trace_input ("xorw", OP_CONSTANT16, OP_REG, OP_VOID);
5923 tmp = a ^ b;
5924 SET_GPR (OP[1], tmp);
267b3b8e 5925 trace_output_16 (sd, tmp);
fee8ec00
SR		 5926}
5927
5928/* xorw. */
5929void
267b3b8e 5930OP_2B_8 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5931{
5932 uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
5933 trace_input ("xorw", OP_REG, OP_REG, OP_VOID);
5934 tmp = a ^ b;
5935 SET_GPR (OP[1], tmp);
267b3b8e 5936 trace_output_16 (sd, tmp);
fee8ec00
SR		 5937}
5938
5939/*REVISIT FOR LPR/SPR . */
5940
5941/* lpr. */
5942void
267b3b8e 5943OP_140_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5944{
5945 uint16 a = GPR (OP[0]);
5946 trace_input ("lpr", OP_REG, OP_REG, OP_VOID);
5947 SET_CREG (OP[1], a);
267b3b8e 5948 trace_output_16 (sd, a);
fee8ec00
SR		 5949}
5950
5951/* lprd. */
5952void
267b3b8e 5953OP_141_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5954{
5955 uint32 a = GPR32 (OP[0]);
5956 trace_input ("lprd", OP_REGP, OP_REG, OP_VOID);
5957 SET_CREG (OP[1], a);
267b3b8e 5958 trace_output_flag (sd);
fee8ec00
SR		 5959}
5960
5961/* spr. */
5962void
267b3b8e 5963OP_142_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5964{
5965 uint16 a = CREG (OP[0]);
5966 trace_input ("spr", OP_REG, OP_REG, OP_VOID);
5967 SET_GPR (OP[1], a);
267b3b8e 5968 trace_output_16 (sd, a);
fee8ec00
SR		 5969}
5970
5971/* sprd. */
5972void
267b3b8e 5973OP_143_14 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5974{
5975 uint32 a = CREG (OP[0]);
5976 trace_input ("sprd", OP_REGP, OP_REGP, OP_VOID);
5977 SET_GPR32 (OP[1], a);
267b3b8e 5978 trace_output_32 (sd, a);
fee8ec00
SR		 5979}
5980
5981/* null. */
5982void
267b3b8e 5983OP_0_20 (SIM_DESC sd, SIM_CPU *cpu)
fee8ec00
SR		 5984{
5985 trace_input ("null", OP_VOID, OP_VOID, OP_VOID);
0ef7f981 5986 sim_engine_halt (sd, cpu, NULL, PC, sim_exited, 0);
fee8ec00 5987}
GDB Binutils - Deliverables
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