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b34f6357 | 1 | /* frv simulator support code |
88b9d363 | 2 | Copyright (C) 1998-2022 Free Software Foundation, Inc. |
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3 | Contributed by Red Hat. |
4 | ||
5 | This file is part of the GNU simulators. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
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9 | the Free Software Foundation; either version 3 of the License, or |
10 | (at your option) any later version. | |
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11 | |
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
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17 | You should have received a copy of the GNU General Public License |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
b34f6357 | 19 | |
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20 | #ifndef FRV_SIM_MAIN_H |
21 | #define FRV_SIM_MAIN_H | |
22 | ||
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23 | /* Main header for the frv. */ |
24 | ||
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25 | /* This is a global setting. Different cpu families can't mix-n-match -scache |
26 | and -pbb. However some cpu families may use -simple while others use | |
27 | one of -scache/-pbb. ???? */ | |
28 | #define WITH_SCACHE_PBB 0 | |
29 | ||
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30 | #include "symcat.h" |
31 | #include "sim-basics.h" | |
32 | #include "cgen-types.h" | |
33 | #include "frv-desc.h" | |
34 | #include "frv-opc.h" | |
35 | #include "arch.h" | |
36 | ||
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37 | #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) \ |
38 | frv_sim_engine_halt_hook ((SD), (LAST_CPU), (CIA)) | |
39 | ||
520ca9a7 | 40 | #define SIM_ENGINE_RESTART_HOOK(SD, LAST_CPU, CIA) |
b34f6357 DB |
41 | |
42 | #include "sim-base.h" | |
43 | #include "cgen-sim.h" | |
44 | #include "frv-sim.h" | |
45 | #include "cache.h" | |
46 | #include "registers.h" | |
47 | #include "profile.h" | |
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48 | |
49 | void frv_sim_engine_halt_hook (SIM_DESC, SIM_CPU *, sim_cia); | |
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50 | |
51 | extern void frv_sim_close (SIM_DESC sd, int quitting); | |
52 | #define SIM_CLOSE_HOOK(...) frv_sim_close (__VA_ARGS__) | |
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53 | \f |
54 | /* The _sim_cpu struct. */ | |
55 | ||
56 | struct _sim_cpu { | |
57 | /* sim/common cpu base. */ | |
58 | sim_cpu_base base; | |
59 | ||
60 | /* Static parts of cgen. */ | |
61 | CGEN_CPU cgen_cpu; | |
62 | ||
63 | /* CPU specific parts go here. | |
64 | Note that in files that don't need to access these pieces WANT_CPU_FOO | |
65 | won't be defined and thus these parts won't appear. This is ok in the | |
66 | sense that things work. It is a source of bugs though. | |
67 | One has to of course be careful to not take the size of this | |
68 | struct and no structure members accessed in non-cpu specific files can | |
69 | go after here. Oh for a better language. */ | |
70 | #if defined (WANT_CPU_FRVBF) | |
71 | FRVBF_CPU_DATA cpu_data; | |
72 | ||
73 | /* Control information for registers */ | |
74 | FRV_REGISTER_CONTROL register_control; | |
75 | #define CPU_REGISTER_CONTROL(cpu) (& (cpu)->register_control) | |
76 | ||
77 | FRV_VLIW vliw; | |
78 | #define CPU_VLIW(cpu) (& (cpu)->vliw) | |
79 | ||
80 | FRV_CACHE insn_cache; | |
81 | #define CPU_INSN_CACHE(cpu) (& (cpu)->insn_cache) | |
82 | ||
83 | FRV_CACHE data_cache; | |
84 | #define CPU_DATA_CACHE(cpu) (& (cpu)->data_cache) | |
85 | ||
86 | FRV_PROFILE_STATE profile_state; | |
87 | #define CPU_PROFILE_STATE(cpu) (& (cpu)->profile_state) | |
88 | ||
89 | int debug_state; | |
90 | #define CPU_DEBUG_STATE(cpu) ((cpu)->debug_state) | |
91 | ||
92 | SI load_address; | |
93 | #define CPU_LOAD_ADDRESS(cpu) ((cpu)->load_address) | |
94 | ||
95 | SI load_length; | |
96 | #define CPU_LOAD_LENGTH(cpu) ((cpu)->load_length) | |
97 | ||
98 | SI load_flag; | |
99 | #define CPU_LOAD_SIGNED(cpu) ((cpu)->load_flag) | |
100 | #define CPU_LOAD_LOCK(cpu) ((cpu)->load_flag) | |
101 | ||
102 | SI store_flag; | |
103 | #define CPU_RSTR_INVALIDATE(cpu) ((cpu)->store_flag) | |
104 | ||
105 | unsigned long elf_flags; | |
106 | #define CPU_ELF_FLAGS(cpu) ((cpu)->elf_flags) | |
107 | #endif /* defined (WANT_CPU_FRVBF) */ | |
108 | }; | |
109 | \f | |
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110 | /* Misc. */ |
111 | ||
112 | /* Catch address exceptions. */ | |
113 | extern SIM_CORE_SIGNAL_FN frv_core_signal; | |
114 | #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ | |
115 | frv_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \ | |
116 | (TRANSFER), (ERROR)) | |
117 | ||
118 | /* Default memory size. */ | |
119 | #define FRV_DEFAULT_MEM_SIZE 0x800000 /* 8M */ | |
a9d20039 MF |
120 | |
121 | void frvbf_model_branch (SIM_CPU *, PCADDR, int hint); | |
122 | void frvbf_perform_writeback (SIM_CPU *); | |
123 | ||
124 | #endif |