[deliverable/binutils-gdb.git] / sim / h8300 / sim-main.h

/* Main header for the Hitachi h8/300 architecture.  */

#include "config.h"
#include "bfd.h"

#ifndef SIM_MAIN_H
#define SIM_MAIN_H

#define DEBUG

/* These define the size of main memory for the simulator.

   Note the size of main memory for the H8/300H is only 256k.  Keeping it
   small makes the simulator run much faster and consume less memory.

   The linker knows about the limited size of the simulator's main memory
   on the H8/300H (via the h8300h.sc linker script).  So if you change
   H8300H_MSIZE, be sure to fix the linker script too.

   Also note that there's a separate "eightbit" area aside from main
   memory.  For simplicity, the simulator assumes any data memory reference
   outside of main memory refers to the eightbit area (in theory, this
   can only happen when simulating H8/300H programs).  We make no attempt
   to catch overlapping addresses, wrapped addresses, etc etc.  */

#define H8300_MSIZE (1 << 16)

/* avolkov: 
   Next 2 macros are ugly for any workstation, but while they're work.
   Memory size MUST be configurable.  */
#define H8300H_MSIZE (1 << 24) 
#define H8300S_MSIZE (1 << 24) 

#define CSIZE 1024

enum h8_regnum {
  R0_REGNUM = 0,
  R1_REGNUM = 1,
  R2_REGNUM = 2,
  R3_REGNUM = 3,
  R4_REGNUM = 4,
  R5_REGNUM = 5,
  R6_REGNUM = 6,
  R7_REGNUM = 7,

  SP_REGNUM = R7_REGNUM,	/* Contains address of top of stack */
  FP_REGNUM = R6_REGNUM,	/* Contains address of executing
				   stack frame */
  CCR_REGNUM = 8,		/* Contains processor status */
  PC_REGNUM  = 9,		/* Contains program counter */
  CYCLE_REGNUM = 10,
  EXR_REGNUM  = 11,
  INST_REGNUM = 12,
  TICK_REGNUM = 13,
  MACH_REGNUM = 14,
  MACL_REGNUM = 15,
  SBR_REGNUM =  16,
  VBR_REGNUM =  17,

  ZERO_REGNUM = 18
};

enum h8_typecodes {
  OP_NULL,
  OP_REG,		/* Register direct.  */
  OP_LOWREG,		/* Special reg syntax for "bra".  */
  OP_DISP,		/* Register indirect w/displacement.  */
  /* Note: h8300, h8300h, and h8300s permit only pre-decr and post-incr.  */
  OP_PREDEC,		/* Register indirect w/pre-decrement.  */
  OP_POSTDEC,		/* Register indirect w/post-decrement.  */
  OP_PREINC,		/* Register indirect w/pre-increment.  */
  OP_POSTINC,		/* Register indirect w/post-increment.  */
  OP_PCREL,		/* PC Relative.  */
  OP_MEM,		/* Absolute memory address.  */
  OP_CCR,		/* Condition Code Register.  */
  OP_IMM,		/* Immediate value.  */
  /*OP_ABS*/		/* Un-used (duplicates op_mem?).  */
  OP_EXR,		/* EXtended control Register.  */
  OP_SBR, 		/* Vector Base Register.  */
  OP_VBR,		/* Short-address Base Register.  */
  OP_MACH,		/* Multiply Accumulator - high.  */
  OP_MACL,		/* Multiply Accumulator - low.   */
  /* FIXME: memory indirect?  */
  OP_INDEXB,		/* Byte index mode */
  OP_INDEXW,		/* Word index mode */
  OP_INDEXL		/* Long index mode */
};

#include "sim-basics.h"
#include "sim-base.h"

/* Structure used to describe addressing */

typedef struct
{
  int type;
  int reg;
  int literal;
} ea_type;

/* Struct for instruction decoder.  */
typedef struct
{
  ea_type src;
  ea_type dst;
  ea_type op3;
  int opcode;
  int next_pc;
  int oldpc;
  int cycles;
#ifdef DEBUG
  struct h8_opcode *op;
#endif
} decoded_inst;

struct _sim_cpu {
  unsigned int regs[20];	/* 8 GR's plus ZERO, SBR, and VBR.  */
  unsigned int pc;

  int macS;			/* MAC Saturating mode */
  int macV;			/* MAC Overflow */
  int macN;			/* MAC Negative */
  int macZ;			/* MAC Zero     */

  int delayed_branch;
  char **command_line;		/* Pointer to command line arguments.  */

  unsigned char *memory;
  unsigned char *eightbit;
  int mask;
  
  sim_cpu_base base;
};

/* The sim_state struct.  */
struct sim_state {
  sim_cpu *cpu[MAX_NR_PROCESSORS];
  unsigned int sim_cache_size;
  decoded_inst *sim_cache;
  unsigned short *cache_idx;
  unsigned long memory_size;
  int cache_top;
  int compiles;
#ifdef ADEBUG
  int stats[O_LAST];
#endif
  sim_state_base base;
};

/* The current state of the processor; registers, memory, etc.  */

#define cpu_set_pc(CPU, VAL)	(((CPU)->pc)  = (VAL))
#define cpu_get_pc(CPU)		(((CPU)->pc))

/* Magic numbers used to distinguish an exit from a breakpoint.  */
#define LIBC_EXIT_MAGIC1 0xdead	
#define LIBC_EXIT_MAGIC2 0xbeef	
/* Local version of macros for decoding exit status.  
   (included here rather than try to find target version of wait.h)
*/
#define SIM_WIFEXITED(V)	(((V) & 0xff) == 0)
#define SIM_WIFSTOPPED(V)	(!SIM_WIFEXITED (V))
#define SIM_WEXITSTATUS(V)	(((V) >> 8) & 0xff)
#define SIM_WSTOPSIG(V)		((V) & 0x7f)

#endif /* SIM_MAIN_H */
Commit	Line	Data
dc5c3759 MS	1	/* Main header for the Hitachi h8/300 architecture. */
dc5c3759 MS	2
a6ff997c	3	#include "config.h"
dc5c3759 MS	4	#include "bfd.h"
	5
	6	#ifndef SIM_MAIN_H
	7	#define SIM_MAIN_H
	8
	9	#define DEBUG
	10
	11	/* These define the size of main memory for the simulator.
	12
	13	Note the size of main memory for the H8/300H is only 256k. Keeping it
	14	small makes the simulator run much faster and consume less memory.
	15
	16	The linker knows about the limited size of the simulator's main memory
	17	on the H8/300H (via the h8300h.sc linker script). So if you change
	18	H8300H_MSIZE, be sure to fix the linker script too.
	19
	20	Also note that there's a separate "eightbit" area aside from main
	21	memory. For simplicity, the simulator assumes any data memory reference
	22	outside of main memory refers to the eightbit area (in theory, this
	23	can only happen when simulating H8/300H programs). We make no attempt
	24	to catch overlapping addresses, wrapped addresses, etc etc. */
	25
	26	#define H8300_MSIZE (1 << 16)
	27
	28	/* avolkov:
	29	Next 2 macros are ugly for any workstation, but while they're work.
	30	Memory size MUST be configurable. */
f5d3df96	31	#define H8300H_MSIZE (1 << 24)
dc5c3759 MS	32	#define H8300S_MSIZE (1 << 24)
	33
	34	#define CSIZE 1024
	35
	36	enum h8_regnum {
	37	R0_REGNUM = 0,
	38	R1_REGNUM = 1,
	39	R2_REGNUM = 2,
	40	R3_REGNUM = 3,
	41	R4_REGNUM = 4,
	42	R5_REGNUM = 5,
	43	R6_REGNUM = 6,
	44	R7_REGNUM = 7,
	45
	46	SP_REGNUM = R7_REGNUM, /* Contains address of top of stack */
	47	FP_REGNUM = R6_REGNUM, /* Contains address of executing
	48	stack frame */
	49	CCR_REGNUM = 8, /* Contains processor status */
	50	PC_REGNUM = 9, /* Contains program counter */
	51	CYCLE_REGNUM = 10,
	52	EXR_REGNUM = 11,
	53	INST_REGNUM = 12,
	54	TICK_REGNUM = 13,
18ad32b5 MS	55	MACH_REGNUM = 14,
	56	MACL_REGNUM = 15,
	57	SBR_REGNUM = 16,
	58	VBR_REGNUM = 17,
dc5c3759 MS	59
	60	ZERO_REGNUM = 18
	61	};
	62
	63	enum h8_typecodes {
	64	OP_NULL,
	65	OP_REG, /* Register direct. */
	66	OP_LOWREG, /* Special reg syntax for "bra". */
	67	OP_DISP, /* Register indirect w/displacement. */
	68	/* Note: h8300, h8300h, and h8300s permit only pre-decr and post-incr. */
	69	OP_PREDEC, /* Register indirect w/pre-decrement. */
	70	OP_POSTDEC, /* Register indirect w/post-decrement. */
	71	OP_PREINC, /* Register indirect w/pre-increment. */
	72	OP_POSTINC, /* Register indirect w/post-increment. */
	73	OP_PCREL, /* PC Relative. */
	74	OP_MEM, /* Absolute memory address. */
	75	OP_CCR, /* Condition Code Register. */
	76	OP_IMM, /* Immediate value. */
	77	/OP_ABS/ /* Un-used (duplicates op_mem?). */
	78	OP_EXR, /* EXtended control Register. */
	79	OP_SBR, /* Vector Base Register. */
	80	OP_VBR, /* Short-address Base Register. */
	81	OP_MACH, /* Multiply Accumulator - high. */
	82	OP_MACL, /* Multiply Accumulator - low. */
	83	/* FIXME: memory indirect? */
	84	OP_INDEXB, /* Byte index mode */
	85	OP_INDEXW, /* Word index mode */
	86	OP_INDEXL /* Long index mode */
	87	};
	88
	89	#include "sim-basics.h"
dc5c3759 MS	90	#include "sim-base.h"
	91
	92	/* Structure used to describe addressing */
	93
	94	typedef struct
	95	{
	96	int type;
	97	int reg;
	98	int literal;
	99	} ea_type;
	100
	101	/* Struct for instruction decoder. */
	102	typedef struct
	103	{
	104	ea_type src;
	105	ea_type dst;
	106	ea_type op3;
	107	int opcode;
	108	int next_pc;
	109	int oldpc;
	110	int cycles;
	111	#ifdef DEBUG
	112	struct h8_opcode *op;
	113	#endif
	114	} decoded_inst;
	115
	116	struct _sim_cpu {
	117	unsigned int regs[20]; /* 8 GR's plus ZERO, SBR, and VBR. */
	118	unsigned int pc;
	119
	120	int macS; /* MAC Saturating mode */
	121	int macV; /* MAC Overflow */
	122	int macN; /* MAC Negative */
	123	int macZ; /* MAC Zero */
	124
	125	int delayed_branch;
	126	char *command_line; / Pointer to command line arguments. */
	127
	128	unsigned char *memory;
	129	unsigned char *eightbit;
	130	int mask;
	131
	132	sim_cpu_base base;
	133	};
	134
	135	/* The sim_state struct. */
	136	struct sim_state {
f95f4ed2	137	sim_cpu *cpu[MAX_NR_PROCESSORS];
dc5c3759 MS	138	unsigned int sim_cache_size;
	139	decoded_inst *sim_cache;
	140	unsigned short *cache_idx;
	141	unsigned long memory_size;
	142	int cache_top;
	143	int compiles;
	144	#ifdef ADEBUG
	145	int stats[O_LAST];
	146	#endif
	147	sim_state_base base;
	148	};
	149
	150	/* The current state of the processor; registers, memory, etc. */
	151
dc5c3759 MS	152	#define cpu_set_pc(CPU, VAL) (((CPU)->pc) = (VAL))
	153	#define cpu_get_pc(CPU) (((CPU)->pc))
	154
	155	/* Magic numbers used to distinguish an exit from a breakpoint. */
	156	#define LIBC_EXIT_MAGIC1 0xdead
	157	#define LIBC_EXIT_MAGIC2 0xbeef
	158	/* Local version of macros for decoding exit status.
	159	(included here rather than try to find target version of wait.h)
	160	*/
f0861129 MS	161	#define SIM_WIFEXITED(V) (((V) & 0xff) == 0)
	162	#define SIM_WIFSTOPPED(V) (!SIM_WIFEXITED (V))
	163	#define SIM_WEXITSTATUS(V) (((V) >> 8) & 0xff)
	164	#define SIM_WSTOPSIG(V) ((V) & 0x7f)
dc5c3759 MS	165
dc5c3759 MS	166	#endif /* SIM_MAIN_H */