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7e927218 DE |
1 | /* collection of junk waiting time to sort out |
2 | Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. | |
3 | Contributed by Cygnus Support. | |
4 | ||
5 | This file is part of the GNU Simulators. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License along | |
18 | with this program; if not, write to the Free Software Foundation, Inc., | |
19 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #ifndef M32R_SIM_H | |
22 | #define M32R_SIM_H | |
23 | ||
24 | /* Register numbers used in gdb interface. */ | |
25 | #define PC_REGNUM 21 | |
26 | #define ACCL_REGNUM 22 | |
27 | #define ACCH_REGNUM 23 | |
28 | \f | |
29 | /* Misc. profile data. */ | |
30 | ||
31 | typedef struct { | |
32 | /* nop insn slot filler count */ | |
33 | unsigned int fillnop_count; | |
34 | /* number of parallel insns */ | |
35 | unsigned int parallel_count; | |
36 | /* number of short insns, not including parallel ones */ | |
37 | unsigned int short_count; | |
38 | /* number of long insns */ | |
39 | unsigned int long_count; | |
40 | } M32R_MISC_PROFILE; | |
41 | ||
42 | /* This is invoked by the nop pattern in the .cpu file. */ | |
43 | #define PROFILE_COUNT_FILLNOPS(cpu, addr) \ | |
44 | do { \ | |
45 | if (PROFILE_INSN_P (cpu) \ | |
46 | && (addr & 3) != 0) \ | |
47 | ++ CPU_M32R_MISC_PROFILE (cpu).fillnop_count; \ | |
48 | } while (0) | |
49 | ||
50 | /* This is invoked by the execute section of mloop{,x}.in. */ | |
51 | #define PROFILE_COUNT_PARINSNS(cpu) \ | |
52 | do { \ | |
53 | if (PROFILE_INSN_P (cpu)) \ | |
54 | ++ CPU_M32R_MISC_PROFILE (cpu).parallel_count; \ | |
55 | } while (0) | |
56 | ||
57 | /* This is invoked by the execute section of mloop{,x}.in. */ | |
58 | #define PROFILE_COUNT_SHORTINSNS(cpu) \ | |
59 | do { \ | |
60 | if (PROFILE_INSN_P (cpu)) \ | |
61 | ++ CPU_M32R_MISC_PROFILE (cpu).short_count; \ | |
62 | } while (0) | |
63 | ||
64 | /* This is invoked by the execute section of mloop{,x}.in. */ | |
65 | #define PROFILE_COUNT_LONGINSNS(cpu) \ | |
66 | do { \ | |
67 | if (PROFILE_INSN_P (cpu)) \ | |
68 | ++ CPU_M32R_MISC_PROFILE (cpu).long_count; \ | |
69 | } while (0) | |
70 | \f | |
71 | #define GETTWI GETTSI | |
72 | #define SETTWI SETTSI | |
73 | \f | |
74 | /* Additional execution support. */ | |
75 | ||
76 | /* Result of semantic function is one of | |
77 | - next address, branch only | |
78 | - NEW_PC_SKIP, sc/snc insn | |
79 | - NEW_PC_2, 2 byte non-branch non-sc/snc insn | |
80 | - NEW_PC_4, 4 byte non-branch insn | |
81 | The special values have bit 1 set so it's cheap to distinguish them. */ | |
82 | #define NEW_PC_BASE 0xffff0001 | |
83 | #define NEW_PC_SKIP NEW_PC_BASE | |
84 | #define NEW_PC_2 (NEW_PC_BASE + 2) | |
85 | #define NEW_PC_4 (NEW_PC_BASE + 4) | |
86 | #define NEW_PC_BRANCH_P(addr) (((addr) & 1) == 0) | |
87 | ||
88 | /* start-sanitize-m32rx */ | |
89 | /* Modify "next pc" handling to handle parallel execution. */ | |
90 | #ifdef WANT_CPU_M32RX | |
91 | #undef SEM_NEXT_PC | |
92 | #define SEM_NEXT_PC(abuf, len) (NEW_PC_BASE + (len)) | |
93 | #endif | |
94 | /* end-sanitize-m32rx */ | |
95 | ||
96 | /* This macro is emitted by the generator to record branch addresses. */ | |
97 | #define BRANCH_NEW_PC(var, addr) \ | |
98 | do { var = (addr); } while (0) | |
99 | \f | |
100 | /* Hardware/device support. */ | |
101 | ||
102 | /* Exception, Interrupt, and Trap addresses */ | |
103 | #define EIT_SYSBREAK_ADDR 0x10 | |
104 | #define EIT_RSVD_INSN_ADDR 0x20 | |
105 | #define EIT_ADDR_EXCP_ADDR 0x30 | |
106 | #define EIT_TRAP_BASE_ADDR 0x40 | |
107 | #define EIT_EXTERN_ADDR 0x80 | |
108 | #define EIT_RESET_ADDR 0x7ffffff0 | |
109 | #define EIT_WAKEUP_ADDR 0x7ffffff0 | |
110 | ||
111 | /* Special purpose traps. */ | |
112 | #define TRAP_SYSCALL 0 | |
113 | #define TRAP_BREAKPOINT 1 | |
114 | ||
115 | /* Support for the MSPR register (Cache Purge Control Register) | |
116 | and the MCCR register (Cache Control Register) are needed in order for | |
117 | overlays to work correctly with the scache. | |
118 | MSPR no longer exists but is supported for upward compatibility with | |
119 | early overlay support. */ | |
120 | ||
121 | /* Cache Purge Control (only exists on early versions of chips) */ | |
122 | #define MSPR_ADDR 0xfffffff7 | |
123 | #define MSPR_PURGE 1 | |
124 | ||
125 | /* Lock Control Register (not supported) */ | |
126 | #define MLCR_ADDR 0xfffffff7 | |
127 | #define MLCR_LM 1 | |
128 | ||
129 | /* Power Management Control Register (not supported) */ | |
130 | #define MPMR_ADDR 0xfffffffb | |
131 | ||
132 | /* Cache Control Register */ | |
133 | #define MCCR_ADDR 0xffffffff | |
134 | #define MCCR_CP 0x80 | |
135 | /* not supported */ | |
136 | #define MCCR_CM0 2 | |
137 | #define MCCR_CM1 1 | |
138 | ||
139 | /* Serial device addresses. */ | |
140 | #define UART_INCHAR_ADDR 0xff102013 | |
141 | #define UART_OUTCHAR_ADDR 0xff10200f | |
142 | #define UART_STATUS_ADDR 0xff102006 | |
143 | #define UART_INPUT_EMPTY 0x4 | |
144 | #define UART_OUTPUT_EMPTY 0x1 | |
145 | ||
146 | /* Start address and length of all device support. */ | |
147 | #define M32R_DEVICE_ADDR 0xff000000 | |
148 | #define M32R_DEVICE_LEN 0x00ffffff | |
149 | ||
150 | /* sim_core_attach device argument. */ | |
151 | extern device m32r_devices; | |
152 | ||
153 | /* FIXME: Temporary, until device support ready. */ | |
154 | struct _device { int foo; }; | |
155 | ||
83e4ce8d DE |
156 | /* Handle the trap insn. */ |
157 | USI m32r_trap (SIM_CPU *, int); | |
158 | ||
7e927218 | 159 | #endif /* M32R_SIM_H */ |