Commit | Line | Data |
---|---|---|
5abb9efa | 1 | /* interp.c -- Simulator for Motorola 68HC11/68HC12 |
88b9d363 | 2 | Copyright (C) 1999-2022 Free Software Foundation, Inc. |
63f36def | 3 | Written by Stephane Carrez (stcarrez@nerim.fr) |
e0709f50 AC |
4 | |
5 | This file is part of GDB, the GNU debugger. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
4744ac1b JB |
9 | the Free Software Foundation; either version 3 of the License, or |
10 | (at your option) any later version. | |
e0709f50 AC |
11 | |
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
4744ac1b JB |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
e0709f50 | 19 | |
6df01ab8 MF |
20 | /* This must come before any other includes. */ |
21 | #include "defs.h" | |
22 | ||
e0709f50 AC |
23 | #include "sim-main.h" |
24 | #include "sim-assert.h" | |
25 | #include "sim-hw.h" | |
26 | #include "sim-options.h" | |
27 | #include "hw-tree.h" | |
28 | #include "hw-device.h" | |
29 | #include "hw-ports.h" | |
77342e5e | 30 | #include "elf32-m68hc1x.h" |
e0709f50 AC |
31 | |
32 | #ifndef MONITOR_BASE | |
33 | # define MONITOR_BASE (0x0C000) | |
34 | # define MONITOR_SIZE (0x04000) | |
35 | #endif | |
36 | ||
37 | static void sim_get_info (SIM_DESC sd, char *cmd); | |
38 | ||
e0709f50 AC |
39 | struct sim_info_list |
40 | { | |
41 | const char *name; | |
42 | const char *device; | |
43 | }; | |
44 | ||
81e09ed8 | 45 | struct sim_info_list dev_list_68hc11[] = { |
e0709f50 AC |
46 | {"cpu", "/m68hc11"}, |
47 | {"timer", "/m68hc11/m68hc11tim"}, | |
48 | {"sio", "/m68hc11/m68hc11sio"}, | |
49 | {"spi", "/m68hc11/m68hc11spi"}, | |
50 | {"eeprom", "/m68hc11/m68hc11eepr"}, | |
51 | {0, 0} | |
52 | }; | |
53 | ||
81e09ed8 SC |
54 | struct sim_info_list dev_list_68hc12[] = { |
55 | {"cpu", "/m68hc12"}, | |
56 | {"timer", "/m68hc12/m68hc12tim"}, | |
57 | {"sio", "/m68hc12/m68hc12sio"}, | |
58 | {"spi", "/m68hc12/m68hc12spi"}, | |
59 | {"eeprom", "/m68hc12/m68hc12eepr"}, | |
60 | {0, 0} | |
61 | }; | |
62 | ||
63 | /* Cover function of sim_state_free to free the cpu buffers as well. */ | |
64 | ||
65 | static void | |
66 | free_state (SIM_DESC sd) | |
67 | { | |
68 | if (STATE_MODULES (sd) != NULL) | |
69 | sim_module_uninstall (sd); | |
70 | ||
71 | sim_state_free (sd); | |
72 | } | |
73 | ||
e0709f50 AC |
74 | /* Give some information about the simulator. */ |
75 | static void | |
76 | sim_get_info (SIM_DESC sd, char *cmd) | |
77 | { | |
78 | sim_cpu *cpu; | |
79 | ||
81e09ed8 | 80 | cpu = STATE_CPU (sd, 0); |
e0709f50 AC |
81 | if (cmd != 0 && (cmd[0] == ' ' || cmd[0] == '-')) |
82 | { | |
83 | int i; | |
84 | struct hw *hw_dev; | |
81e09ed8 SC |
85 | struct sim_info_list *dev_list; |
86 | const struct bfd_arch_info *arch; | |
87 | ||
88 | arch = STATE_ARCHITECTURE (sd); | |
e0709f50 AC |
89 | cmd++; |
90 | ||
81e09ed8 SC |
91 | if (arch->arch == bfd_arch_m68hc11) |
92 | dev_list = dev_list_68hc11; | |
93 | else | |
94 | dev_list = dev_list_68hc12; | |
95 | ||
e0709f50 AC |
96 | for (i = 0; dev_list[i].name; i++) |
97 | if (strcmp (cmd, dev_list[i].name) == 0) | |
98 | break; | |
99 | ||
100 | if (dev_list[i].name == 0) | |
101 | { | |
102 | sim_io_eprintf (sd, "Device '%s' not found.\n", cmd); | |
103 | sim_io_eprintf (sd, "Valid devices: cpu timer sio eeprom\n"); | |
104 | return; | |
105 | } | |
fb8d4e59 | 106 | hw_dev = sim_hw_parse (sd, "%s", dev_list[i].device); |
e0709f50 AC |
107 | if (hw_dev == 0) |
108 | { | |
109 | sim_io_eprintf (sd, "Device '%s' not found\n", dev_list[i].device); | |
110 | return; | |
111 | } | |
112 | hw_ioctl (hw_dev, 23, 0); | |
113 | return; | |
114 | } | |
115 | ||
e0709f50 AC |
116 | cpu_info (sd, cpu); |
117 | interrupts_info (sd, &cpu->cpu_interrupts); | |
118 | } | |
119 | ||
120 | ||
121 | void | |
122 | sim_board_reset (SIM_DESC sd) | |
123 | { | |
124 | struct hw *hw_cpu; | |
125 | sim_cpu *cpu; | |
81e09ed8 SC |
126 | const struct bfd_arch_info *arch; |
127 | const char *cpu_type; | |
e0709f50 AC |
128 | |
129 | cpu = STATE_CPU (sd, 0); | |
81e09ed8 SC |
130 | arch = STATE_ARCHITECTURE (sd); |
131 | ||
e0709f50 | 132 | /* hw_cpu = sim_hw_parse (sd, "/"); */ |
81e09ed8 SC |
133 | if (arch->arch == bfd_arch_m68hc11) |
134 | { | |
135 | cpu->cpu_type = CPU_M6811; | |
136 | cpu_type = "/m68hc11"; | |
137 | } | |
138 | else | |
139 | { | |
140 | cpu->cpu_type = CPU_M6812; | |
141 | cpu_type = "/m68hc12"; | |
142 | } | |
143 | ||
fb8d4e59 | 144 | hw_cpu = sim_hw_parse (sd, "%s", cpu_type); |
e0709f50 AC |
145 | if (hw_cpu == 0) |
146 | { | |
81e09ed8 | 147 | sim_io_eprintf (sd, "%s cpu not found in device tree.", cpu_type); |
e0709f50 AC |
148 | return; |
149 | } | |
150 | ||
151 | cpu_reset (cpu); | |
152 | hw_port_event (hw_cpu, 3, 0); | |
153 | cpu_restart (cpu); | |
154 | } | |
155 | ||
39762100 | 156 | static int |
81e09ed8 SC |
157 | sim_hw_configure (SIM_DESC sd) |
158 | { | |
159 | const struct bfd_arch_info *arch; | |
160 | struct hw *device_tree; | |
81e09ed8 SC |
161 | sim_cpu *cpu; |
162 | ||
163 | arch = STATE_ARCHITECTURE (sd); | |
164 | if (arch == 0) | |
165 | return 0; | |
166 | ||
167 | cpu = STATE_CPU (sd, 0); | |
168 | cpu->cpu_configured_arch = arch; | |
169 | device_tree = sim_hw_parse (sd, "/"); | |
170 | if (arch->arch == bfd_arch_m68hc11) | |
171 | { | |
172 | cpu->cpu_interpretor = cpu_interp_m6811; | |
173 | if (hw_tree_find_property (device_tree, "/m68hc11/reg") == 0) | |
174 | { | |
175 | /* Allocate core managed memory */ | |
176 | ||
177 | /* the monitor */ | |
8e78e9b9 | 178 | sim_do_commandf (sd, "memory region 0x%x@%d,0x%x", |
81e09ed8 SC |
179 | /* MONITOR_BASE, MONITOR_SIZE */ |
180 | 0x8000, M6811_RAM_LEVEL, 0x8000); | |
181 | sim_do_commandf (sd, "memory region 0x000@%d,0x8000", | |
182 | M6811_RAM_LEVEL); | |
183 | sim_hw_parse (sd, "/m68hc11/reg 0x1000 0x03F"); | |
77342e5e SC |
184 | if (cpu->bank_start < cpu->bank_end) |
185 | { | |
8e78e9b9 | 186 | sim_do_commandf (sd, "memory region 0x%x@%d,0x100000", |
77342e5e SC |
187 | cpu->bank_virtual, M6811_RAM_LEVEL); |
188 | sim_hw_parse (sd, "/m68hc11/use_bank 1"); | |
189 | } | |
81e09ed8 | 190 | } |
77342e5e SC |
191 | if (cpu->cpu_start_mode) |
192 | { | |
193 | sim_hw_parse (sd, "/m68hc11/mode %s", cpu->cpu_start_mode); | |
194 | } | |
81e09ed8 SC |
195 | if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11sio/reg") == 0) |
196 | { | |
197 | sim_hw_parse (sd, "/m68hc11/m68hc11sio/reg 0x2b 0x5"); | |
198 | sim_hw_parse (sd, "/m68hc11/m68hc11sio/backend stdio"); | |
199 | sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11sio"); | |
200 | } | |
201 | if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11tim/reg") == 0) | |
202 | { | |
203 | /* M68hc11 Timer configuration. */ | |
204 | sim_hw_parse (sd, "/m68hc11/m68hc11tim/reg 0x1b 0x5"); | |
205 | sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11tim"); | |
827ec39a | 206 | sim_hw_parse (sd, "/m68hc11 > capture capture /m68hc11/m68hc11tim"); |
81e09ed8 SC |
207 | } |
208 | ||
209 | /* Create the SPI device. */ | |
210 | if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11spi/reg") == 0) | |
211 | { | |
212 | sim_hw_parse (sd, "/m68hc11/m68hc11spi/reg 0x28 0x3"); | |
213 | sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11spi"); | |
214 | } | |
215 | if (hw_tree_find_property (device_tree, "/m68hc11/nvram/reg") == 0) | |
216 | { | |
217 | /* M68hc11 persistent ram configuration. */ | |
218 | sim_hw_parse (sd, "/m68hc11/nvram/reg 0x0 256"); | |
219 | sim_hw_parse (sd, "/m68hc11/nvram/file m68hc11.ram"); | |
220 | sim_hw_parse (sd, "/m68hc11/nvram/mode save-modified"); | |
221 | /*sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/pram"); */ | |
222 | } | |
223 | if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11eepr/reg") == 0) | |
224 | { | |
225 | sim_hw_parse (sd, "/m68hc11/m68hc11eepr/reg 0xb000 512"); | |
226 | sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11eepr"); | |
227 | } | |
dcceded2 SC |
228 | sim_hw_parse (sd, "/m68hc11 > port-a cpu-write-port /m68hc11"); |
229 | sim_hw_parse (sd, "/m68hc11 > port-b cpu-write-port /m68hc11"); | |
230 | sim_hw_parse (sd, "/m68hc11 > port-c cpu-write-port /m68hc11"); | |
231 | sim_hw_parse (sd, "/m68hc11 > port-d cpu-write-port /m68hc11"); | |
827ec39a | 232 | cpu->hw_cpu = sim_hw_parse (sd, "/m68hc11"); |
81e09ed8 SC |
233 | } |
234 | else | |
235 | { | |
236 | cpu->cpu_interpretor = cpu_interp_m6812; | |
237 | if (hw_tree_find_property (device_tree, "/m68hc12/reg") == 0) | |
238 | { | |
239 | /* Allocate core external memory. */ | |
8e78e9b9 | 240 | sim_do_commandf (sd, "memory region 0x%x@%d,0x%x", |
77342e5e | 241 | 0x8000, M6811_RAM_LEVEL, 0x8000); |
81e09ed8 SC |
242 | sim_do_commandf (sd, "memory region 0x000@%d,0x8000", |
243 | M6811_RAM_LEVEL); | |
77342e5e SC |
244 | if (cpu->bank_start < cpu->bank_end) |
245 | { | |
8e78e9b9 | 246 | sim_do_commandf (sd, "memory region 0x%x@%d,0x100000", |
77342e5e SC |
247 | cpu->bank_virtual, M6811_RAM_LEVEL); |
248 | sim_hw_parse (sd, "/m68hc12/use_bank 1"); | |
249 | } | |
81e09ed8 SC |
250 | sim_hw_parse (sd, "/m68hc12/reg 0x0 0x3FF"); |
251 | } | |
252 | ||
253 | if (!hw_tree_find_property (device_tree, "/m68hc12/m68hc12sio@1/reg")) | |
254 | { | |
255 | sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/reg 0xC0 0x8"); | |
256 | sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/backend stdio"); | |
257 | sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12sio@1"); | |
258 | } | |
81e09ed8 SC |
259 | if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12tim/reg") == 0) |
260 | { | |
261 | /* M68hc11 Timer configuration. */ | |
262 | sim_hw_parse (sd, "/m68hc12/m68hc12tim/reg 0x1b 0x5"); | |
263 | sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12tim"); | |
dcceded2 | 264 | sim_hw_parse (sd, "/m68hc12 > capture capture /m68hc12/m68hc12tim"); |
81e09ed8 SC |
265 | } |
266 | ||
267 | /* Create the SPI device. */ | |
268 | if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12spi/reg") == 0) | |
269 | { | |
270 | sim_hw_parse (sd, "/m68hc12/m68hc12spi/reg 0x28 0x3"); | |
271 | sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12spi"); | |
272 | } | |
273 | if (hw_tree_find_property (device_tree, "/m68hc12/nvram/reg") == 0) | |
274 | { | |
275 | /* M68hc11 persistent ram configuration. */ | |
276 | sim_hw_parse (sd, "/m68hc12/nvram/reg 0x2000 8192"); | |
277 | sim_hw_parse (sd, "/m68hc12/nvram/file m68hc12.ram"); | |
278 | sim_hw_parse (sd, "/m68hc12/nvram/mode save-modified"); | |
279 | } | |
280 | if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12eepr/reg") == 0) | |
281 | { | |
282 | sim_hw_parse (sd, "/m68hc12/m68hc12eepr/reg 0x0800 2048"); | |
283 | sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12eepr"); | |
284 | } | |
827ec39a | 285 | |
dcceded2 SC |
286 | sim_hw_parse (sd, "/m68hc12 > port-a cpu-write-port /m68hc12"); |
287 | sim_hw_parse (sd, "/m68hc12 > port-b cpu-write-port /m68hc12"); | |
288 | sim_hw_parse (sd, "/m68hc12 > port-c cpu-write-port /m68hc12"); | |
289 | sim_hw_parse (sd, "/m68hc12 > port-d cpu-write-port /m68hc12"); | |
827ec39a | 290 | cpu->hw_cpu = sim_hw_parse (sd, "/m68hc12"); |
81e09ed8 | 291 | } |
39762100 | 292 | return 1; |
81e09ed8 SC |
293 | } |
294 | ||
77342e5e SC |
295 | /* Get the memory bank parameters by looking at the global symbols |
296 | defined by the linker. */ | |
81e09ed8 | 297 | static int |
5357150c | 298 | sim_get_bank_parameters (SIM_DESC sd) |
81e09ed8 SC |
299 | { |
300 | sim_cpu *cpu; | |
77342e5e | 301 | unsigned size; |
5357150c | 302 | bfd_vma addr; |
81e09ed8 SC |
303 | |
304 | cpu = STATE_CPU (sd, 0); | |
305 | ||
5357150c MF |
306 | addr = trace_sym_value (sd, BFD_M68HC11_BANK_START_NAME); |
307 | if (addr != -1) | |
308 | cpu->bank_start = addr; | |
77342e5e | 309 | |
5357150c MF |
310 | size = trace_sym_value (sd, BFD_M68HC11_BANK_SIZE_NAME); |
311 | if (size == -1) | |
312 | size = 0; | |
77342e5e | 313 | |
5357150c MF |
314 | addr = trace_sym_value (sd, BFD_M68HC11_BANK_VIRTUAL_NAME); |
315 | if (addr != -1) | |
316 | cpu->bank_virtual = addr; | |
77342e5e SC |
317 | |
318 | cpu->bank_end = cpu->bank_start + size; | |
319 | cpu->bank_shift = 0; | |
320 | for (; size > 1; size >>= 1) | |
321 | cpu->bank_shift++; | |
322 | ||
323 | return 0; | |
324 | } | |
325 | ||
326 | static int | |
327 | sim_prepare_for_program (SIM_DESC sd, bfd* abfd) | |
328 | { | |
329 | sim_cpu *cpu; | |
330 | int elf_flags = 0; | |
331 | ||
332 | cpu = STATE_CPU (sd, 0); | |
39762100 | 333 | |
81e09ed8 SC |
334 | if (abfd != NULL) |
335 | { | |
31c7c532 | 336 | asection *s; |
77342e5e SC |
337 | |
338 | if (bfd_get_flavour (abfd) == bfd_target_elf_flavour) | |
339 | elf_flags = elf_elfheader (abfd)->e_flags; | |
340 | ||
81e09ed8 | 341 | cpu->cpu_elf_start = bfd_get_start_address (abfd); |
31c7c532 SC |
342 | /* See if any section sets the reset address */ |
343 | cpu->cpu_use_elf_start = 1; | |
344 | for (s = abfd->sections; s && cpu->cpu_use_elf_start; s = s->next) | |
345 | { | |
346 | if (s->flags & SEC_LOAD) | |
347 | { | |
348 | bfd_size_type size; | |
349 | ||
fd361982 | 350 | size = bfd_section_size (s); |
31c7c532 SC |
351 | if (size > 0) |
352 | { | |
353 | bfd_vma lma; | |
354 | ||
355 | if (STATE_LOAD_AT_LMA_P (sd)) | |
fd361982 | 356 | lma = bfd_section_lma (s); |
31c7c532 | 357 | else |
fd361982 | 358 | lma = bfd_section_vma (s); |
31c7c532 SC |
359 | |
360 | if (lma <= 0xFFFE && lma+size >= 0x10000) | |
361 | cpu->cpu_use_elf_start = 0; | |
362 | } | |
363 | } | |
364 | } | |
77342e5e SC |
365 | |
366 | if (elf_flags & E_M68HC12_BANKS) | |
367 | { | |
5357150c | 368 | if (sim_get_bank_parameters (sd) != 0) |
77342e5e SC |
369 | sim_io_eprintf (sd, "Memory bank parameters are not initialized\n"); |
370 | } | |
81e09ed8 SC |
371 | } |
372 | ||
77342e5e SC |
373 | if (!sim_hw_configure (sd)) |
374 | return SIM_RC_FAIL; | |
375 | ||
81e09ed8 SC |
376 | /* reset all state information */ |
377 | sim_board_reset (sd); | |
378 | ||
379 | return SIM_RC_OK; | |
380 | } | |
381 | ||
bea3f671 MF |
382 | static sim_cia |
383 | m68hc11_pc_get (sim_cpu *cpu) | |
384 | { | |
385 | return cpu_get_pc (cpu); | |
386 | } | |
387 | ||
388 | static void | |
389 | m68hc11_pc_set (sim_cpu *cpu, sim_cia pc) | |
390 | { | |
391 | cpu_set_pc (cpu, pc); | |
392 | } | |
393 | ||
e1211e55 MF |
394 | static int m68hc11_reg_fetch (SIM_CPU *, int, unsigned char *, int); |
395 | static int m68hc11_reg_store (SIM_CPU *, int, unsigned char *, int); | |
396 | ||
e0709f50 AC |
397 | SIM_DESC |
398 | sim_open (SIM_OPEN_KIND kind, host_callback *callback, | |
2e3d4f4d | 399 | bfd *abfd, char * const *argv) |
e0709f50 | 400 | { |
bea3f671 | 401 | int i; |
e0709f50 AC |
402 | SIM_DESC sd; |
403 | sim_cpu *cpu; | |
e0709f50 AC |
404 | |
405 | sd = sim_state_alloc (kind, callback); | |
e0709f50 AC |
406 | |
407 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); | |
408 | ||
f9a4d543 MF |
409 | /* Set default options before parsing user options. */ |
410 | current_target_byte_order = BFD_ENDIAN_BIG; | |
411 | ||
bea3f671 | 412 | /* The cpu data is kept in a separately allocated chunk of memory. */ |
d5a71b11 | 413 | if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK) |
bea3f671 MF |
414 | { |
415 | free_state (sd); | |
416 | return 0; | |
417 | } | |
418 | ||
419 | cpu = STATE_CPU (sd, 0); | |
420 | ||
e0709f50 AC |
421 | cpu_initialize (sd, cpu); |
422 | ||
e0709f50 | 423 | if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) |
81e09ed8 SC |
424 | { |
425 | free_state (sd); | |
426 | return 0; | |
427 | } | |
e0709f50 | 428 | |
77cf2ef5 | 429 | /* The parser will print an error message for us, so we silently return. */ |
e0709f50 AC |
430 | if (sim_parse_args (sd, argv) != SIM_RC_OK) |
431 | { | |
432 | /* Uninstall the modules to avoid memory leaks, | |
433 | file descriptor leaks, etc. */ | |
81e09ed8 | 434 | free_state (sd); |
e0709f50 AC |
435 | return 0; |
436 | } | |
437 | ||
e0709f50 AC |
438 | /* Check for/establish the a reference program image. */ |
439 | if (sim_analyze_program (sd, | |
440 | (STATE_PROG_ARGV (sd) != NULL | |
441 | ? *STATE_PROG_ARGV (sd) | |
442 | : NULL), abfd) != SIM_RC_OK) | |
443 | { | |
81e09ed8 | 444 | free_state (sd); |
e0709f50 AC |
445 | return 0; |
446 | } | |
447 | ||
448 | /* Establish any remaining configuration options. */ | |
449 | if (sim_config (sd) != SIM_RC_OK) | |
450 | { | |
81e09ed8 | 451 | free_state (sd); |
e0709f50 AC |
452 | return 0; |
453 | } | |
454 | ||
455 | if (sim_post_argv_init (sd) != SIM_RC_OK) | |
456 | { | |
457 | /* Uninstall the modules to avoid memory leaks, | |
458 | file descriptor leaks, etc. */ | |
81e09ed8 | 459 | free_state (sd); |
e0709f50 AC |
460 | return 0; |
461 | } | |
77342e5e SC |
462 | if (sim_prepare_for_program (sd, abfd) != SIM_RC_OK) |
463 | { | |
464 | free_state (sd); | |
465 | return 0; | |
466 | } | |
e0709f50 | 467 | |
bea3f671 MF |
468 | /* CPU specific initialization. */ |
469 | for (i = 0; i < MAX_NR_PROCESSORS; ++i) | |
470 | { | |
471 | SIM_CPU *cpu = STATE_CPU (sd, i); | |
472 | ||
e1211e55 MF |
473 | CPU_REG_FETCH (cpu) = m68hc11_reg_fetch; |
474 | CPU_REG_STORE (cpu) = m68hc11_reg_store; | |
bea3f671 MF |
475 | CPU_PC_FETCH (cpu) = m68hc11_pc_get; |
476 | CPU_PC_STORE (cpu) = m68hc11_pc_set; | |
477 | } | |
478 | ||
e0709f50 AC |
479 | return sd; |
480 | } | |
481 | ||
e0709f50 AC |
482 | /* Generic implementation of sim_engine_run that works within the |
483 | sim_engine setjmp/longjmp framework. */ | |
484 | ||
485 | void | |
486 | sim_engine_run (SIM_DESC sd, | |
487 | int next_cpu_nr, /* ignore */ | |
488 | int nr_cpus, /* ignore */ | |
489 | int siggnal) /* ignore */ | |
490 | { | |
491 | sim_cpu *cpu; | |
492 | ||
493 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); | |
494 | cpu = STATE_CPU (sd, 0); | |
495 | while (1) | |
496 | { | |
497 | cpu_single_step (cpu); | |
498 | ||
499 | /* process any events */ | |
500 | if (sim_events_tickn (sd, cpu->cpu_current_cycle)) | |
501 | { | |
502 | sim_events_process (sd); | |
503 | } | |
504 | } | |
505 | } | |
506 | ||
e0709f50 AC |
507 | void |
508 | sim_info (SIM_DESC sd, int verbose) | |
509 | { | |
81e09ed8 SC |
510 | const char *cpu_type; |
511 | const struct bfd_arch_info *arch; | |
512 | ||
00d0c012 SC |
513 | /* Nothing to do if there is no verbose flag set. */ |
514 | if (verbose == 0 && STATE_VERBOSE_P (sd) == 0) | |
515 | return; | |
516 | ||
81e09ed8 SC |
517 | arch = STATE_ARCHITECTURE (sd); |
518 | if (arch->arch == bfd_arch_m68hc11) | |
519 | cpu_type = "68HC11"; | |
520 | else | |
521 | cpu_type = "68HC12"; | |
522 | ||
e0709f50 | 523 | sim_io_eprintf (sd, "Simulator info:\n"); |
81e09ed8 | 524 | sim_io_eprintf (sd, " CPU Motorola %s\n", cpu_type); |
e0709f50 AC |
525 | sim_get_info (sd, 0); |
526 | sim_module_info (sd, verbose || STATE_VERBOSE_P (sd)); | |
527 | } | |
528 | ||
529 | SIM_RC | |
6b4a8935 | 530 | sim_create_inferior (SIM_DESC sd, struct bfd *abfd, |
2e3d4f4d | 531 | char * const *argv, char * const *env) |
e0709f50 | 532 | { |
81e09ed8 | 533 | return sim_prepare_for_program (sd, abfd); |
e0709f50 AC |
534 | } |
535 | ||
e1211e55 MF |
536 | static int |
537 | m68hc11_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) | |
e0709f50 | 538 | { |
e0709f50 | 539 | uint16 val; |
63f36def | 540 | int size = 2; |
e0709f50 | 541 | |
e0709f50 AC |
542 | switch (rn) |
543 | { | |
544 | case A_REGNUM: | |
545 | val = cpu_get_a (cpu); | |
63f36def | 546 | size = 1; |
e0709f50 AC |
547 | break; |
548 | ||
549 | case B_REGNUM: | |
550 | val = cpu_get_b (cpu); | |
63f36def | 551 | size = 1; |
e0709f50 AC |
552 | break; |
553 | ||
554 | case D_REGNUM: | |
555 | val = cpu_get_d (cpu); | |
556 | break; | |
557 | ||
558 | case X_REGNUM: | |
559 | val = cpu_get_x (cpu); | |
560 | break; | |
561 | ||
562 | case Y_REGNUM: | |
563 | val = cpu_get_y (cpu); | |
564 | break; | |
565 | ||
566 | case SP_REGNUM: | |
567 | val = cpu_get_sp (cpu); | |
568 | break; | |
569 | ||
570 | case PC_REGNUM: | |
571 | val = cpu_get_pc (cpu); | |
572 | break; | |
573 | ||
574 | case PSW_REGNUM: | |
575 | val = cpu_get_ccr (cpu); | |
63f36def SC |
576 | size = 1; |
577 | break; | |
578 | ||
579 | case PAGE_REGNUM: | |
580 | val = cpu_get_page (cpu); | |
581 | size = 1; | |
e0709f50 AC |
582 | break; |
583 | ||
e0709f50 | 584 | default: |
9830501b | 585 | val = 0; |
e0709f50 AC |
586 | break; |
587 | } | |
00416c6e SC |
588 | if (size == 1) |
589 | { | |
590 | memory[0] = val; | |
591 | } | |
592 | else | |
593 | { | |
594 | memory[0] = val >> 8; | |
595 | memory[1] = val & 0x0FF; | |
596 | } | |
63f36def | 597 | return size; |
e0709f50 AC |
598 | } |
599 | ||
e1211e55 MF |
600 | static int |
601 | m68hc11_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length) | |
e0709f50 AC |
602 | { |
603 | uint16 val; | |
e0709f50 AC |
604 | |
605 | val = *memory++; | |
606 | if (length == 2) | |
607 | val = (val << 8) | *memory; | |
608 | ||
609 | switch (rn) | |
610 | { | |
611 | case D_REGNUM: | |
612 | cpu_set_d (cpu, val); | |
613 | break; | |
614 | ||
615 | case A_REGNUM: | |
616 | cpu_set_a (cpu, val); | |
63f36def | 617 | return 1; |
e0709f50 AC |
618 | |
619 | case B_REGNUM: | |
620 | cpu_set_b (cpu, val); | |
63f36def | 621 | return 1; |
e0709f50 AC |
622 | |
623 | case X_REGNUM: | |
624 | cpu_set_x (cpu, val); | |
625 | break; | |
626 | ||
627 | case Y_REGNUM: | |
628 | cpu_set_y (cpu, val); | |
629 | break; | |
630 | ||
631 | case SP_REGNUM: | |
632 | cpu_set_sp (cpu, val); | |
633 | break; | |
634 | ||
635 | case PC_REGNUM: | |
636 | cpu_set_pc (cpu, val); | |
637 | break; | |
638 | ||
639 | case PSW_REGNUM: | |
640 | cpu_set_ccr (cpu, val); | |
63f36def SC |
641 | return 1; |
642 | ||
643 | case PAGE_REGNUM: | |
644 | cpu_set_page (cpu, val); | |
645 | return 1; | |
e0709f50 | 646 | |
e0709f50 | 647 | default: |
e0709f50 AC |
648 | break; |
649 | } | |
650 | ||
651 | return 2; | |
652 | } |