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sim: mips: rework dynamic printf logic to avoid compiler warnings
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
6828a302
MF		 12021-06-16 Mike Frysinger <vapier@gentoo.org>
2
3 * interp.c (sim_monitor): Change ap type to address_word*.
4 (_P, P): New macros. Rewrite dynamic printf logic to use these.
5
df32b446
MF		 62021-06-16 Mike Frysinger <vapier@gentoo.org>
7
8 * dv-tx3904sio.c (tx3904sio_fifo_push): Change next_buf to
9 unsigned_1.
10
7b2298cb
MF		 112021-06-16 Mike Frysinger <vapier@gentoo.org>
12
13 * dv-tx3904irc.c (tx3904irc_io_write_buffer): Initialize
14 register_value to 0.
15
a8a3d907
MF		 162021-06-16 Mike Frysinger <vapier@gentoo.org>
17
18 * configure: Regenerate.
19
dae666c9
MF		 202021-06-16 Mike Frysinger <vapier@gentoo.org>
21
22 * interp.c (sim_open): Change %lx to %x and PRIx macros.
23
52d37d2c
MF		 242021-06-16 Mike Frysinger <vapier@gentoo.org>
25
26 * configure: Regenerate.
27 * config.in: Removed.
28
bcaa61f7
MF		 292021-06-15 Mike Frysinger <vapier@gentoo.org>
30
31 * config.in, configure: Regenerate.
32
ba307cdd
MF		 332021-06-12 Mike Frysinger <vapier@gentoo.org>
34
35 * configure.ac: Delete call to SIM_AC_OPTION_ALIGNMENT.
36
dba333c1
MF		 372021-06-12 Mike Frysinger <vapier@gentoo.org>
38
39 * aclocal.m4, config.in, configure: Regenerate.
40
b15c5d7a
MF		 412021-06-12 Mike Frysinger <vapier@gentoo.org>
42
43 * configure.ac: Delete call to AC_CHECK_FUNCS.
44 * config.in, configure: Regenerate.
45
a55b92be
MF		 462021-06-08 Mike Frysinger <vapier@gentoo.org>
47
48 * Makefile.in: Replace $(IGEN) with $(IGEN_RUN) and ../igen/igen
49 with $(IGEN).
50
8ea881d9
MF		 512021-05-29 Mike Frysinger <vapier@gentoo.org>
52
53 * interp.c [!HAVE_DV_SOCKSER] (sockser_addr): Define to NULL.
54
b312488f
FS		 552021-05-22 Faraz Shahbazker <fshahbazker@wavecomp.com>
56
168671c1
FS		 57 * interp.c (sim_open): Add shadow mappings from 32-bit
58 address space to 64-bit sign-extended address space.
59
602021-05-22 Faraz Shahbazker <fshahbazker@wavecomp.com>
61
b312488f
FS		 62 * interp.c (sim_create_inferior): Only truncate sign extension
63 bits for 32-bit target models.
64
f4fdd845
MF		 652021-05-17 Mike Frysinger <vapier@gentoo.org>
66
67 * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Delete.
68
8ea7241c
MF		 692021-05-17 Mike Frysinger <vapier@gentoo.org>
70
71 * interp.c (sim_open): Switch to sim_state_alloc_extra.
72 * micromips.igen: Change SD to mips_sim_state.
73 * micromipsrun.c (sim_engine_run): Likewise.
74 * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Define.
75 (watch_options_install): Delete.
76 (struct swatch): Delete.
77 (struct sim_state): Delete.
78 (struct mips_sim_state): New struct.
79 (MIPS_SIM_STATE): Define.
80
6df01ab8
MF		 812021-05-16 Mike Frysinger <vapier@gentoo.org>
82
83 * interp.c: Replace config.h include with defs.h.
84 * cp1.c, dsp.c, dv-tx3904cpu.c, dv-tx3904irc.c, dv-tx3904sio.c,
85 dv-tx3904tmr.c, m16run.c, mdmx.c, micromipsrun.c, sim-main.c:
86 Include defs.h.
87
79633c12
MF		 882021-05-16 Mike Frysinger <vapier@gentoo.org>
89
90 * config.in, configure: Regenerate.
91
df68e12b
MF		 922021-05-14 Mike Frysinger <vapier@gentoo.org>
93
94 * interp.c: Update include path.
95
77c0fdb7
MF		 962021-05-04 Mike Frysinger <vapier@gentoo.org>
97
98 * dv-tx3904sio.c: Include stdlib.h.
99
9b1af85c
MF		 1002021-05-04 Mike Frysinger <vapier@gentoo.org>
101
102 * configure.ac (hw_extra_devices): Inline contents into
103 SIM_AC_OPTION_HARDWARE and delete.
104 * configure: Regenerate.
105
d97ba9c6
MF		 1062021-05-04 Mike Frysinger <vapier@gentoo.org>
107
108 * Makefile.in (SIM_IGEN_OBJ): Change @mips_igen_engine@ to engine.o.
109 (MIPS_EXTRA_LIB, SIM_EXTRA_LIBS): Delete.
110 * configure.ac (mips_igen_engine, mips_extra_libs): Delete.
111 * configure: Regenerate.
112
4df817de
MF		 1132021-05-04 Mike Frysinger <vapier@gentoo.org>
114
115 * mdmx.c (qh_acc): Change 2nd AccAddAQH to AccAddLQH.
116
aa0fca16
MF		 1172021-05-04 Mike Frysinger <vapier@gentoo.org>
118
119 * configure: Regenerate.
120
adbaa7b8
MF		 1212021-05-01 Mike Frysinger <vapier@gentoo.org>
122
123 * cp1.c (store_fcr): Mark static.
124
fe348617
MF		 1252021-05-01 Mike Frysinger <vapier@gentoo.org>
126
127 * config.in, configure: Regenerate.
128
9d903352
MF		 1292021-04-23 Mike Frysinger <vapier@gentoo.org>
130
131 * configure.ac (hw_enabled): Delete.
132 (SIM_AC_OPTION_HARDWARE): Delete first two args.
133 * configure: Regenerate.
134
19f6a43c
TT		 1352021-04-22 Tom Tromey <tom@tromey.com>
136
137 * configure, config.in: Rebuild.
138
e7d8f1da
TT		 1392021-04-22 Tom Tromey <tom@tromey.com>
140
141 * Makefile.in (interp.o, m16run.o, micromipsrun.o, multi-run.o):
142 Remove.
143 (SIM_EXTRA_DEPS): New variable.
144
efd82ac7
TT		 1452021-04-22 Tom Tromey <tom@tromey.com>
146
147 * configure: Rebuild.
148
2662c237
MF		 1492021-04-21 Mike Frysinger <vapier@gentoo.org>
150
151 * aclocal.m4: Regenerate.
152
1f195bc3
SM		 1532021-04-21 Simon Marchi <simon.marchi@polymtl.ca>
154
155 * configure: Regenerate.
156
37e9f182
MF		 1572021-04-18 Mike Frysinger <vapier@gentoo.org>
158
159 * configure: Regenerate.
160
d5a71b11
MF		 1612021-04-12 Mike Frysinger <vapier@gentoo.org>
162
163 * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
164
2b8d134b
SM		 1652021-04-08 Simon Marchi <simon.marchi@polymtl.ca>
166
167 * Makefile.in: Set ASAN_OPTIONS when running igen.
168
5c6f091a
FS		 1692021-04-04 Steve Ellcey <sellcey@mips.com>
170 Faraz Shahbazker <fshahbazker@wavecomp.com>
171
172 * interp.c (sim_monitor): Add switch entries for unlink (13),
173 lseek (14), and stat (15).
174
b6b1c790
MF		 1752021-04-02 Mike Frysinger <vapier@gentoo.org>
176
177 * Makefile.in (../igen/igen): Delete rule.
178 (tmp-igen, tmp-m16, tmp-micromips): Delete ../igen make.
179
c2783492
MF		 1802021-04-02 Mike Frysinger <vapier@gentoo.org>
181
182 * aclocal.m4, configure: Regenerate.
183
ebe9564b
MF		 1842021-02-28 Mike Frysinger <vapier@gentoo.org>
185
186 * configure: Regenerate.
187
f8069d55
MF		 1882021-02-27 Mike Frysinger <vapier@gentoo.org>
189
190 * Makefile.in (SIM_EXTRA_ALL): Delete.
191 (all): New target.
192
760b3e8b
MF		 1932021-02-21 Mike Frysinger <vapier@gentoo.org>
194
195 * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
196 * aclocal.m4, configure: Regenerate.
197
136da8cd
MF		 1982021-02-13 Mike Frysinger <vapier@gentoo.org>
199
200 * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
201 * aclocal.m4, configure: Regenerate.
202
4c0d76b9
MF		 2032021-02-06 Mike Frysinger <vapier@gentoo.org>
204
205 * interp.c (sim_open): Delete call to STATE_WATCHPOINTS.
206
aa09469f
MF		 2072021-02-06 Mike Frysinger <vapier@gentoo.org>
208
209 * configure: Regenerate.
210
d4e3adda
MF		 2112021-01-30 Mike Frysinger <vapier@gentoo.org>
212
213 * interp.c (sim_open): Delete STATE_WATCHPOINTS (sd)->sizeof_pc.
214
68ed2854
MF		 2152021-01-11 Mike Frysinger <vapier@gentoo.org>
216
217 * config.in, configure: Regenerate.
218 * interp.c: Delete HAVE_STRING_H, HAVE_STRINGS_H, HAVE_STDLIB_H,
219 and strings.h include.
220
50df264d
MF		 2212021-01-09 Mike Frysinger <vapier@gentoo.org>
222
223 * configure: Regenerate.
224
bf470982
MF		 2252021-01-09 Mike Frysinger <vapier@gentoo.org>
226
227 * configure.ac (SIM_AC_OPTION_WARNINGS): Pass "no".
228 * configure: Regenerate.
229
46f900c0
MF		 2302021-01-08 Mike Frysinger <vapier@gentoo.org>
231
232 * configure: Regenerate.
233
dfb856ba
MF		 2342021-01-04 Mike Frysinger <vapier@gentoo.org>
235
236 * configure: Regenerate.
237
382bc56b
PK		 2382020-12-31 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
239
240 * sim-main.c: Include <stdlib.h>.
241
ad9675dd
PK		 2422020-12-14 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change)
243
244 * cp1.c: Include <stdlib.h>.
245
f693213d
SM		 2462020-07-29 Simon Marchi <simon.marchi@efficios.com>
247
248 * configure: Re-generate.
249
5c887dd5
JB		 2502017-09-06 John Baldwin <jhb@FreeBSD.org>
251
252 * configure: Regenerate.
253
91588b3a
MF		 2542016-11-11 Mike Frysinger <vapier@gentoo.org>
255
6cb2202b 256 PR sim/20808
91588b3a
MF		 257 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Define CPU to cpu
258 and SD to sd.
259
e04659e8
MF		 2602016-11-11 Mike Frysinger <vapier@gentoo.org>
261
6cb2202b 262 PR sim/20809
e04659e8
MF		 263 * mips.igen (check_u64): Enable for `r3900'.
264
1554f758
MF		 2652016-02-05 Mike Frysinger <vapier@gentoo.org>
266
267 * configure.ac (sim_engine_run): Change sd->base.prog_bfd to
268 STATE_PROG_BFD (sd).
269 * configure: Regenerate.
270
3d304f48
AB		 2712016-01-18 Andrew Bennett <andrew.bennett@imgtec.com>
272 Maciej W. Rozycki <macro@imgtec.com>
273
274 PR sim/19441
275 * micromips.igen (delayslot_micromips): Enable for `micromips32',
276 `micromips64' and `micromipsdsp' only.
277 (process_isa_mode): Enable for `micromips32' and `micromips64' only.
278 (do_micromips_jalr, do_micromips_jal): Likewise.
279 (compute_movep_src_reg): Likewise.
280 (compute_andi16_imm): Likewise.
281 (convert_fmt_micromips): Likewise.
282 (convert_fmt_micromips_cvt_d): Likewise.
283 (convert_fmt_micromips_cvt_s): Likewise.
284 (FMT_MICROMIPS): Likewise.
285 (FMT_MICROMIPS_CVT_D): Likewise.
286 (FMT_MICROMIPS_CVT_S): Likewise.
287
b36d953b
MF		 2882016-01-12 Mike Frysinger <vapier@gentoo.org>
289
290 * interp.c: Include elf-bfd.h.
291 (sim_create_inferior): Truncate pc to 32-bits when EI_CLASS is
292 ELFCLASS32.
293
ce39bd38
MF		 2942016-01-10 Mike Frysinger <vapier@gentoo.org>
295
296 * config.in, configure: Regenerate.
297
99d8e879
MF		 2982016-01-10 Mike Frysinger <vapier@gentoo.org>
299
300 * configure: Regenerate.
301
35656e95
MF		 3022016-01-10 Mike Frysinger <vapier@gentoo.org>
303
304 * configure: Regenerate.
305
16f7876d
MF		 3062016-01-10 Mike Frysinger <vapier@gentoo.org>
307
308 * configure: Regenerate.
309
e19418e0
MF		 3102016-01-10 Mike Frysinger <vapier@gentoo.org>
311
312 * configure: Regenerate.
313
6d90347b
MF		 3142016-01-10 Mike Frysinger <vapier@gentoo.org>
315
316 * configure.ac (SIM_AC_OPTION_SMP): Delete call.
317 * configure: Regenerate.
318
347fe5bb
MF		 3192016-01-10 Mike Frysinger <vapier@gentoo.org>
320
321 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
322 * configure: Regenerate.
323
22be3fbe
MF		 3242016-01-10 Mike Frysinger <vapier@gentoo.org>
325
326 * configure: Regenerate.
327
0dc73ef7
MF		 3282016-01-10 Mike Frysinger <vapier@gentoo.org>
329
330 * configure: Regenerate.
331
936df756
MF		 3322016-01-09 Mike Frysinger <vapier@gentoo.org>
333
334 * config.in, configure: Regenerate.
335
2e3d4f4d
MF		 3362016-01-06 Mike Frysinger <vapier@gentoo.org>
337
338 * interp.c (sim_open): Mark argv const.
339 (sim_create_inferior): Mark argv and env const.
340
9bbf6f91
MF		 3412016-01-04 Mike Frysinger <vapier@gentoo.org>
342
343 * configure: Regenerate.
344
77cf2ef5
MF		 3452016-01-03 Mike Frysinger <vapier@gentoo.org>
346
347 * interp.c (sim_open): Update sim_parse_args comment.
348
0cb8d851
MF		 3492016-01-03 Mike Frysinger <vapier@gentoo.org>
350
351 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
352 * configure: Regenerate.
353
1ac72f06
MF		 3542016-01-02 Mike Frysinger <vapier@gentoo.org>
355
356 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
357 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
358 * configure: Regenerate.
359 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
360
d47f5b30
MF		 3612016-01-02 Mike Frysinger <vapier@gentoo.org>
362
363 * dv-tx3904cpu.c (CPU, SD): Delete.
364
e1211e55
MF		 3652015-12-30 Mike Frysinger <vapier@gentoo.org>
366
367 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
368 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
369 (sim_store_register): Rename to ...
370 (mips_reg_store): ... this. Delete local cpu var.
371 Update sim_io_eprintf calls.
372 (sim_fetch_register): Rename to ...
373 (mips_reg_fetch): ... this. Delete local cpu var.
374 Update sim_io_eprintf calls.
375
5e744ef8
MF		 3762015-12-27 Mike Frysinger <vapier@gentoo.org>
377
378 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
379
1b393626
MF		 3802015-12-26 Mike Frysinger <vapier@gentoo.org>
381
382 * config.in, configure: Regenerate.
383
26f8bf63
MF		 3842015-12-26 Mike Frysinger <vapier@gentoo.org>
385
386 * interp.c (sim_write, sim_read): Delete.
387 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
388 (load_word): Likewise.
389 * micromips.igen (cache): Likewise.
390 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
391 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
392 do_store_left, do_store_right, do_load_double, do_store_double):
393 Likewise.
394 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
395 (do_prefx): Likewise.
396 * sim-main.c (address_translation, prefetch): Delete.
397 (ifetch32, ifetch16): Delete call to AddressTranslation and set
398 paddr=vaddr.
399 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
400 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
401 (LoadMemory, StoreMemory): Delete CCA arg.
402
ef04e371
MF		 4032015-12-24 Mike Frysinger <vapier@gentoo.org>
404
405 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
406 * configure: Regenerated.
407
cb379ede
MF		 4082015-12-24 Mike Frysinger <vapier@gentoo.org>
409
410 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
411 * tconfig.h: Delete.
412
26936211
MF		 4132015-12-24 Mike Frysinger <vapier@gentoo.org>
414
415 * tconfig.h (SIM_HANDLES_LMA): Delete.
416
84e8e361
MF		 4172015-12-24 Mike Frysinger <vapier@gentoo.org>
418
419 * sim-main.h (WITH_WATCHPOINTS): Delete.
420
3cabaf66
MF		 4212015-12-24 Mike Frysinger <vapier@gentoo.org>
422
423 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
424
8abe6c66
MF		 4252015-12-24 Mike Frysinger <vapier@gentoo.org>
426
427 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
428
1d19cae7
DV		 4292015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
430
431 * micromips.igen (process_isa_mode): Fix left shift of negative
432 value.
433
cdf850e9
MF		 4342015-11-17 Mike Frysinger <vapier@gentoo.org>
435
436 * sim-main.h (WITH_MODULO_MEMORY): Delete.
437
797eee42
MF		 4382015-11-15 Mike Frysinger <vapier@gentoo.org>
439
440 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
441
6e4f085c
MF		 4422015-11-14 Mike Frysinger <vapier@gentoo.org>
443
444 * interp.c (sim_close): Rename to ...
445 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
446 sim_io_shutdown.
447 * sim-main.h (mips_sim_close): Declare.
448 (SIM_CLOSE_HOOK): Define.
449
8e394ffc
AB		 4502015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
451 Ali Lown <ali.lown@imgtec.com>
452
453 * Makefile.in (tmp-micromips): New rule.
454 (tmp-mach-multi): Add support for micromips.
455 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
456 that works for both mips64 and micromips64.
457 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
458 micromips32.
459 Add build support for micromips.
460 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
461 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
462 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
463 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
464 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
465 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
466 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
467 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
468 Refactored instruction code to use these functions.
469 * dsp2.igen: Refactored instruction code to use the new functions.
470 * interp.c (decode_coproc): Refactored to work with any instruction
471 encoding.
472 (isa_mode): New variable
473 (RSVD_INSTRUCTION): Changed to 0x00000039.
474 * m16.igen (BREAK16): Refactored instruction to use do_break16.
475 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
476 * micromips.dc: New file.
477 * micromips.igen: New file.
478 * micromips16.dc: New file.
479 * micromipsdsp.igen: New file.
480 * micromipsrun.c: New file.
481 * mips.igen (do_swc1): Changed to work with any instruction encoding.
482 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
483 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
484 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
485 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
486 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
487 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
488 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
489 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
490 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
491 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
492 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
493 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
494 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
495 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
496 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
497 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
498 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
499 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
500 instructions.
501 Refactored instruction code to use these functions.
502 (RSVD): Changed to use new reserved instruction.
503 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
504 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
505 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
506 do_store_double): Added micromips32 and micromips64 models.
507 Added include for micromips.igen and micromipsdsp.igen
508 Add micromips32 and micromips64 models.
509 (DecodeCoproc): Updated to use new macro definition.
510 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
511 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
512 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
513 Refactored instruction code to use these functions.
514 * sim-main.h (CP0_operation): New enum.
515 (DecodeCoproc): Updated macro.
516 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
517 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
518 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
519 ISA_MODE_MICROMIPS): New defines.
520 (sim_state): Add isa_mode field.
521
8d0978fb
MF		 5222015-06-23 Mike Frysinger <vapier@gentoo.org>
523
524 * configure: Regenerate.
525
306f4178
MF		 5262015-06-12 Mike Frysinger <vapier@gentoo.org>
527
528 * configure.ac: Change configure.in to configure.ac.
529 * configure: Regenerate.
530
a3487082
MF		 5312015-06-12 Mike Frysinger <vapier@gentoo.org>
532
533 * configure: Regenerate.
534
29bc024d
MF		 5352015-06-12 Mike Frysinger <vapier@gentoo.org>
536
537 * interp.c [TRACE]: Delete.
538 (TRACE): Change to WITH_TRACE_ANY_P.
539 [!WITH_TRACE_ANY_P] (open_trace): Define.
540 (mips_option_handler, open_trace, sim_close, dotrace):
541 Change defined(TRACE) to WITH_TRACE_ANY_P.
542 (sim_open): Delete TRACE ifdef check.
543 * sim-main.c (load_memory): Delete TRACE ifdef check.
544 (store_memory): Likewise.
545 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
546 [!WITH_TRACE_ANY_P] (dotrace): Define.
547
3ebe2863
MF		 5482015-04-18 Mike Frysinger <vapier@gentoo.org>
549
550 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
551 comments.
552
20bca71d
MF		 5532015-04-18 Mike Frysinger <vapier@gentoo.org>
554
555 * sim-main.h (SIM_CPU): Delete.
556
7e83aa92
MF		 5572015-04-18 Mike Frysinger <vapier@gentoo.org>
558
559 * sim-main.h (sim_cia): Delete.
560
034685f9
MF		 5612015-04-17 Mike Frysinger <vapier@gentoo.org>
562
563 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
564 PU_PC_GET.
565 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
566 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
567 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
568 CIA_SET to CPU_PC_SET.
569 * sim-main.h (CIA_GET, CIA_SET): Delete.
570
78e9aa70
MF		 5712015-04-15 Mike Frysinger <vapier@gentoo.org>
572
573 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
574 * sim-main.h (STATE_CPU): Delete.
575
bf12d44e
MF		 5762015-04-13 Mike Frysinger <vapier@gentoo.org>
577
578 * configure: Regenerate.
579
7bebb329
MF		 5802015-04-13 Mike Frysinger <vapier@gentoo.org>
581
582 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
583 * interp.c (mips_pc_get, mips_pc_set): New functions.
584 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
585 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
586 (sim_pc_get): Delete.
587 * sim-main.h (SIM_CPU): Define.
588 (struct sim_state): Change cpu to an array of pointers.
589 (STATE_CPU): Drop &.
590
8ac57fbd
MF		 5912015-04-13 Mike Frysinger <vapier@gentoo.org>
592
593 * interp.c (mips_option_handler, open_trace, sim_close,
594 sim_write, sim_read, sim_store_register, sim_fetch_register,
595 sim_create_inferior, pr_addr, pr_uword64): Convert old style
596 prototypes.
597 (sim_open): Convert old style prototype. Change casts with
598 sim_write to unsigned char *.
599 (fetch_str): Change null to unsigned char, and change cast to
600 unsigned char *.
601 (sim_monitor): Change c & ch to unsigned char. Change cast to
602 unsigned char *.
603
e787f858
MF		 6042015-04-12 Mike Frysinger <vapier@gentoo.org>
605
606 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
607
122bbfb5
MF		 6082015-04-06 Mike Frysinger <vapier@gentoo.org>
609
610 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
611
0fe84f3f
MF		 6122015-04-01 Mike Frysinger <vapier@gentoo.org>
613
614 * tconfig.h (SIM_HAVE_PROFILE): Delete.
615
aadc9410
MF		 6162015-03-31 Mike Frysinger <vapier@gentoo.org>
617
618 * config.in, configure: Regenerate.
619
05f53ed6
MF		 6202015-03-24 Mike Frysinger <vapier@gentoo.org>
621
622 * interp.c (sim_pc_get): New function.
623
c0931f26
MF		 6242015-03-24 Mike Frysinger <vapier@gentoo.org>
625
626 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
627 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
628
30452bbe
MF		 6292015-03-24 Mike Frysinger <vapier@gentoo.org>
630
631 * configure: Regenerate.
632
64dd13df
MF		 6332015-03-23 Mike Frysinger <vapier@gentoo.org>
634
635 * configure: Regenerate.
636
49cd1634
MF		 6372015-03-23 Mike Frysinger <vapier@gentoo.org>
638
639 * configure: Regenerate.
640 * configure.ac (mips_extra_objs): Delete.
641 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
642 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
643
3649cb06
MF		 6442015-03-23 Mike Frysinger <vapier@gentoo.org>
645
646 * configure: Regenerate.
647 * configure.ac: Delete sim_hw checks for dv-sockser.
648
ae7d0cac
MF		 6492015-03-16 Mike Frysinger <vapier@gentoo.org>
650
651 * config.in, configure: Regenerate.
652 * tconfig.in: Rename file ...
653 * tconfig.h: ... here.
654
8406bb59
MF		 6552015-03-15 Mike Frysinger <vapier@gentoo.org>
656
657 * tconfig.in: Delete includes.
658 [HAVE_DV_SOCKSER]: Delete.
659
465fb143
MF		 6602015-03-14 Mike Frysinger <vapier@gentoo.org>
661
662 * Makefile.in (SIM_RUN_OBJS): Delete.
663
5cddc23a
MF		 6642015-03-14 Mike Frysinger <vapier@gentoo.org>
665
666 * configure.ac (AC_CHECK_HEADERS): Delete.
667 * aclocal.m4, configure: Regenerate.
668
2974be62
AM		 6692014-08-19 Alan Modra <amodra@gmail.com>
670
671 * configure: Regenerate.
672
faa743bb
RM		 6732014-08-15 Roland McGrath <mcgrathr@google.com>
674
675 * configure: Regenerate.
676 * config.in: Regenerate.
677
1a8a700e
MF		 6782014-03-04 Mike Frysinger <vapier@gentoo.org>
679
680 * configure: Regenerate.
681
bf3d9781
AM		 6822013-09-23 Alan Modra <amodra@gmail.com>
683
684 * configure: Regenerate.
685
31e6ad7d
MF		 6862013-06-03 Mike Frysinger <vapier@gentoo.org>
687
688 * aclocal.m4, configure: Regenerate.
689
d3685d60
TT		 6902013-05-10 Freddie Chopin <freddie_chopin@op.pl>
691
692 * configure: Rebuild.
693
1517bd27
MF		 6942013-03-26 Mike Frysinger <vapier@gentoo.org>
695
696 * configure: Regenerate.
697
3be31516
JS		 6982013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
699
700 * configure.ac: Address use of dv-sockser.o.
701 * tconfig.in: Conditionalize use of dv_sockser_install.
702 * configure: Regenerated.
703 * config.in: Regenerated.
704
37cb8f8e
SE		 7052012-10-04 Chao-ying Fu <fu@mips.com>
706 Steve Ellcey <sellcey@mips.com>
707
708 * mips/mips3264r2.igen (rdhwr): New.
709
87c8644f
JS		 7102012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
711
712 * configure.ac: Always link against dv-sockser.o.
713 * configure: Regenerate.
714
5f3ef9d0
JB		 7152012-06-15 Joel Brobecker <brobecker@adacore.com>
716
717 * config.in, configure: Regenerate.
718
a6ff997c
NC		 7192012-05-18 Nick Clifton <nickc@redhat.com>
720
721 PR 14072
722 * interp.c: Include config.h before system header files.
723
2232061b
MF		 7242012-03-24 Mike Frysinger <vapier@gentoo.org>
725
726 * aclocal.m4, config.in, configure: Regenerate.
727
db2e4d67
MF		 7282011-12-03 Mike Frysinger <vapier@gentoo.org>
729
730 * aclocal.m4: New file.
731 * configure: Regenerate.
732
4399a56b
MF		 7332011-10-19 Mike Frysinger <vapier@gentoo.org>
734
735 * configure: Regenerate after common/acinclude.m4 update.
736
9c082ca8
MF		 7372011-10-17 Mike Frysinger <vapier@gentoo.org>
738
739 * configure.ac: Change include to common/acinclude.m4.
740
6ffe910a
MF		 7412011-10-17 Mike Frysinger <vapier@gentoo.org>
742
743 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
744 call. Replace common.m4 include with SIM_AC_COMMON.
745 * configure: Regenerate.
746
31b28250
HPN		 7472011-07-08 Hans-Peter Nilsson <hp@axis.com>
748
3faa01e3
HPN		 749 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
750 $(SIM_EXTRA_DEPS).
751 (tmp-mach-multi): Exit early when igen fails.
31b28250 752
2419798b
MF		 7532011-07-05 Mike Frysinger <vapier@gentoo.org>
754
755 * interp.c (sim_do_command): Delete.
756
d79fe0d6
MF		 7572011-02-14 Mike Frysinger <vapier@gentoo.org>
758
759 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
760 (tx3904sio_fifo_reset): Likewise.
761 * interp.c (sim_monitor): Likewise.
762
5558e7e6
MF		 7632010-04-14 Mike Frysinger <vapier@gentoo.org>
764
765 * interp.c (sim_write): Add const to buffer arg.
766
35aafff4
JB		 7672010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
768
769 * interp.c: Don't include sysdep.h
770
3725885a
RW		 7712010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
772
773 * configure: Regenerate.
774
d6416cdc
RW		 7752009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
776
81ecdfbb
RW		 777 * config.in: Regenerate.
778 * configure: Likewise.
779
d6416cdc
RW		 780 * configure: Regenerate.
781
b5bd9624
HPN		 7822008-07-11 Hans-Peter Nilsson <hp@axis.com>
783
784 * configure: Regenerate to track ../common/common.m4 changes.
785 * config.in: Ditto.
786
6efef468 7872008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 788 Daniel Jacobowitz <dan@codesourcery.com>
789 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 790
791 * configure: Regenerate.
792
60dc88db
RS		 7932007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
794
795 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
796 that unconditionally allows fmt_ps.
797 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
798 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
799 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
800 filter from 64,f to 32,f.
801 (PREFX): Change filter from 64 to 32.
802 (LDXC1, LUXC1): Provide separate mips32r2 implementations
803 that use do_load_double instead of do_load. Make both LUXC1
804 versions unpredictable if SizeFGR () != 64.
805 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
806 instead of do_store. Remove unused variable. Make both SUXC1
807 versions unpredictable if SizeFGR () != 64.
808
599ca73e
RS		 8092007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
810
811 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
812 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
813 shifts for that case.
814
2525df03
NC		 8152007-09-04 Nick Clifton <nickc@redhat.com>
816
817 * interp.c (options enum): Add OPTION_INFO_MEMORY.
818 (display_mem_info): New static variable.
819 (mips_option_handler): Handle OPTION_INFO_MEMORY.
820 (mips_options): Add info-memory and memory-info.
821 (sim_open): After processing the command line and board
822 specification, check display_mem_info. If it is set then
823 call the real handler for the --memory-info command line
824 switch.
825
35ee6e1e
JB		 8262007-08-24 Joel Brobecker <brobecker@adacore.com>
827
828 * configure.ac: Change license of multi-run.c to GPL version 3.
829 * configure: Regenerate.
830
d5fb0879
RS		 8312007-06-28 Richard Sandiford <richard@codesourcery.com>
832
833 * configure.ac, configure: Revert last patch.
834
2a2ce21b
RS		 8352007-06-26 Richard Sandiford <richard@codesourcery.com>
836
837 * configure.ac (sim_mipsisa3264_configs): New variable.
838 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
839 every configuration support all four targets, using the triplet to
840 determine the default.
841 * configure: Regenerate.
842
efdcccc9
RS		 8432007-06-25 Richard Sandiford <richard@codesourcery.com>
844
0a7692b2 845 * Makefile.in (m16run.o): New rule.
efdcccc9 846
f532a356
TS		 8472007-05-15 Thiemo Seufer <ths@mips.com>
848
849 * mips3264r2.igen (DSHD): Fix compile warning.
850
bfe9c90b
TS		 8512007-05-14 Thiemo Seufer <ths@mips.com>
852
853 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
854 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
855 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
856 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
857 for mips32r2.
858
53f4826b
TS		 8592007-03-01 Thiemo Seufer <ths@mips.com>
860
861 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
862 and mips64.
863
8bf3ddc8
TS		 8642007-02-20 Thiemo Seufer <ths@mips.com>
865
866 * dsp.igen: Update copyright notice.
867 * dsp2.igen: Fix copyright notice.
868
8b082fb1 8692007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 870 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 871
872 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
873 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
874 Add dsp2 to sim_igen_machine.
875 * configure: Regenerate.
876 * dsp.igen (do_ph_op): Add MUL support when op = 2.
877 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
878 (mulq_rs.ph): Use do_ph_mulq.
879 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
880 * mips.igen: Add dsp2 model and include dsp2.igen.
881 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
882 for *mips32r2, *mips64r2, *dsp.
883 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
884 for *mips32r2, *mips64r2, *dsp2.
885 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
886
b1004875 8872007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 888 Nigel Stephens <nigel@mips.com>
b1004875
TS		 889
890 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
891 jumps with hazard barrier.
892
f8df4c77 8932007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 894 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 895
896 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
897 after each call to sim_io_write.
898
b1004875 8992007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 900 Nigel Stephens <nigel@mips.com>
b1004875
TS		 901
902 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
903 supported by this simulator.
07802d98
TS		 904 (decode_coproc): Recognise additional CP0 Config registers
905 correctly.
906
14fb6c5a 9072007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 908 Nigel Stephens <nigel@mips.com>
909 David Ung <davidu@mips.com>
14fb6c5a
TS		 910
911 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
912 uninterpreted formats. If fmt is one of the uninterpreted types
913 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
914 fmt_word, and fmt_uninterpreted_64 like fmt_long.
915 (store_fpr): When writing an invalid odd register, set the
916 matching even register to fmt_unknown, not the following register.
917 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
918 the the memory window at offset 0 set by --memory-size command
919 line option.
920 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
921 point register.
922 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
923 register.
924 (sim_monitor): When returning the memory size to the MIPS
925 application, use the value in STATE_MEM_SIZE, not an arbitrary
926 hardcoded value.
927 (cop_lw): Don' mess around with FPR_STATE, just pass
928 fmt_uninterpreted_32 to StoreFPR.
929 (cop_sw): Similarly.
930 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
931 (cop_sd): Similarly.
932 * mips.igen (not_word_value): Single version for mips32, mips64
933 and mips16.
934
c8847145 9352007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 936 Nigel Stephens <nigel@mips.com>
c8847145
TS		 937
938 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
939 MBytes.
940
4b5d35ee
TS		 9412007-02-17 Thiemo Seufer <ths@mips.com>
942
943 * configure.ac (mips*-sde-elf*): Move in front of generic machine
944 configuration.
945 * configure: Regenerate.
946
3669427c
TS		 9472007-02-17 Thiemo Seufer <ths@mips.com>
948
949 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
950 Add mdmx to sim_igen_machine.
951 (mipsisa64*-*-*): Likewise. Remove dsp.
952 (mipsisa32*-*-*): Remove dsp.
953 * configure: Regenerate.
954
109ad085
TS		 9552007-02-13 Thiemo Seufer <ths@mips.com>
956
957 * configure.ac: Add mips*-sde-elf* target.
958 * configure: Regenerate.
959
921d7ad3
HPN		 9602006-12-21 Hans-Peter Nilsson <hp@axis.com>
961
962 * acconfig.h: Remove.
963 * config.in, configure: Regenerate.
964
02f97da7
TS		 9652006-11-07 Thiemo Seufer <ths@mips.com>
966
967 * dsp.igen (do_w_op): Fix compiler warning.
968
2d2733fc 9692006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 970 David Ung <davidu@mips.com>
2d2733fc
TS		 971
972 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
973 sim_igen_machine.
974 * configure: Regenerate.
975 * mips.igen (model): Add smartmips.
976 (MADDU): Increment ACX if carry.
977 (do_mult): Clear ACX.
978 (ROR,RORV): Add smartmips.
72f4393d 979 (include): Include smartmips.igen.
2d2733fc
TS		 980 * sim-main.h (ACX): Set to REGISTERS[89].
981 * smartmips.igen: New file.
982
d85c3a10 9832006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 984 David Ung <davidu@mips.com>
d85c3a10
TS		 985
986 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
987 mips3264r2.igen. Add missing dependency rules.
988 * m16e.igen: Support for mips16e save/restore instructions.
989
e85e3205
RE		 9902006-06-13 Richard Earnshaw <rearnsha@arm.com>
991
992 * configure: Regenerated.
993
2f0122dc
DJ		 9942006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
995
996 * configure: Regenerated.
997
20e95c23
DJ		 9982006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
999
1000 * configure: Regenerated.
1001
69088b17
CF		 10022006-05-15 Chao-ying Fu <fu@mips.com>
1003
1004 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
1005
0275de4e
NC		 10062006-04-18 Nick Clifton <nickc@redhat.com>
1007
1008 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
1009 statement.
1010
b3a3ffef
HPN		 10112006-03-29 Hans-Peter Nilsson <hp@axis.com>
1012
1013 * configure: Regenerate.
1014
40a5538e
CF		 10152005-12-14 Chao-ying Fu <fu@mips.com>
1016
1017 * Makefile.in (SIM_OBJS): Add dsp.o.
1018 (dsp.o): New dependency.
1019 (IGEN_INCLUDE): Add dsp.igen.
1020 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
1021 mipsisa64*-*-*): Add dsp to sim_igen_machine.
1022 * configure: Regenerate.
1023 * mips.igen: Add dsp model and include dsp.igen.
1024 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
1025 because these instructions are extended in DSP ASE.
1026 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
1027 adding 6 DSP accumulator registers and 1 DSP control register.
1028 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
1029 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
1030 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
1031 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
1032 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
1033 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
1034 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
1035 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
1036 DSPCR_CCOND_SMASK): New define.
1037 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
1038 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
1039
21d14896
ILT		 10402005-07-08 Ian Lance Taylor <ian@airs.com>
1041
1042 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
1043
b16d63da 10442005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 1045 Nigel Stephens <nigel@mips.com>
1046
1047 * mips.igen: New mips16e model and include m16e.igen.
1048 (check_u64): Add mips16e tag.
1049 * m16e.igen: New file for MIPS16e instructions.
1050 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
1051 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
1052 models.
1053 * configure: Regenerate.
b16d63da 1054
e70cb6cd 10552005-05-26 David Ung <davidu@mips.com>
72f4393d 1056
e70cb6cd
CD		 1057 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
1058 tags to all instructions which are applicable to the new ISAs.
1059 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
1060 vr.igen.
1061 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 1062 instructions.
e70cb6cd
CD		 1063 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
1064 to mips.igen.
1065 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
1066 * configure: Regenerate.
72f4393d 1067
2b193c4a
MK		 10682005-03-23 Mark Kettenis <kettenis@gnu.org>
1069
1070 * configure: Regenerate.
1071
35695fd6
AC		 10722005-01-14 Andrew Cagney <cagney@gnu.org>
1073
1074 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
1075 explicit call to AC_CONFIG_HEADER.
1076 * configure: Regenerate.
1077
f0569246
AC		 10782005-01-12 Andrew Cagney <cagney@gnu.org>
1079
1080 * configure.ac: Update to use ../common/common.m4.
1081 * configure: Re-generate.
1082
38f48d72
AC		 10832005-01-11 Andrew Cagney <cagney@localhost.localdomain>
1084
1085 * configure: Regenerated to track ../common/aclocal.m4 changes.
1086
b7026657
AC		 10872005-01-07 Andrew Cagney <cagney@gnu.org>
1088
1089 * configure.ac: Rename configure.in, require autoconf 2.59.
1090 * configure: Re-generate.
1091
379832de
HPN		 10922004-12-08 Hans-Peter Nilsson <hp@axis.com>
1093
1094 * configure: Regenerate for ../common/aclocal.m4 update.
1095
cd62154c 10962004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 1097
cd62154c
AC		 1098 Committed by Andrew Cagney.
1099 * m16.igen (CMP, CMPI): Fix assembler.
1100
e5da76ec
CD		 11012004-08-18 Chris Demetriou <cgd@broadcom.com>
1102
1103 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
1104 * configure: Regenerate.
1105
139181c8
CD		 11062004-06-25 Chris Demetriou <cgd@broadcom.com>
1107
1108 * configure.in (sim_m16_machine): Include mipsIII.
1109 * configure: Regenerate.
1110
1a27f959
CD		 11112004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
1112
72f4393d 1113 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 1114 from COP0_BADVADDR.
1115 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
1116
5dbb7b5a
CD		 11172004-04-10 Chris Demetriou <cgd@broadcom.com>
1118
1119 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
1120
14234056
CD		 11212004-04-09 Chris Demetriou <cgd@broadcom.com>
1122
1123 * mips.igen (check_fmt): Remove.
1124 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
1125 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
1126 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
1127 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
1128 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
1129 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
1130 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1131 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
1132 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
1133 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
1134
c6f9085c
CD		 11352004-04-09 Chris Demetriou <cgd@broadcom.com>
1136
1137 * sb1.igen (check_sbx): New function.
1138 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
1139
11d66e66 11402004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 1141 Richard Sandiford <rsandifo@redhat.com>
1142
1143 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
1144 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
1145 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
1146 separate implementations for mipsIV and mipsV. Use new macros to
1147 determine whether the restrictions apply.
1148
b3208fb8
CD		 11492004-01-19 Chris Demetriou <cgd@broadcom.com>
1150
1151 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
1152 (check_mult_hilo): Improve comments.
1153 (check_div_hilo): Likewise. Also, fork off a new version
1154 to handle mips32/mips64 (since there are no hazards to check
1155 in MIPS32/MIPS64).
1156
9a1d84fb
CD		 11572003-06-17 Richard Sandiford <rsandifo@redhat.com>
1158
1159 * mips.igen (do_dmultx): Fix check for negative operands.
1160
ae451ac6
ILT		 11612003-05-16 Ian Lance Taylor <ian@airs.com>
1162
1163 * Makefile.in (SHELL): Make sure this is defined.
1164 (various): Use $(SHELL) whenever we invoke move-if-change.
1165
dd69d292
CD		 11662003-05-03 Chris Demetriou <cgd@broadcom.com>
1167
1168 * cp1.c: Tweak attribution slightly.
1169 * cp1.h: Likewise.
1170 * mdmx.c: Likewise.
1171 * mdmx.igen: Likewise.
1172 * mips3d.igen: Likewise.
1173 * sb1.igen: Likewise.
1174
bcd0068e
CD		 11752003-04-15 Richard Sandiford <rsandifo@redhat.com>
1176
1177 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
1178 unsigned operands.
1179
6b4a8935
AC		 11802003-02-27 Andrew Cagney <cagney@redhat.com>
1181
601da316
AC		 1182 * interp.c (sim_open): Rename _bfd to bfd.
1183 (sim_create_inferior): Ditto.
6b4a8935 1184
d29e330f
CD		 11852003-01-14 Chris Demetriou <cgd@broadcom.com>
1186
1187 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
1188
a2353a08
CD		 11892003-01-14 Chris Demetriou <cgd@broadcom.com>
1190
1191 * mips.igen (EI, DI): Remove.
1192
80551777
CD		 11932003-01-05 Richard Sandiford <rsandifo@redhat.com>
1194
1195 * Makefile.in (tmp-run-multi): Fix mips16 filter.
1196
4c54fc26
CD		 11972003-01-04 Richard Sandiford <rsandifo@redhat.com>
1198 Andrew Cagney <ac131313@redhat.com>
1199 Gavin Romig-Koch <gavin@redhat.com>
1200 Graydon Hoare <graydon@redhat.com>
1201 Aldy Hernandez <aldyh@redhat.com>
1202 Dave Brolley <brolley@redhat.com>
1203 Chris Demetriou <cgd@broadcom.com>
1204
1205 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
1206 (sim_mach_default): New variable.
1207 (mips64vr-*-*, mips64vrel-*-*): New configurations.
1208 Add a new simulator generator, MULTI.
1209 * configure: Regenerate.
1210 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
1211 (multi-run.o): New dependency.
1212 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
1213 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
1214 (tmp-multi): Combine them.
1215 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
1216 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
1217 (distclean-extra): New rule.
1218 * sim-main.h: Include bfd.h.
1219 (MIPS_MACH): New macro.
1220 * mips.igen (vr4120, vr5400, vr5500): New models.
1221 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
1222 * vr.igen: Replace with new version.
1223
e6c674b8
CD		 12242003-01-04 Chris Demetriou <cgd@broadcom.com>
1225
1226 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
1227 * configure: Regenerate.
1228
28f50ac8
CD		 12292002-12-31 Chris Demetriou <cgd@broadcom.com>
1230
1231 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
1232 * mips.igen: Remove all invocations of check_branch_bug and
1233 mark_branch_bug.
1234
5071ffe6
CD		 12352002-12-16 Chris Demetriou <cgd@broadcom.com>
1236
72f4393d 1237 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 1238
06e7837e
CD		 12392002-07-30 Chris Demetriou <cgd@broadcom.com>
1240
1241 * mips.igen (do_load_double, do_store_double): New functions.
1242 (LDC1, SDC1): Rename to...
1243 (LDC1b, SDC1b): respectively.
1244 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
1245
2265c243
MS		 12462002-07-29 Michael Snyder <msnyder@redhat.com>
1247
1248 * cp1.c (fp_recip2): Modify initialization expression so that
1249 GCC will recognize it as constant.
1250
a2f8b4f3
CD		 12512002-06-18 Chris Demetriou <cgd@broadcom.com>
1252
1253 * mdmx.c (SD_): Delete.
1254 (Unpredictable): Re-define, for now, to directly invoke
1255 unpredictable_action().
1256 (mdmx_acc_op): Fix error in .ob immediate handling.
1257
b4b6c939
AC		 12582002-06-18 Andrew Cagney <cagney@redhat.com>
1259
1260 * interp.c (sim_firmware_command): Initialize `address'.
1261
c8cca39f
AC		 12622002-06-16 Andrew Cagney <ac131313@redhat.com>
1263
1264 * configure: Regenerated to track ../common/aclocal.m4 changes.
1265
e7e81181 12662002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 1267 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 1268
1269 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
1270 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
1271 * mips.igen: Include mips3d.igen.
1272 (mips3d): New model name for MIPS-3D ASE instructions.
1273 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 1274 instructions.
e7e81181
CD		 1275 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
1276 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
1277 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
1278 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
1279 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
1280 (RSquareRoot1, RSquareRoot2): New macros.
1281 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
1282 (fp_rsqrt2): New functions.
1283 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
1284 * configure: Regenerate.
1285
3a2b820e 12862002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 1287 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 1288
1289 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
1290 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
1291 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
1292 (convert): Note that this function is not used for paired-single
1293 format conversions.
1294 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
1295 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
1296 (check_fmt_p): Enable paired-single support.
1297 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
1298 (PUU.PS): New instructions.
1299 (CVT.S.fmt): Don't use this instruction for paired-single format
1300 destinations.
1301 * sim-main.h (FP_formats): New value 'fmt_ps.'
1302 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
1303 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
1304
d18ea9c2
CD		 13052002-06-12 Chris Demetriou <cgd@broadcom.com>
1306
1307 * mips.igen: Fix formatting of function calls in
1308 many FP operations.
1309
95fd5cee
CD		 13102002-06-12 Chris Demetriou <cgd@broadcom.com>
1311
1312 * mips.igen (MOVN, MOVZ): Trace result.
1313 (TNEI): Print "tnei" as the opcode name in traces.
1314 (CEIL.W): Add disassembly string for traces.
1315 (RSQRT.fmt): Make location of disassembly string consistent
1316 with other instructions.
1317
4f0d55ae
CD		 13182002-06-12 Chris Demetriou <cgd@broadcom.com>
1319
1320 * mips.igen (X): Delete unused function.
1321
3c25f8c7
AC		 13222002-06-08 Andrew Cagney <cagney@redhat.com>
1323
1324 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1325
f3c08b7e 13262002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1327 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 1328
1329 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1330 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1331 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1332 (fp_nmsub): New prototypes.
1333 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1334 (NegMultiplySub): New defines.
1335 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1336 (MADD.D, MADD.S): Replace with...
1337 (MADD.fmt): New instruction.
1338 (MSUB.D, MSUB.S): Replace with...
1339 (MSUB.fmt): New instruction.
1340 (NMADD.D, NMADD.S): Replace with...
1341 (NMADD.fmt): New instruction.
1342 (NMSUB.D, MSUB.S): Replace with...
1343 (NMSUB.fmt): New instruction.
1344
52714ff9 13452002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1346 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1347
1348 * cp1.c: Fix more comment spelling and formatting.
1349 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1350 (denorm_mode): New function.
1351 (fpu_unary, fpu_binary): Round results after operation, collect
1352 status from rounding operations, and update the FCSR.
1353 (convert): Collect status from integer conversions and rounding
1354 operations, and update the FCSR. Adjust NaN values that result
1355 from conversions. Convert to use sim_io_eprintf rather than
1356 fprintf, and remove some debugging code.
1357 * cp1.h (fenr_FS): New define.
1358
577d8c4b
CD		 13592002-06-07 Chris Demetriou <cgd@broadcom.com>
1360
1361 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1362 rounding mode to sim FP rounding mode flag conversion code into...
1363 (rounding_mode): New function.
1364
196496ed
CD		 13652002-06-07 Chris Demetriou <cgd@broadcom.com>
1366
1367 * cp1.c: Clean up formatting of a few comments.
1368 (value_fpr): Reformat switch statement.
1369
cfe9ea23 13702002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1371 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1372
1373 * cp1.h: New file.
1374 * sim-main.h: Include cp1.h.
1375 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1376 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1377 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1378 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1379 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1380 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1381 * cp1.c: Don't include sim-fpu.h; already included by
1382 sim-main.h. Clean up formatting of some comments.
1383 (NaN, Equal, Less): Remove.
1384 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1385 (fp_cmp): New functions.
1386 * mips.igen (do_c_cond_fmt): Remove.
1387 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1388 Compare. Add result tracing.
1389 (CxC1): Remove, replace with...
1390 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1391 (DMxC1): Remove, replace with...
1392 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1393 (MxC1): Remove, replace with...
1394 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1395
ee7254b0
CD		 13962002-06-04 Chris Demetriou <cgd@broadcom.com>
1397
1398 * sim-main.h (FGRIDX): Remove, replace all uses with...
1399 (FGR_BASE): New macro.
1400 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1401 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1402 (NR_FGR, FGR): Likewise.
1403 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1404 * mips.igen: Likewise.
1405
d3eb724f
CD		 14062002-06-04 Chris Demetriou <cgd@broadcom.com>
1407
1408 * cp1.c: Add an FSF Copyright notice to this file.
1409
ba46ddd0 14102002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1411 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1412
1413 * cp1.c (Infinity): Remove.
1414 * sim-main.h (Infinity): Likewise.
1415
1416 * cp1.c (fp_unary, fp_binary): New functions.
1417 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1418 (fp_sqrt): New functions, implemented in terms of the above.
1419 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1420 (Recip, SquareRoot): Remove (replaced by functions above).
1421 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1422 (fp_recip, fp_sqrt): New prototypes.
1423 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1424 (Recip, SquareRoot): Replace prototypes with #defines which
1425 invoke the functions above.
72f4393d 1426
18d8a52d
CD		 14272002-06-03 Chris Demetriou <cgd@broadcom.com>
1428
1429 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1430 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1431 file, remove PARAMS from prototypes.
1432 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1433 simulator state arguments.
1434 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1435 pass simulator state arguments.
1436 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1437 (store_fpr, convert): Remove 'sd' argument.
1438 (value_fpr): Likewise. Convert to use 'SD' instead.
1439
0f154cbd
CD		 14402002-06-03 Chris Demetriou <cgd@broadcom.com>
1441
1442 * cp1.c (Min, Max): Remove #if 0'd functions.
1443 * sim-main.h (Min, Max): Remove.
1444
e80fc152
CD		 14452002-06-03 Chris Demetriou <cgd@broadcom.com>
1446
1447 * cp1.c: fix formatting of switch case and default labels.
1448 * interp.c: Likewise.
1449 * sim-main.c: Likewise.
1450
bad673a9
CD		 14512002-06-03 Chris Demetriou <cgd@broadcom.com>
1452
1453 * cp1.c: Clean up comments which describe FP formats.
1454 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1455
7cbea089 14562002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1457 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1458
1459 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1460 Broadcom SiByte SB-1 processor configurations.
1461 * configure: Regenerate.
1462 * sb1.igen: New file.
1463 * mips.igen: Include sb1.igen.
1464 (sb1): New model.
1465 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1466 * mdmx.igen: Add "sb1" model to all appropriate functions and
1467 instructions.
1468 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1469 (ob_func, ob_acc): Reference the above.
1470 (qh_acc): Adjust to keep the same size as ob_acc.
1471 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1472 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1473
909daa82
CD		 14742002-06-03 Chris Demetriou <cgd@broadcom.com>
1475
1476 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1477
f4f1b9f1 14782002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1479 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1480
1481 * mips.igen (mdmx): New (pseudo-)model.
1482 * mdmx.c, mdmx.igen: New files.
1483 * Makefile.in (SIM_OBJS): Add mdmx.o.
1484 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1485 New typedefs.
1486 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1487 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1488 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1489 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1490 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1491 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1492 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1493 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1494 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1495 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1496 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1497 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1498 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1499 (qh_fmtsel): New macros.
1500 (_sim_cpu): New member "acc".
1501 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1502 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1503
5accf1ff
CD		 15042002-05-01 Chris Demetriou <cgd@broadcom.com>
1505
1506 * interp.c: Use 'deprecated' rather than 'depreciated.'
1507 * sim-main.h: Likewise.
1508
402586aa
CD		 15092002-05-01 Chris Demetriou <cgd@broadcom.com>
1510
1511 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1512 which wouldn't compile anyway.
1513 * sim-main.h (unpredictable_action): New function prototype.
1514 (Unpredictable): Define to call igen function unpredictable().
1515 (NotWordValue): New macro to call igen function not_word_value().
1516 (UndefinedResult): Remove.
1517 * interp.c (undefined_result): Remove.
1518 (unpredictable_action): New function.
1519 * mips.igen (not_word_value, unpredictable): New functions.
1520 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1521 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1522 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1523 NotWordValue() to check for unpredictable inputs, then
1524 Unpredictable() to handle them.
1525
c9b9995a
CD		 15262002-02-24 Chris Demetriou <cgd@broadcom.com>
1527
1528 * mips.igen: Fix formatting of calls to Unpredictable().
1529
e1015982
AC		 15302002-04-20 Andrew Cagney <ac131313@redhat.com>
1531
1532 * interp.c (sim_open): Revert previous change.
1533
b882a66b
AO		 15342002-04-18 Alexandre Oliva <aoliva@redhat.com>
1535
1536 * interp.c (sim_open): Disable chunk of code that wrote code in
1537 vector table entries.
1538
c429b7dd
CD		 15392002-03-19 Chris Demetriou <cgd@broadcom.com>
1540
1541 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1542 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1543 unused definitions.
1544
37d146fa
CD		 15452002-03-19 Chris Demetriou <cgd@broadcom.com>
1546
1547 * cp1.c: Fix many formatting issues.
1548
07892c0b
CD		 15492002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1550
1551 * cp1.c (fpu_format_name): New function to replace...
1552 (DOFMT): This. Delete, and update all callers.
1553 (fpu_rounding_mode_name): New function to replace...
1554 (RMMODE): This. Delete, and update all callers.
1555
487f79b7
CD		 15562002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1557
1558 * interp.c: Move FPU support routines from here to...
1559 * cp1.c: Here. New file.
1560 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1561 (cp1.o): New target.
1562
1e799e28
CD		 15632002-03-12 Chris Demetriou <cgd@broadcom.com>
1564
1565 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1566 * mips.igen (mips32, mips64): New models, add to all instructions
1567 and functions as appropriate.
1568 (loadstore_ea, check_u64): New variant for model mips64.
1569 (check_fmt_p): New variant for models mipsV and mips64, remove
1570 mipsV model marking fro other variant.
1571 (SLL) Rename to...
1572 (SLLa) this.
1573 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1574 for mips32 and mips64.
1575 (DCLO, DCLZ): New instructions for mips64.
1576
82f728db
CD		 15772002-03-07 Chris Demetriou <cgd@broadcom.com>
1578
1579 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1580 immediate or code as a hex value with the "%#lx" format.
1581 (ANDI): Likewise, and fix printed instruction name.
1582
b96e7ef1
CD		 15832002-03-05 Chris Demetriou <cgd@broadcom.com>
1584
1585 * sim-main.h (UndefinedResult, Unpredictable): New macros
1586 which currently do nothing.
1587
d35d4f70
CD		 15882002-03-05 Chris Demetriou <cgd@broadcom.com>
1589
1590 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1591 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1592 (status_CU3): New definitions.
1593
1594 * sim-main.h (ExceptionCause): Add new values for MIPS32
1595 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1596 for DebugBreakPoint and NMIReset to note their status in
1597 MIPS32 and MIPS64.
1598 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1599 (SignalExceptionCacheErr): New exception macros.
1600
3ad6f714
CD		 16012002-03-05 Chris Demetriou <cgd@broadcom.com>
1602
1603 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1604 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1605 is always enabled.
1606 (SignalExceptionCoProcessorUnusable): Take as argument the
1607 unusable coprocessor number.
1608
86b77b47
CD		 16092002-03-05 Chris Demetriou <cgd@broadcom.com>
1610
1611 * mips.igen: Fix formatting of all SignalException calls.
1612
97a88e93 16132002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1614
1615 * sim-main.h (SIGNEXTEND): Remove.
1616
97a88e93 16172002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1618
1619 * mips.igen: Remove gencode comment from top of file, fix
1620 spelling in another comment.
1621
97a88e93 16222002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1623
1624 * mips.igen (check_fmt, check_fmt_p): New functions to check
1625 whether specific floating point formats are usable.
1626 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1627 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1628 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1629 Use the new functions.
1630 (do_c_cond_fmt): Remove format checks...
1631 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1632
97a88e93 16332002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1634
1635 * mips.igen: Fix formatting of check_fpu calls.
1636
41774c9d
CD		 16372002-03-03 Chris Demetriou <cgd@broadcom.com>
1638
1639 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1640
4a0bd876
CD		 16412002-03-03 Chris Demetriou <cgd@broadcom.com>
1642
1643 * mips.igen: Remove whitespace at end of lines.
1644
09297648
CD		 16452002-03-02 Chris Demetriou <cgd@broadcom.com>
1646
1647 * mips.igen (loadstore_ea): New function to do effective
1648 address calculations.
1649 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1650 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1651 CACHE): Use loadstore_ea to do effective address computations.
1652
043b7057
CD		 16532002-03-02 Chris Demetriou <cgd@broadcom.com>
1654
1655 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1656 * mips.igen (LL, CxC1, MxC1): Likewise.
1657
c1e8ada4
CD		 16582002-03-02 Chris Demetriou <cgd@broadcom.com>
1659
1660 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1661 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1662 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1663 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1664 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1665 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1666 Don't split opcode fields by hand, use the opcode field values
1667 provided by igen.
1668
3e1dca16
CD		 16692002-03-01 Chris Demetriou <cgd@broadcom.com>
1670
1671 * mips.igen (do_divu): Fix spacing.
1672
1673 * mips.igen (do_dsllv): Move to be right before DSLLV,
1674 to match the rest of the do_<shift> functions.
1675
fff8d27d
CD		 16762002-03-01 Chris Demetriou <cgd@broadcom.com>
1677
1678 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1679 DSRL32, do_dsrlv): Trace inputs and results.
1680
0d3e762b
CD		 16812002-03-01 Chris Demetriou <cgd@broadcom.com>
1682
1683 * mips.igen (CACHE): Provide instruction-printing string.
1684
1685 * interp.c (signal_exception): Comment tokens after #endif.
1686
eb5fcf93
CD		 16872002-02-28 Chris Demetriou <cgd@broadcom.com>
1688
1689 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1690 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1691 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1692 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1693 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1694 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1695 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1696 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1697
bb22bd7d
CD		 16982002-02-28 Chris Demetriou <cgd@broadcom.com>
1699
1700 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1701 instruction-printing string.
1702 (LWU): Use '64' as the filter flag.
1703
91a177cf
CD		 17042002-02-28 Chris Demetriou <cgd@broadcom.com>
1705
1706 * mips.igen (SDXC1): Fix instruction-printing string.
1707
387f484a
CD		 17082002-02-28 Chris Demetriou <cgd@broadcom.com>
1709
1710 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1711 filter flags "32,f".
1712
3d81f391
CD		 17132002-02-27 Chris Demetriou <cgd@broadcom.com>
1714
1715 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1716 as the filter flag.
1717
af5107af
CD		 17182002-02-27 Chris Demetriou <cgd@broadcom.com>
1719
1720 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1721 add a comma) so that it more closely match the MIPS ISA
1722 documentation opcode partitioning.
1723 (PREF): Put useful names on opcode fields, and include
1724 instruction-printing string.
1725
ca971540
CD		 17262002-02-27 Chris Demetriou <cgd@broadcom.com>
1727
1728 * mips.igen (check_u64): New function which in the future will
1729 check whether 64-bit instructions are usable and signal an
1730 exception if not. Currently a no-op.
1731 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1732 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1733 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1734 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1735
1736 * mips.igen (check_fpu): New function which in the future will
1737 check whether FPU instructions are usable and signal an exception
1738 if not. Currently a no-op.
1739 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1740 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1741 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1742 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1743 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1744 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1745 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1746 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1747
1c47a468
CD		 17482002-02-27 Chris Demetriou <cgd@broadcom.com>
1749
1750 * mips.igen (do_load_left, do_load_right): Move to be immediately
1751 following do_load.
1752 (do_store_left, do_store_right): Move to be immediately following
1753 do_store.
1754
603a98e7
CD		 17552002-02-27 Chris Demetriou <cgd@broadcom.com>
1756
1757 * mips.igen (mipsV): New model name. Also, add it to
1758 all instructions and functions where it is appropriate.
1759
c5d00cc7
CD		 17602002-02-18 Chris Demetriou <cgd@broadcom.com>
1761
1762 * mips.igen: For all functions and instructions, list model
1763 names that support that instruction one per line.
1764
074e9cb8
CD		 17652002-02-11 Chris Demetriou <cgd@broadcom.com>
1766
1767 * mips.igen: Add some additional comments about supported
1768 models, and about which instructions go where.
1769 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1770 order as is used in the rest of the file.
1771
9805e229
CD		 17722002-02-11 Chris Demetriou <cgd@broadcom.com>
1773
1774 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1775 indicating that ALU32_END or ALU64_END are there to check
1776 for overflow.
1777 (DADD): Likewise, but also remove previous comment about
1778 overflow checking.
1779
f701dad2
CD		 17802002-02-10 Chris Demetriou <cgd@broadcom.com>
1781
1782 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1783 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1784 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1785 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1786 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1787 fields (i.e., add and move commas) so that they more closely
1788 match the MIPS ISA documentation opcode partitioning.
1789
17902002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1791
72f4393d
L		 1792 * mips.igen (ADDI): Print immediate value.
1793 (BREAK): Print code.
1794 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1795 (SLL): Print "nop" specially, and don't run the code
1796 that does the shift for the "nop" case.
20ae0098 1797
9e52972e
FF		 17982001-11-17 Fred Fish <fnf@redhat.com>
1799
1800 * sim-main.h (float_operation): Move enum declaration outside
1801 of _sim_cpu struct declaration.
1802
c0efbca4
JB		 18032001-04-12 Jim Blandy <jimb@redhat.com>
1804
1805 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1806 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1807 set of the FCSR.
1808 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1809 PENDING_FILL, and you can get the intended effect gracefully by
1810 calling PENDING_SCHED directly.
1811
fb891446
BE		 18122001-02-23 Ben Elliston <bje@redhat.com>
1813
1814 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1815 already defined elsewhere.
1816
8030f857
BE		 18172001-02-19 Ben Elliston <bje@redhat.com>
1818
1819 * sim-main.h (sim_monitor): Return an int.
1820 * interp.c (sim_monitor): Add return values.
1821 (signal_exception): Handle error conditions from sim_monitor.
1822
56b48a7a
CD		 18232001-02-08 Ben Elliston <bje@redhat.com>
1824
1825 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1826 (store_memory): Likewise, pass cia to sim_core_write*.
1827
d3ee60d9
FCE		 18282000-10-19 Frank Ch. Eigler <fche@redhat.com>
1829
1830 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1831 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1832
071da002
AC		 1833Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1834
1835 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1836 * Makefile.in: Don't delete *.igen when cleaning directory.
1837
a28c02cd
AC		 1838Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1839
1840 * m16.igen (break): Call SignalException not sim_engine_halt.
1841
80ee11fa
AC		 1842Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1843
1844 From Jason Eckhardt:
1845 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1846
673388c0
AC		 1847Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1848
1849 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1850
4c0deff4
NC		 18512000-05-24 Michael Hayes <mhayes@cygnus.com>
1852
1853 * mips.igen (do_dmultx): Fix typo.
1854
eb2d80b4
AC		 1855Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1856
1857 * configure: Regenerated to track ../common/aclocal.m4 changes.
1858
dd37a34b
AC		 1859Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1860
1861 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1862
4c0deff4
NC		 18632000-04-12 Frank Ch. Eigler <fche@redhat.com>
1864
1865 * sim-main.h (GPR_CLEAR): Define macro.
1866
e30db738
AC		 1867Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1868
1869 * interp.c (decode_coproc): Output long using %lx and not %s.
1870
cb7450ea
FCE		 18712000-03-21 Frank Ch. Eigler <fche@redhat.com>
1872
1873 * interp.c (sim_open): Sort & extend dummy memory regions for
1874 --board=jmr3904 for eCos.
1875
a3027dd7
FCE		 18762000-03-02 Frank Ch. Eigler <fche@redhat.com>
1877
1878 * configure: Regenerated.
1879
1880Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1881
1882 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1883 calls, conditional on the simulator being in verbose mode.
1884
dfcd3bfb
JM		 1885Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1886
1887 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1888 cache don't get ReservedInstruction traps.
1889
c2d11a7d
JM		 18901999-11-29 Mark Salter <msalter@cygnus.com>
1891
1892 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1893 to clear status bits in sdisr register. This is how the hardware works.
1894
1895 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1896 being used by cygmon.
1897
4ce44c66
JM		 18981999-11-11 Andrew Haley <aph@cygnus.com>
1899
1900 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1901 instructions.
1902
cff3e48b
JM		 1903Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1904
1905 * mips.igen (MULT): Correct previous mis-applied patch.
1906
d4f3574e
SS		 1907Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1908
1909 * mips.igen (delayslot32): Handle sequence like
1910 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1911 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1912 (MULT): Actually pass the third register...
1913
19141999-09-03 Mark Salter <msalter@cygnus.com>
1915
1916 * interp.c (sim_open): Added more memory aliases for additional
1917 hardware being touched by cygmon on jmr3904 board.
1918
1919Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1920
1921 * configure: Regenerated to track ../common/aclocal.m4 changes.
1922
a0b3c4fd
JM		 1923Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1924
1925 * interp.c (sim_store_register): Handle case where client - GDB -
1926 specifies that a 4 byte register is 8 bytes in size.
1927 (sim_fetch_register): Ditto.
72f4393d 1928
adf40b2e
JM		 19291999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1930
1931 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1932 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1933 (idt_monitor_base): Base address for IDT monitor traps.
1934 (pmon_monitor_base): Ditto for PMON.
1935 (lsipmon_monitor_base): Ditto for LSI PMON.
1936 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1937 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1938 (sim_firmware_command): New function.
1939 (mips_option_handler): Call it for OPTION_FIRMWARE.
1940 (sim_open): Allocate memory for idt_monitor region. If "--board"
1941 option was given, add no monitor by default. Add BREAK hooks only if
1942 monitors are also there.
72f4393d 1943
43e526b9
JM		 1944Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1945
1946 * interp.c (sim_monitor): Flush output before reading input.
1947
1948Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1949
1950 * tconfig.in (SIM_HANDLES_LMA): Always define.
1951
1952Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1953
1954 From Mark Salter <msalter@cygnus.com>:
1955 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1956 (sim_open): Add setup for BSP board.
1957
9846de1b
JM		 1958Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1959
1960 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1961 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1962 them as unimplemented.
1963
cd0fc7c3
SS		 19641999-05-08 Felix Lee <flee@cygnus.com>
1965
1966 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1967
7a292a7a
SS		 19681999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1969
1970 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1971
1972Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1973
1974 * configure.in: Any mips64vr5*-*-* target should have
1975 -DTARGET_ENABLE_FR=1.
1976 (default_endian): Any mips64vr*el-*-* target should default to
1977 LITTLE_ENDIAN.
1978 * configure: Re-generate.
1979
19801999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1981
1982 * mips.igen (ldl): Extend from _16_, not 32.
1983
1984Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1985
1986 * interp.c (sim_store_register): Force registers written to by GDB
1987 into an un-interpreted state.
1988
c906108c
SS		 19891999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1990
1991 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1992 CPU, start periodic background I/O polls.
72f4393d 1993 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 1994
19951998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1996
1997 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 1998
c906108c
SS		 1999Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
2000
2001 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
2002 case statement.
2003
20041998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 2005
2006 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 2007 (load_word): Call SIM_CORE_SIGNAL hook on error.
2008 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
2009 starting. For exception dispatching, pass PC instead of NULL_CIA.
2010 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 2011 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 2012 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
2013 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 2014 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 2015 * mips.igen (*): Replace memory-related SignalException* calls
2016 with references to SIM_CORE_SIGNAL hook.
72f4393d 2017
c906108c
SS		 2018 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
2019 fix.
2020 * sim-main.c (*): Minor warning cleanups.
72f4393d 2021
c906108c
SS		 20221998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
2023
2024 * m16.igen (DADDIU5): Correct type-o.
2025
2026Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
2027
2028 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
2029 variables.
2030
2031Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
2032
2033 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
2034 to include path.
2035 (interp.o): Add dependency on itable.h
2036 (oengine.c, gencode): Delete remaining references.
2037 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 2038
c906108c 20391998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 2040
c906108c
SS		 2041 * vr4run.c: New.
2042 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
2043 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
2044 tmp-run-hack) : New.
2045 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 2046 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 2047 Drop the "64" qualifier to get the HACK generator working.
2048 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
2049 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
2050 qualifier to get the hack generator working.
2051 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
2052 (DSLL): Use do_dsll.
2053 (DSLLV): Use do_dsllv.
2054 (DSRA): Use do_dsra.
2055 (DSRL): Use do_dsrl.
2056 (DSRLV): Use do_dsrlv.
2057 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 2058 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 2059 get the HACK generator working.
2060 (MACC) Rename to get the HACK generator working.
2061 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 2062
c906108c
SS		 20631998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
2064
2065 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
2066 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 2067
c906108c
SS		 20681998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
2069
2070 * mips/interp.c (DEBUG): Cleanups.
2071
20721998-12-10 Frank Ch. Eigler <fche@cygnus.com>
2073
2074 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
2075 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 2076
c906108c
SS		 20771998-12-03 Frank Ch. Eigler <fche@cygnus.com>
2078
2079 * interp.c (sim_close): Uninstall modules.
2080
2081Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
2082
2083 * sim-main.h, interp.c (sim_monitor): Change to global
2084 function.
2085
2086Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2087
2088 * configure.in (vr4100): Only include vr4100 instructions in
2089 simulator.
2090 * configure: Re-generate.
2091 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
2092
2093Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
2094
2095 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
2096 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
2097 true alternative.
2098
2099 * configure.in (sim_default_gen, sim_use_gen): Replace with
2100 sim_gen.
2101 (--enable-sim-igen): Delete config option. Always using IGEN.
2102 * configure: Re-generate.
72f4393d 2103
c906108c
SS		 2104 * Makefile.in (gencode): Kill, kill, kill.
2105 * gencode.c: Ditto.
72f4393d 2106
c906108c
SS		 2107Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
2108
2109 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
2110 bit mips16 igen simulator.
2111 * configure: Re-generate.
2112
2113 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
2114 as part of vr4100 ISA.
2115 * vr.igen: Mark all instructions as 64 bit only.
2116
2117Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2118
2119 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
2120 Pacify GCC.
2121
2122Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
2123
2124 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
2125 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
2126 * configure: Re-generate.
2127
2128 * m16.igen (BREAK): Define breakpoint instruction.
2129 (JALX32): Mark instruction as mips16 and not r3900.
2130 * mips.igen (C.cond.fmt): Fix typo in instruction format.
2131
2132 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
2133
2134Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2135
2136 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
2137 insn as a debug breakpoint.
2138
2139 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
2140 pending.slot_size.
2141 (PENDING_SCHED): Clean up trace statement.
2142 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
2143 (PENDING_FILL): Delay write by only one cycle.
2144 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
2145
2146 * sim-main.c (pending_tick): Clean up trace statements. Add trace
2147 of pending writes.
2148 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
2149 32 & 64.
2150 (pending_tick): Move incrementing of index to FOR statement.
2151 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 2152
c906108c
SS		 2153 * configure.in: Add explicit mips-lsi-* target. Use gencode to
2154 build simulator.
2155 * configure: Re-generate.
72f4393d 2156
c906108c
SS		 2157 * interp.c (sim_engine_run OLD): Delete explicit call to
2158 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 2159
c906108c
SS		 2160Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
2161
2162 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
2163 interrupt level number to match changed SignalExceptionInterrupt
2164 macro.
2165
2166Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
2167
2168 * interp.c: #include "itable.h" if WITH_IGEN.
2169 (get_insn_name): New function.
2170 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
2171 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
2172
2173Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
2174
2175 * configure: Rebuilt to inhale new common/aclocal.m4.
2176
2177Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
2178
2179 * dv-tx3904sio.c: Include sim-assert.h.
2180
2181Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
2182
2183 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
2184 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
2185 Reorganize target-specific sim-hardware checks.
2186 * configure: rebuilt.
2187 * interp.c (sim_open): For tx39 target boards, set
2188 OPERATING_ENVIRONMENT, add tx3904sio devices.
2189 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
2190 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 2191
c906108c
SS		 2192 * dv-tx3904irc.c: Compiler warning clean-up.
2193 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
2194 frequent hw-trace messages.
2195
2196Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
2197
2198 * vr.igen (MulAcc): Identify as a vr4100 specific function.
2199
2200Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2201
2202 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
2203
2204 * vr.igen: New file.
2205 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
2206 * mips.igen: Define vr4100 model. Include vr.igen.
2207Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
2208
2209 * mips.igen (check_mf_hilo): Correct check.
2210
2211Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2212
2213 * sim-main.h (interrupt_event): Add prototype.
2214
2215 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
2216 register_ptr, register_value.
2217 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
2218
2219 * sim-main.h (tracefh): Make extern.
2220
2221Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
2222
2223 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 2224 Reduce unnecessarily high timer event frequency.
c906108c 2225 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 2226
c906108c
SS		 2227Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
2228
2229 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
2230 to allay warnings.
2231 (interrupt_event): Made non-static.
72f4393d 2232
c906108c
SS		 2233 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
2234 interchange of configuration values for external vs. internal
2235 clock dividers.
72f4393d 2236
c906108c
SS		 2237Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
2238
72f4393d 2239 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 2240 simulator-reserved break instructions.
2241 * gencode.c (build_instruction): Ditto.
2242 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 2243 reserved instructions now use exception vector, rather
c906108c
SS		 2244 than halting sim.
2245 * sim-main.h: Moved magic constants to here.
2246
2247Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
2248
2249 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
2250 register upon non-zero interrupt event level, clear upon zero
2251 event value.
2252 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
2253 by passing zero event value.
2254 (*_io_{read,write}_buffer): Endianness fixes.
2255 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
2256 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
2257
2258 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
2259 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 2260
c906108c
SS		 2261Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
2262
72f4393d 2263 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 2264 and BigEndianCPU.
2265
2266Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
2267
2268 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
2269 parts.
2270 * configure: Update.
2271
2272Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
2273
2274 * dv-tx3904tmr.c: New file - implements tx3904 timer.
2275 * dv-tx3904{irc,cpu}.c: Mild reformatting.
2276 * configure.in: Include tx3904tmr in hw_device list.
2277 * configure: Rebuilt.
2278 * interp.c (sim_open): Instantiate three timer instances.
2279 Fix address typo of tx3904irc instance.
2280
2281Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
2282
2283 * interp.c (signal_exception): SystemCall exception now uses
2284 the exception vector.
2285
2286Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
2287
2288 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
2289 to allay warnings.
2290
2291Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2292
2293 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
2294
2295Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
2296
2297 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
2298
2299 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
2300 sim-main.h. Declare a struct hw_descriptor instead of struct
2301 hw_device_descriptor.
2302
2303Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2304
2305 * mips.igen (do_store_left, do_load_left): Compute nr of left and
2306 right bits and then re-align left hand bytes to correct byte
2307 lanes. Fix incorrect computation in do_store_left when loading
2308 bytes from second word.
2309
2310Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2311
2312 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
2313 * interp.c (sim_open): Only create a device tree when HW is
2314 enabled.
2315
2316 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
2317 * interp.c (signal_exception): Ditto.
2318
2319Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
2320
2321 * gencode.c: Mark BEGEZALL as LIKELY.
2322
2323Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
2324
2325 * sim-main.h (ALU32_END): Sign extend 32 bit results.
2326 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 2327
c906108c
SS		 2328Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2329
2330 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2331 modules. Recognize TX39 target with "mips*tx39" pattern.
2332 * configure: Rebuilt.
2333 * sim-main.h (*): Added many macros defining bits in
2334 TX39 control registers.
2335 (SignalInterrupt): Send actual PC instead of NULL.
2336 (SignalNMIReset): New exception type.
2337 * interp.c (board): New variable for future use to identify
2338 a particular board being simulated.
2339 (mips_option_handler,mips_options): Added "--board" option.
2340 (interrupt_event): Send actual PC.
2341 (sim_open): Make memory layout conditional on board setting.
2342 (signal_exception): Initial implementation of hardware interrupt
2343 handling. Accept another break instruction variant for simulator
2344 exit.
2345 (decode_coproc): Implement RFE instruction for TX39.
2346 (mips.igen): Decode RFE instruction as such.
2347 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2348 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2349 bbegin to implement memory map.
2350 * dv-tx3904cpu.c: New file.
2351 * dv-tx3904irc.c: New file.
2352
2353Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2354
2355 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2356
2357Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2358
2359 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2360 with calls to check_div_hilo.
2361
2362Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2363
2364 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2365 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2366 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2367 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2368 with calls to check_mult_hilo.
2369 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2370 with calls to check_div_hilo.
2371
2372Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2373
2374 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2375 Document a replacement.
2376
2377Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2378
2379 * interp.c (sim_monitor): Make mon_printf work.
2380
2381Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2382
2383 * sim-main.h (INSN_NAME): New arg `cpu'.
2384
2385Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2386
72f4393d 2387 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2388
2389Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2390
2391 * configure: Regenerated to track ../common/aclocal.m4 changes.
2392 * config.in: Ditto.
2393
2394Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2395
2396 * acconfig.h: New file.
2397 * configure.in: Reverted change of Apr 24; use sinclude again.
2398
2399Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2400
2401 * configure: Regenerated to track ../common/aclocal.m4 changes.
2402 * config.in: Ditto.
2403
2404Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2405
2406 * configure.in: Don't call sinclude.
2407
2408Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2409
2410 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2411
2412Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2413
2414 * mips.igen (ERET): Implement.
2415
2416 * interp.c (decode_coproc): Return sign-extended EPC.
2417
2418 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2419
2420 * interp.c (signal_exception): Do not ignore Trap.
2421 (signal_exception): On TRAP, restart at exception address.
2422 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2423 (signal_exception): Update.
2424 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2425 so that TRAP instructions are caught.
2426
2427Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2428
2429 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2430 contains HI/LO access history.
2431 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2432 (HIACCESS, LOACCESS): Delete, replace with
2433 (HIHISTORY, LOHISTORY): New macros.
2434 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2435
c906108c
SS		 2436 * gencode.c (build_instruction): Do not generate checks for
2437 correct HI/LO register usage.
2438
2439 * interp.c (old_engine_run): Delete checks for correct HI/LO
2440 register usage.
2441
2442 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2443 check_mf_cycles): New functions.
2444 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2445 do_divu, domultx, do_mult, do_multu): Use.
2446
2447 * tx.igen ("madd", "maddu"): Use.
72f4393d 2448
c906108c
SS		 2449Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2450
2451 * mips.igen (DSRAV): Use function do_dsrav.
2452 (SRAV): Use new function do_srav.
2453
2454 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2455 (B): Sign extend 11 bit immediate.
2456 (EXT-B*): Shift 16 bit immediate left by 1.
2457 (ADDIU*): Don't sign extend immediate value.
2458
2459Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2460
2461 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2462
2463 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2464 functions.
2465
2466 * mips.igen (delayslot32, nullify_next_insn): New functions.
2467 (m16.igen): Always include.
2468 (do_*): Add more tracing.
2469
2470 * m16.igen (delayslot16): Add NIA argument, could be called by a
2471 32 bit MIPS16 instruction.
72f4393d 2472
c906108c
SS		 2473 * interp.c (ifetch16): Move function from here.
2474 * sim-main.c (ifetch16): To here.
72f4393d 2475
c906108c
SS		 2476 * sim-main.c (ifetch16, ifetch32): Update to match current
2477 implementations of LH, LW.
2478 (signal_exception): Don't print out incorrect hex value of illegal
2479 instruction.
2480
2481Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2482
2483 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2484 instruction.
2485
2486 * m16.igen: Implement MIPS16 instructions.
72f4393d 2487
c906108c
SS		 2488 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2489 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2490 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2491 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2492 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2493 bodies of corresponding code from 32 bit insn to these. Also used
2494 by MIPS16 versions of functions.
72f4393d 2495
c906108c
SS		 2496 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2497 (IMEM16): Drop NR argument from macro.
2498
2499Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2500
2501 * Makefile.in (SIM_OBJS): Add sim-main.o.
2502
2503 * sim-main.h (address_translation, load_memory, store_memory,
2504 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2505 as INLINE_SIM_MAIN.
2506 (pr_addr, pr_uword64): Declare.
2507 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2508
c906108c
SS		 2509 * interp.c (address_translation, load_memory, store_memory,
2510 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2511 from here.
2512 * sim-main.c: To here. Fix compilation problems.
72f4393d 2513
c906108c
SS		 2514 * configure.in: Enable inlining.
2515 * configure: Re-config.
2516
2517Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2518
2519 * configure: Regenerated to track ../common/aclocal.m4 changes.
2520
2521Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2522
2523 * mips.igen: Include tx.igen.
2524 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2525 * tx.igen: New file, contains MADD and MADDU.
2526
2527 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2528 the hardwired constant `7'.
2529 (store_memory): Ditto.
2530 (LOADDRMASK): Move definition to sim-main.h.
2531
2532 mips.igen (MTC0): Enable for r3900.
2533 (ADDU): Add trace.
2534
2535 mips.igen (do_load_byte): Delete.
2536 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2537 do_store_right): New functions.
2538 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2539
2540 configure.in: Let the tx39 use igen again.
2541 configure: Update.
72f4393d 2542
c906108c
SS		 2543Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2544
2545 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2546 not an address sized quantity. Return zero for cache sizes.
2547
2548Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2549
2550 * mips.igen (r3900): r3900 does not support 64 bit integer
2551 operations.
2552
2553Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2554
2555 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2556 than igen one.
2557 * configure : Rebuild.
72f4393d 2558
c906108c
SS		 2559Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2560
2561 * configure: Regenerated to track ../common/aclocal.m4 changes.
2562
2563Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2564
2565 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2566
2567Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2568
2569 * configure: Regenerated to track ../common/aclocal.m4 changes.
2570 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2571
2572Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2573
2574 * configure: Regenerated to track ../common/aclocal.m4 changes.
2575
2576Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2577
2578 * interp.c (Max, Min): Comment out functions. Not yet used.
2579
2580Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2581
2582 * configure: Regenerated to track ../common/aclocal.m4 changes.
2583
2584Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2585
2586 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2587 configurable settings for stand-alone simulator.
72f4393d 2588
c906108c 2589 * configure.in: Added X11 search, just in case.
72f4393d 2590
c906108c
SS		 2591 * configure: Regenerated.
2592
2593Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2594
2595 * interp.c (sim_write, sim_read, load_memory, store_memory):
2596 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2597
2598Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2599
2600 * sim-main.h (GETFCC): Return an unsigned value.
2601
2602Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2603
2604 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2605 (DADD): Result destination is RD not RT.
2606
2607Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2608
2609 * sim-main.h (HIACCESS, LOACCESS): Always define.
2610
2611 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2612
2613 * interp.c (sim_info): Delete.
2614
2615Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2616
2617 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2618 (mips_option_handler): New argument `cpu'.
2619 (sim_open): Update call to sim_add_option_table.
2620
2621Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2622
2623 * mips.igen (CxC1): Add tracing.
2624
2625Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2626
2627 * sim-main.h (Max, Min): Declare.
2628
2629 * interp.c (Max, Min): New functions.
2630
2631 * mips.igen (BC1): Add tracing.
72f4393d 2632
c906108c 2633Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2634
c906108c 2635 * interp.c Added memory map for stack in vr4100
72f4393d 2636
c906108c
SS		 2637Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2638
2639 * interp.c (load_memory): Add missing "break"'s.
2640
2641Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2642
2643 * interp.c (sim_store_register, sim_fetch_register): Pass in
2644 length parameter. Return -1.
2645
2646Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2647
2648 * interp.c: Added hardware init hook, fixed warnings.
2649
2650Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2651
2652 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2653
2654Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2655
2656 * interp.c (ifetch16): New function.
2657
2658 * sim-main.h (IMEM32): Rename IMEM.
2659 (IMEM16_IMMED): Define.
2660 (IMEM16): Define.
2661 (DELAY_SLOT): Update.
72f4393d 2662
c906108c 2663 * m16run.c (sim_engine_run): New file.
72f4393d 2664
c906108c
SS		 2665 * m16.igen: All instructions except LB.
2666 (LB): Call do_load_byte.
2667 * mips.igen (do_load_byte): New function.
2668 (LB): Call do_load_byte.
2669
2670 * mips.igen: Move spec for insn bit size and high bit from here.
2671 * Makefile.in (tmp-igen, tmp-m16): To here.
2672
2673 * m16.dc: New file, decode mips16 instructions.
2674
2675 * Makefile.in (SIM_NO_ALL): Define.
2676 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2677
2678Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2679
2680 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2681 point unit to 32 bit registers.
2682 * configure: Re-generate.
2683
2684Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2685
2686 * configure.in (sim_use_gen): Make IGEN the default simulator
2687 generator for generic 32 and 64 bit mips targets.
2688 * configure: Re-generate.
2689
2690Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2691
2692 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2693 bitsize.
2694
2695 * interp.c (sim_fetch_register, sim_store_register): Read/write
2696 FGR from correct location.
2697 (sim_open): Set size of FGR's according to
2698 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2699
c906108c
SS		 2700 * sim-main.h (FGR): Store floating point registers in a separate
2701 array.
2702
2703Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2704
2705 * configure: Regenerated to track ../common/aclocal.m4 changes.
2706
2707Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2708
2709 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2710
2711 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2712
2713 * interp.c (pending_tick): New function. Deliver pending writes.
2714
2715 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2716 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2717 it can handle mixed sized quantites and single bits.
72f4393d 2718
c906108c
SS		 2719Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2720
2721 * interp.c (oengine.h): Do not include when building with IGEN.
2722 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2723 (sim_info): Ditto for PROCESSOR_64BIT.
2724 (sim_monitor): Replace ut_reg with unsigned_word.
2725 (*): Ditto for t_reg.
2726 (LOADDRMASK): Define.
2727 (sim_open): Remove defunct check that host FP is IEEE compliant,
2728 using software to emulate floating point.
2729 (value_fpr, ...): Always compile, was conditional on HASFPU.
2730
2731Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2732
2733 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2734 size.
2735
2736 * interp.c (SD, CPU): Define.
2737 (mips_option_handler): Set flags in each CPU.
2738 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2739 (sim_close): Do not clear STATE, deleted anyway.
2740 (sim_write, sim_read): Assume CPU zero's vm should be used for
2741 data transfers.
2742 (sim_create_inferior): Set the PC for all processors.
2743 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2744 argument.
2745 (mips16_entry): Pass correct nr of args to store_word, load_word.
2746 (ColdReset): Cold reset all cpu's.
2747 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2748 (sim_monitor, load_memory, store_memory, signal_exception): Use
2749 `CPU' instead of STATE_CPU.
2750
2751
2752 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2753 SD or CPU_.
72f4393d 2754
c906108c
SS		 2755 * sim-main.h (signal_exception): Add sim_cpu arg.
2756 (SignalException*): Pass both SD and CPU to signal_exception.
2757 * interp.c (signal_exception): Update.
72f4393d 2758
c906108c
SS		 2759 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2760 Ditto
2761 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2762 address_translation): Ditto
2763 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2764
c906108c
SS		 2765Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2766
2767 * configure: Regenerated to track ../common/aclocal.m4 changes.
2768
2769Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2770
2771 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2772
72f4393d 2773 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2774
2775 * sim-main.h (CPU_CIA): Delete.
2776 (SET_CIA, GET_CIA): Define
2777
2778Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2779
2780 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2781 regiser.
2782
2783 * configure.in (default_endian): Configure a big-endian simulator
2784 by default.
2785 * configure: Re-generate.
72f4393d 2786
c906108c
SS		 2787Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2788
2789 * configure: Regenerated to track ../common/aclocal.m4 changes.
2790
2791Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2792
2793 * interp.c (sim_monitor): Handle Densan monitor outbyte
2794 and inbyte functions.
2795
27961997-12-29 Felix Lee <flee@cygnus.com>
2797
2798 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2799
2800Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2801
2802 * Makefile.in (tmp-igen): Arrange for $zero to always be
2803 reset to zero after every instruction.
2804
2805Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2806
2807 * configure: Regenerated to track ../common/aclocal.m4 changes.
2808 * config.in: Ditto.
2809
2810Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2811
2812 * mips.igen (MSUB): Fix to work like MADD.
2813 * gencode.c (MSUB): Similarly.
2814
2815Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2816
2817 * configure: Regenerated to track ../common/aclocal.m4 changes.
2818
2819Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2820
2821 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2822
2823Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2824
2825 * sim-main.h (sim-fpu.h): Include.
2826
2827 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2828 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2829 using host independant sim_fpu module.
2830
2831Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2832
2833 * interp.c (signal_exception): Report internal errors with SIGABRT
2834 not SIGQUIT.
2835
2836 * sim-main.h (C0_CONFIG): New register.
2837 (signal.h): No longer include.
2838
2839 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2840
2841Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2842
2843 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2844
2845Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2846
2847 * mips.igen: Tag vr5000 instructions.
2848 (ANDI): Was missing mipsIV model, fix assembler syntax.
2849 (do_c_cond_fmt): New function.
2850 (C.cond.fmt): Handle mips I-III which do not support CC field
2851 separatly.
2852 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2853 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2854 in IV3.2 spec.
2855 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2856 vr5000 which saves LO in a GPR separatly.
72f4393d 2857
c906108c
SS		 2858 * configure.in (enable-sim-igen): For vr5000, select vr5000
2859 specific instructions.
2860 * configure: Re-generate.
72f4393d 2861
c906108c
SS		 2862Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2863
2864 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2865
2866 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2867 fmt_uninterpreted_64 bit cases to switch. Convert to
2868 fmt_formatted,
2869
2870 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2871
2872 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2873 as specified in IV3.2 spec.
2874 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2875
2876Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2877
2878 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2879 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2880 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2881 PENDING_FILL versions of instructions. Simplify.
2882 (X): New function.
2883 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2884 instructions.
2885 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2886 a signed value.
2887 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2888
c906108c
SS		 2889 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2890 global.
2891 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2892
2893Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2894
2895 * gencode.c (build_mips16_operands): Replace IPC with cia.
2896
2897 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2898 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2899 IPC to `cia'.
2900 (UndefinedResult): Replace function with macro/function
2901 combination.
2902 (sim_engine_run): Don't save PC in IPC.
2903
2904 * sim-main.h (IPC): Delete.
2905
2906
2907 * interp.c (signal_exception, store_word, load_word,
2908 address_translation, load_memory, store_memory, cache_op,
2909 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2910 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2911 current instruction address - cia - argument.
2912 (sim_read, sim_write): Call address_translation directly.
2913 (sim_engine_run): Rename variable vaddr to cia.
2914 (signal_exception): Pass cia to sim_monitor
72f4393d 2915
c906108c
SS		 2916 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2917 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2918 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2919
2920 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2921 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2922 SIM_ASSERT.
72f4393d 2923
c906108c
SS		 2924 * interp.c (signal_exception): Pass restart address to
2925 sim_engine_restart.
2926
2927 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2928 idecode.o): Add dependency.
2929
2930 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2931 Delete definitions
2932 (DELAY_SLOT): Update NIA not PC with branch address.
2933 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2934
2935 * mips.igen: Use CIA not PC in branch calculations.
2936 (illegal): Call SignalException.
2937 (BEQ, ADDIU): Fix assembler.
2938
2939Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2940
2941 * m16.igen (JALX): Was missing.
2942
2943 * configure.in (enable-sim-igen): New configuration option.
2944 * configure: Re-generate.
72f4393d 2945
c906108c
SS		 2946 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2947
2948 * interp.c (load_memory, store_memory): Delete parameter RAW.
2949 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2950 bypassing {load,store}_memory.
2951
2952 * sim-main.h (ByteSwapMem): Delete definition.
2953
2954 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2955
2956 * interp.c (sim_do_command, sim_commands): Delete mips specific
2957 commands. Handled by module sim-options.
72f4393d 2958
c906108c
SS		 2959 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2960 (WITH_MODULO_MEMORY): Define.
2961
2962 * interp.c (sim_info): Delete code printing memory size.
2963
2964 * interp.c (mips_size): Nee sim_size, delete function.
2965 (power2): Delete.
2966 (monitor, monitor_base, monitor_size): Delete global variables.
2967 (sim_open, sim_close): Delete code creating monitor and other
2968 memory regions. Use sim-memopts module, via sim_do_commandf, to
2969 manage memory regions.
2970 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2971
c906108c
SS		 2972 * interp.c (address_translation): Delete all memory map code
2973 except line forcing 32 bit addresses.
2974
2975Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2976
2977 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2978 trace options.
2979
2980 * interp.c (logfh, logfile): Delete globals.
2981 (sim_open, sim_close): Delete code opening & closing log file.
2982 (mips_option_handler): Delete -l and -n options.
2983 (OPTION mips_options): Ditto.
2984
2985 * interp.c (OPTION mips_options): Rename option trace to dinero.
2986 (mips_option_handler): Update.
2987
2988Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2989
2990 * interp.c (fetch_str): New function.
2991 (sim_monitor): Rewrite using sim_read & sim_write.
2992 (sim_open): Check magic number.
2993 (sim_open): Write monitor vectors into memory using sim_write.
2994 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2995 (sim_read, sim_write): Simplify - transfer data one byte at a
2996 time.
2997 (load_memory, store_memory): Clarify meaning of parameter RAW.
2998
2999 * sim-main.h (isHOST): Defete definition.
3000 (isTARGET): Mark as depreciated.
3001 (address_translation): Delete parameter HOST.
3002
3003 * interp.c (address_translation): Delete parameter HOST.
3004
3005Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3006
72f4393d 3007 * mips.igen:
c906108c
SS		 3008
3009 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
3010 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
3011
3012Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
3013
3014 * mips.igen: Add model filter field to records.
3015
3016Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
3017
3018 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 3019
c906108c
SS		 3020 interp.c (sim_engine_run): Do not compile function sim_engine_run
3021 when WITH_IGEN == 1.
3022
3023 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
3024 target architecture.
3025
3026 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
3027 igen. Replace with configuration variables sim_igen_flags /
3028 sim_m16_flags.
3029
3030 * m16.igen: New file. Copy mips16 insns here.
3031 * mips.igen: From here.
3032
3033Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
3034
3035 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
3036 to top.
3037 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
3038
3039Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
3040
3041 * gencode.c (build_instruction): Follow sim_write's lead in using
3042 BigEndianMem instead of !ByteSwapMem.
3043
3044Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
3045
3046 * configure.in (sim_gen): Dependent on target, select type of
3047 generator. Always select old style generator.
3048
3049 configure: Re-generate.
3050
3051 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
3052 targets.
3053 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
3054 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
3055 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
3056 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
3057 SIM_@sim_gen@_*, set by autoconf.
72f4393d 3058
c906108c
SS		 3059Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3060
3061 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
3062
3063 * interp.c (ColdReset): Remove #ifdef HASFPU, check
3064 CURRENT_FLOATING_POINT instead.
3065
3066 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
3067 (address_translation): Raise exception InstructionFetch when
3068 translation fails and isINSTRUCTION.
72f4393d 3069
c906108c
SS		 3070 * interp.c (sim_open, sim_write, sim_monitor, store_word,
3071 sim_engine_run): Change type of of vaddr and paddr to
3072 address_word.
3073 (address_translation, prefetch, load_memory, store_memory,
3074 cache_op): Change type of vAddr and pAddr to address_word.
3075
3076 * gencode.c (build_instruction): Change type of vaddr and paddr to
3077 address_word.
3078
3079Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
3080
3081 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
3082 macro to obtain result of ALU op.
3083
3084Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3085
3086 * interp.c (sim_info): Call profile_print.
3087
3088Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3089
3090 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
3091
3092 * sim-main.h (WITH_PROFILE): Do not define, defined in
3093 common/sim-config.h. Use sim-profile module.
3094 (simPROFILE): Delete defintion.
3095
3096 * interp.c (PROFILE): Delete definition.
3097 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
3098 (sim_close): Delete code writing profile histogram.
3099 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
3100 Delete.
3101 (sim_engine_run): Delete code profiling the PC.
3102
3103Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3104
3105 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
3106
3107 * interp.c (sim_monitor): Make register pointers of type
3108 unsigned_word*.
3109
3110 * sim-main.h: Make registers of type unsigned_word not
3111 signed_word.
3112
3113Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3114
3115 * interp.c (sync_operation): Rename from SyncOperation, make
3116 global, add SD argument.
3117 (prefetch): Rename from Prefetch, make global, add SD argument.
3118 (decode_coproc): Make global.
3119
3120 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
3121
3122 * gencode.c (build_instruction): Generate DecodeCoproc not
3123 decode_coproc calls.
3124
3125 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
3126 (SizeFGR): Move to sim-main.h
3127 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
3128 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
3129 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
3130 sim-main.h.
3131 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
3132 FP_RM_TOMINF, GETRM): Move to sim-main.h.
3133 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
3134 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
3135 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
3136 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 3137
c906108c
SS		 3138 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
3139 exception.
3140 (sim-alu.h): Include.
3141 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
3142 (sim_cia): Typedef to instruction_address.
72f4393d 3143
c906108c
SS		 3144Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
3145
3146 * Makefile.in (interp.o): Rename generated file engine.c to
3147 oengine.c.
72f4393d 3148
c906108c 3149 * interp.c: Update.
72f4393d 3150
c906108c
SS		 3151Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
3152
3153 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 3154
c906108c
SS		 3155Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3156
3157 * gencode.c (build_instruction): For "FPSQRT", output correct
3158 number of arguments to Recip.
72f4393d 3159
c906108c
SS		 3160Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
3161
3162 * Makefile.in (interp.o): Depends on sim-main.h
3163
3164 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
3165
3166 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
3167 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
3168 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
3169 STATE, DSSTATE): Define
3170 (GPR, FGRIDX, ..): Define.
3171
3172 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
3173 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
3174 (GPR, FGRIDX, ...): Delete macros.
72f4393d 3175
c906108c 3176 * interp.c: Update names to match defines from sim-main.h
72f4393d 3177
c906108c
SS		 3178Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
3179
3180 * interp.c (sim_monitor): Add SD argument.
3181 (sim_warning): Delete. Replace calls with calls to
3182 sim_io_eprintf.
3183 (sim_error): Delete. Replace calls with sim_io_error.
3184 (open_trace, writeout32, writeout16, getnum): Add SD argument.
3185 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
3186 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
3187 argument.
3188 (mips_size): Rename from sim_size. Add SD argument.
3189
3190 * interp.c (simulator): Delete global variable.
3191 (callback): Delete global variable.
3192 (mips_option_handler, sim_open, sim_write, sim_read,
3193 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
3194 sim_size,sim_monitor): Use sim_io_* not callback->*.
3195 (sim_open): ZALLOC simulator struct.
3196 (PROFILE): Do not define.
3197
3198Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3199
3200 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
3201 support.h with corresponding code.
3202
3203 * sim-main.h (word64, uword64), support.h: Move definition to
3204 sim-main.h.
3205 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
3206
3207 * support.h: Delete
3208 * Makefile.in: Update dependencies
3209 * interp.c: Do not include.
72f4393d 3210
c906108c
SS		 3211Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3212
3213 * interp.c (address_translation, load_memory, store_memory,
3214 cache_op): Rename to from AddressTranslation et.al., make global,
3215 add SD argument
72f4393d 3216
c906108c
SS		 3217 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
3218 CacheOp): Define.
72f4393d 3219
c906108c
SS		 3220 * interp.c (SignalException): Rename to signal_exception, make
3221 global.
3222
3223 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 3224
c906108c
SS		 3225 * sim-main.h (SignalException, SignalExceptionInterrupt,
3226 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
3227 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
3228 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
3229 Define.
72f4393d 3230
c906108c 3231 * interp.c, support.h: Use.
72f4393d 3232
c906108c
SS		 3233Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3234
3235 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
3236 to value_fpr / store_fpr. Add SD argument.
3237 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
3238 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
3239
3240 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 3241
c906108c
SS		 3242Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
3243
3244 * interp.c (sim_engine_run): Check consistency between configure
3245 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
3246 and HASFPU.
3247
3248 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 3249 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 3250 (mips_endian): Configure WITH_TARGET_ENDIAN.
3251 * configure: Update.
3252
3253Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3254
3255 * configure: Regenerated to track ../common/aclocal.m4 changes.
3256
3257Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
3258
3259 * configure: Regenerated.
3260
3261Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
3262
3263 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
3264
3265Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3266
3267 * gencode.c (print_igen_insn_models): Assume certain architectures
3268 include all mips* instructions.
3269 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
3270 instruction.
3271
3272 * Makefile.in (tmp.igen): Add target. Generate igen input from
3273 gencode file.
3274
3275 * gencode.c (FEATURE_IGEN): Define.
3276 (main): Add --igen option. Generate output in igen format.
3277 (process_instructions): Format output according to igen option.
3278 (print_igen_insn_format): New function.
3279 (print_igen_insn_models): New function.
3280 (process_instructions): Only issue warnings and ignore
3281 instructions when no FEATURE_IGEN.
3282
3283Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3284
3285 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
3286 MIPS targets.
3287
3288Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3289
3290 * configure: Regenerated to track ../common/aclocal.m4 changes.
3291
3292Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
3293
3294 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
3295 SIM_RESERVED_BITS): Delete, moved to common.
3296 (SIM_EXTRA_CFLAGS): Update.
72f4393d 3297
c906108c
SS		 3298Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3299
3300 * configure.in: Configure non-strict memory alignment.
3301 * configure: Regenerated to track ../common/aclocal.m4 changes.
3302
3303Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
3304
3305 * configure: Regenerated to track ../common/aclocal.m4 changes.
3306
3307Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
3308
3309 * gencode.c (SDBBP,DERET): Added (3900) insns.
3310 (RFE): Turn on for 3900.
3311 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
3312 (dsstate): Made global.
3313 (SUBTARGET_R3900): Added.
3314 (CANCELDELAYSLOT): New.
3315 (SignalException): Ignore SystemCall rather than ignore and
3316 terminate. Add DebugBreakPoint handling.
3317 (decode_coproc): New insns RFE, DERET; and new registers Debug
3318 and DEPC protected by SUBTARGET_R3900.
3319 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3320 bits explicitly.
3321 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 3322 * configure: Update.
c906108c
SS		 3323
3324Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
3325
3326 * gencode.c: Add r3900 (tx39).
72f4393d 3327
c906108c
SS		 3328
3329Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3330
3331 * gencode.c (build_instruction): Don't need to subtract 4 for
3332 JALR, just 2.
3333
3334Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3335
3336 * interp.c: Correct some HASFPU problems.
3337
3338Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3339
3340 * configure: Regenerated to track ../common/aclocal.m4 changes.
3341
3342Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3343
3344 * interp.c (mips_options): Fix samples option short form, should
3345 be `x'.
3346
3347Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3348
3349 * interp.c (sim_info): Enable info code. Was just returning.
3350
3351Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3352
3353 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3354 MFC0.
3355
3356Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3357
3358 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3359 constants.
3360 (build_instruction): Ditto for LL.
3361
3362Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3363
3364 * configure: Regenerated to track ../common/aclocal.m4 changes.
3365
3366Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3367
3368 * configure: Regenerated to track ../common/aclocal.m4 changes.
3369 * config.in: Ditto.
3370
3371Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3372
3373 * interp.c (sim_open): Add call to sim_analyze_program, update
3374 call to sim_config.
3375
3376Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3377
3378 * interp.c (sim_kill): Delete.
3379 (sim_create_inferior): Add ABFD argument. Set PC from same.
3380 (sim_load): Move code initializing trap handlers from here.
3381 (sim_open): To here.
3382 (sim_load): Delete, use sim-hload.c.
3383
3384 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3385
3386Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3387
3388 * configure: Regenerated to track ../common/aclocal.m4 changes.
3389 * config.in: Ditto.
3390
3391Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3392
3393 * interp.c (sim_open): Add ABFD argument.
3394 (sim_load): Move call to sim_config from here.
3395 (sim_open): To here. Check return status.
3396
3397Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3398
c906108c
SS		 3399 * gencode.c (build_instruction): Two arg MADD should
3400 not assign result to $0.
72f4393d 3401
c906108c
SS		 3402Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3403
3404 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3405 * sim/mips/configure.in: Regenerate.
3406
3407Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3408
3409 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3410 signed8, unsigned8 et.al. types.
3411
3412 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3413 hosts when selecting subreg.
3414
3415Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3416
3417 * interp.c (sim_engine_run): Reset the ZERO register to zero
3418 regardless of FEATURE_WARN_ZERO.
3419 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3420
3421Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3422
3423 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3424 (SignalException): For BreakPoints ignore any mode bits and just
3425 save the PC.
3426 (SignalException): Always set the CAUSE register.
3427
3428Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3429
3430 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3431 exception has been taken.
3432
3433 * interp.c: Implement the ERET and mt/f sr instructions.
3434
3435Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3436
3437 * interp.c (SignalException): Don't bother restarting an
3438 interrupt.
3439
3440Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3441
3442 * interp.c (SignalException): Really take an interrupt.
3443 (interrupt_event): Only deliver interrupts when enabled.
3444
3445Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3446
3447 * interp.c (sim_info): Only print info when verbose.
3448 (sim_info) Use sim_io_printf for output.
72f4393d 3449
c906108c
SS		 3450Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3451
3452 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3453 mips architectures.
3454
3455Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3456
3457 * interp.c (sim_do_command): Check for common commands if a
3458 simulator specific command fails.
3459
3460Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3461
3462 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3463 and simBE when DEBUG is defined.
3464
3465Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3466
3467 * interp.c (interrupt_event): New function. Pass exception event
3468 onto exception handler.
3469
3470 * configure.in: Check for stdlib.h.
3471 * configure: Regenerate.
3472
3473 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3474 variable declaration.
3475 (build_instruction): Initialize memval1.
3476 (build_instruction): Add UNUSED attribute to byte, bigend,
3477 reverse.
3478 (build_operands): Ditto.
3479
3480 * interp.c: Fix GCC warnings.
3481 (sim_get_quit_code): Delete.
3482
3483 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3484 * Makefile.in: Ditto.
3485 * configure: Re-generate.
72f4393d 3486
c906108c
SS		 3487 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3488
3489Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3490
3491 * interp.c (mips_option_handler): New function parse argumes using
3492 sim-options.
3493 (myname): Replace with STATE_MY_NAME.
3494 (sim_open): Delete check for host endianness - performed by
3495 sim_config.
3496 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3497 (sim_open): Move much of the initialization from here.
3498 (sim_load): To here. After the image has been loaded and
3499 endianness set.
3500 (sim_open): Move ColdReset from here.
3501 (sim_create_inferior): To here.
3502 (sim_open): Make FP check less dependant on host endianness.
3503
3504 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3505 run.
3506 * interp.c (sim_set_callbacks): Delete.
3507
3508 * interp.c (membank, membank_base, membank_size): Replace with
3509 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3510 (sim_open): Remove call to callback->init. gdb/run do this.
3511
3512 * interp.c: Update
3513
3514 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3515
3516 * interp.c (big_endian_p): Delete, replaced by
3517 current_target_byte_order.
3518
3519Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3520
3521 * interp.c (host_read_long, host_read_word, host_swap_word,
3522 host_swap_long): Delete. Using common sim-endian.
3523 (sim_fetch_register, sim_store_register): Use H2T.
3524 (pipeline_ticks): Delete. Handled by sim-events.
3525 (sim_info): Update.
3526 (sim_engine_run): Update.
3527
3528Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3529
3530 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3531 reason from here.
3532 (SignalException): To here. Signal using sim_engine_halt.
3533 (sim_stop_reason): Delete, moved to common.
72f4393d 3534
c906108c
SS		 3535Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3536
3537 * interp.c (sim_open): Add callback argument.
3538 (sim_set_callbacks): Delete SIM_DESC argument.
3539 (sim_size): Ditto.
3540
3541Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3542
3543 * Makefile.in (SIM_OBJS): Add common modules.
3544
3545 * interp.c (sim_set_callbacks): Also set SD callback.
3546 (set_endianness, xfer_*, swap_*): Delete.
3547 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3548 Change to functions using sim-endian macros.
3549 (control_c, sim_stop): Delete, use common version.
3550 (simulate): Convert into.
3551 (sim_engine_run): This function.
3552 (sim_resume): Delete.
72f4393d 3553
c906108c
SS		 3554 * interp.c (simulation): New variable - the simulator object.
3555 (sim_kind): Delete global - merged into simulation.
3556 (sim_load): Cleanup. Move PC assignment from here.
3557 (sim_create_inferior): To here.
3558
3559 * sim-main.h: New file.
3560 * interp.c (sim-main.h): Include.
72f4393d 3561
c906108c
SS		 3562Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3563
3564 * configure: Regenerated to track ../common/aclocal.m4 changes.
3565
3566Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3567
3568 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3569
3570Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3571
72f4393d
L		 3572 * gencode.c (build_instruction): DIV instructions: check
3573 for division by zero and integer overflow before using
c906108c
SS		 3574 host's division operation.
3575
3576Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3577
3578 * Makefile.in (SIM_OBJS): Add sim-load.o.
3579 * interp.c: #include bfd.h.
3580 (target_byte_order): Delete.
3581 (sim_kind, myname, big_endian_p): New static locals.
3582 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3583 after argument parsing. Recognize -E arg, set endianness accordingly.
3584 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3585 load file into simulator. Set PC from bfd.
3586 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3587 (set_endianness): Use big_endian_p instead of target_byte_order.
3588
3589Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3590
3591 * interp.c (sim_size): Delete prototype - conflicts with
3592 definition in remote-sim.h. Correct definition.
3593
3594Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3595
3596 * configure: Regenerated to track ../common/aclocal.m4 changes.
3597 * config.in: Ditto.
3598
3599Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3600
3601 * interp.c (sim_open): New arg `kind'.
3602
3603 * configure: Regenerated to track ../common/aclocal.m4 changes.
3604
3605Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3606
3607 * configure: Regenerated to track ../common/aclocal.m4 changes.
3608
3609Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3610
3611 * interp.c (sim_open): Set optind to 0 before calling getopt.
3612
3613Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3614
3615 * configure: Regenerated to track ../common/aclocal.m4 changes.
3616
3617Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3618
3619 * interp.c : Replace uses of pr_addr with pr_uword64
3620 where the bit length is always 64 independent of SIM_ADDR.
3621 (pr_uword64) : added.
3622
3623Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3624
3625 * configure: Re-generate.
3626
3627Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3628
3629 * configure: Regenerate to track ../common/aclocal.m4 changes.
3630
3631Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3632
3633 * interp.c (sim_open): New SIM_DESC result. Argument is now
3634 in argv form.
3635 (other sim_*): New SIM_DESC argument.
3636
3637Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3638
3639 * interp.c: Fix printing of addresses for non-64-bit targets.
3640 (pr_addr): Add function to print address based on size.
3641
3642Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3643
3644 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3645
3646Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3647
3648 * gencode.c (build_mips16_operands): Correct computation of base
3649 address for extended PC relative instruction.
3650
3651Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3652
3653 * interp.c (mips16_entry): Add support for floating point cases.
3654 (SignalException): Pass floating point cases to mips16_entry.
3655 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3656 registers.
3657 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3658 or fmt_word.
3659 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3660 and then set the state to fmt_uninterpreted.
3661 (COP_SW): Temporarily set the state to fmt_word while calling
3662 ValueFPR.
3663
3664Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3665
3666 * gencode.c (build_instruction): The high order may be set in the
3667 comparison flags at any ISA level, not just ISA 4.
3668
3669Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3670
3671 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3672 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3673 * configure.in: sinclude ../common/aclocal.m4.
3674 * configure: Regenerated.
3675
3676Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3677
3678 * configure: Rebuild after change to aclocal.m4.
3679
3680Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3681
3682 * configure configure.in Makefile.in: Update to new configure
3683 scheme which is more compatible with WinGDB builds.
3684 * configure.in: Improve comment on how to run autoconf.
3685 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3686 * Makefile.in: Use autoconf substitution to install common
3687 makefile fragment.
3688
3689Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3690
3691 * gencode.c (build_instruction): Use BigEndianCPU instead of
3692 ByteSwapMem.
3693
3694Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3695
3696 * interp.c (sim_monitor): Make output to stdout visible in
3697 wingdb's I/O log window.
3698
3699Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3700
3701 * support.h: Undo previous change to SIGTRAP
3702 and SIGQUIT values.
3703
3704Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3705
3706 * interp.c (store_word, load_word): New static functions.
3707 (mips16_entry): New static function.
3708 (SignalException): Look for mips16 entry and exit instructions.
3709 (simulate): Use the correct index when setting fpr_state after
3710 doing a pending move.
3711
3712Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3713
3714 * interp.c: Fix byte-swapping code throughout to work on
3715 both little- and big-endian hosts.
3716
3717Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3718
3719 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3720 with gdb/config/i386/xm-windows.h.
3721
3722Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3723
3724 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3725 that messes up arithmetic shifts.
3726
3727Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3728
3729 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3730 SIGTRAP and SIGQUIT for _WIN32.
3731
3732Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3733
3734 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3735 force a 64 bit multiplication.
3736 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3737 destination register is 0, since that is the default mips16 nop
3738 instruction.
3739
3740Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3741
3742 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3743 (build_endian_shift): Don't check proc64.
3744 (build_instruction): Always set memval to uword64. Cast op2 to
3745 uword64 when shifting it left in memory instructions. Always use
3746 the same code for stores--don't special case proc64.
3747
3748 * gencode.c (build_mips16_operands): Fix base PC value for PC
3749 relative operands.
3750 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3751 jal instruction.
3752 * interp.c (simJALDELAYSLOT): Define.
3753 (JALDELAYSLOT): Define.
3754 (INDELAYSLOT, INJALDELAYSLOT): Define.
3755 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3756
3757Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3758
3759 * interp.c (sim_open): add flush_cache as a PMON routine
3760 (sim_monitor): handle flush_cache by ignoring it
3761
3762Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3763
3764 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3765 BigEndianMem.
3766 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3767 (BigEndianMem): Rename to ByteSwapMem and change sense.
3768 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3769 BigEndianMem references to !ByteSwapMem.
3770 (set_endianness): New function, with prototype.
3771 (sim_open): Call set_endianness.
3772 (sim_info): Use simBE instead of BigEndianMem.
3773 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3774 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3775 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3776 ifdefs, keeping the prototype declaration.
3777 (swap_word): Rewrite correctly.
3778 (ColdReset): Delete references to CONFIG. Delete endianness related
3779 code; moved to set_endianness.
72f4393d 3780
c906108c
SS		 3781Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3782
3783 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3784 * interp.c (CHECKHILO): Define away.
3785 (simSIGINT): New macro.
3786 (membank_size): Increase from 1MB to 2MB.
3787 (control_c): New function.
3788 (sim_resume): Rename parameter signal to signal_number. Add local
3789 variable prev. Call signal before and after simulate.
3790 (sim_stop_reason): Add simSIGINT support.
3791 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3792 functions always.
3793 (sim_warning): Delete call to SignalException. Do call printf_filtered
3794 if logfh is NULL.
3795 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3796 a call to sim_warning.
3797
3798Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3799
3800 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3801 16 bit instructions.
3802
3803Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3804
3805 Add support for mips16 (16 bit MIPS implementation):
3806 * gencode.c (inst_type): Add mips16 instruction encoding types.
3807 (GETDATASIZEINSN): Define.
3808 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3809 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3810 mtlo.
3811 (MIPS16_DECODE): New table, for mips16 instructions.
3812 (bitmap_val): New static function.
3813 (struct mips16_op): Define.
3814 (mips16_op_table): New table, for mips16 operands.
3815 (build_mips16_operands): New static function.
3816 (process_instructions): If PC is odd, decode a mips16
3817 instruction. Break out instruction handling into new
3818 build_instruction function.
3819 (build_instruction): New static function, broken out of
3820 process_instructions. Check modifiers rather than flags for SHIFT
3821 bit count and m[ft]{hi,lo} direction.
3822 (usage): Pass program name to fprintf.
3823 (main): Remove unused variable this_option_optind. Change
3824 ``*loptarg++'' to ``loptarg++''.
3825 (my_strtoul): Parenthesize && within ||.
3826 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3827 (simulate): If PC is odd, fetch a 16 bit instruction, and
3828 increment PC by 2 rather than 4.
3829 * configure.in: Add case for mips16*-*-*.
3830 * configure: Rebuild.
3831
3832Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3833
3834 * interp.c: Allow -t to enable tracing in standalone simulator.
3835 Fix garbage output in trace file and error messages.
3836
3837Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3838
3839 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3840 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3841 * configure.in: Simplify using macros in ../common/aclocal.m4.
3842 * configure: Regenerated.
3843 * tconfig.in: New file.
3844
3845Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3846
3847 * interp.c: Fix bugs in 64-bit port.
3848 Use ansi function declarations for msvc compiler.
3849 Initialize and test file pointer in trace code.
3850 Prevent duplicate definition of LAST_EMED_REGNUM.
3851
3852Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3853
3854 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3855
3856Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3857
3858 * interp.c (SignalException): Check for explicit terminating
3859 breakpoint value.
3860 * gencode.c: Pass instruction value through SignalException()
3861 calls for Trap, Breakpoint and Syscall.
3862
3863Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3864
3865 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3866 only used on those hosts that provide it.
3867 * configure.in: Add sqrt() to list of functions to be checked for.
3868 * config.in: Re-generated.
3869 * configure: Re-generated.
3870
3871Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3872
3873 * gencode.c (process_instructions): Call build_endian_shift when
3874 expanding STORE RIGHT, to fix swr.
3875 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3876 clear the high bits.
3877 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3878 Fix float to int conversions to produce signed values.
3879
3880Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3881
3882 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3883 (process_instructions): Correct handling of nor instruction.
3884 Correct shift count for 32 bit shift instructions. Correct sign
3885 extension for arithmetic shifts to not shift the number of bits in
3886 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3887 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3888 Fix madd.
3889 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3890 It's OK to have a mult follow a mult. What's not OK is to have a
3891 mult follow an mfhi.
3892 (Convert): Comment out incorrect rounding code.
3893
3894Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3895
3896 * interp.c (sim_monitor): Improved monitor printf
3897 simulation. Tidied up simulator warnings, and added "--log" option
3898 for directing warning message output.
3899 * gencode.c: Use sim_warning() rather than WARNING macro.
3900
3901Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3902
3903 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3904 getopt1.o, rather than on gencode.c. Link objects together.
3905 Don't link against -liberty.
3906 (gencode.o, getopt.o, getopt1.o): New targets.
3907 * gencode.c: Include <ctype.h> and "ansidecl.h".
3908 (AND): Undefine after including "ansidecl.h".
3909 (ULONG_MAX): Define if not defined.
3910 (OP_*): Don't define macros; now defined in opcode/mips.h.
3911 (main): Call my_strtoul rather than strtoul.
3912 (my_strtoul): New static function.
3913
3914Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3915
3916 * gencode.c (process_instructions): Generate word64 and uword64
3917 instead of `long long' and `unsigned long long' data types.
3918 * interp.c: #include sysdep.h to get signals, and define default
3919 for SIGBUS.
3920 * (Convert): Work around for Visual-C++ compiler bug with type
3921 conversion.
3922 * support.h: Make things compile under Visual-C++ by using
3923 __int64 instead of `long long'. Change many refs to long long
3924 into word64/uword64 typedefs.
3925
3926Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3927
72f4393d
L		 3928 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3929 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3930 (docdir): Removed.
3931 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3932 (AC_PROG_INSTALL): Added.
c906108c 3933 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3934 * configure: Rebuilt.
3935
c906108c
SS		 3936Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3937
3938 * configure.in: Define @SIMCONF@ depending on mips target.
3939 * configure: Rebuild.
3940 * Makefile.in (run): Add @SIMCONF@ to control simulator
3941 construction.
3942 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3943 * interp.c: Remove some debugging, provide more detailed error
3944 messages, update memory accesses to use LOADDRMASK.
72f4393d 3945
c906108c
SS		 3946Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3947
3948 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3949 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3950 stamp-h.
3951 * configure: Rebuild.
3952 * config.in: New file, generated by autoheader.
3953 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3954 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3955 HAVE_ANINT and HAVE_AINT, as appropriate.
3956 * Makefile.in (run): Use @LIBS@ rather than -lm.
3957 (interp.o): Depend upon config.h.
3958 (Makefile): Just rebuild Makefile.
3959 (clean): Remove stamp-h.
3960 (mostlyclean): Make the same as clean, not as distclean.
3961 (config.h, stamp-h): New targets.
3962
3963Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3964
3965 * interp.c (ColdReset): Fix boolean test. Make all simulator
3966 globals static.
3967
3968Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3969
3970 * interp.c (xfer_direct_word, xfer_direct_long,
3971 swap_direct_word, swap_direct_long, xfer_big_word,
3972 xfer_big_long, xfer_little_word, xfer_little_long,
3973 swap_word,swap_long): Added.
3974 * interp.c (ColdReset): Provide function indirection to
3975 host<->simulated_target transfer routines.
3976 * interp.c (sim_store_register, sim_fetch_register): Updated to
3977 make use of indirected transfer routines.
3978
3979Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3980
3981 * gencode.c (process_instructions): Ensure FP ABS instruction
3982 recognised.
3983 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3984 system call support.
3985
3986Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3987
3988 * interp.c (sim_do_command): Complain if callback structure not
3989 initialised.
3990
3991Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3992
3993 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3994 support for Sun hosts.
3995 * Makefile.in (gencode): Ensure the host compiler and libraries
3996 used for cross-hosted build.
3997
3998Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3999
4000 * interp.c, gencode.c: Some more (TODO) tidying.
4001
4002Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
4003
4004 * gencode.c, interp.c: Replaced explicit long long references with
4005 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
4006 * support.h (SET64LO, SET64HI): Macros added.
4007
4008Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
4009
4010 * configure: Regenerate with autoconf 2.7.
4011
4012Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
4013
4014 * interp.c (LoadMemory): Enclose text following #endif in /* */.
4015 * support.h: Remove superfluous "1" from #if.
4016 * support.h (CHECKSIM): Remove stray 'a' at end of line.
4017
4018Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
4019
4020 * interp.c (StoreFPR): Control UndefinedResult() call on
4021 WARN_RESULT manifest.
4022
4023Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
4024
4025 * gencode.c: Tidied instruction decoding, and added FP instruction
4026 support.
4027
4028 * interp.c: Added dineroIII, and BSD profiling support. Also
4029 run-time FP handling.
4030
4031Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
4032
4033 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
4034 gencode.c, interp.c, support.h: created.
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