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Fixup readline and sim including of override.m4
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
d6416cdc
RW		 12009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
2
3 * configure: Regenerate.
4
b5bd9624
HPN		 52008-07-11 Hans-Peter Nilsson <hp@axis.com>
6
7 * configure: Regenerate to track ../common/common.m4 changes.
8 * config.in: Ditto.
9
6efef468
JM		 102008-06-06 Vladimir Prus <vladimir@codesourcery.com>
11 Daniel Jacobowitz <dan@codesourcery.com>
12 Joseph Myers <joseph@codesourcery.com>
13
14 * configure: Regenerate.
15
60dc88db
RS		 162007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
17
18 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
19 that unconditionally allows fmt_ps.
20 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
21 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
22 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
23 filter from 64,f to 32,f.
24 (PREFX): Change filter from 64 to 32.
25 (LDXC1, LUXC1): Provide separate mips32r2 implementations
26 that use do_load_double instead of do_load. Make both LUXC1
27 versions unpredictable if SizeFGR () != 64.
28 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
29 instead of do_store. Remove unused variable. Make both SUXC1
30 versions unpredictable if SizeFGR () != 64.
31
599ca73e
RS		 322007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
33
34 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
35 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
36 shifts for that case.
37
2525df03
NC		 382007-09-04 Nick Clifton <nickc@redhat.com>
39
40 * interp.c (options enum): Add OPTION_INFO_MEMORY.
41 (display_mem_info): New static variable.
42 (mips_option_handler): Handle OPTION_INFO_MEMORY.
43 (mips_options): Add info-memory and memory-info.
44 (sim_open): After processing the command line and board
45 specification, check display_mem_info. If it is set then
46 call the real handler for the --memory-info command line
47 switch.
48
35ee6e1e
JB		 492007-08-24 Joel Brobecker <brobecker@adacore.com>
50
51 * configure.ac: Change license of multi-run.c to GPL version 3.
52 * configure: Regenerate.
53
d5fb0879
RS		 542007-06-28 Richard Sandiford <richard@codesourcery.com>
55
56 * configure.ac, configure: Revert last patch.
57
2a2ce21b
RS		 582007-06-26 Richard Sandiford <richard@codesourcery.com>
59
60 * configure.ac (sim_mipsisa3264_configs): New variable.
61 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
62 every configuration support all four targets, using the triplet to
63 determine the default.
64 * configure: Regenerate.
65
efdcccc9
RS		 662007-06-25 Richard Sandiford <richard@codesourcery.com>
67
0a7692b2 68 * Makefile.in (m16run.o): New rule.
efdcccc9 69
f532a356
TS		 702007-05-15 Thiemo Seufer <ths@mips.com>
71
72 * mips3264r2.igen (DSHD): Fix compile warning.
73
bfe9c90b
TS		 742007-05-14 Thiemo Seufer <ths@mips.com>
75
76 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
77 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
78 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
79 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
80 for mips32r2.
81
53f4826b
TS		 822007-03-01 Thiemo Seufer <ths@mips.com>
83
84 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
85 and mips64.
86
8bf3ddc8
TS		 872007-02-20 Thiemo Seufer <ths@mips.com>
88
89 * dsp.igen: Update copyright notice.
90 * dsp2.igen: Fix copyright notice.
91
8b082fb1
TS		 922007-02-20 Thiemo Seufer <ths@mips.com>
93 Chao-Ying Fu <fu@mips.com>
94
95 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
96 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
97 Add dsp2 to sim_igen_machine.
98 * configure: Regenerate.
99 * dsp.igen (do_ph_op): Add MUL support when op = 2.
100 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
101 (mulq_rs.ph): Use do_ph_mulq.
102 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
103 * mips.igen: Add dsp2 model and include dsp2.igen.
104 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
105 for *mips32r2, *mips64r2, *dsp.
106 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
107 for *mips32r2, *mips64r2, *dsp2.
108 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
109
b1004875
TS		 1102007-02-19 Thiemo Seufer <ths@mips.com>
111 Nigel Stephens <nigel@mips.com>
112
113 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
114 jumps with hazard barrier.
115
f8df4c77
TS		 1162007-02-19 Thiemo Seufer <ths@mips.com>
117 Nigel Stephens <nigel@mips.com>
118
119 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
120 after each call to sim_io_write.
121
b1004875 1222007-02-19 Thiemo Seufer <ths@mips.com>
07802d98 123 Nigel Stephens <nigel@mips.com>
b1004875
TS		 124
125 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
126 supported by this simulator.
07802d98
TS		 127 (decode_coproc): Recognise additional CP0 Config registers
128 correctly.
129
14fb6c5a
TS		 1302007-02-19 Thiemo Seufer <ths@mips.com>
131 Nigel Stephens <nigel@mips.com>
132 David Ung <davidu@mips.com>
133
134 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
135 uninterpreted formats. If fmt is one of the uninterpreted types
136 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
137 fmt_word, and fmt_uninterpreted_64 like fmt_long.
138 (store_fpr): When writing an invalid odd register, set the
139 matching even register to fmt_unknown, not the following register.
140 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
141 the the memory window at offset 0 set by --memory-size command
142 line option.
143 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
144 point register.
145 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
146 register.
147 (sim_monitor): When returning the memory size to the MIPS
148 application, use the value in STATE_MEM_SIZE, not an arbitrary
149 hardcoded value.
150 (cop_lw): Don' mess around with FPR_STATE, just pass
151 fmt_uninterpreted_32 to StoreFPR.
152 (cop_sw): Similarly.
153 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
154 (cop_sd): Similarly.
155 * mips.igen (not_word_value): Single version for mips32, mips64
156 and mips16.
157
c8847145
TS		 1582007-02-19 Thiemo Seufer <ths@mips.com>
159 Nigel Stephens <nigel@mips.com>
160
161 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
162 MBytes.
163
4b5d35ee
TS		 1642007-02-17 Thiemo Seufer <ths@mips.com>
165
166 * configure.ac (mips*-sde-elf*): Move in front of generic machine
167 configuration.
168 * configure: Regenerate.
169
3669427c
TS		 1702007-02-17 Thiemo Seufer <ths@mips.com>
171
172 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
173 Add mdmx to sim_igen_machine.
174 (mipsisa64*-*-*): Likewise. Remove dsp.
175 (mipsisa32*-*-*): Remove dsp.
176 * configure: Regenerate.
177
109ad085
TS		 1782007-02-13 Thiemo Seufer <ths@mips.com>
179
180 * configure.ac: Add mips*-sde-elf* target.
181 * configure: Regenerate.
182
921d7ad3
HPN		 1832006-12-21 Hans-Peter Nilsson <hp@axis.com>
184
185 * acconfig.h: Remove.
186 * config.in, configure: Regenerate.
187
02f97da7
TS		 1882006-11-07 Thiemo Seufer <ths@mips.com>
189
190 * dsp.igen (do_w_op): Fix compiler warning.
191
2d2733fc
TS		 1922006-08-29 Thiemo Seufer <ths@mips.com>
193 David Ung <davidu@mips.com>
194
195 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
196 sim_igen_machine.
197 * configure: Regenerate.
198 * mips.igen (model): Add smartmips.
199 (MADDU): Increment ACX if carry.
200 (do_mult): Clear ACX.
201 (ROR,RORV): Add smartmips.
202 (include): Include smartmips.igen.
203 * sim-main.h (ACX): Set to REGISTERS[89].
204 * smartmips.igen: New file.
205
d85c3a10
TS		 2062006-08-29 Thiemo Seufer <ths@mips.com>
207 David Ung <davidu@mips.com>
208
209 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
210 mips3264r2.igen. Add missing dependency rules.
211 * m16e.igen: Support for mips16e save/restore instructions.
212
e85e3205
RE		 2132006-06-13 Richard Earnshaw <rearnsha@arm.com>
214
215 * configure: Regenerated.
216
2f0122dc
DJ		 2172006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
218
219 * configure: Regenerated.
220
20e95c23
DJ		 2212006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
222
223 * configure: Regenerated.
224
69088b17
CF		 2252006-05-15 Chao-ying Fu <fu@mips.com>
226
227 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
228
0275de4e
NC		 2292006-04-18 Nick Clifton <nickc@redhat.com>
230
231 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
232 statement.
233
b3a3ffef
HPN		 2342006-03-29 Hans-Peter Nilsson <hp@axis.com>
235
236 * configure: Regenerate.
237
40a5538e
CF		 2382005-12-14 Chao-ying Fu <fu@mips.com>
239
240 * Makefile.in (SIM_OBJS): Add dsp.o.
241 (dsp.o): New dependency.
242 (IGEN_INCLUDE): Add dsp.igen.
243 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
244 mipsisa64*-*-*): Add dsp to sim_igen_machine.
245 * configure: Regenerate.
246 * mips.igen: Add dsp model and include dsp.igen.
247 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
248 because these instructions are extended in DSP ASE.
249 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
250 adding 6 DSP accumulator registers and 1 DSP control register.
251 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
252 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
253 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
254 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
255 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
256 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
257 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
258 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
259 DSPCR_CCOND_SMASK): New define.
260 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
261 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
262
21d14896
ILT		 2632005-07-08 Ian Lance Taylor <ian@airs.com>
264
265 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
266
b16d63da
DU		 2672005-06-16 David Ung <davidu@mips.com>
268 Nigel Stephens <nigel@mips.com>
269
270 * mips.igen: New mips16e model and include m16e.igen.
271 (check_u64): Add mips16e tag.
272 * m16e.igen: New file for MIPS16e instructions.
273 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
274 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
275 models.
276 * configure: Regenerate.
277
e70cb6cd
CD		 2782005-05-26 David Ung <davidu@mips.com>
279
280 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
281 tags to all instructions which are applicable to the new ISAs.
282 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
283 vr.igen.
284 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
285 instructions.
286 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
287 to mips.igen.
288 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
289 * configure: Regenerate.
290
2b193c4a
MK		 2912005-03-23 Mark Kettenis <kettenis@gnu.org>
292
293 * configure: Regenerate.
294
35695fd6
AC		 2952005-01-14 Andrew Cagney <cagney@gnu.org>
296
297 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
298 explicit call to AC_CONFIG_HEADER.
299 * configure: Regenerate.
300
f0569246
AC		 3012005-01-12 Andrew Cagney <cagney@gnu.org>
302
303 * configure.ac: Update to use ../common/common.m4.
304 * configure: Re-generate.
305
38f48d72
AC		 3062005-01-11 Andrew Cagney <cagney@localhost.localdomain>
307
308 * configure: Regenerated to track ../common/aclocal.m4 changes.
309
b7026657
AC		 3102005-01-07 Andrew Cagney <cagney@gnu.org>
311
312 * configure.ac: Rename configure.in, require autoconf 2.59.
313 * configure: Re-generate.
314
379832de
HPN		 3152004-12-08 Hans-Peter Nilsson <hp@axis.com>
316
317 * configure: Regenerate for ../common/aclocal.m4 update.
318
cd62154c
AC		 3192004-09-24 Monika Chaddha <monika@acmet.com>
320
321 Committed by Andrew Cagney.
322 * m16.igen (CMP, CMPI): Fix assembler.
323
e5da76ec
CD		 3242004-08-18 Chris Demetriou <cgd@broadcom.com>
325
326 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
327 * configure: Regenerate.
328
139181c8
CD		 3292004-06-25 Chris Demetriou <cgd@broadcom.com>
330
331 * configure.in (sim_m16_machine): Include mipsIII.
332 * configure: Regenerate.
333
1a27f959
CD		 3342004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
335
336 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
337 from COP0_BADVADDR.
338 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
339
5dbb7b5a
CD		 3402004-04-10 Chris Demetriou <cgd@broadcom.com>
341
342 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
343
14234056
CD		 3442004-04-09 Chris Demetriou <cgd@broadcom.com>
345
346 * mips.igen (check_fmt): Remove.
347 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
348 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
349 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
350 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
351 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
352 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
353 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
354 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
355 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
356 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
357
c6f9085c
CD		 3582004-04-09 Chris Demetriou <cgd@broadcom.com>
359
360 * sb1.igen (check_sbx): New function.
361 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
362
11d66e66 3632004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 364 Richard Sandiford <rsandifo@redhat.com>
365
366 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
367 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
368 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
369 separate implementations for mipsIV and mipsV. Use new macros to
370 determine whether the restrictions apply.
371
b3208fb8
CD		 3722004-01-19 Chris Demetriou <cgd@broadcom.com>
373
374 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
375 (check_mult_hilo): Improve comments.
376 (check_div_hilo): Likewise. Also, fork off a new version
377 to handle mips32/mips64 (since there are no hazards to check
378 in MIPS32/MIPS64).
379
9a1d84fb
CD		 3802003-06-17 Richard Sandiford <rsandifo@redhat.com>
381
382 * mips.igen (do_dmultx): Fix check for negative operands.
383
ae451ac6
ILT		 3842003-05-16 Ian Lance Taylor <ian@airs.com>
385
386 * Makefile.in (SHELL): Make sure this is defined.
387 (various): Use $(SHELL) whenever we invoke move-if-change.
388
dd69d292
CD		 3892003-05-03 Chris Demetriou <cgd@broadcom.com>
390
391 * cp1.c: Tweak attribution slightly.
392 * cp1.h: Likewise.
393 * mdmx.c: Likewise.
394 * mdmx.igen: Likewise.
395 * mips3d.igen: Likewise.
396 * sb1.igen: Likewise.
397
bcd0068e
CD		 3982003-04-15 Richard Sandiford <rsandifo@redhat.com>
399
400 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
401 unsigned operands.
402
6b4a8935
AC		 4032003-02-27 Andrew Cagney <cagney@redhat.com>
404
601da316
AC		 405 * interp.c (sim_open): Rename _bfd to bfd.
406 (sim_create_inferior): Ditto.
6b4a8935 407
d29e330f
CD		 4082003-01-14 Chris Demetriou <cgd@broadcom.com>
409
410 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
411
a2353a08
CD		 4122003-01-14 Chris Demetriou <cgd@broadcom.com>
413
414 * mips.igen (EI, DI): Remove.
415
80551777
CD		 4162003-01-05 Richard Sandiford <rsandifo@redhat.com>
417
418 * Makefile.in (tmp-run-multi): Fix mips16 filter.
419
4c54fc26
CD		 4202003-01-04 Richard Sandiford <rsandifo@redhat.com>
421 Andrew Cagney <ac131313@redhat.com>
422 Gavin Romig-Koch <gavin@redhat.com>
423 Graydon Hoare <graydon@redhat.com>
424 Aldy Hernandez <aldyh@redhat.com>
425 Dave Brolley <brolley@redhat.com>
426 Chris Demetriou <cgd@broadcom.com>
427
428 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
429 (sim_mach_default): New variable.
430 (mips64vr-*-*, mips64vrel-*-*): New configurations.
431 Add a new simulator generator, MULTI.
432 * configure: Regenerate.
433 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
434 (multi-run.o): New dependency.
435 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
436 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
437 (tmp-multi): Combine them.
438 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
439 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
440 (distclean-extra): New rule.
441 * sim-main.h: Include bfd.h.
442 (MIPS_MACH): New macro.
443 * mips.igen (vr4120, vr5400, vr5500): New models.
444 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
445 * vr.igen: Replace with new version.
446
e6c674b8
CD		 4472003-01-04 Chris Demetriou <cgd@broadcom.com>
448
449 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
450 * configure: Regenerate.
451
28f50ac8
CD		 4522002-12-31 Chris Demetriou <cgd@broadcom.com>
453
454 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
455 * mips.igen: Remove all invocations of check_branch_bug and
456 mark_branch_bug.
457
5071ffe6
CD		 4582002-12-16 Chris Demetriou <cgd@broadcom.com>
459
460 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
461
06e7837e
CD		 4622002-07-30 Chris Demetriou <cgd@broadcom.com>
463
464 * mips.igen (do_load_double, do_store_double): New functions.
465 (LDC1, SDC1): Rename to...
466 (LDC1b, SDC1b): respectively.
467 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
468
2265c243
MS		 4692002-07-29 Michael Snyder <msnyder@redhat.com>
470
471 * cp1.c (fp_recip2): Modify initialization expression so that
472 GCC will recognize it as constant.
473
a2f8b4f3
CD		 4742002-06-18 Chris Demetriou <cgd@broadcom.com>
475
476 * mdmx.c (SD_): Delete.
477 (Unpredictable): Re-define, for now, to directly invoke
478 unpredictable_action().
479 (mdmx_acc_op): Fix error in .ob immediate handling.
480
b4b6c939
AC		 4812002-06-18 Andrew Cagney <cagney@redhat.com>
482
483 * interp.c (sim_firmware_command): Initialize `address'.
484
c8cca39f
AC		 4852002-06-16 Andrew Cagney <ac131313@redhat.com>
486
487 * configure: Regenerated to track ../common/aclocal.m4 changes.
488
e7e81181
CD		 4892002-06-14 Chris Demetriou <cgd@broadcom.com>
490 Ed Satterthwaite <ehs@broadcom.com>
491
492 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
493 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
494 * mips.igen: Include mips3d.igen.
495 (mips3d): New model name for MIPS-3D ASE instructions.
496 (CVT.W.fmt): Don't use this instruction for word (source) format
497 instructions.
498 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
499 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
500 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
501 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
502 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
503 (RSquareRoot1, RSquareRoot2): New macros.
504 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
505 (fp_rsqrt2): New functions.
506 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
507 * configure: Regenerate.
508
3a2b820e 5092002-06-13 Chris Demetriou <cgd@broadcom.com>
eab54952 510 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 511
512 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
513 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
514 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
515 (convert): Note that this function is not used for paired-single
516 format conversions.
517 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
518 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
519 (check_fmt_p): Enable paired-single support.
520 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
521 (PUU.PS): New instructions.
522 (CVT.S.fmt): Don't use this instruction for paired-single format
523 destinations.
524 * sim-main.h (FP_formats): New value 'fmt_ps.'
525 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
526 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
527
d18ea9c2
CD		 5282002-06-12 Chris Demetriou <cgd@broadcom.com>
529
530 * mips.igen: Fix formatting of function calls in
531 many FP operations.
532
95fd5cee
CD		 5332002-06-12 Chris Demetriou <cgd@broadcom.com>
534
535 * mips.igen (MOVN, MOVZ): Trace result.
536 (TNEI): Print "tnei" as the opcode name in traces.
537 (CEIL.W): Add disassembly string for traces.
538 (RSQRT.fmt): Make location of disassembly string consistent
539 with other instructions.
540
4f0d55ae
CD		 5412002-06-12 Chris Demetriou <cgd@broadcom.com>
542
543 * mips.igen (X): Delete unused function.
544
3c25f8c7
AC		 5452002-06-08 Andrew Cagney <cagney@redhat.com>
546
547 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
548
f3c08b7e
CD		 5492002-06-07 Chris Demetriou <cgd@broadcom.com>
550 Ed Satterthwaite <ehs@broadcom.com>
551
552 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
553 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
554 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
555 (fp_nmsub): New prototypes.
556 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
557 (NegMultiplySub): New defines.
558 * mips.igen (RSQRT.fmt): Use RSquareRoot().
559 (MADD.D, MADD.S): Replace with...
560 (MADD.fmt): New instruction.
561 (MSUB.D, MSUB.S): Replace with...
562 (MSUB.fmt): New instruction.
563 (NMADD.D, NMADD.S): Replace with...
564 (NMADD.fmt): New instruction.
565 (NMSUB.D, MSUB.S): Replace with...
566 (NMSUB.fmt): New instruction.
567
52714ff9
CD		 5682002-06-07 Chris Demetriou <cgd@broadcom.com>
569 Ed Satterthwaite <ehs@broadcom.com>
570
571 * cp1.c: Fix more comment spelling and formatting.
572 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
573 (denorm_mode): New function.
574 (fpu_unary, fpu_binary): Round results after operation, collect
575 status from rounding operations, and update the FCSR.
576 (convert): Collect status from integer conversions and rounding
577 operations, and update the FCSR. Adjust NaN values that result
578 from conversions. Convert to use sim_io_eprintf rather than
579 fprintf, and remove some debugging code.
580 * cp1.h (fenr_FS): New define.
581
577d8c4b
CD		 5822002-06-07 Chris Demetriou <cgd@broadcom.com>
583
584 * cp1.c (convert): Remove unusable debugging code, and move MIPS
585 rounding mode to sim FP rounding mode flag conversion code into...
586 (rounding_mode): New function.
587
196496ed
CD		 5882002-06-07 Chris Demetriou <cgd@broadcom.com>
589
590 * cp1.c: Clean up formatting of a few comments.
591 (value_fpr): Reformat switch statement.
592
cfe9ea23
CD		 5932002-06-06 Chris Demetriou <cgd@broadcom.com>
594 Ed Satterthwaite <ehs@broadcom.com>
595
596 * cp1.h: New file.
597 * sim-main.h: Include cp1.h.
598 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
599 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
600 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
601 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
602 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
603 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
604 * cp1.c: Don't include sim-fpu.h; already included by
605 sim-main.h. Clean up formatting of some comments.
606 (NaN, Equal, Less): Remove.
607 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
608 (fp_cmp): New functions.
609 * mips.igen (do_c_cond_fmt): Remove.
610 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
611 Compare. Add result tracing.
612 (CxC1): Remove, replace with...
613 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
614 (DMxC1): Remove, replace with...
615 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
616 (MxC1): Remove, replace with...
617 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
618
ee7254b0
CD		 6192002-06-04 Chris Demetriou <cgd@broadcom.com>
620
621 * sim-main.h (FGRIDX): Remove, replace all uses with...
622 (FGR_BASE): New macro.
623 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
624 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
625 (NR_FGR, FGR): Likewise.
626 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
627 * mips.igen: Likewise.
628
d3eb724f
CD		 6292002-06-04 Chris Demetriou <cgd@broadcom.com>
630
631 * cp1.c: Add an FSF Copyright notice to this file.
632
ba46ddd0
CD		 6332002-06-04 Chris Demetriou <cgd@broadcom.com>
634 Ed Satterthwaite <ehs@broadcom.com>
635
636 * cp1.c (Infinity): Remove.
637 * sim-main.h (Infinity): Likewise.
638
639 * cp1.c (fp_unary, fp_binary): New functions.
640 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
641 (fp_sqrt): New functions, implemented in terms of the above.
642 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
643 (Recip, SquareRoot): Remove (replaced by functions above).
644 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
645 (fp_recip, fp_sqrt): New prototypes.
646 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
647 (Recip, SquareRoot): Replace prototypes with #defines which
648 invoke the functions above.
649
18d8a52d
CD		 6502002-06-03 Chris Demetriou <cgd@broadcom.com>
651
652 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
653 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
654 file, remove PARAMS from prototypes.
655 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
656 simulator state arguments.
657 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
658 pass simulator state arguments.
659 * cp1.c (SD): Redefine as CPU_STATE(cpu).
660 (store_fpr, convert): Remove 'sd' argument.
661 (value_fpr): Likewise. Convert to use 'SD' instead.
662
0f154cbd
CD		 6632002-06-03 Chris Demetriou <cgd@broadcom.com>
664
665 * cp1.c (Min, Max): Remove #if 0'd functions.
666 * sim-main.h (Min, Max): Remove.
667
e80fc152
CD		 6682002-06-03 Chris Demetriou <cgd@broadcom.com>
669
670 * cp1.c: fix formatting of switch case and default labels.
671 * interp.c: Likewise.
672 * sim-main.c: Likewise.
673
bad673a9
CD		 6742002-06-03 Chris Demetriou <cgd@broadcom.com>
675
676 * cp1.c: Clean up comments which describe FP formats.
677 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
678
7cbea089
CD		 6792002-06-03 Chris Demetriou <cgd@broadcom.com>
680 Ed Satterthwaite <ehs@broadcom.com>
681
682 * configure.in (mipsisa64sb1*-*-*): New target for supporting
683 Broadcom SiByte SB-1 processor configurations.
684 * configure: Regenerate.
685 * sb1.igen: New file.
686 * mips.igen: Include sb1.igen.
687 (sb1): New model.
688 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
689 * mdmx.igen: Add "sb1" model to all appropriate functions and
690 instructions.
691 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
692 (ob_func, ob_acc): Reference the above.
693 (qh_acc): Adjust to keep the same size as ob_acc.
694 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
695 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
696
909daa82
CD		 6972002-06-03 Chris Demetriou <cgd@broadcom.com>
698
699 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
700
f4f1b9f1
CD		 7012002-06-02 Chris Demetriou <cgd@broadcom.com>
702 Ed Satterthwaite <ehs@broadcom.com>
703
704 * mips.igen (mdmx): New (pseudo-)model.
705 * mdmx.c, mdmx.igen: New files.
706 * Makefile.in (SIM_OBJS): Add mdmx.o.
707 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
708 New typedefs.
709 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
710 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
711 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
712 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
713 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
714 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
715 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
716 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
717 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
718 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
719 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
720 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
721 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
722 (qh_fmtsel): New macros.
723 (_sim_cpu): New member "acc".
724 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
725 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
726
5accf1ff
CD		 7272002-05-01 Chris Demetriou <cgd@broadcom.com>
728
729 * interp.c: Use 'deprecated' rather than 'depreciated.'
730 * sim-main.h: Likewise.
731
402586aa
CD		 7322002-05-01 Chris Demetriou <cgd@broadcom.com>
733
734 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
735 which wouldn't compile anyway.
736 * sim-main.h (unpredictable_action): New function prototype.
737 (Unpredictable): Define to call igen function unpredictable().
738 (NotWordValue): New macro to call igen function not_word_value().
739 (UndefinedResult): Remove.
740 * interp.c (undefined_result): Remove.
741 (unpredictable_action): New function.
742 * mips.igen (not_word_value, unpredictable): New functions.
743 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
744 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
745 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
746 NotWordValue() to check for unpredictable inputs, then
747 Unpredictable() to handle them.
748
c9b9995a
CD		 7492002-02-24 Chris Demetriou <cgd@broadcom.com>
750
751 * mips.igen: Fix formatting of calls to Unpredictable().
752
e1015982
AC		 7532002-04-20 Andrew Cagney <ac131313@redhat.com>
754
755 * interp.c (sim_open): Revert previous change.
756
b882a66b
AO		 7572002-04-18 Alexandre Oliva <aoliva@redhat.com>
758
759 * interp.c (sim_open): Disable chunk of code that wrote code in
760 vector table entries.
761
c429b7dd
CD		 7622002-03-19 Chris Demetriou <cgd@broadcom.com>
763
764 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
765 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
766 unused definitions.
767
37d146fa
CD		 7682002-03-19 Chris Demetriou <cgd@broadcom.com>
769
770 * cp1.c: Fix many formatting issues.
771
07892c0b
CD		 7722002-03-19 Chris G. Demetriou <cgd@broadcom.com>
773
774 * cp1.c (fpu_format_name): New function to replace...
775 (DOFMT): This. Delete, and update all callers.
776 (fpu_rounding_mode_name): New function to replace...
777 (RMMODE): This. Delete, and update all callers.
778
487f79b7
CD		 7792002-03-19 Chris G. Demetriou <cgd@broadcom.com>
780
781 * interp.c: Move FPU support routines from here to...
782 * cp1.c: Here. New file.
783 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
784 (cp1.o): New target.
785
1e799e28
CD		 7862002-03-12 Chris Demetriou <cgd@broadcom.com>
787
788 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
789 * mips.igen (mips32, mips64): New models, add to all instructions
790 and functions as appropriate.
791 (loadstore_ea, check_u64): New variant for model mips64.
792 (check_fmt_p): New variant for models mipsV and mips64, remove
793 mipsV model marking fro other variant.
794 (SLL) Rename to...
795 (SLLa) this.
796 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
797 for mips32 and mips64.
798 (DCLO, DCLZ): New instructions for mips64.
799
82f728db
CD		 8002002-03-07 Chris Demetriou <cgd@broadcom.com>
801
802 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
803 immediate or code as a hex value with the "%#lx" format.
804 (ANDI): Likewise, and fix printed instruction name.
805
b96e7ef1
CD		 8062002-03-05 Chris Demetriou <cgd@broadcom.com>
807
808 * sim-main.h (UndefinedResult, Unpredictable): New macros
809 which currently do nothing.
810
d35d4f70
CD		 8112002-03-05 Chris Demetriou <cgd@broadcom.com>
812
813 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
814 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
815 (status_CU3): New definitions.
816
817 * sim-main.h (ExceptionCause): Add new values for MIPS32
818 and MIPS64: MDMX, MCheck, CacheErr. Update comments
819 for DebugBreakPoint and NMIReset to note their status in
820 MIPS32 and MIPS64.
821 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
822 (SignalExceptionCacheErr): New exception macros.
823
3ad6f714
CD		 8242002-03-05 Chris Demetriou <cgd@broadcom.com>
825
826 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
827 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
828 is always enabled.
829 (SignalExceptionCoProcessorUnusable): Take as argument the
830 unusable coprocessor number.
831
86b77b47
CD		 8322002-03-05 Chris Demetriou <cgd@broadcom.com>
833
834 * mips.igen: Fix formatting of all SignalException calls.
835
97a88e93 8362002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 837
838 * sim-main.h (SIGNEXTEND): Remove.
839
97a88e93 8402002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 841
842 * mips.igen: Remove gencode comment from top of file, fix
843 spelling in another comment.
844
97a88e93 8452002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 846
847 * mips.igen (check_fmt, check_fmt_p): New functions to check
848 whether specific floating point formats are usable.
849 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
850 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
851 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
852 Use the new functions.
853 (do_c_cond_fmt): Remove format checks...
854 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
855
97a88e93 8562002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 857
858 * mips.igen: Fix formatting of check_fpu calls.
859
41774c9d
CD		 8602002-03-03 Chris Demetriou <cgd@broadcom.com>
861
862 * mips.igen (FLOOR.L.fmt): Store correct destination register.
863
4a0bd876
CD		 8642002-03-03 Chris Demetriou <cgd@broadcom.com>
865
866 * mips.igen: Remove whitespace at end of lines.
867
09297648
CD		 8682002-03-02 Chris Demetriou <cgd@broadcom.com>
869
870 * mips.igen (loadstore_ea): New function to do effective
871 address calculations.
872 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
873 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
874 CACHE): Use loadstore_ea to do effective address computations.
875
043b7057
CD		 8762002-03-02 Chris Demetriou <cgd@broadcom.com>
877
878 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
879 * mips.igen (LL, CxC1, MxC1): Likewise.
880
c1e8ada4
CD		 8812002-03-02 Chris Demetriou <cgd@broadcom.com>
882
883 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
884 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
885 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
886 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
887 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
888 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
889 Don't split opcode fields by hand, use the opcode field values
890 provided by igen.
891
3e1dca16
CD		 8922002-03-01 Chris Demetriou <cgd@broadcom.com>
893
894 * mips.igen (do_divu): Fix spacing.
895
896 * mips.igen (do_dsllv): Move to be right before DSLLV,
897 to match the rest of the do_<shift> functions.
898
fff8d27d
CD		 8992002-03-01 Chris Demetriou <cgd@broadcom.com>
900
901 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
902 DSRL32, do_dsrlv): Trace inputs and results.
903
0d3e762b
CD		 9042002-03-01 Chris Demetriou <cgd@broadcom.com>
905
906 * mips.igen (CACHE): Provide instruction-printing string.
907
908 * interp.c (signal_exception): Comment tokens after #endif.
909
eb5fcf93
CD		 9102002-02-28 Chris Demetriou <cgd@broadcom.com>
911
912 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
913 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
914 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
915 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
916 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
917 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
918 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
919 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
920
bb22bd7d
CD		 9212002-02-28 Chris Demetriou <cgd@broadcom.com>
922
923 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
924 instruction-printing string.
925 (LWU): Use '64' as the filter flag.
926
91a177cf
CD		 9272002-02-28 Chris Demetriou <cgd@broadcom.com>
928
929 * mips.igen (SDXC1): Fix instruction-printing string.
930
387f484a
CD		 9312002-02-28 Chris Demetriou <cgd@broadcom.com>
932
933 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
934 filter flags "32,f".
935
3d81f391
CD		 9362002-02-27 Chris Demetriou <cgd@broadcom.com>
937
938 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
939 as the filter flag.
940
af5107af
CD		 9412002-02-27 Chris Demetriou <cgd@broadcom.com>
942
943 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
944 add a comma) so that it more closely match the MIPS ISA
945 documentation opcode partitioning.
946 (PREF): Put useful names on opcode fields, and include
947 instruction-printing string.
948
ca971540
CD		 9492002-02-27 Chris Demetriou <cgd@broadcom.com>
950
951 * mips.igen (check_u64): New function which in the future will
952 check whether 64-bit instructions are usable and signal an
953 exception if not. Currently a no-op.
954 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
955 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
956 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
957 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
958
959 * mips.igen (check_fpu): New function which in the future will
960 check whether FPU instructions are usable and signal an exception
961 if not. Currently a no-op.
962 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
963 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
964 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
965 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
966 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
967 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
968 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
969 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
970
1c47a468
CD		 9712002-02-27 Chris Demetriou <cgd@broadcom.com>
972
973 * mips.igen (do_load_left, do_load_right): Move to be immediately
974 following do_load.
975 (do_store_left, do_store_right): Move to be immediately following
976 do_store.
977
603a98e7
CD		 9782002-02-27 Chris Demetriou <cgd@broadcom.com>
979
980 * mips.igen (mipsV): New model name. Also, add it to
981 all instructions and functions where it is appropriate.
982
c5d00cc7
CD		 9832002-02-18 Chris Demetriou <cgd@broadcom.com>
984
985 * mips.igen: For all functions and instructions, list model
986 names that support that instruction one per line.
987
074e9cb8
CD		 9882002-02-11 Chris Demetriou <cgd@broadcom.com>
989
990 * mips.igen: Add some additional comments about supported
991 models, and about which instructions go where.
992 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
993 order as is used in the rest of the file.
994
9805e229
CD		 9952002-02-11 Chris Demetriou <cgd@broadcom.com>
996
997 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
998 indicating that ALU32_END or ALU64_END are there to check
999 for overflow.
1000 (DADD): Likewise, but also remove previous comment about
1001 overflow checking.
1002
f701dad2
CD		 10032002-02-10 Chris Demetriou <cgd@broadcom.com>
1004
1005 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1006 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1007 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1008 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1009 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1010 fields (i.e., add and move commas) so that they more closely
1011 match the MIPS ISA documentation opcode partitioning.
1012
10132002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 1014
1015 * mips.igen (ADDI): Print immediate value.
1016 (BREAK): Print code.
1017 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1018 (SLL): Print "nop" specially, and don't run the code
1019 that does the shift for the "nop" case.
1020
9e52972e
FF		 10212001-11-17 Fred Fish <fnf@redhat.com>
1022
1023 * sim-main.h (float_operation): Move enum declaration outside
1024 of _sim_cpu struct declaration.
1025
c0efbca4
JB		 10262001-04-12 Jim Blandy <jimb@redhat.com>
1027
1028 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1029 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1030 set of the FCSR.
1031 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1032 PENDING_FILL, and you can get the intended effect gracefully by
1033 calling PENDING_SCHED directly.
1034
fb891446
BE		 10352001-02-23 Ben Elliston <bje@redhat.com>
1036
1037 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1038 already defined elsewhere.
1039
8030f857
BE		 10402001-02-19 Ben Elliston <bje@redhat.com>
1041
1042 * sim-main.h (sim_monitor): Return an int.
1043 * interp.c (sim_monitor): Add return values.
1044 (signal_exception): Handle error conditions from sim_monitor.
1045
56b48a7a
CD		 10462001-02-08 Ben Elliston <bje@redhat.com>
1047
1048 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1049 (store_memory): Likewise, pass cia to sim_core_write*.
1050
d3ee60d9
FCE		 10512000-10-19 Frank Ch. Eigler <fche@redhat.com>
1052
1053 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1054 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1055
071da002
AC		 1056Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1057
1058 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1059 * Makefile.in: Don't delete *.igen when cleaning directory.
1060
a28c02cd
AC		 1061Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1062
1063 * m16.igen (break): Call SignalException not sim_engine_halt.
1064
80ee11fa
AC		 1065Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1066
1067 From Jason Eckhardt:
1068 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1069
673388c0
AC		 1070Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1071
1072 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1073
4c0deff4
NC		 10742000-05-24 Michael Hayes <mhayes@cygnus.com>
1075
1076 * mips.igen (do_dmultx): Fix typo.
1077
eb2d80b4
AC		 1078Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1079
1080 * configure: Regenerated to track ../common/aclocal.m4 changes.
1081
dd37a34b
AC		 1082Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1083
1084 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1085
4c0deff4
NC		 10862000-04-12 Frank Ch. Eigler <fche@redhat.com>
1087
1088 * sim-main.h (GPR_CLEAR): Define macro.
1089
e30db738
AC		 1090Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1091
1092 * interp.c (decode_coproc): Output long using %lx and not %s.
1093
cb7450ea
FCE		 10942000-03-21 Frank Ch. Eigler <fche@redhat.com>
1095
1096 * interp.c (sim_open): Sort & extend dummy memory regions for
1097 --board=jmr3904 for eCos.
1098
a3027dd7
FCE		 10992000-03-02 Frank Ch. Eigler <fche@redhat.com>
1100
1101 * configure: Regenerated.
1102
1103Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1104
1105 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1106 calls, conditional on the simulator being in verbose mode.
1107
dfcd3bfb
JM		 1108Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1109
1110 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1111 cache don't get ReservedInstruction traps.
1112
c2d11a7d
JM		 11131999-11-29 Mark Salter <msalter@cygnus.com>
1114
1115 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1116 to clear status bits in sdisr register. This is how the hardware works.
1117
1118 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1119 being used by cygmon.
1120
4ce44c66
JM		 11211999-11-11 Andrew Haley <aph@cygnus.com>
1122
1123 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1124 instructions.
1125
cff3e48b
JM		 1126Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1127
1128 * mips.igen (MULT): Correct previous mis-applied patch.
1129
d4f3574e
SS		 1130Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1131
1132 * mips.igen (delayslot32): Handle sequence like
1133 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1134 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1135 (MULT): Actually pass the third register...
1136
11371999-09-03 Mark Salter <msalter@cygnus.com>
1138
1139 * interp.c (sim_open): Added more memory aliases for additional
1140 hardware being touched by cygmon on jmr3904 board.
1141
1142Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1143
1144 * configure: Regenerated to track ../common/aclocal.m4 changes.
1145
a0b3c4fd
JM		 1146Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1147
1148 * interp.c (sim_store_register): Handle case where client - GDB -
1149 specifies that a 4 byte register is 8 bytes in size.
1150 (sim_fetch_register): Ditto.
1151
adf40b2e
JM		 11521999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1153
1154 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1155 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1156 (idt_monitor_base): Base address for IDT monitor traps.
1157 (pmon_monitor_base): Ditto for PMON.
1158 (lsipmon_monitor_base): Ditto for LSI PMON.
1159 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1160 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1161 (sim_firmware_command): New function.
1162 (mips_option_handler): Call it for OPTION_FIRMWARE.
1163 (sim_open): Allocate memory for idt_monitor region. If "--board"
1164 option was given, add no monitor by default. Add BREAK hooks only if
1165 monitors are also there.
1166
43e526b9
JM		 1167Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1168
1169 * interp.c (sim_monitor): Flush output before reading input.
1170
1171Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1172
1173 * tconfig.in (SIM_HANDLES_LMA): Always define.
1174
1175Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1176
1177 From Mark Salter <msalter@cygnus.com>:
1178 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1179 (sim_open): Add setup for BSP board.
1180
9846de1b
JM		 1181Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1182
1183 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1184 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1185 them as unimplemented.
1186
cd0fc7c3
SS		 11871999-05-08 Felix Lee <flee@cygnus.com>
1188
1189 * configure: Regenerated to track ../common/aclocal.m4 changes.
1190
7a292a7a
SS		 11911999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1192
1193 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1194
1195Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1196
1197 * configure.in: Any mips64vr5*-*-* target should have
1198 -DTARGET_ENABLE_FR=1.
1199 (default_endian): Any mips64vr*el-*-* target should default to
1200 LITTLE_ENDIAN.
1201 * configure: Re-generate.
1202
12031999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1204
1205 * mips.igen (ldl): Extend from _16_, not 32.
1206
1207Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1208
1209 * interp.c (sim_store_register): Force registers written to by GDB
1210 into an un-interpreted state.
1211
c906108c
SS		 12121999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1213
1214 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1215 CPU, start periodic background I/O polls.
1216 (tx3904sio_poll): New function: periodic I/O poller.
1217
12181998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1219
1220 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1221
1222Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1223
1224 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1225 case statement.
1226
12271998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1228
1229 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1230 (load_word): Call SIM_CORE_SIGNAL hook on error.
1231 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1232 starting. For exception dispatching, pass PC instead of NULL_CIA.
1233 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1234 * sim-main.h (COP0_BADVADDR): Define.
1235 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1236 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1237 (_sim_cpu): Add exc_* fields to store register value snapshots.
1238 * mips.igen (*): Replace memory-related SignalException* calls
1239 with references to SIM_CORE_SIGNAL hook.
1240
1241 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1242 fix.
1243 * sim-main.c (*): Minor warning cleanups.
1244
12451998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1246
1247 * m16.igen (DADDIU5): Correct type-o.
1248
1249Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1250
1251 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1252 variables.
1253
1254Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1255
1256 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1257 to include path.
1258 (interp.o): Add dependency on itable.h
1259 (oengine.c, gencode): Delete remaining references.
1260 (BUILT_SRC_FROM_GEN): Clean up.
1261
12621998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1263
1264 * vr4run.c: New.
1265 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1266 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1267 tmp-run-hack) : New.
1268 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1269 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1270 Drop the "64" qualifier to get the HACK generator working.
1271 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1272 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1273 qualifier to get the hack generator working.
1274 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1275 (DSLL): Use do_dsll.
1276 (DSLLV): Use do_dsllv.
1277 (DSRA): Use do_dsra.
1278 (DSRL): Use do_dsrl.
1279 (DSRLV): Use do_dsrlv.
1280 (BC1): Move *vr4100 to get the HACK generator working.
1281 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1282 get the HACK generator working.
1283 (MACC) Rename to get the HACK generator working.
1284 (DMACC,MACCS,DMACCS): Add the 64.
1285
12861998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1287
1288 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1289 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1290
12911998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1292
1293 * mips/interp.c (DEBUG): Cleanups.
1294
12951998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1296
1297 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1298 (tx3904sio_tickle): fflush after a stdout character output.
1299
13001998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1301
1302 * interp.c (sim_close): Uninstall modules.
1303
1304Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1305
1306 * sim-main.h, interp.c (sim_monitor): Change to global
1307 function.
1308
1309Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1310
1311 * configure.in (vr4100): Only include vr4100 instructions in
1312 simulator.
1313 * configure: Re-generate.
1314 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1315
1316Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1317
1318 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1319 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1320 true alternative.
1321
1322 * configure.in (sim_default_gen, sim_use_gen): Replace with
1323 sim_gen.
1324 (--enable-sim-igen): Delete config option. Always using IGEN.
1325 * configure: Re-generate.
1326
1327 * Makefile.in (gencode): Kill, kill, kill.
1328 * gencode.c: Ditto.
1329
1330Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1331
1332 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1333 bit mips16 igen simulator.
1334 * configure: Re-generate.
1335
1336 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1337 as part of vr4100 ISA.
1338 * vr.igen: Mark all instructions as 64 bit only.
1339
1340Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1341
1342 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1343 Pacify GCC.
1344
1345Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1346
1347 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1348 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1349 * configure: Re-generate.
1350
1351 * m16.igen (BREAK): Define breakpoint instruction.
1352 (JALX32): Mark instruction as mips16 and not r3900.
1353 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1354
1355 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1356
1357Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1358
1359 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1360 insn as a debug breakpoint.
1361
1362 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1363 pending.slot_size.
1364 (PENDING_SCHED): Clean up trace statement.
1365 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1366 (PENDING_FILL): Delay write by only one cycle.
1367 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1368
1369 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1370 of pending writes.
1371 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1372 32 & 64.
1373 (pending_tick): Move incrementing of index to FOR statement.
1374 (pending_tick): Only update PENDING_OUT after a write has occured.
1375
1376 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1377 build simulator.
1378 * configure: Re-generate.
1379
1380 * interp.c (sim_engine_run OLD): Delete explicit call to
1381 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1382
1383Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1384
1385 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1386 interrupt level number to match changed SignalExceptionInterrupt
1387 macro.
1388
1389Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1390
1391 * interp.c: #include "itable.h" if WITH_IGEN.
1392 (get_insn_name): New function.
1393 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1394 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1395
1396Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1397
1398 * configure: Rebuilt to inhale new common/aclocal.m4.
1399
1400Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1401
1402 * dv-tx3904sio.c: Include sim-assert.h.
1403
1404Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1405
1406 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1407 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1408 Reorganize target-specific sim-hardware checks.
1409 * configure: rebuilt.
1410 * interp.c (sim_open): For tx39 target boards, set
1411 OPERATING_ENVIRONMENT, add tx3904sio devices.
1412 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1413 ROM executables. Install dv-sockser into sim-modules list.
1414
1415 * dv-tx3904irc.c: Compiler warning clean-up.
1416 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1417 frequent hw-trace messages.
1418
1419Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1420
1421 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1422
1423Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1424
1425 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1426
1427 * vr.igen: New file.
1428 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1429 * mips.igen: Define vr4100 model. Include vr.igen.
1430Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1431
1432 * mips.igen (check_mf_hilo): Correct check.
1433
1434Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1435
1436 * sim-main.h (interrupt_event): Add prototype.
1437
1438 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1439 register_ptr, register_value.
1440 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1441
1442 * sim-main.h (tracefh): Make extern.
1443
1444Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1445
1446 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1447 Reduce unnecessarily high timer event frequency.
1448 * dv-tx3904cpu.c: Ditto for interrupt event.
1449
1450Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1451
1452 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1453 to allay warnings.
1454 (interrupt_event): Made non-static.
1455
1456 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1457 interchange of configuration values for external vs. internal
1458 clock dividers.
1459
1460Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1461
1462 * mips.igen (BREAK): Moved code to here for
1463 simulator-reserved break instructions.
1464 * gencode.c (build_instruction): Ditto.
1465 * interp.c (signal_exception): Code moved from here. Non-
1466 reserved instructions now use exception vector, rather
1467 than halting sim.
1468 * sim-main.h: Moved magic constants to here.
1469
1470Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1471
1472 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1473 register upon non-zero interrupt event level, clear upon zero
1474 event value.
1475 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1476 by passing zero event value.
1477 (*_io_{read,write}_buffer): Endianness fixes.
1478 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1479 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1480
1481 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1482 serial I/O and timer module at base address 0xFFFF0000.
1483
1484Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1485
1486 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1487 and BigEndianCPU.
1488
1489Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1490
1491 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1492 parts.
1493 * configure: Update.
1494
1495Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1496
1497 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1498 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1499 * configure.in: Include tx3904tmr in hw_device list.
1500 * configure: Rebuilt.
1501 * interp.c (sim_open): Instantiate three timer instances.
1502 Fix address typo of tx3904irc instance.
1503
1504Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1505
1506 * interp.c (signal_exception): SystemCall exception now uses
1507 the exception vector.
1508
1509Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1510
1511 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1512 to allay warnings.
1513
1514Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1515
1516 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1517
1518Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1519
1520 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1521
1522 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1523 sim-main.h. Declare a struct hw_descriptor instead of struct
1524 hw_device_descriptor.
1525
1526Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1527
1528 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1529 right bits and then re-align left hand bytes to correct byte
1530 lanes. Fix incorrect computation in do_store_left when loading
1531 bytes from second word.
1532
1533Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1534
1535 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1536 * interp.c (sim_open): Only create a device tree when HW is
1537 enabled.
1538
1539 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1540 * interp.c (signal_exception): Ditto.
1541
1542Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1543
1544 * gencode.c: Mark BEGEZALL as LIKELY.
1545
1546Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1547
1548 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1549 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1550
1551Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1552
1553 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1554 modules. Recognize TX39 target with "mips*tx39" pattern.
1555 * configure: Rebuilt.
1556 * sim-main.h (*): Added many macros defining bits in
1557 TX39 control registers.
1558 (SignalInterrupt): Send actual PC instead of NULL.
1559 (SignalNMIReset): New exception type.
1560 * interp.c (board): New variable for future use to identify
1561 a particular board being simulated.
1562 (mips_option_handler,mips_options): Added "--board" option.
1563 (interrupt_event): Send actual PC.
1564 (sim_open): Make memory layout conditional on board setting.
1565 (signal_exception): Initial implementation of hardware interrupt
1566 handling. Accept another break instruction variant for simulator
1567 exit.
1568 (decode_coproc): Implement RFE instruction for TX39.
1569 (mips.igen): Decode RFE instruction as such.
1570 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1571 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1572 bbegin to implement memory map.
1573 * dv-tx3904cpu.c: New file.
1574 * dv-tx3904irc.c: New file.
1575
1576Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1577
1578 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1579
1580Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1581
1582 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1583 with calls to check_div_hilo.
1584
1585Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1586
1587 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1588 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1589 Add special r3900 version of do_mult_hilo.
1590 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1591 with calls to check_mult_hilo.
1592 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1593 with calls to check_div_hilo.
1594
1595Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1596
1597 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1598 Document a replacement.
1599
1600Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1601
1602 * interp.c (sim_monitor): Make mon_printf work.
1603
1604Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1605
1606 * sim-main.h (INSN_NAME): New arg `cpu'.
1607
1608Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1609
1610 * configure: Regenerated to track ../common/aclocal.m4 changes.
1611
1612Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1613
1614 * configure: Regenerated to track ../common/aclocal.m4 changes.
1615 * config.in: Ditto.
1616
1617Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1618
1619 * acconfig.h: New file.
1620 * configure.in: Reverted change of Apr 24; use sinclude again.
1621
1622Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1623
1624 * configure: Regenerated to track ../common/aclocal.m4 changes.
1625 * config.in: Ditto.
1626
1627Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1628
1629 * configure.in: Don't call sinclude.
1630
1631Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1632
1633 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1634
1635Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1636
1637 * mips.igen (ERET): Implement.
1638
1639 * interp.c (decode_coproc): Return sign-extended EPC.
1640
1641 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1642
1643 * interp.c (signal_exception): Do not ignore Trap.
1644 (signal_exception): On TRAP, restart at exception address.
1645 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1646 (signal_exception): Update.
1647 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1648 so that TRAP instructions are caught.
1649
1650Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1651
1652 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1653 contains HI/LO access history.
1654 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1655 (HIACCESS, LOACCESS): Delete, replace with
1656 (HIHISTORY, LOHISTORY): New macros.
1657 (CHECKHILO): Delete all, moved to mips.igen
1658
1659 * gencode.c (build_instruction): Do not generate checks for
1660 correct HI/LO register usage.
1661
1662 * interp.c (old_engine_run): Delete checks for correct HI/LO
1663 register usage.
1664
1665 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1666 check_mf_cycles): New functions.
1667 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1668 do_divu, domultx, do_mult, do_multu): Use.
1669
1670 * tx.igen ("madd", "maddu"): Use.
1671
1672Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1673
1674 * mips.igen (DSRAV): Use function do_dsrav.
1675 (SRAV): Use new function do_srav.
1676
1677 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1678 (B): Sign extend 11 bit immediate.
1679 (EXT-B*): Shift 16 bit immediate left by 1.
1680 (ADDIU*): Don't sign extend immediate value.
1681
1682Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1683
1684 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1685
1686 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1687 functions.
1688
1689 * mips.igen (delayslot32, nullify_next_insn): New functions.
1690 (m16.igen): Always include.
1691 (do_*): Add more tracing.
1692
1693 * m16.igen (delayslot16): Add NIA argument, could be called by a
1694 32 bit MIPS16 instruction.
1695
1696 * interp.c (ifetch16): Move function from here.
1697 * sim-main.c (ifetch16): To here.
1698
1699 * sim-main.c (ifetch16, ifetch32): Update to match current
1700 implementations of LH, LW.
1701 (signal_exception): Don't print out incorrect hex value of illegal
1702 instruction.
1703
1704Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1705
1706 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1707 instruction.
1708
1709 * m16.igen: Implement MIPS16 instructions.
1710
1711 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1712 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1713 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1714 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1715 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1716 bodies of corresponding code from 32 bit insn to these. Also used
1717 by MIPS16 versions of functions.
1718
1719 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1720 (IMEM16): Drop NR argument from macro.
1721
1722Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1723
1724 * Makefile.in (SIM_OBJS): Add sim-main.o.
1725
1726 * sim-main.h (address_translation, load_memory, store_memory,
1727 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1728 as INLINE_SIM_MAIN.
1729 (pr_addr, pr_uword64): Declare.
1730 (sim-main.c): Include when H_REVEALS_MODULE_P.
1731
1732 * interp.c (address_translation, load_memory, store_memory,
1733 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1734 from here.
1735 * sim-main.c: To here. Fix compilation problems.
1736
1737 * configure.in: Enable inlining.
1738 * configure: Re-config.
1739
1740Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1741
1742 * configure: Regenerated to track ../common/aclocal.m4 changes.
1743
1744Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1745
1746 * mips.igen: Include tx.igen.
1747 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1748 * tx.igen: New file, contains MADD and MADDU.
1749
1750 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1751 the hardwired constant `7'.
1752 (store_memory): Ditto.
1753 (LOADDRMASK): Move definition to sim-main.h.
1754
1755 mips.igen (MTC0): Enable for r3900.
1756 (ADDU): Add trace.
1757
1758 mips.igen (do_load_byte): Delete.
1759 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1760 do_store_right): New functions.
1761 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1762
1763 configure.in: Let the tx39 use igen again.
1764 configure: Update.
1765
1766Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1767
1768 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1769 not an address sized quantity. Return zero for cache sizes.
1770
1771Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1772
1773 * mips.igen (r3900): r3900 does not support 64 bit integer
1774 operations.
1775
1776Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1777
1778 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1779 than igen one.
1780 * configure : Rebuild.
1781
1782Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1783
1784 * configure: Regenerated to track ../common/aclocal.m4 changes.
1785
1786Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1787
1788 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1789
1790Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1791
1792 * configure: Regenerated to track ../common/aclocal.m4 changes.
1793 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1794
1795Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1796
1797 * configure: Regenerated to track ../common/aclocal.m4 changes.
1798
1799Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1800
1801 * interp.c (Max, Min): Comment out functions. Not yet used.
1802
1803Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1804
1805 * configure: Regenerated to track ../common/aclocal.m4 changes.
1806
1807Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1808
1809 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1810 configurable settings for stand-alone simulator.
1811
1812 * configure.in: Added X11 search, just in case.
1813
1814 * configure: Regenerated.
1815
1816Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1817
1818 * interp.c (sim_write, sim_read, load_memory, store_memory):
1819 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1820
1821Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1822
1823 * sim-main.h (GETFCC): Return an unsigned value.
1824
1825Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1826
1827 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1828 (DADD): Result destination is RD not RT.
1829
1830Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1831
1832 * sim-main.h (HIACCESS, LOACCESS): Always define.
1833
1834 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1835
1836 * interp.c (sim_info): Delete.
1837
1838Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1839
1840 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1841 (mips_option_handler): New argument `cpu'.
1842 (sim_open): Update call to sim_add_option_table.
1843
1844Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1845
1846 * mips.igen (CxC1): Add tracing.
1847
1848Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1849
1850 * sim-main.h (Max, Min): Declare.
1851
1852 * interp.c (Max, Min): New functions.
1853
1854 * mips.igen (BC1): Add tracing.
1855
1856Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1857
1858 * interp.c Added memory map for stack in vr4100
1859
1860Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1861
1862 * interp.c (load_memory): Add missing "break"'s.
1863
1864Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1865
1866 * interp.c (sim_store_register, sim_fetch_register): Pass in
1867 length parameter. Return -1.
1868
1869Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1870
1871 * interp.c: Added hardware init hook, fixed warnings.
1872
1873Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1874
1875 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1876
1877Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1878
1879 * interp.c (ifetch16): New function.
1880
1881 * sim-main.h (IMEM32): Rename IMEM.
1882 (IMEM16_IMMED): Define.
1883 (IMEM16): Define.
1884 (DELAY_SLOT): Update.
1885
1886 * m16run.c (sim_engine_run): New file.
1887
1888 * m16.igen: All instructions except LB.
1889 (LB): Call do_load_byte.
1890 * mips.igen (do_load_byte): New function.
1891 (LB): Call do_load_byte.
1892
1893 * mips.igen: Move spec for insn bit size and high bit from here.
1894 * Makefile.in (tmp-igen, tmp-m16): To here.
1895
1896 * m16.dc: New file, decode mips16 instructions.
1897
1898 * Makefile.in (SIM_NO_ALL): Define.
1899 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1900
1901Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1902
1903 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1904 point unit to 32 bit registers.
1905 * configure: Re-generate.
1906
1907Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1908
1909 * configure.in (sim_use_gen): Make IGEN the default simulator
1910 generator for generic 32 and 64 bit mips targets.
1911 * configure: Re-generate.
1912
1913Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1914
1915 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1916 bitsize.
1917
1918 * interp.c (sim_fetch_register, sim_store_register): Read/write
1919 FGR from correct location.
1920 (sim_open): Set size of FGR's according to
1921 WITH_TARGET_FLOATING_POINT_BITSIZE.
1922
1923 * sim-main.h (FGR): Store floating point registers in a separate
1924 array.
1925
1926Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1927
1928 * configure: Regenerated to track ../common/aclocal.m4 changes.
1929
1930Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1931
1932 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1933
1934 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1935
1936 * interp.c (pending_tick): New function. Deliver pending writes.
1937
1938 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1939 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1940 it can handle mixed sized quantites and single bits.
1941
1942Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1943
1944 * interp.c (oengine.h): Do not include when building with IGEN.
1945 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1946 (sim_info): Ditto for PROCESSOR_64BIT.
1947 (sim_monitor): Replace ut_reg with unsigned_word.
1948 (*): Ditto for t_reg.
1949 (LOADDRMASK): Define.
1950 (sim_open): Remove defunct check that host FP is IEEE compliant,
1951 using software to emulate floating point.
1952 (value_fpr, ...): Always compile, was conditional on HASFPU.
1953
1954Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1955
1956 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1957 size.
1958
1959 * interp.c (SD, CPU): Define.
1960 (mips_option_handler): Set flags in each CPU.
1961 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1962 (sim_close): Do not clear STATE, deleted anyway.
1963 (sim_write, sim_read): Assume CPU zero's vm should be used for
1964 data transfers.
1965 (sim_create_inferior): Set the PC for all processors.
1966 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1967 argument.
1968 (mips16_entry): Pass correct nr of args to store_word, load_word.
1969 (ColdReset): Cold reset all cpu's.
1970 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1971 (sim_monitor, load_memory, store_memory, signal_exception): Use
1972 `CPU' instead of STATE_CPU.
1973
1974
1975 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1976 SD or CPU_.
1977
1978 * sim-main.h (signal_exception): Add sim_cpu arg.
1979 (SignalException*): Pass both SD and CPU to signal_exception.
1980 * interp.c (signal_exception): Update.
1981
1982 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1983 Ditto
1984 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1985 address_translation): Ditto
1986 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1987
1988Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1989
1990 * configure: Regenerated to track ../common/aclocal.m4 changes.
1991
1992Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1993
1994 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1995
1996 * mips.igen (model): Map processor names onto BFD name.
1997
1998 * sim-main.h (CPU_CIA): Delete.
1999 (SET_CIA, GET_CIA): Define
2000
2001Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2002
2003 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2004 regiser.
2005
2006 * configure.in (default_endian): Configure a big-endian simulator
2007 by default.
2008 * configure: Re-generate.
2009
2010Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2011
2012 * configure: Regenerated to track ../common/aclocal.m4 changes.
2013
2014Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2015
2016 * interp.c (sim_monitor): Handle Densan monitor outbyte
2017 and inbyte functions.
2018
20191997-12-29 Felix Lee <flee@cygnus.com>
2020
2021 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2022
2023Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2024
2025 * Makefile.in (tmp-igen): Arrange for $zero to always be
2026 reset to zero after every instruction.
2027
2028Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2029
2030 * configure: Regenerated to track ../common/aclocal.m4 changes.
2031 * config.in: Ditto.
2032
2033Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2034
2035 * mips.igen (MSUB): Fix to work like MADD.
2036 * gencode.c (MSUB): Similarly.
2037
2038Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2039
2040 * configure: Regenerated to track ../common/aclocal.m4 changes.
2041
2042Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2043
2044 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2045
2046Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2047
2048 * sim-main.h (sim-fpu.h): Include.
2049
2050 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2051 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2052 using host independant sim_fpu module.
2053
2054Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2055
2056 * interp.c (signal_exception): Report internal errors with SIGABRT
2057 not SIGQUIT.
2058
2059 * sim-main.h (C0_CONFIG): New register.
2060 (signal.h): No longer include.
2061
2062 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2063
2064Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2065
2066 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2067
2068Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2069
2070 * mips.igen: Tag vr5000 instructions.
2071 (ANDI): Was missing mipsIV model, fix assembler syntax.
2072 (do_c_cond_fmt): New function.
2073 (C.cond.fmt): Handle mips I-III which do not support CC field
2074 separatly.
2075 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2076 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2077 in IV3.2 spec.
2078 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2079 vr5000 which saves LO in a GPR separatly.
2080
2081 * configure.in (enable-sim-igen): For vr5000, select vr5000
2082 specific instructions.
2083 * configure: Re-generate.
2084
2085Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2086
2087 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2088
2089 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2090 fmt_uninterpreted_64 bit cases to switch. Convert to
2091 fmt_formatted,
2092
2093 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2094
2095 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2096 as specified in IV3.2 spec.
2097 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2098
2099Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2100
2101 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2102 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2103 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2104 PENDING_FILL versions of instructions. Simplify.
2105 (X): New function.
2106 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2107 instructions.
2108 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2109 a signed value.
2110 (MTHI, MFHI): Disable code checking HI-LO.
2111
2112 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2113 global.
2114 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2115
2116Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2117
2118 * gencode.c (build_mips16_operands): Replace IPC with cia.
2119
2120 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2121 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2122 IPC to `cia'.
2123 (UndefinedResult): Replace function with macro/function
2124 combination.
2125 (sim_engine_run): Don't save PC in IPC.
2126
2127 * sim-main.h (IPC): Delete.
2128
2129
2130 * interp.c (signal_exception, store_word, load_word,
2131 address_translation, load_memory, store_memory, cache_op,
2132 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2133 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2134 current instruction address - cia - argument.
2135 (sim_read, sim_write): Call address_translation directly.
2136 (sim_engine_run): Rename variable vaddr to cia.
2137 (signal_exception): Pass cia to sim_monitor
2138
2139 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2140 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2141 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2142
2143 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2144 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2145 SIM_ASSERT.
2146
2147 * interp.c (signal_exception): Pass restart address to
2148 sim_engine_restart.
2149
2150 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2151 idecode.o): Add dependency.
2152
2153 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2154 Delete definitions
2155 (DELAY_SLOT): Update NIA not PC with branch address.
2156 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2157
2158 * mips.igen: Use CIA not PC in branch calculations.
2159 (illegal): Call SignalException.
2160 (BEQ, ADDIU): Fix assembler.
2161
2162Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2163
2164 * m16.igen (JALX): Was missing.
2165
2166 * configure.in (enable-sim-igen): New configuration option.
2167 * configure: Re-generate.
2168
2169 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2170
2171 * interp.c (load_memory, store_memory): Delete parameter RAW.
2172 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2173 bypassing {load,store}_memory.
2174
2175 * sim-main.h (ByteSwapMem): Delete definition.
2176
2177 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2178
2179 * interp.c (sim_do_command, sim_commands): Delete mips specific
2180 commands. Handled by module sim-options.
2181
2182 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2183 (WITH_MODULO_MEMORY): Define.
2184
2185 * interp.c (sim_info): Delete code printing memory size.
2186
2187 * interp.c (mips_size): Nee sim_size, delete function.
2188 (power2): Delete.
2189 (monitor, monitor_base, monitor_size): Delete global variables.
2190 (sim_open, sim_close): Delete code creating monitor and other
2191 memory regions. Use sim-memopts module, via sim_do_commandf, to
2192 manage memory regions.
2193 (load_memory, store_memory): Use sim-core for memory model.
2194
2195 * interp.c (address_translation): Delete all memory map code
2196 except line forcing 32 bit addresses.
2197
2198Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2199
2200 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2201 trace options.
2202
2203 * interp.c (logfh, logfile): Delete globals.
2204 (sim_open, sim_close): Delete code opening & closing log file.
2205 (mips_option_handler): Delete -l and -n options.
2206 (OPTION mips_options): Ditto.
2207
2208 * interp.c (OPTION mips_options): Rename option trace to dinero.
2209 (mips_option_handler): Update.
2210
2211Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2212
2213 * interp.c (fetch_str): New function.
2214 (sim_monitor): Rewrite using sim_read & sim_write.
2215 (sim_open): Check magic number.
2216 (sim_open): Write monitor vectors into memory using sim_write.
2217 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2218 (sim_read, sim_write): Simplify - transfer data one byte at a
2219 time.
2220 (load_memory, store_memory): Clarify meaning of parameter RAW.
2221
2222 * sim-main.h (isHOST): Defete definition.
2223 (isTARGET): Mark as depreciated.
2224 (address_translation): Delete parameter HOST.
2225
2226 * interp.c (address_translation): Delete parameter HOST.
2227
2228Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2229
2230 * mips.igen:
2231
2232 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2233 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2234
2235Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2236
2237 * mips.igen: Add model filter field to records.
2238
2239Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2240
2241 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2242
2243 interp.c (sim_engine_run): Do not compile function sim_engine_run
2244 when WITH_IGEN == 1.
2245
2246 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2247 target architecture.
2248
2249 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2250 igen. Replace with configuration variables sim_igen_flags /
2251 sim_m16_flags.
2252
2253 * m16.igen: New file. Copy mips16 insns here.
2254 * mips.igen: From here.
2255
2256Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2257
2258 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2259 to top.
2260 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2261
2262Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2263
2264 * gencode.c (build_instruction): Follow sim_write's lead in using
2265 BigEndianMem instead of !ByteSwapMem.
2266
2267Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2268
2269 * configure.in (sim_gen): Dependent on target, select type of
2270 generator. Always select old style generator.
2271
2272 configure: Re-generate.
2273
2274 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2275 targets.
2276 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2277 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2278 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2279 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2280 SIM_@sim_gen@_*, set by autoconf.
2281
2282Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2283
2284 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2285
2286 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2287 CURRENT_FLOATING_POINT instead.
2288
2289 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2290 (address_translation): Raise exception InstructionFetch when
2291 translation fails and isINSTRUCTION.
2292
2293 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2294 sim_engine_run): Change type of of vaddr and paddr to
2295 address_word.
2296 (address_translation, prefetch, load_memory, store_memory,
2297 cache_op): Change type of vAddr and pAddr to address_word.
2298
2299 * gencode.c (build_instruction): Change type of vaddr and paddr to
2300 address_word.
2301
2302Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2303
2304 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2305 macro to obtain result of ALU op.
2306
2307Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2308
2309 * interp.c (sim_info): Call profile_print.
2310
2311Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2312
2313 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2314
2315 * sim-main.h (WITH_PROFILE): Do not define, defined in
2316 common/sim-config.h. Use sim-profile module.
2317 (simPROFILE): Delete defintion.
2318
2319 * interp.c (PROFILE): Delete definition.
2320 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2321 (sim_close): Delete code writing profile histogram.
2322 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2323 Delete.
2324 (sim_engine_run): Delete code profiling the PC.
2325
2326Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2327
2328 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2329
2330 * interp.c (sim_monitor): Make register pointers of type
2331 unsigned_word*.
2332
2333 * sim-main.h: Make registers of type unsigned_word not
2334 signed_word.
2335
2336Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2337
2338 * interp.c (sync_operation): Rename from SyncOperation, make
2339 global, add SD argument.
2340 (prefetch): Rename from Prefetch, make global, add SD argument.
2341 (decode_coproc): Make global.
2342
2343 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2344
2345 * gencode.c (build_instruction): Generate DecodeCoproc not
2346 decode_coproc calls.
2347
2348 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2349 (SizeFGR): Move to sim-main.h
2350 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2351 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2352 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2353 sim-main.h.
2354 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2355 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2356 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2357 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2358 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2359 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2360
2361 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2362 exception.
2363 (sim-alu.h): Include.
2364 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2365 (sim_cia): Typedef to instruction_address.
2366
2367Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2368
2369 * Makefile.in (interp.o): Rename generated file engine.c to
2370 oengine.c.
2371
2372 * interp.c: Update.
2373
2374Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2375
2376 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2377
2378Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2379
2380 * gencode.c (build_instruction): For "FPSQRT", output correct
2381 number of arguments to Recip.
2382
2383Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2384
2385 * Makefile.in (interp.o): Depends on sim-main.h
2386
2387 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2388
2389 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2390 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2391 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2392 STATE, DSSTATE): Define
2393 (GPR, FGRIDX, ..): Define.
2394
2395 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2396 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2397 (GPR, FGRIDX, ...): Delete macros.
2398
2399 * interp.c: Update names to match defines from sim-main.h
2400
2401Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2402
2403 * interp.c (sim_monitor): Add SD argument.
2404 (sim_warning): Delete. Replace calls with calls to
2405 sim_io_eprintf.
2406 (sim_error): Delete. Replace calls with sim_io_error.
2407 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2408 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2409 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2410 argument.
2411 (mips_size): Rename from sim_size. Add SD argument.
2412
2413 * interp.c (simulator): Delete global variable.
2414 (callback): Delete global variable.
2415 (mips_option_handler, sim_open, sim_write, sim_read,
2416 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2417 sim_size,sim_monitor): Use sim_io_* not callback->*.
2418 (sim_open): ZALLOC simulator struct.
2419 (PROFILE): Do not define.
2420
2421Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2422
2423 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2424 support.h with corresponding code.
2425
2426 * sim-main.h (word64, uword64), support.h: Move definition to
2427 sim-main.h.
2428 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2429
2430 * support.h: Delete
2431 * Makefile.in: Update dependencies
2432 * interp.c: Do not include.
2433
2434Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2435
2436 * interp.c (address_translation, load_memory, store_memory,
2437 cache_op): Rename to from AddressTranslation et.al., make global,
2438 add SD argument
2439
2440 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2441 CacheOp): Define.
2442
2443 * interp.c (SignalException): Rename to signal_exception, make
2444 global.
2445
2446 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2447
2448 * sim-main.h (SignalException, SignalExceptionInterrupt,
2449 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2450 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2451 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2452 Define.
2453
2454 * interp.c, support.h: Use.
2455
2456Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2457
2458 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2459 to value_fpr / store_fpr. Add SD argument.
2460 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2461 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2462
2463 * sim-main.h (ValueFPR, StoreFPR): Define.
2464
2465Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2466
2467 * interp.c (sim_engine_run): Check consistency between configure
2468 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2469 and HASFPU.
2470
2471 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2472 (mips_fpu): Configure WITH_FLOATING_POINT.
2473 (mips_endian): Configure WITH_TARGET_ENDIAN.
2474 * configure: Update.
2475
2476Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2477
2478 * configure: Regenerated to track ../common/aclocal.m4 changes.
2479
2480Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2481
2482 * configure: Regenerated.
2483
2484Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2485
2486 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2487
2488Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2489
2490 * gencode.c (print_igen_insn_models): Assume certain architectures
2491 include all mips* instructions.
2492 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2493 instruction.
2494
2495 * Makefile.in (tmp.igen): Add target. Generate igen input from
2496 gencode file.
2497
2498 * gencode.c (FEATURE_IGEN): Define.
2499 (main): Add --igen option. Generate output in igen format.
2500 (process_instructions): Format output according to igen option.
2501 (print_igen_insn_format): New function.
2502 (print_igen_insn_models): New function.
2503 (process_instructions): Only issue warnings and ignore
2504 instructions when no FEATURE_IGEN.
2505
2506Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2507
2508 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2509 MIPS targets.
2510
2511Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2512
2513 * configure: Regenerated to track ../common/aclocal.m4 changes.
2514
2515Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2516
2517 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2518 SIM_RESERVED_BITS): Delete, moved to common.
2519 (SIM_EXTRA_CFLAGS): Update.
2520
2521Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2522
2523 * configure.in: Configure non-strict memory alignment.
2524 * configure: Regenerated to track ../common/aclocal.m4 changes.
2525
2526Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2527
2528 * configure: Regenerated to track ../common/aclocal.m4 changes.
2529
2530Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2531
2532 * gencode.c (SDBBP,DERET): Added (3900) insns.
2533 (RFE): Turn on for 3900.
2534 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2535 (dsstate): Made global.
2536 (SUBTARGET_R3900): Added.
2537 (CANCELDELAYSLOT): New.
2538 (SignalException): Ignore SystemCall rather than ignore and
2539 terminate. Add DebugBreakPoint handling.
2540 (decode_coproc): New insns RFE, DERET; and new registers Debug
2541 and DEPC protected by SUBTARGET_R3900.
2542 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2543 bits explicitly.
2544 * Makefile.in,configure.in: Add mips subtarget option.
2545 * configure: Update.
2546
2547Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2548
2549 * gencode.c: Add r3900 (tx39).
2550
2551
2552Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2553
2554 * gencode.c (build_instruction): Don't need to subtract 4 for
2555 JALR, just 2.
2556
2557Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2558
2559 * interp.c: Correct some HASFPU problems.
2560
2561Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2562
2563 * configure: Regenerated to track ../common/aclocal.m4 changes.
2564
2565Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2566
2567 * interp.c (mips_options): Fix samples option short form, should
2568 be `x'.
2569
2570Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2571
2572 * interp.c (sim_info): Enable info code. Was just returning.
2573
2574Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2575
2576 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2577 MFC0.
2578
2579Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2580
2581 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2582 constants.
2583 (build_instruction): Ditto for LL.
2584
2585Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2586
2587 * configure: Regenerated to track ../common/aclocal.m4 changes.
2588
2589Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2590
2591 * configure: Regenerated to track ../common/aclocal.m4 changes.
2592 * config.in: Ditto.
2593
2594Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2595
2596 * interp.c (sim_open): Add call to sim_analyze_program, update
2597 call to sim_config.
2598
2599Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2600
2601 * interp.c (sim_kill): Delete.
2602 (sim_create_inferior): Add ABFD argument. Set PC from same.
2603 (sim_load): Move code initializing trap handlers from here.
2604 (sim_open): To here.
2605 (sim_load): Delete, use sim-hload.c.
2606
2607 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2608
2609Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2610
2611 * configure: Regenerated to track ../common/aclocal.m4 changes.
2612 * config.in: Ditto.
2613
2614Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2615
2616 * interp.c (sim_open): Add ABFD argument.
2617 (sim_load): Move call to sim_config from here.
2618 (sim_open): To here. Check return status.
2619
2620Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2621
2622 * gencode.c (build_instruction): Two arg MADD should
2623 not assign result to $0.
2624
2625Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2626
2627 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2628 * sim/mips/configure.in: Regenerate.
2629
2630Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2631
2632 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2633 signed8, unsigned8 et.al. types.
2634
2635 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2636 hosts when selecting subreg.
2637
2638Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2639
2640 * interp.c (sim_engine_run): Reset the ZERO register to zero
2641 regardless of FEATURE_WARN_ZERO.
2642 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2643
2644Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2645
2646 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2647 (SignalException): For BreakPoints ignore any mode bits and just
2648 save the PC.
2649 (SignalException): Always set the CAUSE register.
2650
2651Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2652
2653 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2654 exception has been taken.
2655
2656 * interp.c: Implement the ERET and mt/f sr instructions.
2657
2658Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2659
2660 * interp.c (SignalException): Don't bother restarting an
2661 interrupt.
2662
2663Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2664
2665 * interp.c (SignalException): Really take an interrupt.
2666 (interrupt_event): Only deliver interrupts when enabled.
2667
2668Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2669
2670 * interp.c (sim_info): Only print info when verbose.
2671 (sim_info) Use sim_io_printf for output.
2672
2673Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2674
2675 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2676 mips architectures.
2677
2678Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2679
2680 * interp.c (sim_do_command): Check for common commands if a
2681 simulator specific command fails.
2682
2683Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2684
2685 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2686 and simBE when DEBUG is defined.
2687
2688Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2689
2690 * interp.c (interrupt_event): New function. Pass exception event
2691 onto exception handler.
2692
2693 * configure.in: Check for stdlib.h.
2694 * configure: Regenerate.
2695
2696 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2697 variable declaration.
2698 (build_instruction): Initialize memval1.
2699 (build_instruction): Add UNUSED attribute to byte, bigend,
2700 reverse.
2701 (build_operands): Ditto.
2702
2703 * interp.c: Fix GCC warnings.
2704 (sim_get_quit_code): Delete.
2705
2706 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2707 * Makefile.in: Ditto.
2708 * configure: Re-generate.
2709
2710 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2711
2712Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2713
2714 * interp.c (mips_option_handler): New function parse argumes using
2715 sim-options.
2716 (myname): Replace with STATE_MY_NAME.
2717 (sim_open): Delete check for host endianness - performed by
2718 sim_config.
2719 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2720 (sim_open): Move much of the initialization from here.
2721 (sim_load): To here. After the image has been loaded and
2722 endianness set.
2723 (sim_open): Move ColdReset from here.
2724 (sim_create_inferior): To here.
2725 (sim_open): Make FP check less dependant on host endianness.
2726
2727 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2728 run.
2729 * interp.c (sim_set_callbacks): Delete.
2730
2731 * interp.c (membank, membank_base, membank_size): Replace with
2732 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2733 (sim_open): Remove call to callback->init. gdb/run do this.
2734
2735 * interp.c: Update
2736
2737 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2738
2739 * interp.c (big_endian_p): Delete, replaced by
2740 current_target_byte_order.
2741
2742Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2743
2744 * interp.c (host_read_long, host_read_word, host_swap_word,
2745 host_swap_long): Delete. Using common sim-endian.
2746 (sim_fetch_register, sim_store_register): Use H2T.
2747 (pipeline_ticks): Delete. Handled by sim-events.
2748 (sim_info): Update.
2749 (sim_engine_run): Update.
2750
2751Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2752
2753 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2754 reason from here.
2755 (SignalException): To here. Signal using sim_engine_halt.
2756 (sim_stop_reason): Delete, moved to common.
2757
2758Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2759
2760 * interp.c (sim_open): Add callback argument.
2761 (sim_set_callbacks): Delete SIM_DESC argument.
2762 (sim_size): Ditto.
2763
2764Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2765
2766 * Makefile.in (SIM_OBJS): Add common modules.
2767
2768 * interp.c (sim_set_callbacks): Also set SD callback.
2769 (set_endianness, xfer_*, swap_*): Delete.
2770 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2771 Change to functions using sim-endian macros.
2772 (control_c, sim_stop): Delete, use common version.
2773 (simulate): Convert into.
2774 (sim_engine_run): This function.
2775 (sim_resume): Delete.
2776
2777 * interp.c (simulation): New variable - the simulator object.
2778 (sim_kind): Delete global - merged into simulation.
2779 (sim_load): Cleanup. Move PC assignment from here.
2780 (sim_create_inferior): To here.
2781
2782 * sim-main.h: New file.
2783 * interp.c (sim-main.h): Include.
2784
2785Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2786
2787 * configure: Regenerated to track ../common/aclocal.m4 changes.
2788
2789Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2790
2791 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2792
2793Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2794
2795 * gencode.c (build_instruction): DIV instructions: check
2796 for division by zero and integer overflow before using
2797 host's division operation.
2798
2799Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2800
2801 * Makefile.in (SIM_OBJS): Add sim-load.o.
2802 * interp.c: #include bfd.h.
2803 (target_byte_order): Delete.
2804 (sim_kind, myname, big_endian_p): New static locals.
2805 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2806 after argument parsing. Recognize -E arg, set endianness accordingly.
2807 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2808 load file into simulator. Set PC from bfd.
2809 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2810 (set_endianness): Use big_endian_p instead of target_byte_order.
2811
2812Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2813
2814 * interp.c (sim_size): Delete prototype - conflicts with
2815 definition in remote-sim.h. Correct definition.
2816
2817Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2818
2819 * configure: Regenerated to track ../common/aclocal.m4 changes.
2820 * config.in: Ditto.
2821
2822Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2823
2824 * interp.c (sim_open): New arg `kind'.
2825
2826 * configure: Regenerated to track ../common/aclocal.m4 changes.
2827
2828Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2829
2830 * configure: Regenerated to track ../common/aclocal.m4 changes.
2831
2832Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2833
2834 * interp.c (sim_open): Set optind to 0 before calling getopt.
2835
2836Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2837
2838 * configure: Regenerated to track ../common/aclocal.m4 changes.
2839
2840Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2841
2842 * interp.c : Replace uses of pr_addr with pr_uword64
2843 where the bit length is always 64 independent of SIM_ADDR.
2844 (pr_uword64) : added.
2845
2846Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2847
2848 * configure: Re-generate.
2849
2850Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2851
2852 * configure: Regenerate to track ../common/aclocal.m4 changes.
2853
2854Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2855
2856 * interp.c (sim_open): New SIM_DESC result. Argument is now
2857 in argv form.
2858 (other sim_*): New SIM_DESC argument.
2859
2860Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2861
2862 * interp.c: Fix printing of addresses for non-64-bit targets.
2863 (pr_addr): Add function to print address based on size.
2864
2865Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2866
2867 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2868
2869Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2870
2871 * gencode.c (build_mips16_operands): Correct computation of base
2872 address for extended PC relative instruction.
2873
2874Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2875
2876 * interp.c (mips16_entry): Add support for floating point cases.
2877 (SignalException): Pass floating point cases to mips16_entry.
2878 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2879 registers.
2880 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2881 or fmt_word.
2882 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2883 and then set the state to fmt_uninterpreted.
2884 (COP_SW): Temporarily set the state to fmt_word while calling
2885 ValueFPR.
2886
2887Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2888
2889 * gencode.c (build_instruction): The high order may be set in the
2890 comparison flags at any ISA level, not just ISA 4.
2891
2892Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2893
2894 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2895 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2896 * configure.in: sinclude ../common/aclocal.m4.
2897 * configure: Regenerated.
2898
2899Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2900
2901 * configure: Rebuild after change to aclocal.m4.
2902
2903Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2904
2905 * configure configure.in Makefile.in: Update to new configure
2906 scheme which is more compatible with WinGDB builds.
2907 * configure.in: Improve comment on how to run autoconf.
2908 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2909 * Makefile.in: Use autoconf substitution to install common
2910 makefile fragment.
2911
2912Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2913
2914 * gencode.c (build_instruction): Use BigEndianCPU instead of
2915 ByteSwapMem.
2916
2917Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2918
2919 * interp.c (sim_monitor): Make output to stdout visible in
2920 wingdb's I/O log window.
2921
2922Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2923
2924 * support.h: Undo previous change to SIGTRAP
2925 and SIGQUIT values.
2926
2927Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2928
2929 * interp.c (store_word, load_word): New static functions.
2930 (mips16_entry): New static function.
2931 (SignalException): Look for mips16 entry and exit instructions.
2932 (simulate): Use the correct index when setting fpr_state after
2933 doing a pending move.
2934
2935Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2936
2937 * interp.c: Fix byte-swapping code throughout to work on
2938 both little- and big-endian hosts.
2939
2940Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2941
2942 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2943 with gdb/config/i386/xm-windows.h.
2944
2945Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2946
2947 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2948 that messes up arithmetic shifts.
2949
2950Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2951
2952 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2953 SIGTRAP and SIGQUIT for _WIN32.
2954
2955Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2956
2957 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2958 force a 64 bit multiplication.
2959 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2960 destination register is 0, since that is the default mips16 nop
2961 instruction.
2962
2963Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2964
2965 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2966 (build_endian_shift): Don't check proc64.
2967 (build_instruction): Always set memval to uword64. Cast op2 to
2968 uword64 when shifting it left in memory instructions. Always use
2969 the same code for stores--don't special case proc64.
2970
2971 * gencode.c (build_mips16_operands): Fix base PC value for PC
2972 relative operands.
2973 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2974 jal instruction.
2975 * interp.c (simJALDELAYSLOT): Define.
2976 (JALDELAYSLOT): Define.
2977 (INDELAYSLOT, INJALDELAYSLOT): Define.
2978 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2979
2980Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2981
2982 * interp.c (sim_open): add flush_cache as a PMON routine
2983 (sim_monitor): handle flush_cache by ignoring it
2984
2985Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2986
2987 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2988 BigEndianMem.
2989 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2990 (BigEndianMem): Rename to ByteSwapMem and change sense.
2991 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2992 BigEndianMem references to !ByteSwapMem.
2993 (set_endianness): New function, with prototype.
2994 (sim_open): Call set_endianness.
2995 (sim_info): Use simBE instead of BigEndianMem.
2996 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2997 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2998 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2999 ifdefs, keeping the prototype declaration.
3000 (swap_word): Rewrite correctly.
3001 (ColdReset): Delete references to CONFIG. Delete endianness related
3002 code; moved to set_endianness.
3003
3004Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3005
3006 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3007 * interp.c (CHECKHILO): Define away.
3008 (simSIGINT): New macro.
3009 (membank_size): Increase from 1MB to 2MB.
3010 (control_c): New function.
3011 (sim_resume): Rename parameter signal to signal_number. Add local
3012 variable prev. Call signal before and after simulate.
3013 (sim_stop_reason): Add simSIGINT support.
3014 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3015 functions always.
3016 (sim_warning): Delete call to SignalException. Do call printf_filtered
3017 if logfh is NULL.
3018 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3019 a call to sim_warning.
3020
3021Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3022
3023 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3024 16 bit instructions.
3025
3026Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3027
3028 Add support for mips16 (16 bit MIPS implementation):
3029 * gencode.c (inst_type): Add mips16 instruction encoding types.
3030 (GETDATASIZEINSN): Define.
3031 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3032 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3033 mtlo.
3034 (MIPS16_DECODE): New table, for mips16 instructions.
3035 (bitmap_val): New static function.
3036 (struct mips16_op): Define.
3037 (mips16_op_table): New table, for mips16 operands.
3038 (build_mips16_operands): New static function.
3039 (process_instructions): If PC is odd, decode a mips16
3040 instruction. Break out instruction handling into new
3041 build_instruction function.
3042 (build_instruction): New static function, broken out of
3043 process_instructions. Check modifiers rather than flags for SHIFT
3044 bit count and m[ft]{hi,lo} direction.
3045 (usage): Pass program name to fprintf.
3046 (main): Remove unused variable this_option_optind. Change
3047 ``*loptarg++'' to ``loptarg++''.
3048 (my_strtoul): Parenthesize && within ||.
3049 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3050 (simulate): If PC is odd, fetch a 16 bit instruction, and
3051 increment PC by 2 rather than 4.
3052 * configure.in: Add case for mips16*-*-*.
3053 * configure: Rebuild.
3054
3055Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3056
3057 * interp.c: Allow -t to enable tracing in standalone simulator.
3058 Fix garbage output in trace file and error messages.
3059
3060Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3061
3062 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3063 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3064 * configure.in: Simplify using macros in ../common/aclocal.m4.
3065 * configure: Regenerated.
3066 * tconfig.in: New file.
3067
3068Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3069
3070 * interp.c: Fix bugs in 64-bit port.
3071 Use ansi function declarations for msvc compiler.
3072 Initialize and test file pointer in trace code.
3073 Prevent duplicate definition of LAST_EMED_REGNUM.
3074
3075Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3076
3077 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3078
3079Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3080
3081 * interp.c (SignalException): Check for explicit terminating
3082 breakpoint value.
3083 * gencode.c: Pass instruction value through SignalException()
3084 calls for Trap, Breakpoint and Syscall.
3085
3086Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3087
3088 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3089 only used on those hosts that provide it.
3090 * configure.in: Add sqrt() to list of functions to be checked for.
3091 * config.in: Re-generated.
3092 * configure: Re-generated.
3093
3094Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3095
3096 * gencode.c (process_instructions): Call build_endian_shift when
3097 expanding STORE RIGHT, to fix swr.
3098 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3099 clear the high bits.
3100 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3101 Fix float to int conversions to produce signed values.
3102
3103Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3104
3105 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3106 (process_instructions): Correct handling of nor instruction.
3107 Correct shift count for 32 bit shift instructions. Correct sign
3108 extension for arithmetic shifts to not shift the number of bits in
3109 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3110 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3111 Fix madd.
3112 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3113 It's OK to have a mult follow a mult. What's not OK is to have a
3114 mult follow an mfhi.
3115 (Convert): Comment out incorrect rounding code.
3116
3117Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3118
3119 * interp.c (sim_monitor): Improved monitor printf
3120 simulation. Tidied up simulator warnings, and added "--log" option
3121 for directing warning message output.
3122 * gencode.c: Use sim_warning() rather than WARNING macro.
3123
3124Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3125
3126 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3127 getopt1.o, rather than on gencode.c. Link objects together.
3128 Don't link against -liberty.
3129 (gencode.o, getopt.o, getopt1.o): New targets.
3130 * gencode.c: Include <ctype.h> and "ansidecl.h".
3131 (AND): Undefine after including "ansidecl.h".
3132 (ULONG_MAX): Define if not defined.
3133 (OP_*): Don't define macros; now defined in opcode/mips.h.
3134 (main): Call my_strtoul rather than strtoul.
3135 (my_strtoul): New static function.
3136
3137Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3138
3139 * gencode.c (process_instructions): Generate word64 and uword64
3140 instead of `long long' and `unsigned long long' data types.
3141 * interp.c: #include sysdep.h to get signals, and define default
3142 for SIGBUS.
3143 * (Convert): Work around for Visual-C++ compiler bug with type
3144 conversion.
3145 * support.h: Make things compile under Visual-C++ by using
3146 __int64 instead of `long long'. Change many refs to long long
3147 into word64/uword64 typedefs.
3148
3149Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3150
3151 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3152 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3153 (docdir): Removed.
3154 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3155 (AC_PROG_INSTALL): Added.
3156 (AC_PROG_CC): Moved to before configure.host call.
3157 * configure: Rebuilt.
3158
3159Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3160
3161 * configure.in: Define @SIMCONF@ depending on mips target.
3162 * configure: Rebuild.
3163 * Makefile.in (run): Add @SIMCONF@ to control simulator
3164 construction.
3165 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3166 * interp.c: Remove some debugging, provide more detailed error
3167 messages, update memory accesses to use LOADDRMASK.
3168
3169Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3170
3171 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3172 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3173 stamp-h.
3174 * configure: Rebuild.
3175 * config.in: New file, generated by autoheader.
3176 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3177 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3178 HAVE_ANINT and HAVE_AINT, as appropriate.
3179 * Makefile.in (run): Use @LIBS@ rather than -lm.
3180 (interp.o): Depend upon config.h.
3181 (Makefile): Just rebuild Makefile.
3182 (clean): Remove stamp-h.
3183 (mostlyclean): Make the same as clean, not as distclean.
3184 (config.h, stamp-h): New targets.
3185
3186Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3187
3188 * interp.c (ColdReset): Fix boolean test. Make all simulator
3189 globals static.
3190
3191Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3192
3193 * interp.c (xfer_direct_word, xfer_direct_long,
3194 swap_direct_word, swap_direct_long, xfer_big_word,
3195 xfer_big_long, xfer_little_word, xfer_little_long,
3196 swap_word,swap_long): Added.
3197 * interp.c (ColdReset): Provide function indirection to
3198 host<->simulated_target transfer routines.
3199 * interp.c (sim_store_register, sim_fetch_register): Updated to
3200 make use of indirected transfer routines.
3201
3202Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3203
3204 * gencode.c (process_instructions): Ensure FP ABS instruction
3205 recognised.
3206 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3207 system call support.
3208
3209Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3210
3211 * interp.c (sim_do_command): Complain if callback structure not
3212 initialised.
3213
3214Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3215
3216 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3217 support for Sun hosts.
3218 * Makefile.in (gencode): Ensure the host compiler and libraries
3219 used for cross-hosted build.
3220
3221Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3222
3223 * interp.c, gencode.c: Some more (TODO) tidying.
3224
3225Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3226
3227 * gencode.c, interp.c: Replaced explicit long long references with
3228 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3229 * support.h (SET64LO, SET64HI): Macros added.
3230
3231Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3232
3233 * configure: Regenerate with autoconf 2.7.
3234
3235Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3236
3237 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3238 * support.h: Remove superfluous "1" from #if.
3239 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3240
3241Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3242
3243 * interp.c (StoreFPR): Control UndefinedResult() call on
3244 WARN_RESULT manifest.
3245
3246Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3247
3248 * gencode.c: Tidied instruction decoding, and added FP instruction
3249 support.
3250
3251 * interp.c: Added dineroIII, and BSD profiling support. Also
3252 run-time FP handling.
3253
3254Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3255
3256 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3257 gencode.c, interp.c, support.h: created.
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