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gdb: add target_ops::supports_displaced_step
[deliverable/binutils-gdb.git] / sim / mn10300 / mn10300.igen
CommitLineData
c906108c
SS		 1// -*- C -*-
2:option:::insn-bit-size:8
3:option:::insn-specifying-widths:true
4:option:::hi-bit-nr:7
5:model:::mn10300:mn10300:
c2d11a7d 6:model:::am33:am33:
c76b4bab 7:model:::am33_2:am33_2:
c906108c
SS		 8
9// What do we do with an illegal instruction?
10:internal::::illegal:
11{
12 PC = cia;
13 program_interrupt(SD, CPU, cia, SIM_SIGILL);
14}
15
16// 1000 DnDn imm8....; mov imm8,Dn (imm8 is sign extended)
174.0x8,2.DM1,2.DN0=DM1+8.IMM8:S0i:::mov
18"mov"
19*mn10300
c2d11a7d 20*am33
c76b4bab 21*am33_2
c906108c
SS		 22{
23 /* OP_8000 (); */
24 signed32 immed = EXTEND8 (IMM8);
25 State.regs[REG_D0+DN0] = immed;
26 PC = cia;
27}
28
29// 1000 DmDn; mov Dm,Dn (Dm != Dn, see above when Dm == Dn)
304.0x8,2.DM1,2.DN0!DM1:S0:::mov
31"mov"
32*mn10300
c2d11a7d 33*am33
c76b4bab 34*am33_2
c906108c
SS		 35{
36 PC = cia;
37 /* OP_80 (); */
38 State.regs[REG_D0+DN0] = State.regs[REG_D0+DM1];
39}
40
41
42// 1111 0001 1110 DmAn; mov Dm,An
438.0xf1+1110,2.DM1,2.AN0:D0:::mov
44"mov"
45*mn10300
c2d11a7d 46*am33
c76b4bab 47*am33_2
c906108c
SS		 48{
49 /* OP_F1E0 (); */
50 PC = cia;
51 State.regs[REG_A0 + AN0] = State.regs[REG_D0 + DM1];
52}
53
54
55// 1111 0001 1101 AmDn; mov Am,Dn
568.0xf1+1101,2.AM1,2.DN0:D0a:::mov
57"mov"
58*mn10300
c2d11a7d 59*am33
c76b4bab 60*am33_2
c906108c
SS		 61{
62 /* OP_F1D0 (); */
63 PC = cia;
64 State.regs[REG_D0 + DN0] = State.regs[REG_A0 + AM1];
65}
66
67
68// 1001 AnAn imm8....; mov imm8,An (imm8 is zero-extended)
694.0x9,2.AM1,2.AN0=AM1+8.IMM8:S0ai:::mov
70"mov"
71*mn10300
c2d11a7d 72*am33
c76b4bab 73*am33_2
c906108c
SS		 74{
75 PC = cia;
76 /* OP_9000 (); */
77 State.regs[REG_A0+AN0] = IMM8;
78}
79
80
81// 1001 AmAn; mov Am,An (Am != An, save above when Am == An)
824.0x9,2.AM1,2.AN0!AM1:S0a:::mov
83"mov"
84*mn10300
c2d11a7d 85*am33
c76b4bab 86*am33_2
c906108c
SS		 87{
88 PC = cia;
89 /* OP_90 (); */
90 State.regs[REG_A0+AN0] = State.regs[REG_A0+AM1];
91}
92
93
94// 0011 11An; mov SP,An
954.0x3,11,2.AN0:S0b:::mov
96"mov"
97*mn10300
c2d11a7d 98*am33
c76b4bab 99*am33_2
c906108c
SS		 100{
101 /* OP_3C (); */
102 PC = cia;
103 State.regs[REG_A0 + AN0] = State.regs[REG_SP];
104}
105
106
107// 1111 0010 1111 Am00; mov Am,SP
1088.0xf2+4.0xf,2.AM1,00:D0b:::mov
109"mov"
110*mn10300
c2d11a7d 111*am33
c76b4bab 112*am33_2
c906108c
SS		 113{
114 /* OP_F2F0 (); */
115 PC = cia;
116 State.regs[REG_SP] = State.regs[REG_A0 + AM1];
117}
118
119
120// 1111 0010 1110 01Dn; mov PSW,Dn
1218.0xf2+4.0xe,01,2.DN0:D0c:::mov
122"mov"
123*mn10300
c2d11a7d 124*am33
c76b4bab 125*am33_2
c906108c
SS		 126{
127 /* OP_F2E4 (); */
128 PC = cia;
129 State.regs[REG_D0 + DN0] = PSW;
130}
131
132
133// 1111 0010 1111 Dm11; mov Dm,PSW
1348.0xf2+4.0xf,2.DM1,11:D0d:::mov
135"mov"
136*mn10300
c2d11a7d 137*am33
c76b4bab 138*am33_2
c906108c
SS		 139{
140 /* OP_F2F3 (); */
141 PC = cia;
142 PSW = State.regs[REG_D0 + DM1];
143}
144
145
146// 1111 0010 1110 00Dn; mov MDR,Dn
1478.0xf2+4.0xe,00,2.DN0:D0e:::mov
148"mov"
149*mn10300
c2d11a7d 150*am33
c76b4bab 151*am33_2
c906108c
SS		 152{
153 /* OP_F2E0 (); */
154 PC = cia;
155 State.regs[REG_D0 + DN0] = State.regs[REG_MDR];
156}
157
158
159// 1111 0010 1111 Dm10; mov Dm,MDR
1608.0xf2+4.0xf,2.DM1,10:D0f:::mov
161"mov"
162*mn10300
c2d11a7d 163*am33
c76b4bab 164*am33_2
c906108c
SS		 165{
166 /* OP_F2F2 (); */
167 PC = cia;
168 State.regs[REG_MDR] = State.regs[REG_D0 + DM1];
169}
170
171
172// 0111 DnAm; mov (Am),Dn
1734.0x7,2.DN1,2.AM0:S0c:::mov
174"mov"
175*mn10300
c2d11a7d 176*am33
c76b4bab 177*am33_2
c906108c
SS		 178{
179 /* OP_70 (); */
180 PC = cia;
181 State.regs[REG_D0 + DN1] = load_word (State.regs[REG_A0 + AM0]);
182}
183
184
185// 1111 1000 0000 DnAm d8......; mov (d8,Am),Dn (d8 is sign-extended)
1868.0xf8+4.0x0,2.DN1,2.AM0+8.D8:D1:::mov
187"mov"
188*mn10300
c2d11a7d 189*am33
c76b4bab 190*am33_2
c906108c
SS		 191{
192 /* OP_F80000 (); */
193 PC = cia;
194 State.regs[REG_D0 + DN1]
195 = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
196}
197
198
199// 1111 1010 0000 DnAm d16.....; mov (d16,Am),Dn (d16 is sign-extended.)
2008.0xfa+4.0x0,2.DN1,2.AM0+8.D16A+8.D16B:D2:::mov
201"mov"
202*mn10300
c2d11a7d 203*am33
c76b4bab 204*am33_2
c906108c
SS		 205{
206 /* OP_FA000000 (); */
207 PC = cia;
208 State.regs[REG_D0 + DN1]
209 = load_word ((State.regs[REG_A0 + AM0] + EXTEND16 (FETCH16(D16A, D16B))));
210}
211
212
213// 1111 1100 0000 DnAm d32.....; mov (d32,Am),Dn
2148.0xfc+4.0x0,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mov
215"mov"
216*mn10300
c2d11a7d 217*am33
c76b4bab 218*am33_2
c906108c
SS		 219{
220 /* OP_FC000000 (); */
221 PC = cia;
222 State.regs[REG_D0 + DN1]
223 = load_word ((State.regs[REG_A0 + AM0]
224 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
225}
226
227
228// 0101 10Dn d8......; mov (d8,SP),Dn (d8 is zero-extended)
2294.0x5,10,2.DN0+8.D8:S1:::mov
230"mov"
231*mn10300
c2d11a7d 232*am33
c76b4bab 233*am33_2
c906108c
SS		 234{
235 /* OP_5800 (); */
236 PC = cia;
237 State.regs[REG_D0 + DN0] = load_word (State.regs[REG_SP] + D8);
238}
239
240
241// 1111 1010 1011 01Dn d16.....; mov (d16,SP),Dn (d16 is zero-extended.)
2428.0xfa+4.0xb,01,2.DN0+8.IMM16A+8.IMM16B:D2a:::mov
243"mov"
244*mn10300
c2d11a7d 245*am33
c76b4bab 246*am33_2
c906108c
SS		 247{
248 /* OP_FAB40000 (); */
249 PC = cia;
250 State.regs[REG_D0 + DN0]
251 = load_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B));
252}
253
254
255// 1111 1010 1011 01Dn d32.....; mov (d32,SP),Dn
2568.0xfc+4.0xb,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::mov
257"mov"
258*mn10300
c2d11a7d 259*am33
c76b4bab 260*am33_2
c906108c
SS		 261{
262 /* OP_FCB40000 (); */
263 PC = cia;
264 State.regs[REG_D0 + DN0]
265 = load_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
266}
267
268
269// 1111 0011 00Dn DiAm; mov (Di,Am),Dn
2708.0xf3+00,2.DN2,2.DI,2.AM0:D0g:::mov
271"mov"
272*mn10300
c2d11a7d 273*am33
c76b4bab 274*am33_2
c906108c
SS		 275{
276 /* OP_F300 (); */
277 PC = cia;
278 State.regs[REG_D0 + DN2]
279 = load_word ((State.regs[REG_A0 + AM0] + State.regs[REG_D0 + DI]));
280}
281
282
283// 0011 00Dn abs16...; mov (abs16),Dn (abs16 is zero-extended)
2844.0x3,00,2.DN0+8.IMM16A+8.IMM16B:S2:::mov
285"mov"
286*mn10300
c2d11a7d 287*am33
c76b4bab 288*am33_2
c906108c
SS		 289{
290 /* OP_300000 (); */
291 PC = cia;
292 State.regs[REG_D0 + DN0] = load_word (FETCH16(IMM16A, IMM16B));
293}
294
295// 1111 1100 1010 01Dn abs32...; mov (abs32),Dn
2968.0xfc+4.0xa,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::mov
297"mov"
298*mn10300
c2d11a7d 299*am33
c76b4bab 300*am33_2
c906108c
SS		 301{
302 /* OP_FCA40000 (); */
303 PC = cia;
304 State.regs[REG_D0 + DN0] = load_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
305}
306
307
308// 1111 0000 0000 AnAm; mov (Am),An
3098.0xf0+4.0x0,2.AN1,2.AM0:D0h:::mov
310"mov"
311*mn10300
c2d11a7d 312*am33
c76b4bab 313*am33_2
c906108c
SS		 314{
315 /* OP_F000 (); */
316 PC = cia;
317 State.regs[REG_A0 + AN1] = load_word (State.regs[REG_A0 + AM0]);
318}
319
320
321// 1111 1000 0010 AnAm d8......; mov (d8,Am),An (d8 is sign-extended)
3228.0xf8+4.0x2,2.AN1,2.AM0+8.D8:D1a:::mov
323"mov"
324*mn10300
c2d11a7d 325*am33
c76b4bab 326*am33_2
c906108c
SS		 327{
328 /* OP_F82000 (); */
329 PC = cia;
330 State.regs[REG_A0 + AN1]
331 = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
332}
333
334
335// 1111 1010 0010 AnAm d16.....; mov (d16,Am),An (d16 is sign-extended.)
3368.0xfa+4.0x2,2.AN1,2.AM0+8.D16A+8.D16B:D2b:::mov
337"mov"
338*mn10300
c2d11a7d 339*am33
c76b4bab 340*am33_2
c906108c
SS		 341{
342 /* OP_FA200000 (); */
343 PC = cia;
344 State.regs[REG_A0 + AN1]
345 = load_word ((State.regs[REG_A0 + AM0]
346 + EXTEND16 (FETCH16(D16A, D16B))));
347}
348
349
350// 1111 1100 0010 AnAm d32.....; mov (d32,Am),An
3518.0xfc+4.0x2,2.AN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::mov
352"mov"
353*mn10300
c2d11a7d 354*am33
c76b4bab 355*am33_2
c906108c
SS		 356{
357 /* OP_FC200000 (); */
358 PC = cia;
359 State.regs[REG_A0 + AN1]
360 = load_word ((State.regs[REG_A0 + AM0]
361 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
362}
363
364
365// 0101 11An d8......; mov (d8,SP),An (d8 is zero-extended)
3664.0x5,11,2.AN0+8.D8:S1a:::mov
367"mov"
368*mn10300
c2d11a7d 369*am33
c76b4bab 370*am33_2
c906108c
SS		 371{
372 /* OP_5C00 (); */
373 PC = cia;
374 State.regs[REG_A0 + AN0]
375 = load_word (State.regs[REG_SP] + D8);
376}
377
378
379// 1111 1010 1011 00An d16.....; mov (d16,SP),An (d16 is zero-extended.)
3808.0xfa+4.0xb,00,2.AN0+8.IMM16A+8.IMM16B:D2c:::mov
381"mov"
382*mn10300
c2d11a7d 383*am33
c76b4bab 384*am33_2
c906108c
SS		 385{
386 /* OP_FAB00000 (); */
387 PC = cia;
388 State.regs[REG_A0 + AN0]
389 = load_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B));
390}
391
392
393// 1111 1100 1011 00An d32.....; mov (d32,SP),An
3948.0xfc+4.0xb,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::mov
395"mov"
396*mn10300
c2d11a7d 397*am33
c76b4bab 398*am33_2
c906108c
SS		 399{
400 /* OP_FCB00000 (); */
401 PC = cia;
402 State.regs[REG_A0 + AN0]
403 = load_word (State.regs[REG_SP]
404 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
405}
406
407
408// 1111 0011 10An DiAm; mov (Di,Am),An
4098.0xf3+10,2.AN2,2.DI,2.AM0:D0i:::mov
410"mov"
411*mn10300
c2d11a7d 412*am33
c76b4bab 413*am33_2
c906108c
SS		 414{
415 /* OP_F380 (); */
416 PC = cia;
417 State.regs[REG_A0 + AN2]
418 = load_word ((State.regs[REG_A0 + AM0]
419 + State.regs[REG_D0 + DI]));
420}
421
422
423// 1111 1010 1010 00An abs16...; mov (abs16),An (abs16 is zero-extended)
4248.0xfa+4.0xa,00,2.AN0+8.IMM16A+8.IMM16B:D2d:::mov
425"mov"
426*mn10300
c2d11a7d 427*am33
c76b4bab 428*am33_2
c906108c
SS		 429{
430 /* OP_FAA00000 (); */
431 PC = cia;
432 State.regs[REG_A0 + AN0] = load_word (FETCH16(IMM16A, IMM16B));
433}
434
435
436// 1111 1100 1010 00An abs32...; mov (abs32),An
4378.0xfc+4.0xa,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::mov
438"mov"
439*mn10300
c2d11a7d 440*am33
c76b4bab 441*am33_2
c906108c
SS		 442{
443 /* OP_FCA00000 (); */
444 PC = cia;
445 State.regs[REG_A0 + AN0]
446 = load_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
447}
448
449
450// 1111 1000 1111 00Am d8......; mov (d8,Am),SP (d8 is sign-extended)
4518.0xf8+4.0xf,00,2.AM0+8.D8:D1b:::mov
452"mov"
453*mn10300
c2d11a7d 454*am33
c76b4bab 455*am33_2
c906108c
SS		 456{
457 /* OP_F8F000 (); */
458 PC = cia;
459 State.regs[REG_SP]
460 = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
461}
462
463
464// 0110 DmAn; mov Dm,(An)
4654.0x6,2.DM1,2.AN0:S0d:::mov
466"mov"
467*mn10300
c2d11a7d 468*am33
c76b4bab 469*am33_2
c906108c
SS		 470{
471 /* OP_60 (); */
472 PC = cia;
473 store_word (State.regs[REG_A0 + AN0], State.regs[REG_D0 + DM1]);
474}
475
476
477// 1111 1000 0001 DmAn d8......; mov Dm,(d8,An) (d8 is sign-extended)
4788.0xf8+4.0x1,2.DM1,2.AN0+8.D8:D1c:::mov
479"mov"
480*mn10300
c2d11a7d 481*am33
c76b4bab 482*am33_2
c906108c
SS		 483{
484 /* OP_F81000 (); */
485 PC = cia;
486 store_word ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
487 State.regs[REG_D0 + DM1]);
488}
489
490
491// 1111 1010 0001 DmAn d16.....; mov Dm,(d16,An) (d16 is sign-extended.)
4928.0xfa+4.0x1,2.DM1,2.AN0+8.D16A+8.D16B:D2e:::mov
493"mov"
494*mn10300
c2d11a7d 495*am33
c76b4bab 496*am33_2
c906108c
SS		 497{
498 /* OP_FA100000 (); */
499 PC = cia;
500 store_word ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
501 State.regs[REG_D0 + DM1]);
502}
503
504
505// 1111 1100 0001 DmAn d32.....; mov Dm,(d32,An)
5068.0xfc+4.0x1,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4f:::mov
507"mov"
508*mn10300
c2d11a7d 509*am33
c76b4bab 510*am33_2
c906108c
SS		 511{
512 /* OP_FC100000 (); */
513 PC = cia;
514 store_word ((State.regs[REG_A0 + AN0]
515 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
516 State.regs[REG_D0 + DM1]);
517}
518
519
520// 0100 Dm10 d8......; mov Dm,(d8,SP) (d8 is zero-extended)
5214.0x4,2.DM1,10+8.D8:S1b:::mov
522"mov"
523*mn10300
c2d11a7d 524*am33
c76b4bab 525*am33_2
c906108c
SS		 526{
527 /* OP_4200 (); */
528 PC = cia;
529 store_word (State.regs[REG_SP] + D8, State.regs[REG_D0 + DM1]);
530}
531
532
533// 1111 1010 1001 Dm01 d16.....; mov Dm,(d16,SP) (d16 is zero-extended.)
5348.0xfa+4.0x9,2.DM1,01+8.IMM16A+8.IMM16B:D2f:::mov
535"mov"
536*mn10300
c2d11a7d 537*am33
c76b4bab 538*am33_2
c906108c
SS		 539{
540 /* OP_FA910000 (); */
541 PC = cia;
542 store_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
543 State.regs[REG_D0 + DM1]);
544}
545
546
547// 1111 1100 1001 Dm01 d32.....; mov Dm,(d32,SP)
5488.0xfc+4.0x9,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4g:::mov
549"mov"
550*mn10300
c2d11a7d 551*am33
c76b4bab 552*am33_2
c906108c
SS		 553{
554 /* OP_FC910000 (); */
555 PC = cia;
556 store_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
557 State.regs[REG_D0 + DM1]);
558}
559
560
561// 1111 0011 01Dm DiAn; mov Dm,(Di,An)
5628.0xf3+01,2.DM2,2.DI,2.AN0:D0j:::mov
563"mov"
564*mn10300
c2d11a7d 565*am33
c76b4bab 566*am33_2
c906108c
SS		 567{
568 /* OP_F340 (); */
569 PC = cia;
570 store_word ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
571 State.regs[REG_D0 + DM2]);
572}
573
574
575// 0000 Dm01 abs16..., mov Dm,(abs16) (abs16 is zero-extended).
5764.0x0,2.DM1,01+8.IMM16A+8.IMM16B:S2a:::mov
577"mov"
578*mn10300
c2d11a7d 579*am33
c76b4bab 580*am33_2
c906108c
SS		 581{
582 /* OP_10000 (); */
583 PC = cia;
584 store_word (FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DM1]);
585}
586
587
588// 1111 1100 1000 Dm01 abs32...; mov Dm,(abs32)
5898.0xfc+4.0x8,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4h:::mov
590"mov"
591*mn10300
c2d11a7d 592*am33
c76b4bab 593*am33_2
c906108c
SS		 594{
595 /* OP_FC810000 (); */
596 PC = cia;
597 store_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
598 State.regs[REG_D0 + DM1]);
599}
600
601
602// 1111 0000 0001 AmAn; mov Am,(An)
6038.0xf0+4.0x1,2.AM1,2.AN0:D0k:::mov
604"mov"
605*mn10300
c2d11a7d 606*am33
c76b4bab 607*am33_2
c906108c
SS		 608{
609 /* OP_F010 (); */
610 PC = cia;
611 store_word (State.regs[REG_A0 + AN0], State.regs[REG_A0 + AM1]);
612}
613
614
615// 1111 1000 0011 AmAn d8......; mov Am,(d8,An) (d8 is sign-extended)
6168.0xf8+4.0x3,2.AM1,2.AN0+8.D8:D1d:::mov
617"mov"
618*mn10300
c2d11a7d 619*am33
c76b4bab 620*am33_2
c906108c
SS		 621{
622 /* OP_F83000 (); */
623 PC = cia;
624 store_word ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
625 State.regs[REG_A0 + AM1]);
626}
627
628
629// 1111 1010 0011 AmAn d16.....; mov Am,(d16,An) (d16 is sign-extended.)
6308.0xfa+4.0x3,2.AM1,2.AN0+8.D16A+8.D16B:D2g:::mov
631"mov"
632*mn10300
c2d11a7d 633*am33
c76b4bab 634*am33_2
c906108c
SS		 635{
636 /* OP_FA300000 (); */
637 PC = cia;
638 store_word ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
639 State.regs[REG_A0 + AM1]);
640}
641
642
643// 1111 1100 0011 AmAn d32.....; mov Am,(d32,An)
6448.0xfc+4.0x3,2.AM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4i:::mov
645"mov"
646*mn10300
c2d11a7d 647*am33
c76b4bab 648*am33_2
c906108c
SS		 649{
650 /* OP_FC300000 (); */
651 PC = cia;
652 store_word ((State.regs[REG_A0 + AN0]
653 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
654 State.regs[REG_A0 + AM1]);
655}
656
657
658// 0100 Am11 d8......; mov Am,(d8,SP) (d8 is zero-extended)
6594.0x4,2.AM1,11+8.D8:S1c:::mov
660"mov"
661*mn10300
c2d11a7d
JM		 662
663*am33
c76b4bab 664*am33_2
c2d11a7d 665
c906108c
SS		 666{
667 /* OP_4300 (); */
668 PC = cia;
669 store_word (State.regs[REG_SP] + (D8), State.regs[REG_A0 + (AM1)]);
670}
671
672
673// 1111 1010 1001 Am00 d16.....; mov Am,(d16,SP) (d16 is zero-extended.)
6748.0xfa+4.0x9,2.AM1,00+8.IMM16A+8.IMM16B:D2h:::mov
675"mov"
676*mn10300
c2d11a7d
JM		 677
678*am33
c76b4bab 679*am33_2
c2d11a7d 680
c906108c
SS		 681{
682 /* OP_FA900000 (); */
683 PC = cia;
684 store_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
685 State.regs[REG_A0 + AM1]);
686}
687
688
689// 1111 1100 1001 Am00 d32.....; mov Am,(d32,SP)
6908.0xfc+4.0x9,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4j:::mov
691"mov"
692*mn10300
c2d11a7d
JM		 693
694*am33
c76b4bab 695*am33_2
c2d11a7d 696
c906108c
SS		 697{
698 /* OP_FC900000 (); */
699 PC = cia;
700 store_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
701 State.regs[REG_A0 + AM1]);
702}
703
704
705// 1111 0011 11Am DiAn; mov Am,(Di,An)
7068.0xf3+11,2.AM2,2.DI,2.AN0:D0l:::mov
707"mov"
708*mn10300
c2d11a7d
JM		 709
710*am33
c76b4bab 711*am33_2
c2d11a7d 712
c906108c
SS		 713{
714 /* OP_F3C0 (); */
715 PC = cia;
716 store_word ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
717 State.regs[REG_A0 + AM2]);
718}
719
720
721// 1111 1010 1000 Am00 abs16...; mov Am,(abs16) (abs16 is zero-extended)
7228.0xfa+4.0x8,2.AM1,00+8.IMM16A+8.IMM16B:D2i:::mov
723"mov"
724*mn10300
c2d11a7d
JM		 725
726*am33
c76b4bab 727*am33_2
c2d11a7d 728
c906108c
SS		 729{
730 /* OP_FA800000 (); */
731 PC = cia;
732 store_word (FETCH16(IMM16A, IMM16B),
733 State.regs[REG_A0 + AM1]);
734}
735
736
737// 1111 1100 1000 Am00 abs32...; mov Am,(abs32)
7388.0xfc+4.0x8,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4k:::mov
739"mov"
740*mn10300
c2d11a7d
JM		 741
742*am33
c76b4bab 743*am33_2
c2d11a7d 744
c906108c
SS		 745{
746 /* OP_FC800000 (); */
747 PC = cia;
748 store_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
749 State.regs[REG_A0 + AM1]);
750}
751
752
753// 1111 1000 1111 01An d8......; mov SP,(d8,An) (d8 is sign-extended)
7548.0xf8+4.0xf,01,2.AN0+8.D8:D1e:::mov
755"mov"
756*mn10300
c2d11a7d
JM		 757
758*am33
c76b4bab 759*am33_2
c2d11a7d 760
c906108c
SS		 761{
762 /* OP_F8F400 (); */
763 PC = cia;
764 store_word (State.regs[REG_A0 + AN0] + EXTEND8 (D8),
765 State.regs[REG_SP]);
766}
767
768
769// 0010 11Dn imm16...; mov imm16,Dn (imm16 is sign-extended)
7704.0x2,11,2.DN0+8.IMM16A+8.IMM16B:S2b:::mov
771"mov"
772*mn10300
c2d11a7d
JM		 773
774*am33
c76b4bab 775*am33_2
c2d11a7d 776
c906108c
SS		 777{
778 /* OP_2C0000 (); */
24a39d88 779 unsigned32 value;
c906108c
SS		 780
781 PC = cia;
782 value = EXTEND16 (FETCH16(IMM16A, IMM16B));
783 State.regs[REG_D0 + DN0] = value;
784}
785
786
787// 1111 1100 1100 11Dn imm32...; mov imm32,Dn
7888.0xfc+4.0xc,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4l:::mov
789"mov"
790*mn10300
c2d11a7d
JM		 791
792*am33
c76b4bab 793*am33_2
c2d11a7d 794
c906108c
SS		 795{
796 /* OP_FCCC0000 (); */
24a39d88 797 unsigned32 value;
c906108c
SS		 798
799 PC = cia;
800 value = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
801 State.regs[REG_D0 + DN0] = value;
802}
803
804
805// 0010 01An imm16...; mov imm16,An (imm16 is zero-extended)
8064.0x2,01,2.AN0+8.IMM16A+8.IMM16B:S2c:::mov
807"mov"
808*mn10300
c2d11a7d
JM		 809
810*am33
c76b4bab 811*am33_2
c2d11a7d 812
c906108c
SS		 813{
814 /* OP_240000 (); */
24a39d88 815 unsigned32 value;
c906108c
SS		 816
817 PC = cia;
818 value = FETCH16(IMM16A, IMM16B);
819 State.regs[REG_A0 + AN0] = value;
820}
821
822
823// 1111 1100 1101 11An imm32...; mov imm32,An
8248.0xfc+4.0xd,11,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4m:::mov
825"mov"
826*mn10300
c2d11a7d
JM		 827
828*am33
c76b4bab 829*am33_2
c2d11a7d 830
c906108c
SS		 831{
832 /* OP_FCDC0000 (); */
833 PC = cia;
834 State.regs[REG_A0 + AN0] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
835}
836
837
838// 1111 0000 0100 DnAm; movbu (Am),Dn
8398.0xf0+4.0x4,2.DN1,2.AM0:D0:::movbu
840"movbu"
841*mn10300
c2d11a7d
JM		 842
843*am33
c76b4bab 844*am33_2
c2d11a7d 845
c906108c
SS		 846{
847 /* OP_F040 (); */
848 PC = cia;
849 State.regs[REG_D0 + DN1]
850 = load_byte (State.regs[REG_A0 + AM0]);
851}
852
853
854// 1111 1000 0100 DnAm d8......; movbu (d8,Am),Dn (d8 is sign-extended)
8558.0xf8+4.0x4,2.DN1,2.AM0+8.D8:D1f:::movbu
856"movbu"
857*mn10300
c2d11a7d
JM		 858
859*am33
c76b4bab 860*am33_2
c2d11a7d 861
c906108c
SS		 862{
863 /* OP_F84000 (); */
864 PC = cia;
865 State.regs[REG_D0 + DN1]
866 = load_byte ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
867}
868
869
870// 1111 1010 0100 DnAm d16.....; movbu (d16,Am),Dn (d16 is sign-extended.)
8718.0xfa+4.0x4,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movbu
872"movbu"
873*mn10300
c2d11a7d
JM		 874
875*am33
c76b4bab 876*am33_2
c2d11a7d 877
c906108c
SS		 878{
879 /* OP_FA400000 (); */
880 PC = cia;
881 State.regs[REG_D0 + DN1]
882 = load_byte ((State.regs[REG_A0 + AM0]
883 + EXTEND16 (FETCH16(D16A, D16B))));
884}
885
886
887// 1111 1100 0100 DnAm d32.....; movbu (d32,Am),Dn
8888.0xfc+4.0x4,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movbu
889"movbu"
890*mn10300
c2d11a7d
JM		 891
892*am33
c76b4bab 893*am33_2
c2d11a7d 894
c906108c
SS		 895{
896 /* OP_FC400000 (); */
897 PC = cia;
898 State.regs[REG_D0 + DN1]
899 = load_byte ((State.regs[REG_A0 + AM0]
900 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
901}
902
903
904// 1111 1000 1011 10Dn d8......; movbu (d8,SP),Dn (d8 is zero-extended)
9058.0xf8+4.0xb,10,2.DN0+8.D8:D1a:::movbu
906"movbu"
907*mn10300
c2d11a7d
JM		 908
909*am33
c76b4bab 910*am33_2
c2d11a7d 911
c906108c
SS		 912{
913 /* OP_F8B800 (); */
914 PC = cia;
915 State.regs[REG_D0 + DN0]
916 = load_byte ((State.regs[REG_SP] + (D8)));
917}
918
919
920// 1111 1010 1011 10Dn d16.....; movbu (d16,SP),Dn (d16 is zero-extended.)
9218.0xfa+4.0xb,10,2.DN0+8.IMM16A+8.IMM16B:D2a:::movbu
922"movbu"
923*mn10300
c2d11a7d
JM		 924
925*am33
c76b4bab 926*am33_2
c2d11a7d 927
c906108c
SS		 928{
929 /* OP_FAB80000 (); */
930 PC = cia;
931 State.regs[REG_D0 + DN0]
932 = load_byte ((State.regs[REG_SP]
933 + FETCH16(IMM16A, IMM16B)));
934}
935
936
937// 1111 1100 1011 10Dn d32.....; movbu (d32,SP),Dn
9388.0xfc+4.0xb,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movbu
939"movbu"
940*mn10300
c2d11a7d
JM		 941
942*am33
c76b4bab 943*am33_2
c2d11a7d 944
c906108c
SS		 945{
946 /* OP_FCB80000 (); */
947 PC = cia;
948 State.regs[REG_D0 + DN0]
949 = load_byte (State.regs[REG_SP]
950 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
951}
952
953
954// 1111 0100 00Dn DiAm; movbu (Di,Am),Dn
9558.0xf4+00,2.DN2,2.DI,2.AM0:D0a:::movbu
956"movbu"
957*mn10300
c2d11a7d
JM		 958
959*am33
c76b4bab 960*am33_2
c2d11a7d 961
c906108c
SS		 962{
963 /* OP_F400 (); */
964 PC = cia;
965 State.regs[REG_D0 + DN2]
966 = load_byte ((State.regs[REG_A0 + AM0]
967 + State.regs[REG_D0 + DI]));
968}
969
970
971// 0011 01Dn abs16...; movbu (abs16),Dn (abs16 is zero-extended)
9724.0x3,01,2.DN0+8.IMM16A+8.IMM16B:S2:::movbu
973"movbu"
974*mn10300
c2d11a7d
JM		 975
976*am33
c76b4bab 977*am33_2
c2d11a7d 978
c906108c
SS		 979{
980 /* OP_340000 (); */
981 PC = cia;
982 State.regs[REG_D0 + DN0] = load_byte (FETCH16(IMM16A, IMM16B));
983}
984
985
986// 1111 1100 1010 10Dn abs32...; movbu (abs32),Dn
9878.0xfc+4.0xa,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movbu
988"movbu"
989*mn10300
c2d11a7d
JM		 990
991*am33
c76b4bab 992*am33_2
c2d11a7d 993
c906108c
SS		 994{
995 /* OP_FCA80000 (); */
996 PC = cia;
997 State.regs[REG_D0 + DN0]
998 = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
999}
1000
1001
1002// 1111 0000 0101 DmAn; movbu Dm,(An)
10038.0xf0+4.0x5,2.DM1,2.AN0:D0b:::movbu
1004"movbu"
1005*mn10300
c2d11a7d
JM		 1006
1007*am33
c76b4bab 1008*am33_2
c2d11a7d 1009
c906108c
SS		 1010{
1011 /* OP_F050 (); */
1012 PC = cia;
1013 store_byte (State.regs[REG_A0 + AN0], State.regs[REG_D0 + DM1]);
1014}
1015
1016
1017// 1111 1000 0101 DmAn d8......; movbu Dm,(d8,An) (d8 is sign-extended)
10188.0xf8+4.0x5,2.DM1,2.AN0+8.D8:D1b:::movbu
1019"movbu"
1020*mn10300
c2d11a7d
JM		 1021
1022*am33
c76b4bab 1023*am33_2
c2d11a7d 1024
c906108c
SS		 1025{
1026 /* OP_F85000 (); */
1027 PC = cia;
1028 store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
1029 State.regs[REG_D0 + DM1]);
1030}
1031
1032
1033// 1111 1010 0101 DmAn d16.....; movbu Dm,(d16,An) (d16 is sign-extended.)
10348.0xfa+4.0x5,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movbu
1035"movbu"
1036*mn10300
c2d11a7d
JM		 1037
1038*am33
c76b4bab 1039*am33_2
c2d11a7d 1040
c906108c
SS		 1041{
1042 /* OP_FA500000 (); */
1043 PC = cia;
1044 store_byte ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
1045 State.regs[REG_D0 + DM1]);
1046}
1047
1048
1049// 1111 1100 0101 DmAn d32.....; movbu Dm,(d32,An)
10508.0xfc+4.0x5,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movbu
1051"movbu"
1052*mn10300
c2d11a7d
JM		 1053
1054*am33
c76b4bab 1055*am33_2
c2d11a7d 1056
c906108c
SS		 1057{
1058 /* OP_FC500000 (); */
1059 PC = cia;
1060 store_byte ((State.regs[REG_A0 + AN0]
1061 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
1062 State.regs[REG_D0 + DM1]);
1063}
1064
1065
1066// 1111 1000 1001 Dm10 d8......; movbu Dm,(d8,SP) (d8 is zero-extended)
10678.0xf8+4.0x9,2.DM1,10+8.D8:D1c:::movbu
1068"movbu"
1069*mn10300
c2d11a7d
JM		 1070
1071*am33
c76b4bab 1072*am33_2
c2d11a7d 1073
c906108c
SS		 1074{
1075 /* OP_F89200 (); */
1076 PC = cia;
1077 store_byte (State.regs[REG_SP] + (D8), State.regs[REG_D0 + DM1]);
1078}
1079
1080
1081// 1111 1010 1001 Dm10 d16.....; movbu Dm,(d16,SP) (d16 is zero-extended.)
10828.0xfa+4.0x9,2.DM1,10+8.IMM16A+8.IMM16B:D2c:::movbu
1083"movbu"
1084*mn10300
c2d11a7d
JM		 1085
1086*am33
c76b4bab 1087*am33_2
c2d11a7d 1088
c906108c
SS		 1089{
1090 /* OP_FA920000 (); */
1091 PC = cia;
1092 store_byte (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
1093 State.regs[REG_D0 + DM1]);
1094}
1095
1096
1097// 1111 1100 1001 Dm10 d32.....; movbu Dm,(d32,SP)
10988.0xfc+4.0x9,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movbu
1099"movbu"
1100*mn10300
c2d11a7d
JM		 1101
1102*am33
c76b4bab 1103*am33_2
c2d11a7d 1104
c906108c
SS		 1105{
1106 /* OP_FC920000 (); */
1107 PC = cia;
1108 store_byte (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1109 State.regs[REG_D0 + DM1]);
1110}
1111
1112
1113// 1111 0100 01Dm DiAn; movbu Dm,(Di,An)
11148.0xf4+01,2.DM2,2.DI,2.AN0:D0c:::movbu
1115"movbu"
1116*mn10300
c2d11a7d
JM		 1117
1118*am33
c76b4bab 1119*am33_2
c2d11a7d 1120
c906108c
SS		 1121{
1122 /* OP_F440 (); */
1123 PC = cia;
1124 store_byte ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
1125 State.regs[REG_D0 + DM2]);
1126}
1127
1128
1129// 0000 Dm10 abs16...; movbu Dm,(abs16) (abs16 is zero-extended)
11304.0x0,2.DM1,10+8.IMM16A+8.IMM16B:S2a:::movbu
1131"movbu"
1132*mn10300
c2d11a7d
JM		 1133
1134*am33
c76b4bab 1135*am33_2
c2d11a7d 1136
c906108c
SS		 1137{
1138 /* OP_20000 (); */
1139 PC = cia;
1140 store_byte (FETCH16(IMM16A, IMM16B),
1141 State.regs[REG_D0 + DM1]);
1142}
1143
1144
1145// 1111 1100 1000 Dm10 abs32...; movbu Dm,(abs32)
11468.0xfc+4.0x8,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movbu
1147"movbu"
1148*mn10300
c2d11a7d
JM		 1149
1150*am33
c76b4bab 1151*am33_2
c2d11a7d 1152
c906108c
SS		 1153{
1154 /* OP_FC820000 (); */
1155 PC = cia;
1156 store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1157 State.regs[REG_D0 + DM1]);
1158}
1159
1160
1161// 1111 0000 0110 DnAm; movhu (Am),Dn
11628.0xf0+4.0x6,2.DN1,2.AM0:D0:::movhu
1163"movhu"
1164*mn10300
c2d11a7d
JM		 1165
1166*am33
c76b4bab 1167*am33_2
c2d11a7d 1168
c906108c
SS		 1169{
1170 /* OP_F060 (); */
1171 PC = cia;
1172 State.regs[REG_D0 + DN1]
1173 = load_half (State.regs[REG_A0 + AM0]);
1174}
1175
1176
1177// 1111 1000 0110 DnAm d8......; movhu (d8,Am),Dn (d8 is sign-extended)
11788.0xf8+4.0x6,2.DN1,2.AM0+8.D8:D1d:::movhu
1179"movhu"
1180*mn10300
c2d11a7d
JM		 1181
1182*am33
c76b4bab 1183*am33_2
c2d11a7d 1184
c906108c
SS		 1185{
1186 /* OP_F86000 (); */
1187 PC = cia;
1188 State.regs[REG_D0 + DN1]
1189 = load_half ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
1190}
1191
1192
1193// 1111 1010 0110 DnAm d16.....; movhu (d16,Am),Dn (d16 is sign-extended.)
11948.0xfa+4.0x6,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movhu
1195"movhu"
1196*mn10300
c2d11a7d
JM		 1197
1198*am33
c76b4bab 1199*am33_2
c2d11a7d 1200
c906108c
SS		 1201{
1202 /* OP_FA600000 (); */
1203 PC = cia;
1204 State.regs[REG_D0 + DN1]
1205 = load_half ((State.regs[REG_A0 + AM0]
1206 + EXTEND16 (FETCH16(D16A, D16B))));
1207}
1208
1209
1210// 1111 1100 0110 DnAm d32.....; movhu (d32,Am),Dn
12118.0xfc+4.0x6,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movhu
1212"movhu"
1213*mn10300
c2d11a7d
JM		 1214
1215*am33
c76b4bab 1216*am33_2
c2d11a7d 1217
c906108c
SS		 1218{
1219 /* OP_FC600000 (); */
1220 PC = cia;
1221 State.regs[REG_D0 + DN1]
1222 = load_half ((State.regs[REG_A0 + AM0]
1223 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
1224}
1225
1226
1227// 1111 1000 1011 11Dn d8.....; movhu (d8,SP),Dn (d8 is zero-extended)
12288.0xf8+4.0xb,11,2.DN0+8.D8:D1a:::movhu
1229"movhu"
1230*mn10300
c2d11a7d
JM		 1231
1232*am33
c76b4bab 1233*am33_2
c2d11a7d 1234
c906108c
SS		 1235{
1236 /* OP_F8BC00 (); */
1237 PC = cia;
1238 State.regs[REG_D0 + DN0]
1239 = load_half ((State.regs[REG_SP] + (D8)));
1240}
1241
1242
1243// 1111 1010 1011 11Dn d16.....; movhu (d16,SP),Dn (d16 is zero-extended.)
12448.0xfa+4.0xb,11,2.DN0+8.IMM16A+8.IMM16B:D2a:::movhu
1245"movhu"
1246*mn10300
c2d11a7d
JM		 1247
1248*am33
c76b4bab 1249*am33_2
c2d11a7d 1250
c906108c
SS		 1251{
1252 /* OP_FABC0000 (); */
1253 PC = cia;
1254 State.regs[REG_D0 + DN0]
1255 = load_half ((State.regs[REG_SP] + FETCH16(IMM16A, IMM16B)));
1256}
1257
1258
1259// 1111 1100 1011 11Dn d32.....; movhu (d32,SP),Dn
12608.0xfc+4.0xb,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movhu
1261"movhu"
1262*mn10300
c2d11a7d
JM		 1263
1264*am33
c76b4bab 1265*am33_2
c2d11a7d 1266
c906108c
SS		 1267{
1268 /* OP_FCBC0000 (); */
1269 PC = cia;
1270 State.regs[REG_D0 + DN0]
1271 = load_half (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
1272}
1273
1274
1275// 1111 0100 10Dn DiAm; movhu (Di,Am),Dn
12768.0xf4+10,2.DN2,2.DI,2.AM0:D0a:::movhu
1277"movhu"
1278*mn10300
c2d11a7d
JM		 1279
1280*am33
c76b4bab 1281*am33_2
c2d11a7d 1282
c906108c
SS		 1283{
1284 /* OP_F480 (); */
1285 PC = cia;
1286 State.regs[REG_D0 + DN2]
1287 = load_half ((State.regs[REG_A0 + AM0] + State.regs[REG_D0 + DI]));
1288}
1289
1290
1291// 0011 10Dn abs16...; movhu (abs16),Dn (abs16 is zero-extended)
12924.0x3,10,2.DN0+8.IMM16A+8.IMM16B:S2:::movhu
1293"movhu"
1294*mn10300
c2d11a7d
JM		 1295
1296*am33
c76b4bab 1297*am33_2
c2d11a7d 1298
c906108c
SS		 1299{
1300 /* OP_380000 (); */
1301 PC = cia;
1302 State.regs[REG_D0 + DN0] = load_half (FETCH16(IMM16A, IMM16B));
1303}
1304
1305
1306// 1111 1100 1010 11Dn abs32...; movhu (abs32),Dn
13078.0xfc+4.0xa,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movhu
1308"movhu"
1309*mn10300
c2d11a7d
JM		 1310
1311*am33
c76b4bab 1312*am33_2
c2d11a7d 1313
c906108c
SS		 1314{
1315 /* OP_FCAC0000 (); */
1316 PC = cia;
1317 State.regs[REG_D0 + DN0]
1318 = load_half (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
1319}
1320
1321
1322// 1111 0000 0111 DmAn; movhu Dm,(An)
13238.0xf0+4.0x7,2.DM1,2.AN0:D0b:::movhu
1324"movhu"
1325*mn10300
c2d11a7d
JM		 1326
1327*am33
c76b4bab 1328*am33_2
c2d11a7d 1329
c906108c
SS		 1330{
1331 /* OP_F070 (); */
1332 PC = cia;
1333 store_half (State.regs[REG_A0 + AN0],
1334 State.regs[REG_D0 + DM1]);
1335}
1336
1337
1338// 1111 1000 0111 DmAn d8......; movhu Dm,(d8,An) (d8 is sign-extended)
13398.0xf8+4.0x7,2.DM1,2.AN0+8.D8:D1b:::movhu
1340"movhu"
1341*mn10300
c2d11a7d
JM		 1342
1343*am33
c76b4bab 1344*am33_2
c2d11a7d 1345
c906108c
SS		 1346{
1347 /* OP_F87000 (); */
1348 PC = cia;
1349 store_half ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
1350 State.regs[REG_D0 + DM1]);
1351}
1352
1353
1354// 1111 1010 0111 DnAm d16.....; movhu Dm,(d16,An) (d16 is sign-extended.)
13558.0xfa+4.0x7,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movhu
1356"movhu"
1357*mn10300
c2d11a7d
JM		 1358
1359*am33
c76b4bab 1360*am33_2
c2d11a7d 1361
c906108c
SS		 1362{
1363 /* OP_FA700000 (); */
1364 PC = cia;
1365 store_half ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
1366 State.regs[REG_D0 + DM1]);
1367}
1368
1369
1370// 1111 1100 0111 DmAn d32.....; movhu Dm,(d32,An)
13718.0xfc+4.0x7,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movhu
1372"movhu"
1373*mn10300
c2d11a7d
JM		 1374
1375*am33
c76b4bab 1376*am33_2
c2d11a7d 1377
c906108c
SS		 1378{
1379 /* OP_FC700000 (); */
1380 PC = cia;
1381 store_half ((State.regs[REG_A0 + AN0]
1382 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
1383 State.regs[REG_D0 + DM1]);
1384}
1385
1386
1387// 1111 1000 1001 Dm11 d8....; movhu Dm,(d8,SP) (d8 is zero-extended)
13888.0xf8+4.0x9,2.DM1,11+8.D8:D1c:::movhu
1389"movhu"
1390*mn10300
c2d11a7d
JM		 1391
1392*am33
c76b4bab 1393*am33_2
c2d11a7d 1394
c906108c
SS		 1395{
1396 /* OP_F89300 (); */
1397 PC = cia;
1398 store_half (State.regs[REG_SP] + (D8),
1399 State.regs[REG_D0 + DM1]);
1400}
1401
1402
1403// 1111 1010 1001 Dm11 d16.....; movhu Dm,(d16,SP) (d16 is zero-extended.)
14048.0xfa+4.0x9,2.DM1,11+8.IMM16A+8.IMM16B:D2c:::movhu
1405"movhu"
1406*mn10300
c2d11a7d
JM		 1407
1408*am33
c76b4bab 1409*am33_2
c2d11a7d 1410
c906108c
SS		 1411{
1412 /* OP_FA930000 (); */
1413 PC = cia;
1414 store_half (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
1415 State.regs[REG_D0 + DM1]);
1416}
1417
1418
1419// 1111 1100 1001 Dm11 d32.....; movhu Dm,(d32,SP)
14208.0xfc+4.0x9,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movhu
1421"movhu"
1422*mn10300
c2d11a7d
JM		 1423
1424*am33
c76b4bab 1425*am33_2
c2d11a7d 1426
c906108c
SS		 1427{
1428 /* OP_FC930000 (); */
1429 PC = cia;
1430 store_half (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1431 State.regs[REG_D0 + DM1]);
1432}
1433
1434
1435// 1111 0100 11Dm DiAn; movhu Dm,(Di,An)
14368.0xf4+11,2.DM2,2.DI,2.AN0:D0c:::movhu
1437"movhu"
1438*mn10300
c2d11a7d
JM		 1439
1440*am33
c76b4bab 1441*am33_2
c2d11a7d 1442
c906108c
SS		 1443{
1444 /* OP_F4C0 (); */
1445 PC = cia;
1446 store_half ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
1447 State.regs[REG_D0 + DM2]);
1448}
1449
1450
1451// 0000 Dm11 abs16...; movhu Dm,(abs16) (abs16 is zero-extended)
14524.0x0,2.DM1,11+8.IMM16A+8.IMM16B:S2a:::movhu
1453"movhu"
1454*mn10300
c2d11a7d
JM		 1455
1456*am33
c76b4bab 1457*am33_2
c2d11a7d 1458
c906108c
SS		 1459{
1460 /* OP_30000 (); */
1461 PC = cia;
1462 store_half (FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DM1]);
1463}
1464
1465
1466// 1111 1100 1000 Dm11 abs32...; movhu Dm,(abs32)
14678.0xfc+4.0x8,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movhu
1468"movhu"
1469*mn10300
c2d11a7d
JM		 1470
1471*am33
c76b4bab 1472*am33_2
c2d11a7d 1473
c906108c
SS		 1474{
1475 /* OP_FC830000 (); */
1476 PC = cia;
1477 store_half (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1478 State.regs[REG_D0 + DM1]);
1479}
1480
1481
1482// 1111 0010 1101 00Dn; ext Dn
14838.0xf2+4.0xd,00,2.DN0:D0:::ext
1484"ext"
1485*mn10300
c2d11a7d
JM		 1486
1487*am33
c76b4bab 1488*am33_2
c2d11a7d 1489
c906108c
SS		 1490{
1491 /* OP_F2D0 (); */
1492 PC = cia;
1493 if (State.regs[REG_D0 + DN0] & 0x80000000)
1494 State.regs[REG_MDR] = -1;
1495 else
1496 State.regs[REG_MDR] = 0;
1497}
1498
1499
1500// 0001 00Dn; extb Dn
15014.0x1,00,2.DN0:S0:::extb
1502"extb"
1503*mn10300
c2d11a7d
JM		 1504
1505*am33
c76b4bab 1506*am33_2
c2d11a7d 1507
c906108c
SS		 1508{
1509 /* OP_10 (); */
1510 PC = cia;
1511 State.regs[REG_D0 + DN0] = EXTEND8 (State.regs[REG_D0 + DN0]);
1512}
1513
1514
1515// 0001 01Dn; extbu Dn
15164.0x1,01,2.DN0:S0:::extbu
1517"extbu"
1518*mn10300
c2d11a7d
JM		 1519
1520*am33
c76b4bab 1521*am33_2
c2d11a7d 1522
c906108c
SS		 1523{
1524 /* OP_14 (); */
1525 PC = cia;
1526 State.regs[REG_D0 + DN0] &= 0xff;
1527}
1528
1529
1530// 0001 10Dn; exth Dn
15314.0x1,10,2.DN0:S0:::exth
1532"exth"
1533*mn10300
c2d11a7d
JM		 1534
1535*am33
c76b4bab 1536*am33_2
c2d11a7d 1537
c906108c
SS		 1538{
1539 /* OP_18 (); */
1540 PC = cia;
1541 State.regs[REG_D0 + DN0] = EXTEND16 (State.regs[REG_D0 + DN0]);
1542}
1543
1544
1545// 0001 11Dn; exthu Dn
15464.0x1,11,2.DN0:S0:::exthu
1547"exthu"
1548*mn10300
c2d11a7d
JM		 1549
1550*am33
c76b4bab 1551*am33_2
c2d11a7d 1552
c906108c
SS		 1553{
1554 /* OP_1C (); */
1555 PC = cia;
1556 State.regs[REG_D0 + DN0] &= 0xffff;
1557}
1558
1559
1560// 0000 Dn00; clr Dn
15614.0x0,2.DN1,00:S0:::clr
1562"clr"
1563*mn10300
c2d11a7d
JM		 1564
1565*am33
c76b4bab 1566*am33_2
c2d11a7d 1567
c906108c
SS		 1568{
1569 /* OP_0 (); */
1570 PC = cia;
1571 State.regs[REG_D0 + DN1] = 0;
1572
1573 PSW |= PSW_Z;
1574 PSW &= ~(PSW_V | PSW_C | PSW_N);
1575}
1576
1577
1578// 1110 DmDn; add Dm,Dn
15794.0xe,2.DM1,2.DN0:S0:::add
1580"add"
1581*mn10300
c2d11a7d
JM		 1582
1583*am33
c76b4bab 1584*am33_2
c2d11a7d 1585
c906108c
SS		 1586{
1587 /* OP_E0 (); */
1588 PC = cia;
1589 genericAdd(State.regs[REG_D0 + DM1], REG_D0 + DN0);
1590}
1591
1592// 1111 0001 0110 DmAn; add Dm,An
15938.0xf1+4.0x6,2.DM1,2.AN0:D0:::add
1594"add"
1595*mn10300
c2d11a7d
JM		 1596
1597*am33
c76b4bab 1598*am33_2
c2d11a7d 1599
c906108c
SS		 1600{
1601 /* OP_F160 (); */
1602 PC = cia;
1603 genericAdd(State.regs[REG_D0 + DM1], REG_A0 + AN0);
1604}
1605
1606
1607// 1111 0001 0101 AmDn; add Am,Dn
16088.0xf1+4.0x5,2.AM1,2.DN0:D0a:::add
1609"add"
1610*mn10300
c2d11a7d
JM		 1611
1612*am33
c76b4bab 1613*am33_2
c2d11a7d 1614
c906108c
SS		 1615{
1616 /* OP_F150 (); */
1617 PC = cia;
1618 genericAdd(State.regs[REG_A0 + AM1], REG_D0 + DN0);
1619}
1620
1621
1622// 1111 0001 0111 AmAn; add Am,An
16238.0xf1+4.0x7,2.AM1,2.AN0:D0b:::add
1624"add"
1625*mn10300
c2d11a7d
JM		 1626
1627*am33
c76b4bab 1628*am33_2
c2d11a7d 1629
c906108c
SS		 1630{
1631 /* OP_F170 (); */
1632 PC = cia;
1633 genericAdd(State.regs[REG_A0 + AM1], REG_A0 + AN0);
1634}
1635
1636
1637// 0010 10Dn imm8....; add imm8,Dn (imm8 is sign-extended)
16384.0x2,10,2.DN0+8.IMM8:S1:::add
1639"add"
1640*mn10300
c2d11a7d
JM		 1641
1642*am33
c76b4bab 1643*am33_2
c2d11a7d 1644
c906108c
SS		 1645{
1646 /* OP_2800 (); */
1647 PC = cia;
1648 genericAdd(EXTEND8(IMM8), REG_D0 + DN0);
1649}
1650
1651
1652// 1111 1010 1100 00Dn imm16...; add imm16,Dn
16538.0xfa+4.0xc,00,2.DN0+8.IMM16A+8.IMM16B:D2:::add
1654"add"
1655*mn10300
c2d11a7d
JM		 1656
1657*am33
c76b4bab 1658*am33_2
c2d11a7d 1659
c906108c
SS		 1660{
1661 /* OP_FAC00000 (); */
1662 PC = cia;
1663 genericAdd(EXTEND16(FETCH16(IMM16A, IMM16B)), REG_D0 + DN0);
1664}
1665
1666
1667// 1111 1100 1100 00Dn imm32...; add imm32,Dn
16688.0xfc+4.0xc,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::add
1669"add"
1670*mn10300
c2d11a7d
JM		 1671
1672*am33
c76b4bab 1673*am33_2
c2d11a7d 1674
c906108c
SS		 1675{
1676 /* OP_FCC00000 (); */
1677 PC = cia;
1678 genericAdd(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
1679}
1680
1681
1682// 0010 00An imm8....; add imm8,An (imm8 is sign-extended)
16834.0x2,00,2.AN0+8.IMM8:S1a:::add
1684"add"
1685*mn10300
c2d11a7d
JM		 1686
1687*am33
c76b4bab 1688*am33_2
c2d11a7d 1689
c906108c
SS		 1690{
1691 /* OP_2000 (); */
1692 PC = cia;
1693 genericAdd(EXTEND8(IMM8), REG_A0 + AN0);
1694}
1695
1696
1697// 1111 1010 1101 00An imm16...; add imm16,An (imm16 is sign-extended.)
16988.0xfa+4.0xd,00,2.AN0+8.IMM16A+8.IMM16B:D2a:::add
1699"add"
1700*mn10300
c2d11a7d
JM		 1701
1702*am33
c76b4bab 1703*am33_2
c2d11a7d 1704
c906108c
SS		 1705{
1706 /* OP_FAD00000 (); */
1707 PC = cia;
1708 genericAdd(EXTEND16(FETCH16(IMM16A, IMM16B)), REG_A0 + AN0);
1709}
1710
1711
1712// 1111 1100 1101 00An imm32...; add imm32,An
17138.0xfc+4.0xd,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::add
1714"add"
1715*mn10300
c2d11a7d
JM		 1716
1717*am33
c76b4bab 1718*am33_2
c2d11a7d 1719
c906108c
SS		 1720{
1721 /* OP_FCD00000 (); */
1722 PC = cia;
1723 genericAdd(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_A0 + AN0);
1724}
1725
1726
1727// 1111 1000 1111 1110 imm8....; add imm8,SP (imm8 is sign-extended.)
17288.0xf8+8.0xfe+8.IMM8:D1:::add
1729"add"
1730*mn10300
c2d11a7d
JM		 1731
1732*am33
c76b4bab 1733*am33_2
c2d11a7d 1734
c906108c
SS		 1735{
1736 /* OP_F8FE00 (); */
24a39d88 1737 unsigned32 imm;
c906108c
SS		 1738
1739 /* Note: no PSW changes. */
1740 PC = cia;
1741 imm = EXTEND8 (IMM8);
1742 State.regs[REG_SP] += imm;
1743}
1744
1745
1746// 1111 1010 1111 1110 imm16...; add imm16,SP (imm16 is sign-extended.)
17478.0xfa+8.0xfe+8.IMM16A+8.IMM16B:D2b:::add
1748"add"
1749*mn10300
c2d11a7d
JM		 1750
1751*am33
c76b4bab 1752*am33_2
c2d11a7d 1753
c906108c
SS		 1754{
1755 /* OP_FAFE0000 (); */
24a39d88 1756 unsigned32 imm;
c906108c
SS		 1757
1758 /* Note: no PSW changes. */
1759 PC = cia;
1760 imm = EXTEND16 (FETCH16(IMM16A, IMM16B));
1761 State.regs[REG_SP] += imm;
1762}
1763
1764
1765// 1111 1100 1111 1110 imm32...; add imm32,SP
17668.0xfc+8.0xfe+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::add
1767"add"
1768*mn10300
c2d11a7d
JM		 1769
1770*am33
c76b4bab 1771*am33_2
c2d11a7d 1772
c906108c
SS		 1773{
1774 /* OP_FCFE0000 (); */
24a39d88 1775 unsigned32 imm;
c906108c
SS		 1776
1777 /* Note: no PSW changes. */
1778 PC = cia;
1779 imm = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
1780 State.regs[REG_SP] += imm;
1781}
1782
1783
1784// 1111 0001 0100 DmDn; addc Dm,Dn
17858.0xf1+4.0x4,2.DM1,2.DN0:D0:::addc
1786"addc"
1787*mn10300
c2d11a7d
JM		 1788
1789*am33
c76b4bab 1790*am33_2
c2d11a7d 1791
c906108c
SS		 1792{
1793 /* OP_F140 (); */
1794 int z, c, n, v;
24a39d88 1795 unsigned32 reg1, reg2, sum;
c906108c
SS		 1796
1797 PC = cia;
1798 reg1 = State.regs[REG_D0 + DM1];
1799 reg2 = State.regs[REG_D0 + DN0];
1800 sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
1801 State.regs[REG_D0 + DN0] = sum;
1802
1803 z = ((PSW & PSW_Z) != 0) && (sum == 0);
1804 n = (sum & 0x80000000);
1805 c = (sum < reg1) || (sum < reg2);
1806 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
1807 && (reg2 & 0x80000000) != (sum & 0x80000000));
1808
1809 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1810 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1811 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1812}
1813
1814
1815// 1111 0001 0000 DmDn; sub Dm,Dn
18168.0xf1+4.0x0,2.DM1,2.DN0:D0:::sub
1817"sub"
1818*mn10300
c2d11a7d
JM		 1819
1820*am33
c76b4bab 1821*am33_2
c2d11a7d 1822
c906108c
SS		 1823{
1824 /* OP_F100 (); */
1825 PC = cia;
1826 genericSub(State.regs[REG_D0 + DM1], REG_D0 + DN0);
1827}
1828
1829// 1111 0001 0010 DmAn; sub DmAn
18308.0xf1+4.0x2,2.DM1,2.AN0:D0a:::sub
1831"sub"
1832*mn10300
c2d11a7d
JM		 1833
1834*am33
c76b4bab 1835*am33_2
c2d11a7d 1836
c906108c
SS		 1837{
1838 /* OP_F120 (); */
1839 PC = cia;
1840 genericSub(State.regs[REG_D0 + DM1], REG_A0 + AN0);
1841}
1842
1843
1844// 1111 0001 0001 AmDn; sub AmDn
18458.0xf1+4.0x1,2.AM1,2.DN0:D0b:::sub
1846"sub"
1847*mn10300
c2d11a7d
JM		 1848
1849*am33
c76b4bab 1850*am33_2
c2d11a7d 1851
c906108c
SS		 1852{
1853 /* OP_F110 (); */
1854 PC = cia;
1855 genericSub(State.regs[REG_A0 + AM1], REG_D0 + DN0);
1856}
1857
1858
1859// 1111 0001 0011 AmAn; sub Am,An
18608.0xf1+4.0x3,2.AM1,2.AN0:D0c:::sub
1861"sub"
1862*mn10300
c2d11a7d
JM		 1863
1864*am33
c76b4bab 1865*am33_2
c2d11a7d 1866
c906108c
SS		 1867{
1868 /* OP_F130 (); */
1869 PC = cia;
1870 genericSub(State.regs[REG_A0 + AM1], REG_A0 + AN0);
1871}
1872
1873
1874// 1111 1100 1100 01Dn imm32...; sub imm32,Dn
18758.0xfc+4.0xc,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::sub
1876"sub"
1877*mn10300
c2d11a7d
JM		 1878
1879*am33
c76b4bab 1880*am33_2
c2d11a7d 1881
c906108c
SS		 1882{
1883 /* OP_FCC40000 (); */
1884 PC = cia;
1885 genericSub(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
1886}
1887
1888
1889// 1111 1100 1101 01An imm32...; sub imm32,An
18908.0xfc+4.0xd,01,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::sub
1891"sub"
1892*mn10300
c2d11a7d
JM		 1893
1894*am33
c76b4bab 1895*am33_2
c2d11a7d 1896
c906108c
SS		 1897{
1898 /* OP_FCD40000 (); */
1899 PC = cia;
1900 genericSub(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_A0 + AN0);
1901}
1902
1903
1904// 1111 0001 1000 DmDn; subc Dm,Dn
19058.0xf1+4.0x8,2.DM1,2.DN0:D0:::subc
1906"subc"
1907*mn10300
c2d11a7d
JM		 1908
1909*am33
c76b4bab 1910*am33_2
c2d11a7d 1911
c906108c
SS		 1912{
1913 /* OP_F180 (); */
1914 int z, c, n, v;
24a39d88 1915 unsigned32 reg1, reg2, difference;
c906108c
SS		 1916
1917 PC = cia;
1918 reg1 = State.regs[REG_D0 + DM1];
1919 reg2 = State.regs[REG_D0 + DN0];
1920 difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
1921 State.regs[REG_D0 + DN0] = difference;
1922
1923 z = ((PSW & PSW_Z) != 0) && (difference == 0);
1924 n = (difference & 0x80000000);
1925 c = (reg1 > reg2);
1926 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1927 && (reg2 & 0x80000000) != (difference & 0x80000000));
1928
1929 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1930 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1931 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1932}
1933
1934
1935// 1111 0010 0100 DmDn; mul Dm,Dn
19368.0xf2+4.0x4,2.DM1,2.DN0:D0:::mul
1937"mul"
1938*mn10300
c2d11a7d
JM		 1939
1940*am33
c76b4bab 1941*am33_2
c2d11a7d 1942
c906108c
SS		 1943{
1944 /* OP_F240 (); */
24a39d88 1945 unsigned64 temp;
c906108c
SS		 1946 int n, z;
1947
1948 PC = cia;
1949 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
1950 * (signed64)(signed32)State.regs[REG_D0 + DM1]);
1951 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1952 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1953 z = (State.regs[REG_D0 + DN0] == 0);
1954 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1955 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1956 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1957}
1958
1959
1960// 1111 0010 0101 DmDn; mulu Dm,Dn
19618.0xf2+4.0x5,2.DM1,2.DN0:D0:::mulu
1962"mulu"
1963*mn10300
c2d11a7d
JM		 1964
1965*am33
c76b4bab 1966*am33_2
c2d11a7d 1967
c906108c
SS		 1968{
1969 /* OP_F250 (); */
24a39d88 1970 unsigned64 temp;
c906108c
SS		 1971 int n, z;
1972
1973 PC = cia;
1974 temp = ((unsigned64)State.regs[REG_D0 + DN0]
1975 * (unsigned64)State.regs[REG_D0 + DM1]);
1976 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1977 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1978 z = (State.regs[REG_D0 + DN0] == 0);
1979 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1980 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1981 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1982}
1983
1984
1985// 1111 0010 0110 DmDn; div Dm,Dn
19868.0xf2+4.0x6,2.DM1,2.DN0:D0:::div
1987"div"
1988*mn10300
c2d11a7d
JM		 1989
1990*am33
c76b4bab 1991*am33_2
c2d11a7d 1992
c906108c
SS		 1993{
1994 /* OP_F260 (); */
1995 signed64 temp;
1996 signed32 denom;
1997 int n, z, v;
1998
1999 PC = cia;
2000 denom = (signed32)State.regs[REG_D0 + DM1];
2001
2002 temp = State.regs[REG_MDR];
2003 temp <<= 32;
2004 temp |= State.regs[REG_D0 + DN0];
2005 if ( !(v = (0 == denom)) )
2006 {
2007 State.regs[REG_MDR] = temp % (signed32)State.regs[REG_D0 + DM1];
2008 temp /= (signed32)State.regs[REG_D0 + DM1];
2009 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
2010 }
2011 else
2012 {
2013 State.regs[REG_MDR] = temp;
2014 State.regs[REG_D0 + DN0] = 0xff;
2015 }
2016 z = (State.regs[REG_D0 + DN0] == 0);
2017 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2018 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2019 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (v ? PSW_V : 0));
2020}
2021
2022
2023// 1111 0010 0111 DmDn; divu Dm,Dn
20248.0xf2+4.0x7,2.DM1,2.DN0:D0:::divu
2025"divu"
2026*mn10300
c2d11a7d
JM		 2027
2028*am33
c76b4bab 2029*am33_2
c2d11a7d 2030
c906108c
SS		 2031{
2032 /* OP_F270 (); */
2033 unsigned64 temp;
2034 unsigned32 denom;
2035 int n, z, v;
2036
2037 PC = cia;
2038 denom = (unsigned32)State.regs[REG_D0 + DM1];
2039 temp = State.regs[REG_MDR];
2040 temp <<= 32;
2041 temp |= State.regs[REG_D0 + DN0];
2042 if ( !(v = (0 == denom)) )
2043 {
2044 State.regs[REG_MDR] = temp % State.regs[REG_D0 + DM1];
2045 temp /= State.regs[REG_D0 + DM1];
2046 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
2047 }
2048 else
2049 {
2050 State.regs[REG_MDR] = temp;
2051 State.regs[REG_D0 + DN0] = 0xff;
2052 }
2053 z = (State.regs[REG_D0 + DN0] == 0);
2054 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2055 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2056 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (v ? PSW_V : 0));
2057}
2058
2059
2060// 0100 Dn00; inc Dn
20614.0x4,2.DN1,00:S0:::inc
2062"inc"
2063*mn10300
c2d11a7d
JM		 2064
2065*am33
c76b4bab 2066*am33_2
c2d11a7d 2067
c906108c
SS		 2068{
2069 /* OP_40 (); */
24a39d88 2070 unsigned32 imm;
c906108c
SS		 2071
2072 PC = cia;
2073 imm = 1;
2074 genericAdd(imm, REG_D0 + DN1);
2075}
2076
2077
2078// 0100 An01
20794.0x4,2.AN1,01:S0a:::inc
2080"inc"
2081*mn10300
c2d11a7d
JM		 2082
2083*am33
c76b4bab 2084*am33_2
c2d11a7d 2085
c906108c
SS		 2086{
2087 /* OP_41 (); */
2088 PC = cia;
2089 State.regs[REG_A0 + AN1] += 1;
2090}
2091
2092
2093// 0101 00An; inc4 An
20944.0x5,00,2.AN0:S0:::inc4
2095"inc4"
2096*mn10300
c2d11a7d
JM		 2097
2098*am33
c76b4bab 2099*am33_2
c2d11a7d 2100
c906108c
SS		 2101{
2102 /* OP_50 (); */
2103 PC = cia;
2104 State.regs[REG_A0 + AN0] += 4;
2105}
2106
2107
2108// 1010 DnDn imm8....; cmp imm8,Dn (imm8 is sign-extended.)
21094.0xa,2.DM1,2.DN0=DM1+IMM8:S0i:::cmp
2110"cmp"
2111*mn10300
c2d11a7d
JM		 2112
2113*am33
c76b4bab 2114*am33_2
c2d11a7d 2115
c906108c
SS		 2116{
2117 PC = cia;
2118 /* OP_A000 (); */
2119 genericCmp(EXTEND8 (IMM8), State.regs[REG_D0 + DN0]);
2120}
2121
2122
2123// 1010 DmDn; cmp Dm,Dn (Dm != Dn, see above when Dm == Dn)
21244.0xa,2.DM1,2.DN0!DM1:S0:::cmp
2125"cmp"
2126*mn10300
c2d11a7d
JM		 2127
2128*am33
c76b4bab 2129*am33_2
c2d11a7d 2130
c906108c
SS		 2131{
2132 PC = cia;
2133 /* OP_A0 (); */
2134 genericCmp(State.regs[REG_D0 + DM1], State.regs[REG_D0 + DN0]);
2135}
2136
2137
2138// 1111 0001 1010 DmAn; cmp Dm,An
21398.0xf1+4.0xa,2.DM1,2.AN0:D0:::cmp
2140"cmp"
2141*mn10300
c2d11a7d
JM		 2142
2143*am33
c76b4bab 2144*am33_2
c2d11a7d 2145
c906108c
SS		 2146{
2147 /* OP_F1A0 (); */
2148 PC = cia;
2149 genericCmp(State.regs[REG_D0 + DM1], State.regs[REG_A0 + AN0]);
2150}
2151
2152
2153// 1111 0001 1001 AmDn; cmp Am,Dn
21548.0xf1+4.0x9,2.AM1,2.DN0:D0a:::cmp
2155"cmp"
2156*mn10300
c2d11a7d
JM		 2157
2158*am33
c76b4bab 2159*am33_2
c2d11a7d 2160
c906108c
SS		 2161{
2162 /* OP_F190 (); */
2163 PC = cia;
2164 genericCmp(State.regs[REG_A0 + AM1], State.regs[REG_D0 + DN0]);
2165}
2166
2167
2168// 1011 AnAn imm8....; cmp imm8,An (imm8 is zero-extended.)
21694.0xb,2.AM1,2.AN0=AM1+IMM8:S0ai:::cmp
2170"cmp"
2171*mn10300
c2d11a7d
JM		 2172
2173*am33
c76b4bab 2174*am33_2
c2d11a7d 2175
c906108c
SS		 2176{
2177 PC = cia;
2178 /* OP_B000 (); */
2179 genericCmp(IMM8,
2180 State.regs[REG_A0 + AN0]);
2181}
2182
2183
2184// 1011 AmAn; cmp Am,An (Dm != Dn, see above when Dm == Dn)
21854.0xb,2.AM1,2.AN0!AM1:S0a:::cmp
2186"cmp"
2187*mn10300
c2d11a7d
JM		 2188
2189*am33
c76b4bab 2190*am33_2
c2d11a7d 2191
c906108c
SS		 2192{
2193 PC = cia;
2194 /* OP_B0 (); */
2195 genericCmp(State.regs[REG_A0 + AM1], State.regs[REG_A0 + AN0]);
2196}
2197
2198
2199// 1111 1010 1100 10Dn imm16...; cmp imm16,Dn (imm16 is sign-extended.)
22008.0xfa+4.0xc,10,2.DN0+8.IMM16A+8.IMM16B:D2:::cmp
2201"cmp"
2202*mn10300
c2d11a7d
JM		 2203
2204*am33
c76b4bab 2205*am33_2
c2d11a7d 2206
c906108c
SS		 2207{
2208 /* OP_FAC80000 (); */
2209 PC = cia;
2210 genericCmp(EXTEND16(FETCH16(IMM16A, IMM16B)),
2211 State.regs[REG_D0 + DN0]);
2212}
2213
2214
2215// 1111 1100 1100 10Dn imm32...; cmp imm32,Dn
22168.0xfc+4.0xc,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::cmp
2217"cmp"
2218*mn10300
c2d11a7d
JM		 2219
2220*am33
c76b4bab 2221*am33_2
c2d11a7d 2222
c906108c
SS		 2223{
2224 /* OP_FCC80000 (); */
2225 PC = cia;
2226 genericCmp(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
2227 State.regs[REG_D0 + DN0]);
2228}
2229
2230
2231// 1111 1010 1101 10An imm16...; cmp imm16,An (imm16 is zero-extended.)
22328.0xfa+4.0xd,10,2.AN0+8.IMM16A+8.IMM16B:D2a:::cmp
2233"cmp"
2234*mn10300
c2d11a7d
JM		 2235
2236*am33
c76b4bab 2237*am33_2
c2d11a7d 2238
c906108c
SS		 2239{
2240 /* OP_FAD80000 (); */
2241 PC = cia;
2242 genericCmp(FETCH16(IMM16A, IMM16B),
2243 State.regs[REG_A0 + AN0]);
2244}
2245
2246
2247// 1111 1100 1101 10An imm32...; cmp imm32,An
22488.0xfc+4.0xd,10,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::cmp
2249"cmp"
2250*mn10300
c2d11a7d
JM		 2251
2252*am33
c76b4bab 2253*am33_2
c2d11a7d 2254
c906108c
SS		 2255{
2256 /* OP_FCD80000 (); */
2257 PC = cia;
2258 genericCmp(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
2259 State.regs[REG_A0 + AN0]);
2260}
2261
2262
2263// 1111 0010 0000 DmDn; and Dm,Dn
22648.0xf2+4.0x0,2.DM1,2.DN0:D0:::and
2265"and"
2266*mn10300
c2d11a7d
JM		 2267
2268*am33
c76b4bab 2269*am33_2
c2d11a7d 2270
c906108c
SS		 2271{
2272 /* OP_F200 (); */
2273 int n, z;
2274
2275 PC = cia;
2276 State.regs[REG_D0 + DN0] &= State.regs[REG_D0 + DM1];
2277 z = (State.regs[REG_D0 + DN0] == 0);
2278 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2279 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2280 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2281}
2282
2283
2284// 1111 1000 1110 00Dn imm8....; and imm8,Dn (imm8 is zero-extended.)
22858.0xf8+4.0xe,00,2.DN0+8.IMM8:D1:::and
2286"and"
2287*mn10300
c2d11a7d
JM		 2288
2289*am33
c76b4bab 2290*am33_2
c2d11a7d 2291
c906108c
SS		 2292{
2293 /* OP_F8E000 (); */
2294 int n, z;
2295
2296 PC = cia;
2297 State.regs[REG_D0 + DN0] &= IMM8;
2298 z = (State.regs[REG_D0 + DN0] == 0);
2299 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2300 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2301 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2302}
2303
2304
2305// 1111 1010 1110 00Dn imm16...; and imm16,Dn (imm16 is zero-extended.)
23068.0xfa+4.0xe,00,2.DN0+8.IMM16A+8.IMM16B:D2:::and
2307"and"
2308*mn10300
c2d11a7d
JM		 2309
2310*am33
c76b4bab 2311*am33_2
c2d11a7d 2312
c906108c
SS		 2313{
2314 /* OP_FAE00000 (); */
2315 int n, z;
2316
2317 PC = cia;
2318 State.regs[REG_D0 + DN0] &= FETCH16(IMM16A, IMM16B);
2319 z = (State.regs[REG_D0 + DN0] == 0);
2320 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2321 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2322 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2323}
2324
2325
2326// 1111 1100 1110 00Dn imm32...; and imm32,Dn
23278.0xfc+4.0xe,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::and
2328"and"
2329*mn10300
c2d11a7d
JM		 2330
2331*am33
c76b4bab 2332*am33_2
c2d11a7d 2333
c906108c
SS		 2334{
2335 /* OP_FCE00000 (); */
2336 int n, z;
2337
2338 PC = cia;
2339 State.regs[REG_D0 + DN0]
2340 &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
2341 z = (State.regs[REG_D0 + DN0] == 0);
2342 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2343 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2344 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2345}
2346
2347
2348// 1111 1010 1111 1100 imm16...; and imm16,PSW (imm16 is zero-extended.)
23498.0xfa+8.0xfc+8.IMM16A+8.IMM16B:D2a:::and
2350"and"
2351*mn10300
c2d11a7d
JM		 2352
2353*am33
c76b4bab 2354*am33_2
c2d11a7d 2355
c906108c
SS		 2356{
2357 /* OP_FAFC0000 (); */
2358 PC = cia;
2359 PSW &= FETCH16(IMM16A, IMM16B);
2360}
2361
2362
2363
2364// 1111 0010 0001 DmDn; or DmDn
23658.0xf2+4.0x1,2.DM1,2.DN0:D0:::or
2366"or"
2367*mn10300
c2d11a7d
JM		 2368
2369*am33
c76b4bab 2370*am33_2
c2d11a7d 2371
c906108c
SS		 2372{
2373 /* OP_F210 (); */
2374 PC = cia;
2375 genericOr(State.regs[REG_D0 + DM1], REG_D0 + DN0);
2376}
2377
2378
2379// 1111 1000 1110 01Dn imm8....; or imm8,Dn (imm8 is zero-extended.)n
23808.0xf8+4.0xe,01,2.DN0+8.IMM8:D1:::or
2381"or"
2382*mn10300
c2d11a7d
JM		 2383
2384*am33
c76b4bab 2385*am33_2
c2d11a7d 2386
c906108c
SS		 2387{
2388 /* OP_F8E400 (); */
2389 PC = cia;
2390 genericOr(IMM8, REG_D0 + DN0);
2391}
2392
2393
2394// 1111 1010 1110 01Dn imm16...; or imm16,DN (imm16 is zero-extended.)
23958.0xfa+4.0xe,01,2.DN0+8.IMM16A+8.IMM16B:D2:::or
2396"or"
2397*mn10300
c2d11a7d
JM		 2398
2399*am33
c76b4bab 2400*am33_2
c2d11a7d 2401
c906108c
SS		 2402{
2403 /* OP_FAE40000 (); */
2404 PC = cia;
2405 genericOr(FETCH16(IMM16A, IMM16B), REG_D0 + DN0);
2406}
2407
2408
2409// 1111 1100 1110 01Dn imm32...; or imm32,Dn
24108.0xfc+4.0xe,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::or
2411"or"
2412*mn10300
c2d11a7d
JM		 2413
2414*am33
c76b4bab 2415*am33_2
c2d11a7d 2416
c906108c
SS		 2417{
2418 /* OP_FCE40000 (); */
2419 PC = cia;
2420 genericOr(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
2421}
2422
2423
2424// 1111 1010 1111 1101 imm16...; or imm16,PSW (imm16 is zero-extended.)
24258.0xfa+8.0xfd+8.IMM16A+8.IMM16B:D2a:::or
2426"or"
2427*mn10300
c2d11a7d
JM		 2428
2429*am33
c76b4bab 2430*am33_2
c2d11a7d 2431
c906108c
SS		 2432{
2433 /* OP_FAFD0000 (); */
2434 PC = cia;
2435 PSW |= FETCH16(IMM16A, IMM16B);
2436}
2437
2438
2439// 1111 0010 0010 DmDn; xor Dm,Dn
24408.0xf2+4.0x2,2.DM1,2.DN0:D0:::xor
2441"xor"
2442*mn10300
c2d11a7d
JM		 2443
2444*am33
c76b4bab 2445*am33_2
c2d11a7d 2446
c906108c
SS		 2447{
2448 /* OP_F220 (); */
2449 PC = cia;
2450 genericXor(State.regs[REG_D0 + DM1], REG_D0 + DN0);
2451}
2452
2453
2454// 1111 1010 1110 10Dn imm16...; xor imm16,Dn (imm16 is zero-extended.)
24558.0xfa+4.0xe,10,2.DN0+8.IMM16A+8.IMM16B:D2:::xor
2456"xor"
2457*mn10300
c2d11a7d
JM		 2458
2459*am33
c76b4bab 2460*am33_2
c2d11a7d 2461
c906108c
SS		 2462{
2463 /* OP_FAE80000 (); */
2464 PC = cia;
2465 genericXor(FETCH16(IMM16A, IMM16B), REG_D0 + DN0);
2466}
2467
2468
2469// 1111 1100 1110 10Dn imm32...; xor imm32,Dn
24708.0xfc+4.0xe,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::xor
2471"xor"
2472*mn10300
c2d11a7d
JM		 2473
2474*am33
c76b4bab 2475*am33_2
c2d11a7d 2476
c906108c
SS		 2477{
2478 /* OP_FCE80000 (); */
2479 PC = cia;
2480 genericXor(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
2481}
2482
2483
2484// 1111 0010 0011 00Dn; not Dn
24858.0xf2+4.0x3,00,2.DN0:D0:::not
2486"not"
2487*mn10300
c2d11a7d
JM		 2488
2489*am33
c76b4bab 2490*am33_2
c2d11a7d 2491
c906108c
SS		 2492{
2493 /* OP_F230 (); */
2494 int n, z;
2495
2496 PC = cia;
2497 State.regs[REG_D0 + DN0] = ~State.regs[REG_D0 + DN0];
2498 z = (State.regs[REG_D0 + DN0] == 0);
2499 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2500 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2501 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2502}
2503
2504
2505// 1111 1000 1110 11Dn imm8....; btst imm8,Dn (imm8 is zero-extended.)
25068.0xf8+4.0xe,11,2.DN0+8.IMM8:D1:::btst
2507"btst"
2508*mn10300
c2d11a7d
JM		 2509
2510*am33
c76b4bab 2511*am33_2
c2d11a7d 2512
c906108c
SS		 2513{
2514 /* OP_F8EC00 (); */
2515 PC = cia;
2516 genericBtst(IMM8, State.regs[REG_D0 + DN0]);
2517}
2518
2519
2520// 1111 1010 1110 11Dn imm16.....; btst imm16,Dn (imm16 is zero-extended.)
25218.0xfa+4.0xe,11,2.DN0+8.IMM16A+8.IMM16B:D2:::btst
2522"btst"
2523*mn10300
c2d11a7d
JM		 2524
2525*am33
c76b4bab 2526*am33_2
c2d11a7d 2527
c906108c
SS		 2528{
2529 /* OP_FAEC0000 (); */
2530 PC = cia;
2531 genericBtst(FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DN0]);
2532}
2533
2534
2535// 1111 1100 1110 11Dn imm32...; btst imm32,Dn
25368.0xfc+4.0xe,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::btst
2537"btst"
2538*mn10300
c2d11a7d
JM		 2539
2540*am33
c76b4bab 2541*am33_2
c2d11a7d 2542
c906108c
SS		 2543{
2544 /* OP_FCEC0000 (); */
2545 PC = cia;
2546 genericBtst(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
2547 State.regs[REG_D0 + DN0]);
2548}
2549
2550
2551// 1111 1110 0000 0010 abs32... imm8....; btst imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
25528.0xfe+8.0x02+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::btst
2553"btst"
2554*mn10300
c2d11a7d
JM		 2555
2556*am33
c76b4bab 2557*am33_2
c2d11a7d 2558
c906108c
SS		 2559{
2560 /* OP_FE020000 (); */
2561 PC = cia;
2562 genericBtst(IMM8,
2563 load_byte(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
2564}
2565
2566
2567// 1111 1010 1111 10An d8...... imm8....;
2568// btst imm8,(d8,An) (d8 is sign-extended,imm8 is zero-extended., processing unit: byte)
25698.0xfa+4.0xf,10,2.AN0+8.D8+8.IMM8:D2a:::btst
2570"btst"
2571*mn10300
c2d11a7d
JM		 2572
2573*am33
c76b4bab 2574*am33_2
c2d11a7d 2575
c906108c
SS		 2576{
2577 /* OP_FAF80000 (); */
2578 PC = cia;
2579 genericBtst(IMM8,
2580 load_byte(State.regs[REG_A0 + AN0] + EXTEND8(D8)));
2581}
2582
2583
2584// 1111 0000 1000 DmAn; bset Dm,(An) (Processing unit byte)
25858.0xf0+4.8,2.DM1,2.AN0:D0:::bset
2586"bset"
2587*mn10300
c2d11a7d
JM		 2588
2589*am33
c76b4bab 2590*am33_2
c2d11a7d 2591
c906108c
SS		 2592{
2593 /* OP_F080 (); */
24a39d88 2594 unsigned32 temp;
c906108c
SS		 2595 int z;
2596
2597 PC = cia;
2598 temp = load_byte (State.regs[REG_A0 + AN0]);
2599 z = (temp & State.regs[REG_D0 + DM1]) == 0;
2600 temp |= State.regs[REG_D0 + DM1];
2601 store_byte (State.regs[REG_A0 + AN0], temp);
2602 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2603 PSW |= (z ? PSW_Z : 0);
2604}
2605
2606
2607// 1111 1110 0000 0000 abs32... imm8....;
2608// bset imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
26098.0xfe+8.0x00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bset
2610"bset"
2611*mn10300
c2d11a7d
JM		 2612
2613*am33
c76b4bab 2614*am33_2
c2d11a7d 2615
c906108c
SS		 2616{
2617 /* OP_FE000000 (); */
24a39d88 2618 unsigned32 temp;
c906108c
SS		 2619 int z;
2620
2621 PC = cia;
2622 temp = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
2623 z = (temp & IMM8) == 0;
2624 temp |= IMM8;
2625 store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), temp);
2626 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2627 PSW |= (z ? PSW_Z : 0);
2628}
2629
2630
2631// 1111 1010 1111 00AnAn d8...... imm8....;
2632// bset imm8,(d8,An) (d8 is sign-extended, imm8 is zero-extended., processing unit: byte)
26338.0xfa+4.0xf,00,2.AN0+8.D8+8.IMM8:D2:::bset
2634"bset"
2635*mn10300
c2d11a7d
JM		 2636
2637*am33
c76b4bab 2638*am33_2
c2d11a7d 2639
c906108c
SS		 2640{
2641 /* OP_FAF00000 (); */
24a39d88 2642 unsigned32 temp;
c906108c
SS		 2643 int z;
2644
2645 PC = cia;
2646 temp = load_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)));
2647 z = (temp & (IMM8)) == 0;
2648 temp |= (IMM8);
2649 store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), temp);
2650 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2651 PSW |= (z ? PSW_Z : 0);
2652}
2653
2654
2655// 1111 0000 1001 DmAn; bclr Dm,(An) (Processing unit byte)
26568.0xf0+4.0x9,2.DM1,2.AN0:D0:::bclr
2657"bclr"
2658*mn10300
c2d11a7d
JM		 2659
2660*am33
c76b4bab 2661*am33_2
c2d11a7d 2662
c906108c
SS		 2663{
2664 /* OP_F090 (); */
24a39d88 2665 unsigned32 temp;
c906108c
SS		 2666 int z;
2667
2668 PC = cia;
2669 temp = load_byte (State.regs[REG_A0 + AN0]);
2670 z = (temp & State.regs[REG_D0 + DM1]) == 0;
2671 temp = temp & ~State.regs[REG_D0 + DM1];
2672 store_byte (State.regs[REG_A0 + AN0], temp);
2673 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2674 PSW |= (z ? PSW_Z : 0);
2675}
2676
2677
2678// 1111 1110 0000 0001 abs32... imm8....;
2679// bclr imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
26808.0xfe+8.0x01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bclr
2681"bclr"
2682*mn10300
c2d11a7d
JM		 2683
2684*am33
c76b4bab 2685*am33_2
c2d11a7d 2686
c906108c
SS		 2687{
2688 /* OP_FE010000 (); */
24a39d88 2689 unsigned32 temp;
c906108c
SS		 2690 int z;
2691
2692 PC = cia;
2693 temp = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
2694 z = (temp & IMM8) == 0;
2695 temp = temp & ~(IMM8);
2696 store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), temp);
2697 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2698 PSW |= (z ? PSW_Z : 0);
2699}
2700
2701
2702// 1111 1010 1111 01An d8...... imm8....;
2703// bclr imm8,(d8,An) (d8 is sign-extended, imm8 is zero-extended., processing unit: byte)
27048.0xfa+4.0xf,01,2.AN0+8.D8+8.IMM8:D2:::bclr
2705"bclr"
2706*mn10300
c2d11a7d
JM		 2707
2708*am33
c76b4bab 2709*am33_2
c2d11a7d 2710
c906108c
SS		 2711{
2712 /* OP_FAF40000 (); */
24a39d88 2713 unsigned32 temp;
c906108c
SS		 2714 int z;
2715
2716 PC = cia;
2717 temp = load_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)));
2718 z = (temp & (IMM8)) == 0;
2719 temp = temp & ~(IMM8);
2720 store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), temp);
2721 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2722 PSW |= (z ? PSW_Z : 0);
2723}
2724
2725
2726// 1111 0010 1011 DmDn; asr Dm,Dn
27278.0xf2+4.0xb,2.DM1,2.DN0:D0:::asr
2728"asr"
2729*mn10300
c2d11a7d
JM		 2730
2731*am33
c76b4bab 2732*am33_2
c2d11a7d 2733
c906108c
SS		 2734{
2735 /* OP_F2B0 (); */
24a39d88 2736 signed32 temp;
c906108c
SS		 2737 int z, n, c;
2738
2739 PC = cia;
2740 temp = State.regs[REG_D0 + DN0];
2741 c = temp & 1;
2742 temp >>= State.regs[REG_D0 + DM1];
2743 State.regs[REG_D0 + DN0] = temp;
2744 z = (State.regs[REG_D0 + DN0] == 0);
2745 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2746 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2747 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2748}
2749
2750
2751// 1111 1000 1100 10Dn imm8...; asr imm8,Dn (imm8 is zero-extended.)
27528.0xf8+4.0xc,10,2.DN0+8.IMM8:D1:::asr
2753"asr"
2754*mn10300
c2d11a7d
JM		 2755
2756*am33
c76b4bab 2757*am33_2
c2d11a7d 2758
c906108c
SS		 2759{
2760 /* OP_F8C800 (); */
24a39d88 2761 signed32 temp;
c906108c
SS		 2762 int z, n, c;
2763
2764 PC = cia;
2765 temp = State.regs[REG_D0 + DN0];
2766 c = temp & 1;
2767 temp >>= IMM8;
2768 State.regs[REG_D0 + DN0] = temp;
2769 z = (State.regs[REG_D0 + DN0] == 0);
2770 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2771 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2772 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2773}
2774
2775
2776// 1111 0010 1010 DmDn; lsr Dm,Dn
27778.0xf2+4.0xa,2.DM1,2.DN0:D0:::lsr
2778"lsr"
2779*mn10300
c2d11a7d
JM		 2780
2781*am33
c76b4bab 2782*am33_2
c2d11a7d 2783
c906108c
SS		 2784{
2785 /* OP_F2A0 (); */
2786 int z, n, c;
2787
2788 PC = cia;
2789 c = State.regs[REG_D0 + DN0] & 1;
2790 State.regs[REG_D0 + DN0]
2791 >>= State.regs[REG_D0 + DM1];
2792 z = (State.regs[REG_D0 + DN0] == 0);
2793 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2794 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2795 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2796}
2797
2798
2799// 1111 1000 1100 01Dn imm8...; lsr imm8,Dn (imm8 is zero-extended.)
28008.0xf8+4.0xc,01,2.DN0+8.IMM8:D1:::lsr
2801"lsr"
2802*mn10300
c2d11a7d
JM		 2803
2804*am33
c76b4bab 2805*am33_2
c2d11a7d 2806
c906108c
SS		 2807{
2808 /* OP_F8C400 (); */
2809 int z, n, c;
2810
2811 PC = cia;
2812 c = State.regs[REG_D0 + DN0] & 1;
2813 State.regs[REG_D0 + DN0] >>= IMM8;
2814 z = (State.regs[REG_D0 + DN0] == 0);
2815 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2816 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2817 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2818}
2819
2820
2821// 1111 0010 1001 DmDn; asl Dm,Dn
28228.0xf2+4.0x9,2.DM1,2.DN0:D0:::asl
2823"asl"
2824*mn10300
c2d11a7d
JM		 2825
2826*am33
c76b4bab 2827*am33_2
c2d11a7d 2828
c906108c
SS		 2829{
2830 /* OP_F290 (); */
2831 int n, z;
2832
2833 PC = cia;
2834 State.regs[REG_D0 + DN0]
2835 <<= State.regs[REG_D0 + DM1];
2836 z = (State.regs[REG_D0 + DN0] == 0);
2837 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2838 PSW &= ~(PSW_Z | PSW_N);
2839 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2840}
2841
2842
2843// 1111 1000 1100 00Dn imm8...; asl imm8,Dn (imm8 is zero-extended.)
28448.0xf8+4.0xc,00,2.DN0+8.IMM8:D1:::asl
2845"asl"
2846*mn10300
c2d11a7d
JM		 2847
2848*am33
c76b4bab 2849*am33_2
c2d11a7d 2850
c906108c
SS		 2851{
2852 /* OP_F8C000 (); */
2853 int n, z;
2854
2855 PC = cia;
2856 State.regs[REG_D0 + DN0] <<= IMM8;
2857 z = (State.regs[REG_D0 + DN0] == 0);
2858 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2859 PSW &= ~(PSW_Z | PSW_N);
2860 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2861}
2862
2863
2864// 0101 01Dn; als2 Dn
28654.0x5,01,2.DN0:S0:::asl2
2866"asl2"
2867*mn10300
c2d11a7d
JM		 2868
2869*am33
c76b4bab 2870*am33_2
c2d11a7d 2871
c906108c
SS		 2872{
2873 /* OP_54 (); */
2874 int n, z;
2875 PC = cia;
2876
2877 State.regs[REG_D0 + DN0] <<= 2;
2878 z = (State.regs[REG_D0 + DN0] == 0);
2879 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2880 PSW &= ~(PSW_Z | PSW_N);
2881 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2882}
2883
2884
2885// 1111 0010 1000 01Dn; ror Dn
28868.0xf2+4.0x8,01,2.DN0:D0:::ror
2887"ror"
2888*mn10300
c2d11a7d
JM		 2889
2890*am33
c76b4bab 2891*am33_2
c2d11a7d 2892
c906108c
SS		 2893{
2894 /* OP_F284 (); */
24a39d88 2895 unsigned32 value;
c906108c
SS		 2896 int c,n,z;
2897
2898 PC = cia;
2899 value = State.regs[REG_D0 + DN0];
2900 c = (value & 0x1);
2901
2902 value >>= 1;
2903 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
2904 State.regs[REG_D0 + DN0] = value;
2905 z = (value == 0);
2906 n = (value & 0x80000000) != 0;
2907 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2908 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2909}
2910
2911
2912// 1111 0010 1000 00Dn; rol Dn
29138.0xf2+4.0x8,00,2.DN0:D0:::rol
2914"rol"
2915*mn10300
c2d11a7d
JM		 2916
2917*am33
c76b4bab 2918*am33_2
c2d11a7d 2919
c906108c
SS		 2920{
2921 /* OP_F280 (); */
24a39d88 2922 unsigned32 value;
c906108c
SS		 2923 int c,n,z;
2924
2925 PC = cia;
2926 value = State.regs[REG_D0 + DN0];
2927 c = (value & 0x80000000) ? 1 : 0;
2928
2929 value <<= 1;
2930 value |= ((PSW & PSW_C) != 0);
2931 State.regs[REG_D0 + DN0] = value;
2932 z = (value == 0);
2933 n = (value & 0x80000000) != 0;
2934 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2935 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2936}
2937
2938
2939// 1100 1000 d8......; beq (d8,PC) (d8 is sign-extended)
29408.0xc8+8.D8:S1:::beq
2941"beq"
2942*mn10300
c2d11a7d
JM		 2943
2944*am33
c76b4bab 2945*am33_2
c2d11a7d 2946
c906108c
SS		 2947{
2948 /* OP_C800 (); */
2949 PC = cia;
2950 if ((PSW & PSW_Z))
2951 {
2952 State.regs[REG_PC] += EXTEND8 (D8);
2953 nia = PC;
2954 }
2955}
2956
2957
2958// 1100 1001 d8......; bne (d8,PC) (d8 is sign-extended)
29598.0xc9+8.D8:S1:::bne
2960"bne"
2961*mn10300
c2d11a7d
JM		 2962
2963*am33
c76b4bab 2964*am33_2
c2d11a7d 2965
c906108c
SS		 2966{
2967 /* OP_C900 (); */
2968 PC = cia;
2969 if (!(PSW & PSW_Z))
2970 {
2971 State.regs[REG_PC] += EXTEND8 (D8);
2972 nia = PC;
2973 }
2974}
2975
2976
2977// 1100 0001 d8......; bgt (d8,PC) (d8 is sign-extended)
29788.0xc1+8.D8:S1:::bgt
2979"bgt"
2980*mn10300
c2d11a7d
JM		 2981
2982*am33
c76b4bab 2983*am33_2
c2d11a7d 2984
c906108c
SS		 2985{
2986 /* OP_C100 (); */
2987 PC = cia;
2988 if (!((PSW & PSW_Z)
2989 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
2990 {
2991 State.regs[REG_PC] += EXTEND8 (D8);
2992 nia = PC;
2993 }
2994}
2995
2996
2997// 1100 0010 d8......; bge (d8,PC) (d8 is sign-extended)
29988.0xc2+8.D8:S1:::bge
2999"bge"
3000*mn10300
c2d11a7d
JM		 3001
3002*am33
c76b4bab 3003*am33_2
c2d11a7d 3004
c906108c
SS		 3005{
3006 /* OP_C200 (); */
3007 PC = cia;
3008 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
3009 {
3010 State.regs[REG_PC] += EXTEND8 (D8);
3011 nia = PC;
3012 }
3013}
3014
3015
3016// 1100 0011 d8......; ble (d8,PC) (d8 is sign-extended)
30178.0xc3+8.D8:S1:::ble
3018"ble"
3019*mn10300
c2d11a7d
JM		 3020
3021*am33
c76b4bab 3022*am33_2
c2d11a7d 3023
c906108c
SS		 3024{
3025 /* OP_C300 (); */
3026 PC = cia;
3027 if ((PSW & PSW_Z)
3028 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
3029 {
3030 State.regs[REG_PC] += EXTEND8 (D8);
3031 nia = PC;
3032 }
3033}
3034
3035
3036// 1100 0000 d8......; blt (d8,PC) (d8 is sign-extended)
30378.0xc0+8.D8:S1:::blt
3038"blt"
3039*mn10300
c2d11a7d
JM		 3040
3041*am33
c76b4bab 3042*am33_2
c2d11a7d 3043
c906108c
SS		 3044{
3045 /* OP_C000 (); */
3046 PC = cia;
3047 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
3048 {
3049 State.regs[REG_PC] += EXTEND8 (D8);
3050 nia = PC;
3051 }
3052}
3053
3054
3055// 1100 0101 d8......; bhi (d8,PC) (d8 is sign-extended)
30568.0xc5+8.D8:S1:::bhi
3057"bhi"
3058*mn10300
c2d11a7d
JM		 3059
3060*am33
c76b4bab 3061*am33_2
c2d11a7d 3062
c906108c
SS		 3063{
3064 /* OP_C500 (); */
3065 PC = cia;
3066 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
3067 {
3068 State.regs[REG_PC] += EXTEND8 (D8);
3069 nia = PC;
3070 }
3071}
3072
3073
3074// 1100 0110 d8......; bcc (d8,PC) (d8 is sign-extended)
30758.0xc6+8.D8:S1:::bcc
3076"bcc"
3077*mn10300
c2d11a7d
JM		 3078
3079*am33
c76b4bab 3080*am33_2
c2d11a7d 3081
c906108c
SS		 3082{
3083 /* OP_C600 (); */
3084 PC = cia;
3085 if (!(PSW & PSW_C))
3086 {
3087 State.regs[REG_PC] += EXTEND8 (D8);
3088 nia = PC;
3089 }
3090}
3091
3092
3093// 1100 0101 d8......; bls (d8,PC) (d8 is sign-extended)
30948.0xc7+8.D8:S1:::bls
3095"bls"
3096*mn10300
c2d11a7d
JM		 3097
3098*am33
c76b4bab 3099*am33_2
c2d11a7d 3100
c906108c
SS		 3101{
3102 /* OP_C700 (); */
3103 PC = cia;
3104 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
3105 {
3106 State.regs[REG_PC] += EXTEND8 (D8);
3107 nia = PC;
3108 }
3109}
3110
3111
3112// 1100 0100 d8......; bcs (d8,PC) (d8 is sign-extended)
31138.0xc4+8.D8:S1:::bcs
3114"bcs"
3115*mn10300
c2d11a7d
JM		 3116
3117*am33
c76b4bab 3118*am33_2
c2d11a7d 3119
c906108c
SS		 3120{
3121 /* OP_C400 (); */
3122 PC = cia;
3123 if (PSW & PSW_C)
3124 {
3125 State.regs[REG_PC] += EXTEND8 (D8);
3126 nia = PC;
3127 }
3128}
3129
3130
3131// 1111 1000 1110 1000 d8......; bvc (d8,PC) (d8 is sign-extended)
31328.0xf8+8.0xe8+8.D8:D1:::bvc
3133"bvc"
3134*mn10300
c2d11a7d
JM		 3135
3136*am33
c76b4bab 3137*am33_2
c2d11a7d 3138
c906108c
SS		 3139{
3140 /* OP_F8E800 (); */
3141 PC = cia;
3142 if (!(PSW & PSW_V))
3143 {
3144 State.regs[REG_PC] += EXTEND8 (D8);
3145 nia = PC;
3146 }
3147}
3148
3149
3150// 1111 1000 1110 1001 d8......; bvs (d8,PC) (d8 is sign-extended)
31518.0xf8+8.0xe9+8.D8:D1:::bvs
3152"bvs"
3153*mn10300
c2d11a7d
JM		 3154
3155*am33
c76b4bab 3156*am33_2
c2d11a7d 3157
c906108c
SS		 3158{
3159 /* OP_F8E900 (); */
3160 PC = cia;
3161 if (PSW & PSW_V)
3162 {
3163 State.regs[REG_PC] += EXTEND8 (D8);
3164 nia = PC;
3165 }
3166}
3167
3168
3169// 1111 1000 1110 1010 d8......; bnc (d8,PC) (d8 is sign-extended)
31708.0xf8+8.0xea+8.D8:D1:::bnc
3171"bnc"
3172*mn10300
c2d11a7d
JM		 3173
3174*am33
c76b4bab 3175*am33_2
c2d11a7d 3176
c906108c
SS		 3177{
3178 /* OP_F8EA00 (); */
3179 PC = cia;
3180 if (!(PSW & PSW_N))
3181 {
3182 State.regs[REG_PC] += EXTEND8 (D8);
3183 nia = PC;
3184 }
3185}
3186
3187
3188// 1111 1000 1110 1010 d8......; bns (d8,PC) (d8 is sign-extended)
31898.0xf8+8.0xeb+8.D8:D1:::bns
3190"bns"
3191*mn10300
c2d11a7d
JM		 3192
3193*am33
c76b4bab 3194*am33_2
c2d11a7d 3195
c906108c
SS		 3196{
3197 /* OP_F8EB00 (); */
3198 PC = cia;
3199 if (PSW & PSW_N)
3200 {
3201 State.regs[REG_PC] += EXTEND8 (D8);
3202 nia = PC;
3203 }
3204}
3205
3206
3207// 1100 1010 d8......; bra (d8,PC) (d8 is sign-extended)
32088.0xca+8.D8:S1:::bra
3209"bra"
3210*mn10300
c2d11a7d
JM		 3211
3212*am33
c76b4bab 3213*am33_2
c2d11a7d 3214
c906108c
SS		 3215{
3216 /* OP_CA00 (); */
3217 PC = cia;
3218 State.regs[REG_PC] += EXTEND8 (D8);
3219 nia = PC;
3220}
3221
3222
3223// 1101 1000; leq
32248.0xd8:S0:::leq
3225"leq"
3226*mn10300
c2d11a7d
JM		 3227
3228*am33
c76b4bab 3229*am33_2
c2d11a7d 3230
c906108c
SS		 3231{
3232 /* OP_D8 (); */
3233 PC = cia;
3234 if (PSW & PSW_Z)
3235 {
3236 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3237 nia = PC;
3238 }
3239}
3240
3241
3242// 1101 1001; lne
32438.0xd9:S0:::lne
3244"lne"
3245*mn10300
c2d11a7d
JM		 3246
3247*am33
c76b4bab 3248*am33_2
c2d11a7d 3249
c906108c
SS		 3250{
3251 /* OP_D9 (); */
3252 PC = cia;
3253 if (!(PSW & PSW_Z))
3254 {
3255 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3256 nia = PC;
3257 }
3258}
3259
3260
3261// 1101 0001; lgt
32628.0xd1:S0:::lgt
3263"lgt"
3264*mn10300
c2d11a7d
JM		 3265
3266*am33
c76b4bab 3267*am33_2
c2d11a7d 3268
c906108c
SS		 3269{
3270 /* OP_D1 (); */
3271 PC = cia;
3272 if (!((PSW & PSW_Z)
3273 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
3274 {
3275 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3276 nia = PC;
3277 }
3278}
3279
3280
3281// 1101 0010; lge
32828.0xd2:S0:::lge
3283"lge"
3284*mn10300
c2d11a7d
JM		 3285
3286*am33
c76b4bab 3287*am33_2
c2d11a7d 3288
c906108c
SS		 3289{
3290 /* OP_D2 (); */
3291 PC = cia;
3292 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
3293 {
3294 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3295 nia = PC;
3296 }
3297}
3298
3299
3300// 1101 0011; lle
33018.0xd3:S0:::lle
3302"lle"
3303*mn10300
c2d11a7d
JM		 3304
3305*am33
c76b4bab 3306*am33_2
c2d11a7d 3307
c906108c
SS		 3308{
3309 /* OP_D3 (); */
3310 PC = cia;
3311 if ((PSW & PSW_Z)
3312 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
3313 {
3314 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3315 nia = PC;
3316 }
3317}
3318
3319
3320// 1101 0000; llt
33218.0xd0:S0:::llt
3322"llt"
3323*mn10300
c2d11a7d
JM		 3324
3325*am33
c76b4bab 3326*am33_2
c2d11a7d 3327
c906108c
SS		 3328{
3329 /* OP_D0 (); */
3330 PC = cia;
3331 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
3332 {
3333 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3334 nia = PC;
3335 }
3336}
3337
3338
3339// 1101 0101; lhi
33408.0xd5:S0:::lhi
3341"lhi"
3342*mn10300
c2d11a7d
JM		 3343
3344*am33
c76b4bab 3345*am33_2
c2d11a7d 3346
c906108c
SS		 3347{
3348 /* OP_D5 (); */
3349 PC = cia;
3350 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
3351 {
3352 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3353 nia = PC;
3354 }
3355}
3356
3357
3358// 1101 0110; lcc
33598.0xd6:S0:::lcc
3360"lcc"
3361*mn10300
c2d11a7d
JM		 3362
3363*am33
c76b4bab 3364*am33_2
c2d11a7d 3365
c906108c
SS		 3366{
3367 /* OP_D6 (); */
3368 PC = cia;
3369 if (!(PSW & PSW_C))
3370 {
3371 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3372 nia = PC;
3373 }
3374}
3375
3376
3377// 1101 0111; lls
33788.0xd7:S0:::lls
3379"lls"
3380*mn10300
c2d11a7d
JM		 3381
3382*am33
c76b4bab 3383*am33_2
c2d11a7d 3384
c906108c
SS		 3385{
3386 /* OP_D7 (); */
3387 PC = cia;
3388 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
3389 {
3390 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3391 nia = PC;
3392 }
3393}
3394
3395
3396// 1101 0100; lcs
33978.0xd4:S0:::lcs
3398"lcs"
3399*mn10300
c2d11a7d
JM		 3400
3401*am33
c76b4bab 3402*am33_2
c2d11a7d 3403
c906108c
SS		 3404{
3405 /* OP_D4 (); */
3406 PC = cia;
3407 if (PSW & PSW_C)
3408 {
3409 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3410 nia = PC;
3411 }
3412}
3413
3414
3415// 1101 1010; lra
34168.0xda:S0:::lra
3417"lra"
3418*mn10300
c2d11a7d
JM		 3419
3420*am33
c76b4bab 3421*am33_2
c2d11a7d 3422
c906108c
SS		 3423{
3424 /* OP_DA (); */
3425 PC = cia;
3426 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3427 nia = PC;
3428}
3429
3430
3431// 1101 1010; setlb
34328.0xdb:S0:::setlb
3433"setlb"
3434*mn10300
c2d11a7d
JM		 3435
3436*am33
c76b4bab 3437*am33_2
c2d11a7d 3438
c906108c
SS		 3439{
3440 /* OP_DB (); */
3441 PC = cia;
3442 State.regs[REG_LIR] = load_word (State.regs[REG_PC] + 1);
3443 State.regs[REG_LAR] = State.regs[REG_PC] + 5;
3444}
3445
3446
3447// 1111 0000 1111 01An; jmp (An)
34488.0xf0+4.0xf,01,2.AN0:D0:::jmp
3449"jmp"
3450*mn10300
c2d11a7d
JM		 3451
3452*am33
c76b4bab 3453*am33_2
c2d11a7d 3454
c906108c
SS		 3455{
3456 /* OP_F0F4 (); */
3457 PC = State.regs[REG_A0 + AN0];
3458 nia = PC;
3459}
3460
3461
3462// 1100 1100 d16.....; jmp (d16,PC) (d16 is sign-extended.)
34638.0xcc+8.D16A+8.D16B:S2:::jmp
3464"jmp"
3465*mn10300
c2d11a7d
JM		 3466
3467*am33
c76b4bab 3468*am33_2
c2d11a7d 3469
c906108c
SS		 3470{
3471 /* OP_CC0000 (); */
3472 PC = cia + EXTEND16(FETCH16(D16A, D16B));
3473 nia = PC;
3474}
3475
3476
3477// 1101 1100 d32........; jmp (d32, PC)
34788.0xdc+8.D32A+8.D32B+8.D32C+8.D32D:S4:::jmp
3479"jmp"
3480*mn10300
c2d11a7d
JM		 3481
3482*am33
c76b4bab 3483*am33_2
c2d11a7d 3484
c906108c
SS		 3485{
3486 /* OP_DC000000 (); */
3487 PC = cia + FETCH32(D32A, D32B, D32C, D32D);
3488 nia = PC;
3489}
3490
3491
3492// 1111 0000 1111 00An; calls (An)
34938.0xf0+4.0xf,00,2.AN0:D0:::calls
3494"calls"
3495*mn10300
c2d11a7d
JM		 3496
3497*am33
c76b4bab 3498*am33_2
c2d11a7d 3499
c906108c
SS		 3500{
3501 /* OP_F0F0 (); */
24a39d88 3502 unsigned32 next_pc, sp;
c906108c
SS		 3503
3504 PC = cia;
3505 sp = State.regs[REG_SP];
3506 next_pc = State.regs[REG_PC] + 2;
3507 store_word(sp, next_pc);
3508 State.regs[REG_MDR] = next_pc;
3509 State.regs[REG_PC] = State.regs[REG_A0 + AN0];
3510 nia = PC;
3511}
3512
3513
3514// 1111 1010 1111 1111 d16.....; calls (d16,PC) (d16 is sign-extended.)
35158.0xfa+8.0xff+8.D16A+8.D16B:D2:::calls
3516"calls"
3517*mn10300
c2d11a7d
JM		 3518
3519*am33
c76b4bab 3520*am33_2
c2d11a7d 3521
c906108c
SS		 3522{
3523 /* OP_FAFF0000 (); */
24a39d88 3524 unsigned32 next_pc, sp;
c906108c
SS		 3525
3526 PC = cia;
3527 sp = State.regs[REG_SP];
3528 next_pc = State.regs[REG_PC] + 4;
3529 store_word(sp, next_pc);
3530 State.regs[REG_MDR] = next_pc;
3531 State.regs[REG_PC] += EXTEND16 (FETCH16(D16A, D16B));
3532 nia = PC;
3533}
3534
3535
3536// 1111 1100 1111 1111 d32.....; calls (d32,PC)
35378.0xfc+8.0xff+8.D32A+8.D32B+8.D32C+8.D32D:D4:::calls
3538"calls"
3539*mn10300
c2d11a7d
JM		 3540
3541*am33
c76b4bab 3542*am33_2
c2d11a7d 3543
c906108c
SS		 3544{
3545 /* OP_FCFF0000 (); */
24a39d88 3546 unsigned32 next_pc, sp;
c906108c
SS		 3547
3548 PC = cia;
3549 sp = State.regs[REG_SP];
3550 next_pc = State.regs[REG_PC] + 6;
3551 store_word(sp, next_pc);
3552 State.regs[REG_MDR] = next_pc;
3553 State.regs[REG_PC] += FETCH32(D32A, D32B, D32C, D32D);
3554 nia = PC;
3555}
3556
3557
3558// 1111 0000 1111 1100; rets
35598.0xf0+8.0xfc:D0:::rets
3560"rets"
3561*mn10300
c2d11a7d
JM		 3562
3563*am33
c76b4bab 3564*am33_2
c2d11a7d 3565
c906108c
SS		 3566{
3567 /* OP_F0FC (); */
24a39d88 3568 unsigned32 sp;
c906108c
SS		 3569
3570 sp = State.regs[REG_SP];
3571 State.regs[REG_PC] = load_word(sp);
3572 nia = PC;
3573}
3574
3575
3576// 1111 0000 1111 1101; rti
35778.0xf0+8.0xfd:D0:::rti
3578"rti"
3579*mn10300
c2d11a7d
JM		 3580
3581*am33
c76b4bab 3582*am33_2
c2d11a7d 3583
c906108c
SS		 3584{
3585 /* OP_F0FD (); */
24a39d88 3586 unsigned32 sp;
c906108c
SS		 3587
3588 sp = State.regs[REG_SP];
3589 PSW = load_half(sp);
3590 State.regs[REG_PC] = load_word(sp+4);
3591 State.regs[REG_SP] +=8;
3592 nia = PC;
3593}
3594
3595
3596// 1111 0000 1111 1110; trap
35978.0xf0+8.0xfe:D0:::trap
3598"trap"
3599*mn10300
c2d11a7d
JM		 3600
3601*am33
c76b4bab 3602*am33_2
c2d11a7d 3603
c906108c
SS		 3604{
3605 /* OP_F0FE (); */
24a39d88 3606 unsigned32 sp, next_pc;
c906108c
SS		 3607
3608 PC = cia;
3609 sp = State.regs[REG_SP];
3610 next_pc = State.regs[REG_PC] + 2;
3611 store_word(sp, next_pc);
3612 nia = PC;
3613}
3614
3615
3616// 1111 0000 1111 1111; rtm
36178.0xf0+8.0xff:D0:::rtm
3618"rtm"
3619*mn10300
c2d11a7d
JM		 3620
3621*am33
c76b4bab 3622*am33_2
c2d11a7d 3623
c906108c
SS		 3624{
3625 /* OP_F0FF (); */
3626 PC = cia;
3627 abort ();
3628}
3629
3630
3631// 1100 1011; nop
36328.0xcb:S0:::nop
3633"nop"
3634*mn10300
c2d11a7d
JM		 3635
3636*am33
c76b4bab 3637*am33_2
c2d11a7d 3638
c906108c
SS		 3639{
3640 /* OP_CB (); */
3641 PC = cia;
3642}
3643
3644
3645// 1111 0101 0000 DmDn; udf20 Dm,Dn
36468.0xf5+4.0x0,2.DM1,2.DN0:D0:::putx
3647"putx"
3648*mn10300
3649{
3650 /* OP_F500 (); */
3651 PC = cia;
3652 State.regs[REG_MDRQ] = State.regs[REG_D0 + DN0];
3653}
3654
3655
3656// 1111 0110 1111 DmDn; udf15 Dm,Dn
36578.0xf6+4.0xf,2.DM1,2.DN0:D0:::getx
3658"getx"
3659*mn10300
c2d11a7d
JM		 3660
3661*am33
c76b4bab 3662*am33_2
c2d11a7d 3663
c906108c
SS		 3664{
3665 /* OP_F6F0 (); */
3666 int z, n;
3667
3668 PC = cia;
3669 z = (State.regs[REG_MDRQ] == 0);
3670 n = ((State.regs[REG_MDRQ] & 0x80000000) != 0);
3671 State.regs[REG_D0 + DN0] = State.regs[REG_MDRQ];
3672
3673 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3674 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
3675}
3676
3677
3678// 1111 0110 0000 DmDn; udf00 Dm,Dn
36798.0xf6+4.0x0,2.DM1,2.DN0:D0:::mulq
3680"mulq"
3681*mn10300
c2d11a7d
JM		 3682
3683*am33
c76b4bab 3684*am33_2
c2d11a7d 3685
c906108c
SS		 3686{
3687 /* OP_F600 (); */
24a39d88 3688 unsigned64 temp;
c906108c
SS		 3689 int n, z;
3690
3691 PC = cia;
3692 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3693 * (signed64)(signed32)State.regs[REG_D0 + DM1]);
3694 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3695 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3696 z = (State.regs[REG_D0 + DN0] == 0);
3697 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3698 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3699 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3700}
3701
3702
3703// 1111 1001 0000 00Dn imm8....; udf00 imm8,Dn (imm8 is sign-extended.)
37048.0xf9+4.0x,00,2.DN0+8.IMM8:D1:::mulq
3705"mulq"
3706*mn10300
c2d11a7d
JM		 3707
3708*am33
c76b4bab 3709*am33_2
c2d11a7d 3710
c906108c
SS		 3711{
3712 /* OP_F90000 (); */
24a39d88 3713 unsigned64 temp;
c906108c
SS		 3714 int n, z;
3715
3716 PC = cia;
3717 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3718 * (signed64)(signed32)EXTEND8 (IMM8));
3719 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3720 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3721 z = (State.regs[REG_D0 + DN0] == 0);
3722 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3723 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3724 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3725}
3726
3727
3728// 1111 1011 0000 00Dn imm16...; udf00 imm16,Dn (imm16 is sign-extended.)
37298.0xfb+4.0x0,00,2.DN0+8.IMM16A+8.IMM16B:D2:::mulq
3730"mulq"
3731*mn10300
c2d11a7d
JM		 3732
3733*am33
c76b4bab 3734*am33_2
c2d11a7d 3735
c906108c
SS		 3736{
3737 /* OP_FB000000 (); */
24a39d88 3738 unsigned64 temp;
c906108c
SS		 3739 int n, z;
3740
3741 PC = cia;
3742 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3743 * (signed64)(signed32)EXTEND16 (FETCH16(IMM16A, IMM16B)));
3744 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3745 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3746 z = (State.regs[REG_D0 + DN0] == 0);
3747 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3748 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3749 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3750}
3751
3752
3753// 1111 1101 0000 00Dn imm32...; udf00 imm32,Dn
37548.0xfd+4.0x0,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulq
3755"mulq"
3756*mn10300
c2d11a7d
JM		 3757
3758*am33
c76b4bab 3759*am33_2
c2d11a7d 3760
c906108c
SS		 3761{
3762 /* OP_FD000000 (); */
24a39d88 3763 unsigned64 temp;
c906108c
SS		 3764 int n, z;
3765
3766 PC = cia;
3767 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3768 * (signed64)(signed32)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
3769 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3770 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3771 z = (State.regs[REG_D0 + DN0] == 0);
3772 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3773 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3774 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3775}
3776
3777
3778// 1111 0110 0001 DmDn; udf01 Dm,Dn
37798.0xf6+4.0x1,2.DM1,2.DN0:D0:::mulqu
3780"mulqu"
3781*mn10300
c2d11a7d
JM		 3782
3783*am33
c76b4bab 3784*am33_2
c2d11a7d 3785
c906108c
SS		 3786{
3787 /* OP_F610 (); */
24a39d88 3788 unsigned64 temp;
c906108c
SS		 3789 int n, z;
3790
3791 PC = cia;
3792 temp = ((unsigned64) State.regs[REG_D0 + DN0]
3793 * (unsigned64) State.regs[REG_D0 + DM1]);
3794 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3795 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3796 z = (State.regs[REG_D0 + DN0] == 0);
3797 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3798 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3799 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3800}
3801
3802
3803// 1111 1001 0001 01Dn imm8....; udfu01 imm8,Dn (imm8 is zero-extended.)
38048.0xf9+4.0x1,01,2.DN0+8.IMM8:D1:::mulqu
3805"mulqu"
3806*mn10300
c2d11a7d
JM		 3807
3808*am33
c76b4bab 3809*am33_2
c2d11a7d 3810
c906108c
SS		 3811{
3812 /* OP_F91400 (); */
24a39d88 3813 unsigned64 temp;
c906108c
SS		 3814 int n, z;
3815
3816 PC = cia;
3817 temp = ((unsigned64)State.regs[REG_D0 + DN0]
3818 * (unsigned64)EXTEND8 (IMM8));
3819 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3820 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3821 z = (State.regs[REG_D0 + DN0] == 0);
3822 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3823 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3824 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3825}
3826
3827
3828// 1111 1011 0001 01Dn imm16...; udfu01 imm16,Dn (imm16 is zero-extended.)
38298.0xfb+4.0x1,01,2.DN0+8.IMM16A+8.IMM16B:D2:::mulqu
3830"mulqu"
3831*mn10300
c2d11a7d
JM		 3832
3833*am33
c76b4bab 3834*am33_2
c2d11a7d 3835
c906108c
SS		 3836{
3837 /* OP_FB140000 (); */
24a39d88 3838 unsigned64 temp;
c906108c
SS		 3839 int n, z;
3840
3841 PC = cia;
3842 temp = ((unsigned64)State.regs[REG_D0 + DN0]
3843 * (unsigned64) EXTEND16 (FETCH16(IMM16A, IMM16B)));
3844 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3845 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3846 z = (State.regs[REG_D0 + DN0] == 0);
3847 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3848 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3849 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3850}
3851
3852
3853// 1111 1101 0001 01Dn imm32...; udfu01 imm32,Dn
38548.0xfd+4.0x1,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulqu
3855"mulqu"
3856*mn10300
c2d11a7d
JM		 3857
3858*am33
c76b4bab 3859*am33_2
c2d11a7d 3860
c906108c
SS		 3861{
3862 /* OP_FD140000 (); */
24a39d88 3863 unsigned64 temp;
c906108c
SS		 3864 int n, z;
3865
3866 PC = cia;
3867 temp = ((unsigned64)State.regs[REG_D0 + DN0]
3868 * (unsigned64)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
3869 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3870 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3871 z = (State.regs[REG_D0 + DN0] == 0);
3872 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3873 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3874 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3875}
3876
3877
3878// 1111 0110 0100 DmDn; udf04 Dm,Dn
38798.0xf6+4.0x4,2.DM1,2.DN0:D0:::sat16
3880"sat16"
3881*mn10300
c2d11a7d
JM		 3882
3883*am33
c76b4bab 3884*am33_2
c2d11a7d 3885
c906108c
SS		 3886{
3887 /* OP_F640 (); */
3888 int temp;
3889
3890 PC = cia;
3891 temp = State.regs[REG_D0 + DM1];
3892 temp = (temp > 0x7fff ? 0x7fff : temp);
3893 temp = (temp < -0x8000 ? -0x8000 : temp);
3894 State.regs[REG_D0 + DN0] = temp;
3895}
3896
3897
3898// 1111 0110 0101 DmDn; udf05 Dm,Dn
38998.0xf6+4.0x5,2.DM1,2.DN0:D0:::sat24
3900"sat24"
3901*mn10300
c2d11a7d
JM		 3902
3903*am33
c76b4bab 3904*am33_2
c2d11a7d 3905
c906108c
SS		 3906{
3907 /* OP_F650 (); */
3908 int temp;
3909
3910 PC = cia;
3911 temp = State.regs[REG_D0 + DM1];
3912 temp = (temp > 0x7fffff ? 0x7fffff : temp);
3913 temp = (temp < -0x800000 ? -0x800000 : temp);
3914 State.regs[REG_D0 + DN0] = temp;
3915}
3916
3917
3918// 1111 0110 0111 DmDn; udf07 Dm,Dn
39198.0xf6+4.0x7,2.DM1,2.DN0:D0:::bsch
3920"bsch"
3921*mn10300
c2d11a7d
JM		 3922
3923*am33
c76b4bab 3924*am33_2
c2d11a7d 3925
c906108c
SS		 3926{
3927 /* OP_F670 (); */
3928 int temp, c;
3929
3930 PC = cia;
3931 temp = State.regs[REG_D0 + DM1];
3932 temp <<= (State.regs[REG_D0 + DN0] & 0x1f);
3933 c = (temp != 0 ? 1 : 0);
3934 PSW &= ~(PSW_C);
3935 PSW |= (c ? PSW_C : 0);
3936}
3937
3938
3939// 1111 0000 1100 0000; syscall
39408.0xf0+8.0xc0:D0:::syscall
3941"syscall"
3942*mn10300
c2d11a7d
JM		 3943
3944*am33
c76b4bab 3945*am33_2
c2d11a7d 3946
c906108c
SS		 3947{
3948 /* OP_F0C0 (); */
3949 PC = cia;
3950 do_syscall ();
3951}
3952
3953
3954// 1111 1111; break
39558.0xff:S0:::break
3956"break"
3957*mn10300
c2d11a7d
JM		 3958
3959*am33
c76b4bab 3960*am33_2
c2d11a7d 3961
c906108c
SS		 3962{
3963 /* OP_FF (); */
3964 PC = cia;
3965 program_interrupt(SD, CPU, cia, SIM_SIGTRAP);
3966}
3967
3968// 1100 1110 regs....; movm (SP),regs
39698.0xce+8.REGS:S1:::movm
3970"movm"
3971*mn10300
c2d11a7d
JM		 3972
3973*am33
c76b4bab 3974*am33_2
c2d11a7d 3975
c906108c
SS		 3976{
3977 /* OP_CE00 (); */
24a39d88
AO		 3978 unsigned32 sp = State.regs[REG_SP];
3979 unsigned32 mask;
c906108c
SS		 3980
3981 PC = cia;
3982 mask = REGS;
3983
3984 if (mask & 0x8)
3985 {
3986 sp += 4;
3987 State.regs[REG_LAR] = load_word (sp);
3988 sp += 4;
3989 State.regs[REG_LIR] = load_word (sp);
3990 sp += 4;
3991 State.regs[REG_MDR] = load_word (sp);
3992 sp += 4;
3993 State.regs[REG_A0 + 1] = load_word (sp);
3994 sp += 4;
3995 State.regs[REG_A0] = load_word (sp);
3996 sp += 4;
3997 State.regs[REG_D0 + 1] = load_word (sp);
3998 sp += 4;
3999 State.regs[REG_D0] = load_word (sp);
4000 sp += 4;
4001 }
4002
4003 if (mask & 0x10)
4004 {
4005 State.regs[REG_A0 + 3] = load_word (sp);
4006 sp += 4;
4007 }
4008
4009 if (mask & 0x20)
4010 {
4011 State.regs[REG_A0 + 2] = load_word (sp);
4012 sp += 4;
4013 }
4014
4015 if (mask & 0x40)
4016 {
4017 State.regs[REG_D0 + 3] = load_word (sp);
4018 sp += 4;
4019 }
4020
4021 if (mask & 0x80)
4022 {
4023 State.regs[REG_D0 + 2] = load_word (sp);
4024 sp += 4;
4025 }
4026
ceec3559 4027 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
c76b4bab 4028 || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
ceec3559 4029 )
c2d11a7d
JM		 4030 {
4031 if (mask & 0x1)
4032 {
be5fcb10 4033 /* Need to restore MDRQ, MCRH, MCRL, and MCVF */
c2d11a7d
JM		 4034 sp += 16;
4035 State.regs[REG_E0 + 1] = load_word (sp);
4036 sp += 4;
4037 State.regs[REG_E0 + 0] = load_word (sp);
4038 sp += 4;
4039 }
4040
4041 if (mask & 0x2)
4042 {
4043 State.regs[REG_E0 + 7] = load_word (sp);
4044 sp += 4;
4045 State.regs[REG_E0 + 6] = load_word (sp);
4046 sp += 4;
4047 State.regs[REG_E0 + 5] = load_word (sp);
4048 sp += 4;
4049 State.regs[REG_E0 + 4] = load_word (sp);
4050 sp += 4;
4051 }
4052
4053 if (mask & 0x4)
4054 {
4055 State.regs[REG_E0 + 3] = load_word (sp);
4056 sp += 4;
4057 State.regs[REG_E0 + 2] = load_word (sp);
4058 sp += 4;
4059 }
4060 }
c906108c
SS		 4061
4062 /* And make sure to update the stack pointer. */
4063 State.regs[REG_SP] = sp;
4064}
4065
4066
4067// 1100 1111 regs....; movm regs,(SP)
40688.0xcf+8.REGS:S1a:::movm
4069"movm"
4070*mn10300
c2d11a7d
JM		 4071
4072*am33
c76b4bab 4073*am33_2
c2d11a7d 4074
c906108c
SS		 4075{
4076 /* OP_CF00 (); */
24a39d88
AO		 4077 unsigned32 sp = State.regs[REG_SP];
4078 unsigned32 mask;
c906108c
SS		 4079
4080 PC = cia;
4081 mask = REGS;
4082
ceec3559 4083 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
c76b4bab 4084 || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
ceec3559 4085 )
c2d11a7d
JM		 4086 {
4087 if (mask & 0x4)
4088 {
4089 sp -= 4;
4090 store_word (sp, State.regs[REG_E0 + 2]);
4091 sp -= 4;
4092 store_word (sp, State.regs[REG_E0 + 3]);
4093 }
4094
4095 if (mask & 0x2)
4096 {
4097 sp -= 4;
4098 store_word (sp, State.regs[REG_E0 + 4]);
4099 sp -= 4;
4100 store_word (sp, State.regs[REG_E0 + 5]);
4101 sp -= 4;
4102 store_word (sp, State.regs[REG_E0 + 6]);
4103 sp -= 4;
4104 store_word (sp, State.regs[REG_E0 + 7]);
4105 }
4106
4107 if (mask & 0x1)
4108 {
4109 sp -= 4;
4110 store_word (sp, State.regs[REG_E0 + 0]);
4111 sp -= 4;
4112 store_word (sp, State.regs[REG_E0 + 1]);
4113 sp -= 16;
be5fcb10 4114 /* Need to save MDRQ, MCRH, MCRL, and MCVF */
c2d11a7d
JM		 4115 }
4116 }
c906108c
SS		 4117
4118 if (mask & 0x80)
4119 {
4120 sp -= 4;
4121 store_word (sp, State.regs[REG_D0 + 2]);
4122 }
4123
4124 if (mask & 0x40)
4125 {
4126 sp -= 4;
4127 store_word (sp, State.regs[REG_D0 + 3]);
4128 }
4129
4130 if (mask & 0x20)
4131 {
4132 sp -= 4;
4133 store_word (sp, State.regs[REG_A0 + 2]);
4134 }
4135
4136 if (mask & 0x10)
4137 {
4138 sp -= 4;
4139 store_word (sp, State.regs[REG_A0 + 3]);
4140 }
4141
4142 if (mask & 0x8)
4143 {
4144 sp -= 4;
4145 store_word (sp, State.regs[REG_D0]);
4146 sp -= 4;
4147 store_word (sp, State.regs[REG_D0 + 1]);
4148 sp -= 4;
4149 store_word (sp, State.regs[REG_A0]);
4150 sp -= 4;
4151 store_word (sp, State.regs[REG_A0 + 1]);
4152 sp -= 4;
4153 store_word (sp, State.regs[REG_MDR]);
4154 sp -= 4;
4155 store_word (sp, State.regs[REG_LIR]);
4156 sp -= 4;
4157 store_word (sp, State.regs[REG_LAR]);
4158 sp -= 4;
4159 }
4160
4161 /* And make sure to update the stack pointer. */
4162 State.regs[REG_SP] = sp;
4163}
4164
4165// 1100 1101 d16..... regs.... imm8....;
4166// call (d16,PC),regs,imm8 (d16 is sign-extended., imm8 is zero-extended.)
41678.0xcd+8.D16A+8.D16B+8.REGS+8.IMM8:S4:::call
4168"call"
4169*mn10300
c2d11a7d
JM		 4170
4171*am33
c76b4bab 4172*am33_2
c2d11a7d 4173
c906108c
SS		 4174{
4175 /* OP_CD000000 (); */
24a39d88
AO		 4176 unsigned32 next_pc, sp;
4177 unsigned32 mask;
c906108c
SS		 4178
4179 PC = cia;
4180 sp = State.regs[REG_SP];
4181 next_pc = PC + 5;
4182 store_word(sp, next_pc);
4183
4184 mask = REGS;
4185
ceec3559 4186 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
c76b4bab 4187 || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
ceec3559 4188 )
c2d11a7d
JM		 4189 {
4190 if (mask & 0x4)
4191 {
4192 sp -= 4;
4193 store_word (sp, State.regs[REG_E0 + 2]);
4194 sp -= 4;
4195 store_word (sp, State.regs[REG_E0 + 3]);
4196 }
4197
4198 if (mask & 0x2)
4199 {
4200 sp -= 4;
4201 store_word (sp, State.regs[REG_E0 + 4]);
4202 sp -= 4;
4203 store_word (sp, State.regs[REG_E0 + 5]);
4204 sp -= 4;
4205 store_word (sp, State.regs[REG_E0 + 6]);
4206 sp -= 4;
4207 store_word (sp, State.regs[REG_E0 + 7]);
4208 }
4209
4210 if (mask & 0x1)
4211 {
4212 sp -= 4;
4213 store_word (sp, State.regs[REG_E0 + 0]);
4214 sp -= 4;
4215 store_word (sp, State.regs[REG_E0 + 1]);
4216 sp -= 16;
be5fcb10 4217 /* Need to save MDRQ, MCRH, MCRL, and MCVF */
c2d11a7d
JM		 4218 }
4219 }
c906108c
SS		 4220
4221 if (mask & 0x80)
4222 {
4223 sp -= 4;
4224 store_word (sp, State.regs[REG_D0 + 2]);
4225 }
4226
4227 if (mask & 0x40)
4228 {
4229 sp -= 4;
4230 store_word (sp, State.regs[REG_D0 + 3]);
4231 }
4232
4233 if (mask & 0x20)
4234 {
4235 sp -= 4;
4236 store_word (sp, State.regs[REG_A0 + 2]);
4237 }
4238
4239 if (mask & 0x10)
4240 {
4241 sp -= 4;
4242 store_word (sp, State.regs[REG_A0 + 3]);
4243 }
4244
4245 if (mask & 0x8)
4246 {
4247 sp -= 4;
4248 store_word (sp, State.regs[REG_D0]);
4249 sp -= 4;
4250 store_word (sp, State.regs[REG_D0 + 1]);
4251 sp -= 4;
4252 store_word (sp, State.regs[REG_A0]);
4253 sp -= 4;
4254 store_word (sp, State.regs[REG_A0 + 1]);
4255 sp -= 4;
4256 store_word (sp, State.regs[REG_MDR]);
4257 sp -= 4;
4258 store_word (sp, State.regs[REG_LIR]);
4259 sp -= 4;
4260 store_word (sp, State.regs[REG_LAR]);
4261 sp -= 4;
4262 }
4263
4264 /* Update the stack pointer, note that the register saves to do not
4265 modify SP. The SP adjustment is derived totally from the imm8
4266 field. */
4267 State.regs[REG_SP] -= IMM8;
4268 State.regs[REG_MDR] = next_pc;
4269 State.regs[REG_PC] += EXTEND16 (FETCH16(D16A, D16B));
4270 nia = PC;
4271}
4272
4273
4274// 1101 1101 d32..... regs.... imm8....;
4275// call (d32,PC),regs,imm8 (imm8 is zero-extended.)
42768.0xdd+8.D32A+8.D32B+8.D32C+8.D32D+8.REGS+8.IMM8:S6:::call
4277"call"
4278*mn10300
c2d11a7d
JM		 4279
4280*am33
c76b4bab 4281*am33_2
c2d11a7d 4282
c906108c
SS		 4283{
4284 /* OP_DD000000 (); */
24a39d88
AO		 4285 unsigned32 next_pc, sp;
4286 unsigned32 mask;
c906108c
SS		 4287
4288 PC = cia;
4289 sp = State.regs[REG_SP];
4290 next_pc = State.regs[REG_PC] + 7;
4291 /* could assert that nia == next_pc here */
4292 store_word(sp, next_pc);
4293
4294 mask = REGS;
4295
ceec3559 4296 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
c76b4bab 4297 || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
ceec3559 4298 )
c2d11a7d
JM		 4299 {
4300 if (mask & 0x4)
4301 {
4302 sp -= 4;
4303 store_word (sp, State.regs[REG_E0 + 2]);
4304 sp -= 4;
4305 store_word (sp, State.regs[REG_E0 + 3]);
4306 }
4307
4308 if (mask & 0x2)
4309 {
4310 sp -= 4;
4311 store_word (sp, State.regs[REG_E0 + 4]);
4312 sp -= 4;
4313 store_word (sp, State.regs[REG_E0 + 5]);
4314 sp -= 4;
4315 store_word (sp, State.regs[REG_E0 + 6]);
4316 sp -= 4;
4317 store_word (sp, State.regs[REG_E0 + 7]);
4318 }
4319
4320 if (mask & 0x1)
4321 {
4322 sp -= 4;
4323 store_word (sp, State.regs[REG_E0 + 0]);
4324 sp -= 4;
4325 store_word (sp, State.regs[REG_E0 + 1]);
4326 sp -= 16;
be5fcb10 4327 /* Need to save MDRQ, MCRH, MCRL, and MCVF */
c2d11a7d
JM		 4328 }
4329 }
c906108c
SS		 4330
4331 if (mask & 0x80)
4332 {
4333 sp -= 4;
4334 store_word (sp, State.regs[REG_D0 + 2]);
4335 }
4336
4337 if (mask & 0x40)
4338 {
4339 sp -= 4;
4340 store_word (sp, State.regs[REG_D0 + 3]);
4341 }
4342
4343 if (mask & 0x20)
4344 {
4345 sp -= 4;
4346 store_word (sp, State.regs[REG_A0 + 2]);
4347 }
4348
4349 if (mask & 0x10)
4350 {
4351 sp -= 4;
4352 store_word (sp, State.regs[REG_A0 + 3]);
4353 }
4354
4355 if (mask & 0x8)
4356 {
4357 sp -= 4;
4358 store_word (sp, State.regs[REG_D0]);
4359 sp -= 4;
4360 store_word (sp, State.regs[REG_D0 + 1]);
4361 sp -= 4;
4362 store_word (sp, State.regs[REG_A0]);
4363 sp -= 4;
4364 store_word (sp, State.regs[REG_A0 + 1]);
4365 sp -= 4;
4366 store_word (sp, State.regs[REG_MDR]);
4367 sp -= 4;
4368 store_word (sp, State.regs[REG_LIR]);
4369 sp -= 4;
4370 store_word (sp, State.regs[REG_LAR]);
4371 sp -= 4;
4372 }
4373
4374 /* Update the stack pointer, note that the register saves to do not
4375 modify SP. The SP adjustment is derived totally from the imm8
4376 field. */
4377 State.regs[REG_SP] -= IMM8;
4378 State.regs[REG_MDR] = next_pc;
4379 State.regs[REG_PC] += FETCH32(D32A, D32B, D32C, D32D);
4380 nia = PC;
4381}
4382
4383
4384// 1101 1111 regs.... imm8....; ret regs,imm8 (imm8 is zero-extended.)
43858.0xdf+8.REGS+8.IMM8:S2:::ret
4386"ret"
4387*mn10300
c2d11a7d
JM		 4388
4389*am33
c76b4bab 4390*am33_2
c2d11a7d 4391
c906108c
SS		 4392{
4393 /* OP_DF0000 (); */
24a39d88
AO		 4394 unsigned32 sp, offset;
4395 unsigned32 mask;
c906108c
SS		 4396
4397 PC = cia;
4398 State.regs[REG_SP] += IMM8;
4399 sp = State.regs[REG_SP];
4400
4401 offset = -4;
4402 mask = REGS;
4403
ceec3559 4404 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
c76b4bab 4405 || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
ceec3559 4406 )
c2d11a7d
JM		 4407 {
4408
4409 if (mask & 0x4)
4410 {
4411 State.regs[REG_E0 + 2] = load_word (sp + offset);
4412 offset -= 4;
4413 State.regs[REG_E0 + 3] = load_word (sp + offset);
4414 offset -= 4;
4415 }
4416
4417 if (mask & 0x2)
4418 {
4419 State.regs[REG_E0 + 4] = load_word (sp + offset);
4420 offset -= 4;
4421 State.regs[REG_E0 + 5] = load_word (sp + offset);
4422 offset -= 4;
4423 State.regs[REG_E0 + 6] = load_word (sp + offset);
4424 offset -= 4;
4425 State.regs[REG_E0 + 7] = load_word (sp + offset);
4426 offset -= 4;
4427 }
4428
4429 if (mask & 0x1)
4430 {
be5fcb10 4431 /* Need to restore MDRQ, MCRH, MCRL, and MCVF */
c2d11a7d
JM		 4432 offset -= 16;
4433 State.regs[REG_E0 + 0] = load_word (sp + offset);
4434 offset -= 4;
4435 State.regs[REG_E0 + 1] = load_word (sp + offset);
4436 offset -= 4;
4437 }
4438
4439 }
c906108c
SS		 4440
4441 if (mask & 0x80)
4442 {
4443 State.regs[REG_D0 + 2] = load_word (sp + offset);
4444 offset -= 4;
4445 }
4446
4447 if (mask & 0x40)
4448 {
4449 State.regs[REG_D0 + 3] = load_word (sp + offset);
4450 offset -= 4;
4451 }
4452
4453 if (mask & 0x20)
4454 {
4455 State.regs[REG_A0 + 2] = load_word (sp + offset);
4456 offset -= 4;
4457 }
4458
4459 if (mask & 0x10)
4460 {
4461 State.regs[REG_A0 + 3] = load_word (sp + offset);
4462 offset -= 4;
4463 }
4464
4465 if (mask & 0x8)
4466 {
4467 State.regs[REG_D0] = load_word (sp + offset);
4468 offset -= 4;
4469 State.regs[REG_D0 + 1] = load_word (sp + offset);
4470 offset -= 4;
4471 State.regs[REG_A0] = load_word (sp + offset);
4472 offset -= 4;
4473 State.regs[REG_A0 + 1] = load_word (sp + offset);
4474 offset -= 4;
4475 State.regs[REG_MDR] = load_word (sp + offset);
4476 offset -= 4;
4477 State.regs[REG_LIR] = load_word (sp + offset);
4478 offset -= 4;
4479 State.regs[REG_LAR] = load_word (sp + offset);
4480 offset -= 4;
4481 }
4482
4483 /* Restore the PC value. */
4484 State.regs[REG_PC] = load_word(sp);
4485 nia = PC;
4486}
4487
4488
4489// 1101 1110 regs.... imm8....; retf regs,imm8 (imm8 is zero-extended.)
44908.0xde+8.REGS+8.IMM8:S2:::retf
4491"retf"
4492*mn10300
c2d11a7d
JM		 4493
4494*am33
c76b4bab 4495*am33_2
c2d11a7d 4496
c906108c
SS		 4497{
4498 /* OP_DE0000 (); */
24a39d88
AO		 4499 unsigned32 sp, offset;
4500 unsigned32 mask;
c906108c
SS		 4501
4502 PC = cia;
4503 State.regs[REG_SP] += IMM8;
4504 sp = State.regs[REG_SP];
7a292a7a 4505 State.regs[REG_PC] = State.regs[REG_MDR];
c906108c
SS		 4506
4507 offset = -4;
4508 mask = REGS;
4509
ceec3559 4510 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
c76b4bab 4511 || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
ceec3559 4512 )
c2d11a7d
JM		 4513 {
4514
4515 if (mask & 0x4)
4516 {
4517 State.regs[REG_E0 + 2] = load_word (sp + offset);
4518 offset -= 4;
4519 State.regs[REG_E0 + 3] = load_word (sp + offset);
4520 offset -= 4;
4521 }
4522
4523 if (mask & 0x2)
4524 {
4525 State.regs[REG_E0 + 4] = load_word (sp + offset);
4526 offset -= 4;
4527 State.regs[REG_E0 + 5] = load_word (sp + offset);
4528 offset -= 4;
4529 State.regs[REG_E0 + 6] = load_word (sp + offset);
4530 offset -= 4;
4531 State.regs[REG_E0 + 7] = load_word (sp + offset);
4532 offset -= 4;
4533 }
4534
4535 if (mask & 0x1)
4536 {
be5fcb10 4537 /* Need to restore MDRQ, MCRH, MCRL, and MCVF */
c2d11a7d
JM		 4538 offset -= 16;
4539 State.regs[REG_E0 + 0] = load_word (sp + offset);
4540 offset -= 4;
4541 State.regs[REG_E0 + 1] = load_word (sp + offset);
4542 offset -= 4;
4543 }
4544
4545 }
c906108c
SS		 4546
4547 if (mask & 0x80)
4548 {
4549 State.regs[REG_D0 + 2] = load_word (sp + offset);
4550 offset -= 4;
4551 }
4552
4553 if (mask & 0x40)
4554 {
4555 State.regs[REG_D0 + 3] = load_word (sp + offset);
4556 offset -= 4;
4557 }
4558
4559 if (mask & 0x20)
4560 {
4561 State.regs[REG_A0 + 2] = load_word (sp + offset);
4562 offset -= 4;
4563 }
4564
4565 if (mask & 0x10)
4566 {
4567 State.regs[REG_A0 + 3] = load_word (sp + offset);
4568 offset -= 4;
4569 }
4570
4571 if (mask & 0x8)
4572 {
4573 State.regs[REG_D0] = load_word (sp + offset);
4574 offset -= 4;
4575 State.regs[REG_D0 + 1] = load_word (sp + offset);
4576 offset -= 4;
4577 State.regs[REG_A0] = load_word (sp + offset);
4578 offset -= 4;
4579 State.regs[REG_A0 + 1] = load_word (sp + offset);
4580 offset -= 4;
4581 State.regs[REG_MDR] = load_word (sp + offset);
4582 offset -= 4;
4583 State.regs[REG_LIR] = load_word (sp + offset);
4584 offset -= 4;
4585 State.regs[REG_LAR] = load_word (sp + offset);
4586 offset -= 4;
4587 }
7a292a7a 4588 nia = PC;
c906108c
SS		 4589}
4590
c2d11a7d
JM		 4591
4592:include::am33:am33.igen
4593
GDB Binutils - Deliverables
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