gdb: add target_ops::supports_displaced_step
[deliverable/binutils-gdb.git] / sim / or1k / mloop.in
CommitLineData
fa8b7c21
SH
1# Simulator main loop for or1k. -*- C -*-
2#
b811d2c2 3# Copyright (C) 2017-2020 Free Software Foundation, Inc.
fa8b7c21
SH
4#
5# This file is part of the GNU Simulators.
6#
7# This program is free software; you can redistribute it and/or modify
8# it under the terms of the GNU General Public License as published by
9# the Free Software Foundation; either version 3 of the License, or
10# (at your option) any later version.
11#
12# This program is distributed in the hope that it will be useful,
13# but WITHOUT ANY WARRANTY; without even the implied warranty of
14# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15# GNU General Public License for more details.
16#
17# You should have received a copy of the GNU General Public License
18# along with this program. If not, see <http://www.gnu.org/licenses/>.
19
20# Syntax:
21# /bin/sh mainloop.in command
22#
23# Command is one of:
24#
25# init
26# support
27# extract-{simple,scache,pbb}
28# {full,fast}-exec-{simple,scache,pbb}
29#
30# A target need only provide a "full" version of one of simple,scache,pbb.
31# If the target wants it can also provide a fast version of same, or if
32# the slow (full featured) version is `simple', then the fast version can be
33# one of scache/pbb.
34# A target can't provide more than this.
35# However for illustration's sake this file provides examples of all.
36
37# ??? After a few more ports are done, revisit.
38# Will eventually need to machine generate a lot of this.
39
40case "x$1" in
41
42xsupport)
43
44cat <<EOF
45
46static INLINE const IDESC *
47extract (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
48 ARGBUF *abuf, int fast_p)
49{
50 const IDESC *id = @cpu@_decode (current_cpu, pc, insn, insn, abuf);
51 @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
52 if (!fast_p)
53 {
54 int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
55 int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
56 @cpu@_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p);
57 }
58 return id;
59}
60
61static INLINE SEM_PC
62execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
63{
64 SEM_PC vpc = sc;
65
66 @cpu@_insn_before (current_cpu, vpc, sc->argbuf.idesc);
67
68 if (fast_p)
69 {
70#if ! WITH_SEM_SWITCH_FAST
71#if WITH_SCACHE
72 vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, sc);
73#else
74 vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, &sc->argbuf);
75#endif
76#else
77 abort ();
78#endif /* WITH_SEM_SWITCH_FAST */
79 }
80 else
81 {
82#if ! WITH_SEM_SWITCH_FULL
83 ARGBUF *abuf = &sc->argbuf;
84 const IDESC *idesc = abuf->idesc;
85 const CGEN_INSN *idata = idesc->idata;
86#if WITH_SCACHE_PBB
87 int virtual_p = CGEN_INSN_ATTR_VALUE (idata, CGEN_INSN_VIRTUAL);
88#else
89 int virtual_p = 0;
90#endif
91
92 if (! virtual_p)
93 {
94 /* FIXME: call x-before */
95 if (ARGBUF_PROFILE_P (abuf))
96 PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num);
97 /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */
98 if (PROFILE_MODEL_P (current_cpu)
99 && ARGBUF_PROFILE_P (abuf))
100 @cpu@_model_insn_before (current_cpu, 1 /*first_p*/);
101 CGEN_TRACE_INSN_INIT (current_cpu, abuf, 1);
102 CGEN_TRACE_INSN (current_cpu, idata,
103 (const struct argbuf *) abuf, abuf->addr);
104 }
105#if WITH_SCACHE
106 vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc);
107#else
108 vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, abuf);
109#endif
110 if (! virtual_p)
111 {
112 /* FIXME: call x-after */
113 if (PROFILE_MODEL_P (current_cpu)
114 && ARGBUF_PROFILE_P (abuf))
115 {
116 int cycles;
117
118 cycles = (*idesc->timing->model_fn) (current_cpu, sc);
119 @cpu@_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
120 }
121 CGEN_TRACE_INSN_FINI (current_cpu, abuf, 1);
122 }
123#else
124 abort ();
125#endif /* WITH_SEM_SWITCH_FULL */
126 }
127
128 @cpu@_insn_after (current_cpu, vpc, sc->argbuf.idesc);
129
130 return vpc;
131}
132
133EOF
134
135;;
136
137xinit)
138
139# Nothing needed.
140
141;;
142
143xextract-simple | xextract-scache)
144
145cat <<EOF
146{
147 USI insn = GETIMEMUSI (current_cpu, pc);
148 extract (current_cpu, pc, insn, sc, FAST_P);
149 SEM_SKIP_COMPILE (current_cpu, sc, 1);
150}
151EOF
152
153;;
154
155xextract-pbb)
156
157# Inputs: current_cpu, pc, sc, max_insns, FAST_P
158# Outputs: sc, pc
159# sc must be left pointing past the last created entry.
160# pc must be left pointing past the last created entry.
161# If the pbb is terminated by a cti insn, SET_CTI_VPC(sc) must be called
162# to record the vpc of the cti insn.
163# SET_INSN_COUNT(n) must be called to record number of real insns.
164
165cat <<EOF
166{
167 const IDESC *idesc;
168 int icount = 0;
169
170 while (max_insns > 0) {
171
172 USI insn = GETIMEMUSI (current_cpu, pc);
173
174 idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
175
176 SEM_SKIP_COMPILE (current_cpu, sc, 1);
177
178 ++sc;
179 --max_insns;
180 ++icount;
181 pc += 4;
182
183 if (CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->idata)) & CGEN_ATTR_MASK (CGEN_INSN_FORCED_CTI))
184 {
185
186 SET_CTI_VPC (sc - 1);
187
188 break;
189
190 }
191 else if (CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->idata)) & CGEN_ATTR_MASK (CGEN_INSN_DELAYED_CTI))
192 {
193
194 /* handle delay slot */
195 SET_CTI_VPC (sc - 1);
196
197 insn = GETIMEMUSI (current_cpu, pc);
198
199 idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
200
201 ++sc;
202 --max_insns;
203 ++icount;
204 pc += 4;
205
206 break;
207 }
208 }
209
210 SET_INSN_COUNT (icount);
211
212}
213EOF
214
215;;
216
217xfull-exec-* | xfast-exec-*)
218
219# Inputs: current_cpu, vpc, FAST_P
220# Outputs: vpc
221# vpc is the virtual program counter.
222
223cat <<EOF
224#if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST)
225#define DEFINE_SWITCH
226#ifdef WANT_CPU_OR1K32BF
227#include "sem-switch.c"
228#endif
229#else
230 vpc = execute (current_cpu, vpc, FAST_P);
231#endif
232EOF
233
234;;
235
236*)
237 echo "Invalid argument to mainloop.in: $1" >&2
238 exit 1
239 ;;
240
241esac
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