[deliverable/binutils-gdb.git] / sim / or1k / or1k.c

/* OpenRISC simulator support code
   Copyright (C) 2017-2022 Free Software Foundation, Inc.

   This file is part of GDB, the GNU debugger.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

/* This must come before any other includes.  */
#include "defs.h"

#define WANT_CPU_OR1K32BF
#define WANT_CPU

#include "sim-main.h"
#include "symcat.h"
#include "cgen-ops.h"
#include "cgen-mem.h"
#include "cpuall.h"

#include <string.h>

int
or1k32bf_fetch_register (sim_cpu *current_cpu, int rn, unsigned char *buf,
			 int len)
{
  if (rn < 32)
    SETTWI (buf, GET_H_GPR (rn));
  else
    switch (rn)
      {
      case PPC_REGNUM:
	SETTWI (buf, GET_H_SYS_PPC ());
	break;
      case PC_REGNUM:
	SETTWI (buf, GET_H_PC ());
	break;
      case SR_REGNUM:
	SETTWI (buf, GET_H_SYS_SR ());
	break;
      default:
	return 0;
      }
  return sizeof (WI);		/* WI from arch.h */
}

int
or1k32bf_store_register (sim_cpu *current_cpu, int rn, unsigned char *buf,
			 int len)
{
  if (rn < 32)
    SET_H_GPR (rn, GETTWI (buf));
  else
    switch (rn)
      {
      case PPC_REGNUM:
	SET_H_SYS_PPC (GETTWI (buf));
	break;
      case PC_REGNUM:
	SET_H_PC (GETTWI (buf));
	break;
      case SR_REGNUM:
	SET_H_SYS_SR (GETTWI (buf));
	break;
      default:
	return 0;
      }
  return sizeof (WI);		/* WI from arch.h */
}

int
or1k32bf_model_or1200_u_exec (sim_cpu *current_cpu, const IDESC *idesc,
			      int unit_num, int referenced)
{
  return -1;
}

int
or1k32bf_model_or1200nd_u_exec (sim_cpu *current_cpu, const IDESC *idesc,
				int unit_num, int referenced)
{
  return -1;
}

void
or1k32bf_model_insn_before (sim_cpu *current_cpu, int first_p)
{
}

void
or1k32bf_model_insn_after (sim_cpu *current_cpu, int last_p, int cycles)
{
}

USI
or1k32bf_h_spr_get_raw (sim_cpu *current_cpu, USI addr)
{
  SIM_DESC sd = CPU_STATE (current_cpu);
  SIM_ASSERT (addr < NUM_SPR);
  return current_cpu->spr[addr];
}

void
or1k32bf_h_spr_set_raw (sim_cpu *current_cpu, USI addr, USI val)
{
  SIM_DESC sd = CPU_STATE (current_cpu);
  SIM_ASSERT (addr < NUM_SPR);
  current_cpu->spr[addr] = val;
}

USI
or1k32bf_h_spr_field_get_raw (sim_cpu *current_cpu, USI addr, int msb, int lsb)
{
  SIM_DESC sd = CPU_STATE (current_cpu);
  SIM_ASSERT (addr < NUM_SPR);
  return LSEXTRACTED (current_cpu->spr[addr], msb, lsb);
}

void
or1k32bf_h_spr_field_set_raw (sim_cpu *current_cpu, USI addr, int msb, int lsb,
			      USI val)
{
  current_cpu->spr[addr] &= ~LSMASK32 (msb, lsb);
  current_cpu->spr[addr] |= LSINSERTED (val, msb, lsb);
}

/* Initialize a sim cpu object.  */
void
or1k_cpu_init (SIM_DESC sd, sim_cpu *current_cpu, const USI or1k_vr,
	       const USI or1k_upr, const USI or1k_cpucfgr)
{
  /* Set the configuration registers passed from the user.  */
  SET_H_SYS_VR (or1k_vr);
  SET_H_SYS_UPR (or1k_upr);
  SET_H_SYS_CPUCFGR (or1k_cpucfgr);

#define CHECK_SPR_FIELD(GROUP, INDEX, FIELD, test) \
  do \
    { \
      USI field = GET_H_##SYS##_##INDEX##_##FIELD (); \
      if (!(test)) \
	sim_io_eprintf \
	  (sd, "WARNING: unsupported %s field in %s register: 0x%x\n", \
	   #FIELD, #INDEX, field); \
    } while (0)

  /* Set flags indicating if we are in a delay slot or not.  */
  current_cpu->next_delay_slot = 0;
  current_cpu->delay_slot = 0;

  /* Verify any user passed fields and warn on configurations we don't
     support.  */
  CHECK_SPR_FIELD (SYS, UPR, UP, field == 1);
  CHECK_SPR_FIELD (SYS, UPR, DCP, field == 0);
  CHECK_SPR_FIELD (SYS, UPR, ICP, field == 0);
  CHECK_SPR_FIELD (SYS, UPR, DMP, field == 0);
  CHECK_SPR_FIELD (SYS, UPR, MP, field == 0);
  CHECK_SPR_FIELD (SYS, UPR, IMP, field == 0);
  CHECK_SPR_FIELD (SYS, UPR, DUP, field == 0);
  CHECK_SPR_FIELD (SYS, UPR, PCUP, field == 0);
  CHECK_SPR_FIELD (SYS, UPR, PICP, field == 0);
  CHECK_SPR_FIELD (SYS, UPR, PMP, field == 0);
  CHECK_SPR_FIELD (SYS, UPR, TTP, field == 0);
  CHECK_SPR_FIELD (SYS, UPR, CUP, field == 0);

  CHECK_SPR_FIELD (SYS, CPUCFGR, NSGR, field == 0);
  CHECK_SPR_FIELD (SYS, CPUCFGR, CGF, field == 0);
  CHECK_SPR_FIELD (SYS, CPUCFGR, OB32S, field == 1);
  CHECK_SPR_FIELD (SYS, CPUCFGR, OF32S, field == 1);
  CHECK_SPR_FIELD (SYS, CPUCFGR, OB64S, field == 0);
  CHECK_SPR_FIELD (SYS, CPUCFGR, OF64S, field == 0);
  CHECK_SPR_FIELD (SYS, CPUCFGR, OV64S, field == 0);

#undef CHECK_SPR_FIELD

  /* Configure the fpu operations and mark fpu available.  */
  cgen_init_accurate_fpu (current_cpu, CGEN_CPU_FPU (current_cpu),
			  or1k32bf_fpu_error);
  SET_H_SYS_CPUCFGR_OF32S (1);

  /* Set the UPR[UP] flag, even if the user tried to unset it, as we always
     support the Unit Present Register.  */
  SET_H_SYS_UPR_UP (1);

  /* Set the supervisor register to indicate we are in supervisor mode and
     set the Fixed-One bit which must always be set.  */
  SET_H_SYS_SR (SPR_FIELD_MASK_SYS_SR_SM | SPR_FIELD_MASK_SYS_SR_FO);

  /* Clear the floating point control status register.  */
  SET_H_SYS_FPCSR (0);
}

void
or1k32bf_insn_before (sim_cpu *current_cpu, SEM_PC vpc, const IDESC *idesc)
{
  SIM_DESC sd = CPU_STATE (current_cpu);

  current_cpu->delay_slot = current_cpu->next_delay_slot;
  current_cpu->next_delay_slot = 0;

  if (current_cpu->delay_slot &&
      CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->idata)) &
      CGEN_ATTR_MASK (CGEN_INSN_NOT_IN_DELAY_SLOT))
    {
      USI pc;
#ifdef WITH_SCACHE
      pc = vpc->argbuf.addr;
#else
      pc = vpc;
#endif
      sim_io_error (sd, "invalid instruction in a delay slot at PC 0x%08x",
		    pc);
    }

}

void
or1k32bf_insn_after (sim_cpu *current_cpu, SEM_PC vpc, const IDESC *idesc)
{
  SIM_DESC sd = CPU_STATE (current_cpu);
  USI ppc;

#ifdef WITH_SCACHE
  ppc = vpc->argbuf.addr;
#else
  ppc = vpc;
#endif

  SET_H_SYS_PPC (ppc);

  if (!GET_H_SYS_CPUCFGR_ND () &&
      CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->idata)) &
      CGEN_ATTR_MASK (CGEN_INSN_DELAYED_CTI))
    {
      SIM_ASSERT (!current_cpu->delay_slot);
      current_cpu->next_delay_slot = 1;
    }
}

void
or1k32bf_nop (sim_cpu *current_cpu, USI uimm16)
{
  SIM_DESC sd = CPU_STATE (current_cpu);

  switch (uimm16)
    {

    case NOP_NOP:
      break;

    case NOP_EXIT:
      sim_io_printf (CPU_STATE (current_cpu), "exit(%d)\n", GET_H_GPR (3));
      /* fall through */
    case NOP_EXIT_SILENT:
      sim_engine_halt (sd, current_cpu, NULL, CPU_PC_GET (current_cpu),
		       sim_exited, GET_H_GPR (3));
      break;

    case NOP_REPORT:
      sim_io_printf (CPU_STATE (current_cpu), "report(0x%08x);\n",
		     GET_H_GPR (3));
      break;

    case NOP_PUTC:
      sim_io_printf (CPU_STATE (current_cpu), "%c",
		     (char) (GET_H_GPR (3) & 0xff));
      break;

    default:
      sim_io_eprintf (sd, "WARNING: l.nop with unsupported code 0x%08x\n",
		      uimm16);
      break;
    }

}

/* Build an address value used for load and store instructions.  For example,
   the instruction 'l.lws rD, I(rA)' will require to load data from the 4 byte
   address represented by rA + I.  Here the argument base is rA, offset is I
   and the size is the read size in bytes.  Note, OpenRISC requires that word
   and half-word access be word and half-word aligned respectively, the check
   for alignment is not needed here.  */

USI
or1k32bf_make_load_store_addr (sim_cpu *current_cpu, USI base, SI offset,
			       int size)
{
  SIM_DESC sd = CPU_STATE (current_cpu);

  USI addr = base + offset;

  /* If little endian load/store is enabled we adjust the byte and half-word
     addresses to the little endian equivalent.  */
  if (GET_H_SYS_SR_LEE ())
    {
      switch (size)
	{

	case 4: /* We are retrieving the entire word no adjustment.  */
	  break;

	case 2: /* Perform half-word adjustment 0 -> 2, 2 -> 0.  */
	  addr ^= 0x2;
	  break;

	case 1: /* Perform byte adjustment, 0 -> 3, 2 -> 3, etc.  */
	  addr ^= 0x3;
	  break;

	default:
	  SIM_ASSERT (0);
	  return 0;
	}
    }

  return addr;
}

/* The find first 1 instruction returns the location of the first set bit
   in the argument register.  */

USI
or1k32bf_ff1 (sim_cpu *current_cpu, USI val)
{
  USI bit;
  USI ret;
  for (bit = 1, ret = 1; bit; bit <<= 1, ret++)
    {
      if (val & bit)
	return ret;
    }
  return 0;
}

/* The find last 1 instruction returns the location of the last set bit in
   the argument register.  */

USI
or1k32bf_fl1 (sim_cpu *current_cpu, USI val)
{
  USI bit;
  USI ret;
  for (bit = 1 << 31, ret = 32; bit; bit >>= 1, ret--)
    {
      if (val & bit)
	return ret;
    }
  return 0;
}
Commit	Line	Data
fa8b7c21	1	/* OpenRISC simulator support code
88b9d363	2	Copyright (C) 2017-2022 Free Software Foundation, Inc.
fa8b7c21 SH	3
	4	This file is part of GDB, the GNU debugger.
	5
	6	This program is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
	8	the Free Software Foundation; either version 3 of the License, or
	9	(at your option) any later version.
	10
	11	This program is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
	17	along with this program. If not, see <http://www.gnu.org/licenses/>. */
	18
6df01ab8 MF	19	/* This must come before any other includes. */
	20	#include "defs.h"
	21
fa8b7c21 SH	22	#define WANT_CPU_OR1K32BF
	23	#define WANT_CPU
	24
	25	#include "sim-main.h"
	26	#include "symcat.h"
	27	#include "cgen-ops.h"
	28	#include "cgen-mem.h"
	29	#include "cpuall.h"
	30
	31	#include <string.h>
	32
	33	int
	34	or1k32bf_fetch_register (sim_cpu current_cpu, int rn, unsigned char buf,
	35	int len)
	36	{
	37	if (rn < 32)
	38	SETTWI (buf, GET_H_GPR (rn));
	39	else
	40	switch (rn)
	41	{
	42	case PPC_REGNUM:
	43	SETTWI (buf, GET_H_SYS_PPC ());
	44	break;
	45	case PC_REGNUM:
	46	SETTWI (buf, GET_H_PC ());
	47	break;
	48	case SR_REGNUM:
	49	SETTWI (buf, GET_H_SYS_SR ());
	50	break;
	51	default:
	52	return 0;
	53	}
	54	return sizeof (WI); /* WI from arch.h */
	55	}
	56
	57	int
	58	or1k32bf_store_register (sim_cpu current_cpu, int rn, unsigned char buf,
	59	int len)
	60	{
	61	if (rn < 32)
	62	SET_H_GPR (rn, GETTWI (buf));
	63	else
	64	switch (rn)
	65	{
	66	case PPC_REGNUM:
	67	SET_H_SYS_PPC (GETTWI (buf));
	68	break;
	69	case PC_REGNUM:
	70	SET_H_PC (GETTWI (buf));
	71	break;
	72	case SR_REGNUM:
	73	SET_H_SYS_SR (GETTWI (buf));
	74	break;
	75	default:
	76	return 0;
	77	}
	78	return sizeof (WI); /* WI from arch.h */
	79	}
	80
	81	int
	82	or1k32bf_model_or1200_u_exec (sim_cpu current_cpu, const IDESC idesc,
	83	int unit_num, int referenced)
	84	{
	85	return -1;
86	}
87
88	int
89	or1k32bf_model_or1200nd_u_exec (sim_cpu current_cpu, const IDESC idesc,
90	int unit_num, int referenced)
91	{
92	return -1;
93	}
94
95	void
96	or1k32bf_model_insn_before (sim_cpu *current_cpu, int first_p)
97	{
98	}
99
100	void
101	or1k32bf_model_insn_after (sim_cpu *current_cpu, int last_p, int cycles)
102	{
103	}
104
105	USI
106	or1k32bf_h_spr_get_raw (sim_cpu *current_cpu, USI addr)
107	{
108	SIM_DESC sd = CPU_STATE (current_cpu);
109	SIM_ASSERT (addr < NUM_SPR);
110	return current_cpu->spr[addr];
111	}
112
113	void
114	or1k32bf_h_spr_set_raw (sim_cpu *current_cpu, USI addr, USI val)
115	{
116	SIM_DESC sd = CPU_STATE (current_cpu);
117	SIM_ASSERT (addr < NUM_SPR);
118	current_cpu->spr[addr] = val;
119	}
120
121	USI
122	or1k32bf_h_spr_field_get_raw (sim_cpu *current_cpu, USI addr, int msb, int lsb)
123	{
124	SIM_DESC sd = CPU_STATE (current_cpu);
125	SIM_ASSERT (addr < NUM_SPR);
126	return LSEXTRACTED (current_cpu->spr[addr], msb, lsb);
127	}
128
129	void
130	or1k32bf_h_spr_field_set_raw (sim_cpu *current_cpu, USI addr, int msb, int lsb,
131	USI val)
132	{
133	current_cpu->spr[addr] &= ~LSMASK32 (msb, lsb);
134	current_cpu->spr[addr] \|= LSINSERTED (val, msb, lsb);
135	}
136
137	/* Initialize a sim cpu object. */
138	void
139	or1k_cpu_init (SIM_DESC sd, sim_cpu *current_cpu, const USI or1k_vr,
140	const USI or1k_upr, const USI or1k_cpucfgr)
141	{
142	/* Set the configuration registers passed from the user. */
143	SET_H_SYS_VR (or1k_vr);
144	SET_H_SYS_UPR (or1k_upr);
145	SET_H_SYS_CPUCFGR (or1k_cpucfgr);
146
147	#define CHECK_SPR_FIELD(GROUP, INDEX, FIELD, test) \
148	do \
149	{ \
150	USI field = GET_H_##SYS##_##INDEX##_##FIELD (); \
151	if (!(test)) \
152	sim_io_eprintf \
153	(sd, "WARNING: unsupported %s field in %s register: 0x%x\n", \
154	#FIELD, #INDEX, field); \
155	} while (0)
156
157	/* Set flags indicating if we are in a delay slot or not. */
158	current_cpu->next_delay_slot = 0;
159	current_cpu->delay_slot = 0;
160
161	/* Verify any user passed fields and warn on configurations we don't
162	support. */
163	CHECK_SPR_FIELD (SYS, UPR, UP, field == 1);
164	CHECK_SPR_FIELD (SYS, UPR, DCP, field == 0);
165	CHECK_SPR_FIELD (SYS, UPR, ICP, field == 0);
166	CHECK_SPR_FIELD (SYS, UPR, DMP, field == 0);
167	CHECK_SPR_FIELD (SYS, UPR, MP, field == 0);
168	CHECK_SPR_FIELD (SYS, UPR, IMP, field == 0);
169	CHECK_SPR_FIELD (SYS, UPR, DUP, field == 0);
170	CHECK_SPR_FIELD (SYS, UPR, PCUP, field == 0);
171	CHECK_SPR_FIELD (SYS, UPR, PICP, field == 0);
172	CHECK_SPR_FIELD (SYS, UPR, PMP, field == 0);
173	CHECK_SPR_FIELD (SYS, UPR, TTP, field == 0);
174	CHECK_SPR_FIELD (SYS, UPR, CUP, field == 0);
175
176	CHECK_SPR_FIELD (SYS, CPUCFGR, NSGR, field == 0);
177	CHECK_SPR_FIELD (SYS, CPUCFGR, CGF, field == 0);
178	CHECK_SPR_FIELD (SYS, CPUCFGR, OB32S, field == 1);
179	CHECK_SPR_FIELD (SYS, CPUCFGR, OF32S, field == 1);
180	CHECK_SPR_FIELD (SYS, CPUCFGR, OB64S, field == 0);
181	CHECK_SPR_FIELD (SYS, CPUCFGR, OF64S, field == 0);
182	CHECK_SPR_FIELD (SYS, CPUCFGR, OV64S, field == 0);
183
184	#undef CHECK_SPR_FIELD
185
186	/* Configure the fpu operations and mark fpu available. */
187	cgen_init_accurate_fpu (current_cpu, CGEN_CPU_FPU (current_cpu),
188	or1k32bf_fpu_error);
189	SET_H_SYS_CPUCFGR_OF32S (1);
190
191	/* Set the UPR[UP] flag, even if the user tried to unset it, as we always
192	support the Unit Present Register. */
193	SET_H_SYS_UPR_UP (1);
194
195	/* Set the supervisor register to indicate we are in supervisor mode and
196	set the Fixed-One bit which must always be set. */
197	SET_H_SYS_SR (SPR_FIELD_MASK_SYS_SR_SM \| SPR_FIELD_MASK_SYS_SR_FO);
198
199	/* Clear the floating point control status register. */
200	SET_H_SYS_FPCSR (0);
201	}
202
203	void
204	or1k32bf_insn_before (sim_cpu current_cpu, SEM_PC vpc, const IDESC idesc)
205	{
206	SIM_DESC sd = CPU_STATE (current_cpu);
207
208	current_cpu->delay_slot = current_cpu->next_delay_slot;
209	current_cpu->next_delay_slot = 0;
210
211	if (current_cpu->delay_slot &&
212	CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->idata)) &
213	CGEN_ATTR_MASK (CGEN_INSN_NOT_IN_DELAY_SLOT))
214	{
215	USI pc;
216	#ifdef WITH_SCACHE
217	pc = vpc->argbuf.addr;
218	#else
219	pc = vpc;
220	#endif
221	sim_io_error (sd, "invalid instruction in a delay slot at PC 0x%08x",
222	pc);
223	}
224
225	}
226
227	void
228	or1k32bf_insn_after (sim_cpu current_cpu, SEM_PC vpc, const IDESC idesc)
229	{
230	SIM_DESC sd = CPU_STATE (current_cpu);
231	USI ppc;
232
233	#ifdef WITH_SCACHE
234	ppc = vpc->argbuf.addr;
235	#else
236	ppc = vpc;
237	#endif
238
239	SET_H_SYS_PPC (ppc);
240
241	if (!GET_H_SYS_CPUCFGR_ND () &&
242	CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->idata)) &
243	CGEN_ATTR_MASK (CGEN_INSN_DELAYED_CTI))
244	{
245	SIM_ASSERT (!current_cpu->delay_slot);
246	current_cpu->next_delay_slot = 1;
247	}
248	}
249
250	void
251	or1k32bf_nop (sim_cpu *current_cpu, USI uimm16)
252	{
253	SIM_DESC sd = CPU_STATE (current_cpu);
254
255	switch (uimm16)
256	{
257
258	case NOP_NOP:
259	break;
260
261	case NOP_EXIT:
262	sim_io_printf (CPU_STATE (current_cpu), "exit(%d)\n", GET_H_GPR (3));
263	/* fall through */
264	case NOP_EXIT_SILENT:
265	sim_engine_halt (sd, current_cpu, NULL, CPU_PC_GET (current_cpu),
266	sim_exited, GET_H_GPR (3));
267	break;
268
269	case NOP_REPORT:
270	sim_io_printf (CPU_STATE (current_cpu), "report(0x%08x);\n",
271	GET_H_GPR (3));
272	break;
273
274	case NOP_PUTC:
275	sim_io_printf (CPU_STATE (current_cpu), "%c",
276	(char) (GET_H_GPR (3) & 0xff));
277	break;
278
279	default:
280	sim_io_eprintf (sd, "WARNING: l.nop with unsupported code 0x%08x\n",
281	uimm16);
282	break;
283	}
284
285	}
286
287	/* Build an address value used for load and store instructions. For example,
288	the instruction 'l.lws rD, I(rA)' will require to load data from the 4 byte
289	address represented by rA + I. Here the argument base is rA, offset is I
290	and the size is the read size in bytes. Note, OpenRISC requires that word
291	and half-word access be word and half-word aligned respectively, the check
292	for alignment is not needed here. */
293
294	USI
295	or1k32bf_make_load_store_addr (sim_cpu *current_cpu, USI base, SI offset,
296	int size)
297	{
298	SIM_DESC sd = CPU_STATE (current_cpu);
299
300	USI addr = base + offset;
301
302	/* If little endian load/store is enabled we adjust the byte and half-word
303	addresses to the little endian equivalent. */
304	if (GET_H_SYS_SR_LEE ())
305	{
306	switch (size)
307	{
308
309	case 4: /* We are retrieving the entire word no adjustment. */
310	break;
311
312	case 2: /* Perform half-word adjustment 0 -> 2, 2 -> 0. */
313	addr ^= 0x2;
314	break;
315
316	case 1: /* Perform byte adjustment, 0 -> 3, 2 -> 3, etc. */
317	addr ^= 0x3;
318	break;
319
320	default:
321	SIM_ASSERT (0);
322	return 0;
323	}
324	}
325
326	return addr;
327	}
328
329	/* The find first 1 instruction returns the location of the first set bit
330	in the argument register. */
331
332	USI
333	or1k32bf_ff1 (sim_cpu *current_cpu, USI val)
334	{
335	USI bit;
336	USI ret;
337	for (bit = 1, ret = 1; bit; bit <<= 1, ret++)
338	{
339	if (val & bit)
340	return ret;
341	}
342	return 0;
343	}
344
345	/* The find last 1 instruction returns the location of the last set bit in
346	the argument register. */
347
348	USI
349	or1k32bf_fl1 (sim_cpu *current_cpu, USI val)
350	{
351	USI bit;
352	USI ret;
353	for (bit = 1 << 31, ret = 32; bit; bit >>= 1, ret--)
354	{
355	if (val & bit)
356	return ret;
357	}
358	return 0;
359	}