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Merge remote-tracking branch 'battery/for-next'
[deliverable/linux.git] / sound / pci / hda / patch_ca0132.c
CommitLineData
95c6e9cb
IM		 1/*
2 * HD audio interface patch for Creative CA0132 chip
3 *
4 * Copyright (c) 2011, Creative Technology Ltd.
5 *
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
8 *
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/slab.h>
95c6e9cb 27#include <linux/mutex.h>
da155d5b 28#include <linux/module.h>
4aa3bb0c 29#include <linux/firmware.h>
95c6e9cb
IM		 30#include <sound/core.h>
31#include "hda_codec.h"
32#include "hda_local.h"
128bc4ba 33#include "hda_auto_parser.h"
5aaca44d 34#include "hda_jack.h"
95c6e9cb 35
bcd109c0
IM		 36#include "ca0132_regs.h"
37
ef6b2ead
IM		 38/* Enable this to see controls for tuning purpose. */
39/*#define ENABLE_TUNING_CONTROLS*/
40
41#define FLOAT_ZERO 0x00000000
42#define FLOAT_ONE 0x3f800000
43#define FLOAT_TWO 0x40000000
44#define FLOAT_MINUS_5 0xc0a00000
45
ef6b2ead
IM		 46#define UNSOL_TAG_DSP 0x16
47
4aa3bb0c
IM		 48#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
49#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
50
51#define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
52#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
53#define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
54
55#define MASTERCONTROL 0x80
ef6b2ead
IM		 56#define MASTERCONTROL_ALLOC_DMA_CHAN 10
57#define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
4aa3bb0c 58
95c6e9cb
IM		 59#define WIDGET_CHIP_CTRL 0x15
60#define WIDGET_DSP_CTRL 0x16
61
4aa3bb0c
IM		 62#define MEM_CONNID_MICIN1 3
63#define MEM_CONNID_MICIN2 5
64#define MEM_CONNID_MICOUT1 12
65#define MEM_CONNID_MICOUT2 14
66#define MEM_CONNID_WUH 10
67#define MEM_CONNID_DSP 16
68#define MEM_CONNID_DMIC 100
69
70#define SCP_SET 0
71#define SCP_GET 1
72
01ef7dbf
IM		 73#define EFX_FILE "ctefx.bin"
74
24f3cede 75#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf 76MODULE_FIRMWARE(EFX_FILE);
7a527ede 77#endif
01ef7dbf 78
ef6b2ead
IM		 79static char *dirstr[2] = { "Playback", "Capture" };
80
81enum {
82 SPEAKER_OUT,
83 HEADPHONE_OUT
84};
85
86enum {
87 DIGITAL_MIC,
88 LINE_MIC_IN
89};
90
91enum {
92#define VNODE_START_NID 0x80
93 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
94 VNID_MIC,
95 VNID_HP_SEL,
96 VNID_AMIC1_SEL,
97 VNID_HP_ASEL,
98 VNID_AMIC1_ASEL,
99 VNODE_END_NID,
100#define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
101
102#define EFFECT_START_NID 0x90
103#define OUT_EFFECT_START_NID EFFECT_START_NID
104 SURROUND = OUT_EFFECT_START_NID,
105 CRYSTALIZER,
106 DIALOG_PLUS,
107 SMART_VOLUME,
108 X_BASS,
109 EQUALIZER,
110 OUT_EFFECT_END_NID,
111#define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
112
113#define IN_EFFECT_START_NID OUT_EFFECT_END_NID
114 ECHO_CANCELLATION = IN_EFFECT_START_NID,
115 VOICE_FOCUS,
116 MIC_SVM,
117 NOISE_REDUCTION,
118 IN_EFFECT_END_NID,
119#define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
120
121 VOICEFX = IN_EFFECT_END_NID,
122 PLAY_ENHANCEMENT,
123 CRYSTAL_VOICE,
124 EFFECT_END_NID
125#define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
126};
127
128/* Effects values size*/
129#define EFFECT_VALS_MAX_COUNT 12
130
e8412ca4
DR		 131/* Latency introduced by DSP blocks in milliseconds. */
132#define DSP_CAPTURE_INIT_LATENCY 0
133#define DSP_CRYSTAL_VOICE_LATENCY 124
134#define DSP_PLAYBACK_INIT_LATENCY 13
135#define DSP_PLAY_ENHANCEMENT_LATENCY 30
136#define DSP_SPEAKER_OUT_LATENCY 7
137
ef6b2ead 138struct ct_effect {
975cc02a 139 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 140 hda_nid_t nid;
141 int mid; /*effect module ID*/
142 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
143 int direct; /* 0:output; 1:input*/
144 int params; /* number of default non-on/off params */
145 /*effect default values, 1st is on/off. */
146 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
147};
148
149#define EFX_DIR_OUT 0
150#define EFX_DIR_IN 1
151
152static struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
153 { .name = "Surround",
154 .nid = SURROUND,
155 .mid = 0x96,
156 .reqs = {0, 1},
157 .direct = EFX_DIR_OUT,
158 .params = 1,
159 .def_vals = {0x3F800000, 0x3F2B851F}
160 },
161 { .name = "Crystalizer",
162 .nid = CRYSTALIZER,
163 .mid = 0x96,
164 .reqs = {7, 8},
165 .direct = EFX_DIR_OUT,
166 .params = 1,
167 .def_vals = {0x3F800000, 0x3F266666}
168 },
169 { .name = "Dialog Plus",
170 .nid = DIALOG_PLUS,
171 .mid = 0x96,
172 .reqs = {2, 3},
173 .direct = EFX_DIR_OUT,
174 .params = 1,
175 .def_vals = {0x00000000, 0x3F000000}
176 },
177 { .name = "Smart Volume",
178 .nid = SMART_VOLUME,
179 .mid = 0x96,
180 .reqs = {4, 5, 6},
181 .direct = EFX_DIR_OUT,
182 .params = 2,
183 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
184 },
185 { .name = "X-Bass",
186 .nid = X_BASS,
187 .mid = 0x96,
188 .reqs = {24, 23, 25},
189 .direct = EFX_DIR_OUT,
190 .params = 2,
191 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
192 },
193 { .name = "Equalizer",
194 .nid = EQUALIZER,
195 .mid = 0x96,
196 .reqs = {9, 10, 11, 12, 13, 14,
197 15, 16, 17, 18, 19, 20},
198 .direct = EFX_DIR_OUT,
199 .params = 11,
200 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
201 0x00000000, 0x00000000, 0x00000000, 0x00000000,
202 0x00000000, 0x00000000, 0x00000000, 0x00000000}
203 },
204 { .name = "Echo Cancellation",
205 .nid = ECHO_CANCELLATION,
206 .mid = 0x95,
207 .reqs = {0, 1, 2, 3},
208 .direct = EFX_DIR_IN,
209 .params = 3,
210 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
211 },
212 { .name = "Voice Focus",
213 .nid = VOICE_FOCUS,
214 .mid = 0x95,
215 .reqs = {6, 7, 8, 9},
216 .direct = EFX_DIR_IN,
217 .params = 3,
218 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
219 },
220 { .name = "Mic SVM",
221 .nid = MIC_SVM,
222 .mid = 0x95,
223 .reqs = {44, 45},
224 .direct = EFX_DIR_IN,
225 .params = 1,
226 .def_vals = {0x00000000, 0x3F3D70A4}
227 },
228 { .name = "Noise Reduction",
229 .nid = NOISE_REDUCTION,
230 .mid = 0x95,
231 .reqs = {4, 5},
232 .direct = EFX_DIR_IN,
233 .params = 1,
234 .def_vals = {0x3F800000, 0x3F000000}
235 },
236 { .name = "VoiceFX",
237 .nid = VOICEFX,
238 .mid = 0x95,
239 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
240 .direct = EFX_DIR_IN,
241 .params = 8,
242 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
243 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
244 0x00000000}
245 }
246};
247
248/* Tuning controls */
249#ifdef ENABLE_TUNING_CONTROLS
250
251enum {
252#define TUNING_CTL_START_NID 0xC0
253 WEDGE_ANGLE = TUNING_CTL_START_NID,
254 SVM_LEVEL,
255 EQUALIZER_BAND_0,
256 EQUALIZER_BAND_1,
257 EQUALIZER_BAND_2,
258 EQUALIZER_BAND_3,
259 EQUALIZER_BAND_4,
260 EQUALIZER_BAND_5,
261 EQUALIZER_BAND_6,
262 EQUALIZER_BAND_7,
263 EQUALIZER_BAND_8,
264 EQUALIZER_BAND_9,
265 TUNING_CTL_END_NID
266#define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
267};
268
269struct ct_tuning_ctl {
975cc02a 270 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 271 hda_nid_t parent_nid;
272 hda_nid_t nid;
273 int mid; /*effect module ID*/
274 int req; /*effect module request*/
275 int direct; /* 0:output; 1:input*/
276 unsigned int def_val;/*effect default values*/
277};
278
279static struct ct_tuning_ctl ca0132_tuning_ctls[] = {
280 { .name = "Wedge Angle",
281 .parent_nid = VOICE_FOCUS,
282 .nid = WEDGE_ANGLE,
283 .mid = 0x95,
284 .req = 8,
285 .direct = EFX_DIR_IN,
286 .def_val = 0x41F00000
287 },
288 { .name = "SVM Level",
289 .parent_nid = MIC_SVM,
290 .nid = SVM_LEVEL,
291 .mid = 0x95,
292 .req = 45,
293 .direct = EFX_DIR_IN,
294 .def_val = 0x3F3D70A4
295 },
296 { .name = "EQ Band0",
297 .parent_nid = EQUALIZER,
298 .nid = EQUALIZER_BAND_0,
299 .mid = 0x96,
300 .req = 11,
301 .direct = EFX_DIR_OUT,
302 .def_val = 0x00000000
303 },
304 { .name = "EQ Band1",
305 .parent_nid = EQUALIZER,
306 .nid = EQUALIZER_BAND_1,
307 .mid = 0x96,
308 .req = 12,
309 .direct = EFX_DIR_OUT,
310 .def_val = 0x00000000
311 },
312 { .name = "EQ Band2",
313 .parent_nid = EQUALIZER,
314 .nid = EQUALIZER_BAND_2,
315 .mid = 0x96,
316 .req = 13,
317 .direct = EFX_DIR_OUT,
318 .def_val = 0x00000000
319 },
320 { .name = "EQ Band3",
321 .parent_nid = EQUALIZER,
322 .nid = EQUALIZER_BAND_3,
323 .mid = 0x96,
324 .req = 14,
325 .direct = EFX_DIR_OUT,
326 .def_val = 0x00000000
327 },
328 { .name = "EQ Band4",
329 .parent_nid = EQUALIZER,
330 .nid = EQUALIZER_BAND_4,
331 .mid = 0x96,
332 .req = 15,
333 .direct = EFX_DIR_OUT,
334 .def_val = 0x00000000
335 },
336 { .name = "EQ Band5",
337 .parent_nid = EQUALIZER,
338 .nid = EQUALIZER_BAND_5,
339 .mid = 0x96,
340 .req = 16,
341 .direct = EFX_DIR_OUT,
342 .def_val = 0x00000000
343 },
344 { .name = "EQ Band6",
345 .parent_nid = EQUALIZER,
346 .nid = EQUALIZER_BAND_6,
347 .mid = 0x96,
348 .req = 17,
349 .direct = EFX_DIR_OUT,
350 .def_val = 0x00000000
351 },
352 { .name = "EQ Band7",
353 .parent_nid = EQUALIZER,
354 .nid = EQUALIZER_BAND_7,
355 .mid = 0x96,
356 .req = 18,
357 .direct = EFX_DIR_OUT,
358 .def_val = 0x00000000
359 },
360 { .name = "EQ Band8",
361 .parent_nid = EQUALIZER,
362 .nid = EQUALIZER_BAND_8,
363 .mid = 0x96,
364 .req = 19,
365 .direct = EFX_DIR_OUT,
366 .def_val = 0x00000000
367 },
368 { .name = "EQ Band9",
369 .parent_nid = EQUALIZER,
370 .nid = EQUALIZER_BAND_9,
371 .mid = 0x96,
372 .req = 20,
373 .direct = EFX_DIR_OUT,
374 .def_val = 0x00000000
375 }
376};
377#endif
378
379/* Voice FX Presets */
380#define VOICEFX_MAX_PARAM_COUNT 9
381
382struct ct_voicefx {
383 char *name;
384 hda_nid_t nid;
385 int mid;
386 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
387};
388
389struct ct_voicefx_preset {
390 char *name; /*preset name*/
391 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
392};
393
ccd7bd3d 394static struct ct_voicefx ca0132_voicefx = {
ef6b2ead
IM		 395 .name = "VoiceFX Capture Switch",
396 .nid = VOICEFX,
397 .mid = 0x95,
398 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
399};
400
ccd7bd3d 401static struct ct_voicefx_preset ca0132_voicefx_presets[] = {
ef6b2ead
IM		 402 { .name = "Neutral",
403 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
404 0x44FA0000, 0x3F800000, 0x3F800000,
405 0x3F800000, 0x00000000, 0x00000000 }
406 },
407 { .name = "Female2Male",
408 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
409 0x44FA0000, 0x3F19999A, 0x3F866666,
410 0x3F800000, 0x00000000, 0x00000000 }
411 },
412 { .name = "Male2Female",
413 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
414 0x450AC000, 0x4017AE14, 0x3F6B851F,
415 0x3F800000, 0x00000000, 0x00000000 }
416 },
417 { .name = "ScrappyKid",
418 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
419 0x44FA0000, 0x40400000, 0x3F28F5C3,
420 0x3F800000, 0x00000000, 0x00000000 }
421 },
422 { .name = "Elderly",
423 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
424 0x44E10000, 0x3FB33333, 0x3FB9999A,
425 0x3F800000, 0x3E3A2E43, 0x00000000 }
426 },
427 { .name = "Orc",
428 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
429 0x45098000, 0x3F266666, 0x3FC00000,
430 0x3F800000, 0x00000000, 0x00000000 }
431 },
432 { .name = "Elf",
433 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
434 0x45193000, 0x3F8E147B, 0x3F75C28F,
435 0x3F800000, 0x00000000, 0x00000000 }
436 },
437 { .name = "Dwarf",
438 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
439 0x45007000, 0x3F451EB8, 0x3F7851EC,
440 0x3F800000, 0x00000000, 0x00000000 }
441 },
442 { .name = "AlienBrute",
443 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
444 0x451F6000, 0x3F266666, 0x3FA7D945,
445 0x3F800000, 0x3CF5C28F, 0x00000000 }
446 },
447 { .name = "Robot",
448 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
449 0x44FA0000, 0x3FB2718B, 0x3F800000,
450 0xBC07010E, 0x00000000, 0x00000000 }
451 },
452 { .name = "Marine",
453 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
454 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
455 0x3F0A3D71, 0x00000000, 0x00000000 }
456 },
457 { .name = "Emo",
458 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
459 0x44FA0000, 0x3F800000, 0x3F800000,
460 0x3E4CCCCD, 0x00000000, 0x00000000 }
461 },
462 { .name = "DeepVoice",
463 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
464 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
465 0x3F800000, 0x00000000, 0x00000000 }
466 },
467 { .name = "Munchkin",
468 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
469 0x44FA0000, 0x3F800000, 0x3F1A043C,
470 0x3F800000, 0x00000000, 0x00000000 }
471 }
472};
473
95c6e9cb
IM		 474enum hda_cmd_vendor_io {
475 /* for DspIO node */
476 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
477 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
478
479 VENDOR_DSPIO_STATUS = 0xF01,
480 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
481 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
482 VENDOR_DSPIO_DSP_INIT = 0x703,
483 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
484 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
485
486 /* for ChipIO node */
487 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
488 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
489 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
490 VENDOR_CHIPIO_DATA_LOW = 0x300,
491 VENDOR_CHIPIO_DATA_HIGH = 0x400,
492
493 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
494 VENDOR_CHIPIO_STATUS = 0xF01,
495 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
496 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
497
4aa3bb0c
IM		 498 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
499 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
500
95c6e9cb 501 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
4aa3bb0c 502 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
95c6e9cb
IM		 503
504 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
505 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
506 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
507 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
508 VENDOR_CHIPIO_FLAG_SET = 0x70F,
509 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
4aa3bb0c
IM		 510 VENDOR_CHIPIO_PARAM_SET = 0x710,
511 VENDOR_CHIPIO_PARAM_GET = 0xF10,
95c6e9cb
IM		 512
513 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
514 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
515 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
516 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
517
4aa3bb0c
IM		 518 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
519 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
520 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
521 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
522
523 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
524 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
525 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
526 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
527 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
528 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
529
530 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
95c6e9cb
IM		 531};
532
533/*
534 * Control flag IDs
535 */
536enum control_flag_id {
537 /* Connection manager stream setup is bypassed/enabled */
538 CONTROL_FLAG_C_MGR = 0,
539 /* DSP DMA is bypassed/enabled */
540 CONTROL_FLAG_DMA = 1,
541 /* 8051 'idle' mode is disabled/enabled */
542 CONTROL_FLAG_IDLE_ENABLE = 2,
543 /* Tracker for the SPDIF-in path is bypassed/enabled */
544 CONTROL_FLAG_TRACKER = 3,
545 /* DigitalOut to Spdif2Out connection is disabled/enabled */
546 CONTROL_FLAG_SPDIF2OUT = 4,
547 /* Digital Microphone is disabled/enabled */
548 CONTROL_FLAG_DMIC = 5,
549 /* ADC_B rate is 48 kHz/96 kHz */
550 CONTROL_FLAG_ADC_B_96KHZ = 6,
551 /* ADC_C rate is 48 kHz/96 kHz */
552 CONTROL_FLAG_ADC_C_96KHZ = 7,
553 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
554 CONTROL_FLAG_DAC_96KHZ = 8,
555 /* DSP rate is 48 kHz/96 kHz */
556 CONTROL_FLAG_DSP_96KHZ = 9,
557 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
558 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
559 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
560 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
561 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
562 CONTROL_FLAG_DECODE_LOOP = 12,
563 /* De-emphasis filter on DAC-1 disabled/enabled */
564 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
565 /* De-emphasis filter on DAC-2 disabled/enabled */
566 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
567 /* De-emphasis filter on DAC-3 disabled/enabled */
568 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
569 /* High-pass filter on ADC_B disabled/enabled */
570 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
571 /* High-pass filter on ADC_C disabled/enabled */
572 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
573 /* Common mode on Port_A disabled/enabled */
574 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
575 /* Common mode on Port_D disabled/enabled */
576 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
577 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
578 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
579 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
4aa3bb0c 580 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
95c6e9cb
IM		 581 /* ASI rate is 48kHz/96kHz */
582 CONTROL_FLAG_ASI_96KHZ = 22,
583 /* DAC power settings able to control attached ports no/yes */
584 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
585 /* Clock Stop OK reporting is disabled/enabled */
586 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
587 /* Number of control flags */
588 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
589};
590
591/*
592 * Control parameter IDs
593 */
4aa3bb0c 594enum control_param_id {
ef6b2ead
IM		 595 /* 0: None, 1: Mic1In*/
596 CONTROL_PARAM_VIP_SOURCE = 1,
95c6e9cb
IM		 597 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
598 CONTROL_PARAM_SPDIF1_SOURCE = 2,
ef6b2ead
IM		 599 /* Port A output stage gain setting to use when 16 Ohm output
600 * impedance is selected*/
601 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
602 /* Port D output stage gain setting to use when 16 Ohm output
603 * impedance is selected*/
604 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
95c6e9cb
IM		 605
606 /* Stream Control */
607
608 /* Select stream with the given ID */
609 CONTROL_PARAM_STREAM_ID = 24,
610 /* Source connection point for the selected stream */
611 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
612 /* Destination connection point for the selected stream */
613 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
614 /* Number of audio channels in the selected stream */
615 CONTROL_PARAM_STREAMS_CHANNELS = 27,
616 /*Enable control for the selected stream */
617 CONTROL_PARAM_STREAM_CONTROL = 28,
618
619 /* Connection Point Control */
620
621 /* Select connection point with the given ID */
622 CONTROL_PARAM_CONN_POINT_ID = 29,
623 /* Connection point sample rate */
624 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
625
626 /* Node Control */
627
628 /* Select HDA node with the given ID */
629 CONTROL_PARAM_NODE_ID = 31
630};
631
632/*
633 * Dsp Io Status codes
634 */
635enum hda_vendor_status_dspio {
636 /* Success */
637 VENDOR_STATUS_DSPIO_OK = 0x00,
638 /* Busy, unable to accept new command, the host must retry */
639 VENDOR_STATUS_DSPIO_BUSY = 0x01,
640 /* SCP command queue is full */
641 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
642 /* SCP response queue is empty */
643 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
644};
645
646/*
647 * Chip Io Status codes
648 */
649enum hda_vendor_status_chipio {
650 /* Success */
651 VENDOR_STATUS_CHIPIO_OK = 0x00,
652 /* Busy, unable to accept new command, the host must retry */
653 VENDOR_STATUS_CHIPIO_BUSY = 0x01
654};
655
656/*
657 * CA0132 sample rate
658 */
659enum ca0132_sample_rate {
660 SR_6_000 = 0x00,
661 SR_8_000 = 0x01,
662 SR_9_600 = 0x02,
663 SR_11_025 = 0x03,
664 SR_16_000 = 0x04,
665 SR_22_050 = 0x05,
666 SR_24_000 = 0x06,
667 SR_32_000 = 0x07,
668 SR_44_100 = 0x08,
669 SR_48_000 = 0x09,
670 SR_88_200 = 0x0A,
671 SR_96_000 = 0x0B,
672 SR_144_000 = 0x0C,
673 SR_176_400 = 0x0D,
674 SR_192_000 = 0x0E,
675 SR_384_000 = 0x0F,
676
677 SR_COUNT = 0x10,
678
679 SR_RATE_UNKNOWN = 0x1F
680};
681
01ef7dbf
IM		 682enum dsp_download_state {
683 DSP_DOWNLOAD_FAILED = -1,
684 DSP_DOWNLOAD_INIT = 0,
685 DSP_DOWNLOADING = 1,
686 DSP_DOWNLOADED = 2
687};
688
01ef7dbf
IM		 689/* retrieve parameters from hda format */
690#define get_hdafmt_chs(fmt) (fmt & 0xf)
691#define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
692#define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
693#define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
694
695/*
696 * CA0132 specific
697 */
698
699struct ca0132_spec {
a7e76271
IM		 700 struct snd_kcontrol_new *mixers[5];
701 unsigned int num_mixers;
5aaca44d
IM		 702 const struct hda_verb *base_init_verbs;
703 const struct hda_verb *base_exit_verbs;
d5c016b5
GM		 704 const struct hda_verb *chip_init_verbs;
705 struct hda_verb *spec_init_verbs;
01ef7dbf 706 struct auto_pin_cfg autocfg;
5aaca44d
IM		 707
708 /* Nodes configurations */
01ef7dbf
IM		 709 struct hda_multi_out multiout;
710 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
711 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
5aaca44d 712 unsigned int num_outputs;
01ef7dbf
IM		 713 hda_nid_t input_pins[AUTO_PIN_LAST];
714 hda_nid_t adcs[AUTO_PIN_LAST];
715 hda_nid_t dig_out;
716 hda_nid_t dig_in;
717 unsigned int num_inputs;
a7e76271
IM		 718 hda_nid_t shared_mic_nid;
719 hda_nid_t shared_out_nid;
d5c016b5
GM		 720 hda_nid_t unsol_tag_hp;
721 hda_nid_t unsol_tag_amic1;
01ef7dbf
IM		 722
723 /* chip access */
724 struct mutex chipio_mutex; /* chip access mutex */
725 u32 curr_chip_addx;
726
727 /* DSP download related */
728 enum dsp_download_state dsp_state;
729 unsigned int dsp_stream_id;
730 unsigned int wait_scp;
731 unsigned int wait_scp_header;
732 unsigned int wait_num_data;
733 unsigned int scp_resp_header;
734 unsigned int scp_resp_data[4];
735 unsigned int scp_resp_count;
5aaca44d
IM		 736
737 /* mixer and effects related */
738 unsigned char dmic_ctl;
739 int cur_out_type;
740 int cur_mic_type;
741 long vnode_lvol[VNODES_COUNT];
742 long vnode_rvol[VNODES_COUNT];
743 long vnode_lswitch[VNODES_COUNT];
744 long vnode_rswitch[VNODES_COUNT];
745 long effects_switch[EFFECTS_COUNT];
746 long voicefx_val;
747 long cur_mic_boost;
44f0c978 748
993884f6
CCC		 749 struct hda_codec *codec;
750 struct delayed_work unsol_hp_work;
d5c016b5 751 int quirk;
993884f6 752
44f0c978
IM		 753#ifdef ENABLE_TUNING_CONTROLS
754 long cur_ctl_vals[TUNING_CTLS_COUNT];
755#endif
01ef7dbf
IM		 756};
757
d5c016b5
GM		 758/*
759 * CA0132 quirks table
760 */
761enum {
762 QUIRK_NONE,
763 QUIRK_ALIENWARE,
764};
765
fe14f39e
TI		 766static const struct hda_pintbl alienware_pincfgs[] = {
767 { 0x0b, 0x90170110 }, /* Builtin Speaker */
768 { 0x0c, 0x411111f0 }, /* N/A */
769 { 0x0d, 0x411111f0 }, /* N/A */
770 { 0x0e, 0x411111f0 }, /* N/A */
771 { 0x0f, 0x0321101f }, /* HP */
772 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
773 { 0x11, 0x03a11021 }, /* Mic */
774 { 0x12, 0xd5a30140 }, /* Builtin Mic */
775 { 0x13, 0x411111f0 }, /* N/A */
776 { 0x18, 0x411111f0 }, /* N/A */
777 {}
778};
779
d5c016b5 780static const struct snd_pci_quirk ca0132_quirks[] = {
5328e1ea
GM		 781 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
782 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
d5c016b5
GM		 783 {}
784};
785
01ef7dbf
IM		 786/*
787 * CA0132 codec access
788 */
399ae725 789static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
01ef7dbf
IM		 790 unsigned int verb, unsigned int parm, unsigned int *res)
791{
792 unsigned int response;
793 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
794 *res = response;
795
796 return ((response == -1) ? -1 : 0);
797}
798
799static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
800 unsigned short converter_format, unsigned int *res)
801{
802 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
803 converter_format & 0xffff, res);
804}
805
806static int codec_set_converter_stream_channel(struct hda_codec *codec,
807 hda_nid_t nid, unsigned char stream,
808 unsigned char channel, unsigned int *res)
809{
810 unsigned char converter_stream_channel = 0;
811
812 converter_stream_channel = (stream << 4) | (channel & 0x0f);
813 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
814 converter_stream_channel, res);
815}
816
817/* Chip access helper function */
818static int chipio_send(struct hda_codec *codec,
819 unsigned int reg,
820 unsigned int data)
821{
822 unsigned int res;
6d67530e 823 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 824
825 /* send bits of data specified by reg */
826 do {
827 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
828 reg, data);
829 if (res == VENDOR_STATUS_CHIPIO_OK)
830 return 0;
6d67530e
IM		 831 msleep(20);
832 } while (time_before(jiffies, timeout));
833
01ef7dbf
IM		 834 return -EIO;
835}
836
837/*
838 * Write chip address through the vendor widget -- NOT protected by the Mutex!
839 */
840static int chipio_write_address(struct hda_codec *codec,
841 unsigned int chip_addx)
842{
4861af80 843 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 844 int res;
845
4861af80
IM		 846 if (spec->curr_chip_addx == chip_addx)
847 return 0;
848
01ef7dbf
IM		 849 /* send low 16 bits of the address */
850 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
851 chip_addx & 0xffff);
852
853 if (res != -EIO) {
854 /* send high 16 bits of the address */
855 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
856 chip_addx >> 16);
857 }
858
4861af80 859 spec->curr_chip_addx = (res < 0) ? ~0UL : chip_addx;
01ef7dbf 860
4861af80 861 return res;
01ef7dbf
IM		 862}
863
864/*
865 * Write data through the vendor widget -- NOT protected by the Mutex!
866 */
01ef7dbf
IM		 867static int chipio_write_data(struct hda_codec *codec, unsigned int data)
868{
5aaca44d 869 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 870 int res;
871
872 /* send low 16 bits of the data */
873 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
874
875 if (res != -EIO) {
876 /* send high 16 bits of the data */
877 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
878 data >> 16);
879 }
880
5aaca44d
IM		 881 /*If no error encountered, automatically increment the address
882 as per chip behaviour*/
883 spec->curr_chip_addx = (res != -EIO) ?
884 (spec->curr_chip_addx + 4) : ~0UL;
01ef7dbf
IM		 885 return res;
886}
887
d5c21b88
IM		 888/*
889 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
890 */
01ef7dbf
IM		 891static int chipio_write_data_multiple(struct hda_codec *codec,
892 const u32 *data,
893 unsigned int count)
894{
895 int status = 0;
896
897 if (data == NULL) {
4e76a883 898 codec_dbg(codec, "chipio_write_data null ptr\n");
01ef7dbf
IM		 899 return -EINVAL;
900 }
901
902 while ((count-- != 0) && (status == 0))
903 status = chipio_write_data(codec, *data++);
904
905 return status;
906}
907
908
909/*
910 * Read data through the vendor widget -- NOT protected by the Mutex!
911 */
912static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
913{
5aaca44d 914 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 915 int res;
916
917 /* post read */
918 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
919
920 if (res != -EIO) {
921 /* read status */
922 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
923 }
924
925 if (res != -EIO) {
926 /* read data */
927 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
928 VENDOR_CHIPIO_HIC_READ_DATA,
929 0);
930 }
931
5aaca44d
IM		 932 /*If no error encountered, automatically increment the address
933 as per chip behaviour*/
934 spec->curr_chip_addx = (res != -EIO) ?
935 (spec->curr_chip_addx + 4) : ~0UL;
01ef7dbf
IM		 936 return res;
937}
938
939/*
940 * Write given value to the given address through the chip I/O widget.
941 * protected by the Mutex
942 */
943static int chipio_write(struct hda_codec *codec,
944 unsigned int chip_addx, const unsigned int data)
945{
946 struct ca0132_spec *spec = codec->spec;
947 int err;
948
949 mutex_lock(&spec->chipio_mutex);
950
951 /* write the address, and if successful proceed to write data */
952 err = chipio_write_address(codec, chip_addx);
953 if (err < 0)
954 goto exit;
955
956 err = chipio_write_data(codec, data);
957 if (err < 0)
958 goto exit;
959
960exit:
961 mutex_unlock(&spec->chipio_mutex);
962 return err;
963}
964
d5c21b88
IM		 965/*
966 * Write multiple values to the given address through the chip I/O widget.
967 * protected by the Mutex
968 */
01ef7dbf
IM		 969static int chipio_write_multiple(struct hda_codec *codec,
970 u32 chip_addx,
971 const u32 *data,
972 unsigned int count)
973{
974 struct ca0132_spec *spec = codec->spec;
975 int status;
976
977 mutex_lock(&spec->chipio_mutex);
4861af80 978 status = chipio_write_address(codec, chip_addx);
01ef7dbf
IM		 979 if (status < 0)
980 goto error;
981
982 status = chipio_write_data_multiple(codec, data, count);
983error:
984 mutex_unlock(&spec->chipio_mutex);
985
986 return status;
987}
988
989/*
990 * Read the given address through the chip I/O widget
991 * protected by the Mutex
992 */
993static int chipio_read(struct hda_codec *codec,
994 unsigned int chip_addx, unsigned int *data)
995{
996 struct ca0132_spec *spec = codec->spec;
997 int err;
998
999 mutex_lock(&spec->chipio_mutex);
1000
1001 /* write the address, and if successful proceed to write data */
1002 err = chipio_write_address(codec, chip_addx);
1003 if (err < 0)
1004 goto exit;
1005
1006 err = chipio_read_data(codec, data);
1007 if (err < 0)
1008 goto exit;
1009
1010exit:
1011 mutex_unlock(&spec->chipio_mutex);
1012 return err;
1013}
1014
d5c21b88
IM		 1015/*
1016 * Set chip control flags through the chip I/O widget.
1017 */
01ef7dbf
IM		 1018static void chipio_set_control_flag(struct hda_codec *codec,
1019 enum control_flag_id flag_id,
1020 bool flag_state)
1021{
1022 unsigned int val;
1023 unsigned int flag_bit;
1024
1025 flag_bit = (flag_state ? 1 : 0);
1026 val = (flag_bit << 7) | (flag_id);
1027 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1028 VENDOR_CHIPIO_FLAG_SET, val);
1029}
1030
d5c21b88
IM		 1031/*
1032 * Set chip parameters through the chip I/O widget.
1033 */
01ef7dbf
IM		 1034static void chipio_set_control_param(struct hda_codec *codec,
1035 enum control_param_id param_id, int param_val)
1036{
1037 struct ca0132_spec *spec = codec->spec;
1038 int val;
1039
1040 if ((param_id < 32) && (param_val < 8)) {
1041 val = (param_val << 5) | (param_id);
1042 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1043 VENDOR_CHIPIO_PARAM_SET, val);
1044 } else {
1045 mutex_lock(&spec->chipio_mutex);
1046 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1047 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1048 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1049 param_id);
1050 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1051 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1052 param_val);
1053 }
1054 mutex_unlock(&spec->chipio_mutex);
1055 }
1056}
1057
d5c21b88
IM		 1058/*
1059 * Set sampling rate of the connection point.
1060 */
01ef7dbf
IM		 1061static void chipio_set_conn_rate(struct hda_codec *codec,
1062 int connid, enum ca0132_sample_rate rate)
1063{
1064 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1065 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1066 rate);
1067}
1068
d5c21b88
IM		 1069/*
1070 * Enable clocks.
1071 */
01ef7dbf
IM		 1072static void chipio_enable_clocks(struct hda_codec *codec)
1073{
1074 struct ca0132_spec *spec = codec->spec;
1075
1076 mutex_lock(&spec->chipio_mutex);
1077 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1078 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1079 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1080 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1081 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1082 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1083 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1084 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1085 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1086 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1087 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1088 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1089 mutex_unlock(&spec->chipio_mutex);
1090}
1091
1092/*
1093 * CA0132 DSP IO stuffs
1094 */
1095static int dspio_send(struct hda_codec *codec, unsigned int reg,
1096 unsigned int data)
1097{
b645d796 1098 int res;
6d67530e 1099 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 1100
1101 /* send bits of data specified by reg to dsp */
1102 do {
1103 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1104 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1105 return res;
6d67530e
IM		 1106 msleep(20);
1107 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1108
1109 return -EIO;
1110}
1111
d5c21b88
IM		 1112/*
1113 * Wait for DSP to be ready for commands
1114 */
01ef7dbf
IM		 1115static void dspio_write_wait(struct hda_codec *codec)
1116{
4861af80
IM		 1117 int status;
1118 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1119
01ef7dbf 1120 do {
4861af80
IM		 1121 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1122 VENDOR_DSPIO_STATUS, 0);
1123 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1124 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1125 break;
1126 msleep(1);
1127 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1128}
1129
d5c21b88
IM		 1130/*
1131 * Write SCP data to DSP
1132 */
01ef7dbf
IM		 1133static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1134{
1135 struct ca0132_spec *spec = codec->spec;
1136 int status;
1137
1138 dspio_write_wait(codec);
1139
1140 mutex_lock(&spec->chipio_mutex);
1141 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1142 scp_data & 0xffff);
1143 if (status < 0)
1144 goto error;
1145
1146 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1147 scp_data >> 16);
1148 if (status < 0)
1149 goto error;
1150
1151 /* OK, now check if the write itself has executed*/
1152 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1153 VENDOR_DSPIO_STATUS, 0);
1154error:
1155 mutex_unlock(&spec->chipio_mutex);
1156
1157 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1158 -EIO : 0;
1159}
1160
d5c21b88
IM		 1161/*
1162 * Write multiple SCP data to DSP
1163 */
01ef7dbf
IM		 1164static int dspio_write_multiple(struct hda_codec *codec,
1165 unsigned int *buffer, unsigned int size)
1166{
1167 int status = 0;
1168 unsigned int count;
1169
1170 if ((buffer == NULL))
1171 return -EINVAL;
1172
1173 count = 0;
1174 while (count < size) {
1175 status = dspio_write(codec, *buffer++);
1176 if (status != 0)
1177 break;
1178 count++;
1179 }
1180
1181 return status;
1182}
1183
a73d511c
IM		 1184static int dspio_read(struct hda_codec *codec, unsigned int *data)
1185{
1186 int status;
1187
1188 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1189 if (status == -EIO)
1190 return status;
1191
1192 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1193 if (status == -EIO ||
1194 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1195 return -EIO;
1196
1197 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1198 VENDOR_DSPIO_SCP_READ_DATA, 0);
1199
1200 return 0;
1201}
1202
1203static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1204 unsigned int *buf_size, unsigned int size_count)
1205{
1206 int status = 0;
1207 unsigned int size = *buf_size;
1208 unsigned int count;
1209 unsigned int skip_count;
1210 unsigned int dummy;
1211
1212 if ((buffer == NULL))
1213 return -1;
1214
1215 count = 0;
1216 while (count < size && count < size_count) {
1217 status = dspio_read(codec, buffer++);
1218 if (status != 0)
1219 break;
1220 count++;
1221 }
1222
1223 skip_count = count;
1224 if (status == 0) {
1225 while (skip_count < size) {
1226 status = dspio_read(codec, &dummy);
1227 if (status != 0)
1228 break;
1229 skip_count++;
1230 }
1231 }
1232 *buf_size = count;
1233
1234 return status;
1235}
1236
d5c21b88
IM		 1237/*
1238 * Construct the SCP header using corresponding fields
1239 */
01ef7dbf
IM		 1240static inline unsigned int
1241make_scp_header(unsigned int target_id, unsigned int source_id,
1242 unsigned int get_flag, unsigned int req,
1243 unsigned int device_flag, unsigned int resp_flag,
1244 unsigned int error_flag, unsigned int data_size)
1245{
1246 unsigned int header = 0;
1247
1248 header = (data_size & 0x1f) << 27;
1249 header |= (error_flag & 0x01) << 26;
1250 header |= (resp_flag & 0x01) << 25;
1251 header |= (device_flag & 0x01) << 24;
1252 header |= (req & 0x7f) << 17;
1253 header |= (get_flag & 0x01) << 16;
1254 header |= (source_id & 0xff) << 8;
1255 header |= target_id & 0xff;
1256
1257 return header;
1258}
1259
d5c21b88
IM		 1260/*
1261 * Extract corresponding fields from SCP header
1262 */
01ef7dbf
IM		 1263static inline void
1264extract_scp_header(unsigned int header,
1265 unsigned int *target_id, unsigned int *source_id,
1266 unsigned int *get_flag, unsigned int *req,
1267 unsigned int *device_flag, unsigned int *resp_flag,
1268 unsigned int *error_flag, unsigned int *data_size)
1269{
1270 if (data_size)
1271 *data_size = (header >> 27) & 0x1f;
1272 if (error_flag)
1273 *error_flag = (header >> 26) & 0x01;
1274 if (resp_flag)
1275 *resp_flag = (header >> 25) & 0x01;
1276 if (device_flag)
1277 *device_flag = (header >> 24) & 0x01;
1278 if (req)
1279 *req = (header >> 17) & 0x7f;
1280 if (get_flag)
1281 *get_flag = (header >> 16) & 0x01;
1282 if (source_id)
1283 *source_id = (header >> 8) & 0xff;
1284 if (target_id)
1285 *target_id = header & 0xff;
1286}
1287
1288#define SCP_MAX_DATA_WORDS (16)
1289
1290/* Structure to contain any SCP message */
1291struct scp_msg {
1292 unsigned int hdr;
1293 unsigned int data[SCP_MAX_DATA_WORDS];
1294};
1295
a73d511c
IM		 1296static void dspio_clear_response_queue(struct hda_codec *codec)
1297{
1298 unsigned int dummy = 0;
1299 int status = -1;
1300
1301 /* clear all from the response queue */
1302 do {
1303 status = dspio_read(codec, &dummy);
1304 } while (status == 0);
1305}
1306
1307static int dspio_get_response_data(struct hda_codec *codec)
1308{
1309 struct ca0132_spec *spec = codec->spec;
1310 unsigned int data = 0;
1311 unsigned int count;
1312
1313 if (dspio_read(codec, &data) < 0)
1314 return -EIO;
1315
1316 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1317 spec->scp_resp_header = data;
1318 spec->scp_resp_count = data >> 27;
1319 count = spec->wait_num_data;
1320 dspio_read_multiple(codec, spec->scp_resp_data,
1321 &spec->scp_resp_count, count);
1322 return 0;
1323 }
1324
1325 return -EIO;
1326}
1327
d5c21b88
IM		 1328/*
1329 * Send SCP message to DSP
1330 */
01ef7dbf
IM		 1331static int dspio_send_scp_message(struct hda_codec *codec,
1332 unsigned char *send_buf,
1333 unsigned int send_buf_size,
1334 unsigned char *return_buf,
1335 unsigned int return_buf_size,
1336 unsigned int *bytes_returned)
1337{
1338 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1339 int status = -1;
1340 unsigned int scp_send_size = 0;
1341 unsigned int total_size;
1342 bool waiting_for_resp = false;
1343 unsigned int header;
1344 struct scp_msg *ret_msg;
1345 unsigned int resp_src_id, resp_target_id;
1346 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1347
1348 if (bytes_returned)
1349 *bytes_returned = 0;
1350
1351 /* get scp header from buffer */
1352 header = *((unsigned int *)send_buf);
1353 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1354 &device_flag, NULL, NULL, &data_size);
1355 scp_send_size = data_size + 1;
1356 total_size = (scp_send_size * 4);
1357
1358 if (send_buf_size < total_size)
1359 return -EINVAL;
1360
1361 if (get_flag || device_flag) {
1362 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1363 return -EINVAL;
1364
1365 spec->wait_scp_header = *((unsigned int *)send_buf);
1366
1367 /* swap source id with target id */
1368 resp_target_id = src_id;
1369 resp_src_id = target_id;
1370 spec->wait_scp_header &= 0xffff0000;
1371 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1372 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1373 spec->wait_scp = 1;
1374 waiting_for_resp = true;
1375 }
1376
1377 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1378 scp_send_size);
1379 if (status < 0) {
1380 spec->wait_scp = 0;
1381 return status;
1382 }
1383
1384 if (waiting_for_resp) {
6d67530e 1385 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1386 memset(return_buf, 0, return_buf_size);
01ef7dbf
IM		 1387 do {
1388 msleep(20);
6d67530e 1389 } while (spec->wait_scp && time_before(jiffies, timeout));
01ef7dbf 1390 waiting_for_resp = false;
6d67530e 1391 if (!spec->wait_scp) {
01ef7dbf
IM		 1392 ret_msg = (struct scp_msg *)return_buf;
1393 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1394 memcpy(&ret_msg->data, spec->scp_resp_data,
1395 spec->wait_num_data);
1396 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1397 status = 0;
1398 } else {
1399 status = -EIO;
1400 }
1401 spec->wait_scp = 0;
1402 }
1403
1404 return status;
1405}
1406
d5c21b88
IM		 1407/**
1408 * Prepare and send the SCP message to DSP
1409 * @codec: the HDA codec
1410 * @mod_id: ID of the DSP module to send the command
1411 * @req: ID of request to send to the DSP module
1412 * @dir: SET or GET
1413 * @data: pointer to the data to send with the request, request specific
1414 * @len: length of the data, in bytes
1415 * @reply: point to the buffer to hold data returned for a reply
1416 * @reply_len: length of the reply buffer returned from GET
1417 *
1418 * Returns zero or a negative error code.
1419 */
01ef7dbf
IM		 1420static int dspio_scp(struct hda_codec *codec,
1421 int mod_id, int req, int dir, void *data, unsigned int len,
1422 void *reply, unsigned int *reply_len)
1423{
1424 int status = 0;
1425 struct scp_msg scp_send, scp_reply;
1426 unsigned int ret_bytes, send_size, ret_size;
1427 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1428 unsigned int reply_data_size;
1429
1430 memset(&scp_send, 0, sizeof(scp_send));
1431 memset(&scp_reply, 0, sizeof(scp_reply));
1432
1433 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1434 return -EINVAL;
1435
1436 if (dir == SCP_GET && reply == NULL) {
4e76a883 1437 codec_dbg(codec, "dspio_scp get but has no buffer\n");
01ef7dbf
IM		 1438 return -EINVAL;
1439 }
1440
1441 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
4e76a883 1442 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
01ef7dbf
IM		 1443 return -EINVAL;
1444 }
1445
1446 scp_send.hdr = make_scp_header(mod_id, 0x20, (dir == SCP_GET), req,
1447 0, 0, 0, len/sizeof(unsigned int));
1448 if (data != NULL && len > 0) {
1449 len = min((unsigned int)(sizeof(scp_send.data)), len);
1450 memcpy(scp_send.data, data, len);
1451 }
1452
1453 ret_bytes = 0;
1454 send_size = sizeof(unsigned int) + len;
1455 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1456 send_size, (unsigned char *)&scp_reply,
1457 sizeof(scp_reply), &ret_bytes);
1458
1459 if (status < 0) {
4e76a883 1460 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
01ef7dbf
IM		 1461 return status;
1462 }
1463
1464 /* extract send and reply headers members */
1465 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1466 NULL, NULL, NULL, NULL, NULL);
1467 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1468 &reply_resp_flag, &reply_error_flag,
1469 &reply_data_size);
1470
1471 if (!send_get_flag)
1472 return 0;
1473
1474 if (reply_resp_flag && !reply_error_flag) {
1475 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1476 / sizeof(unsigned int);
1477
1478 if (*reply_len < ret_size*sizeof(unsigned int)) {
4e76a883 1479 codec_dbg(codec, "reply too long for buf\n");
01ef7dbf
IM		 1480 return -EINVAL;
1481 } else if (ret_size != reply_data_size) {
4e76a883 1482 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
01ef7dbf
IM		 1483 return -EINVAL;
1484 } else {
1485 *reply_len = ret_size*sizeof(unsigned int);
1486 memcpy(reply, scp_reply.data, *reply_len);
1487 }
1488 } else {
4e76a883 1489 codec_dbg(codec, "reply ill-formed or errflag set\n");
01ef7dbf
IM		 1490 return -EIO;
1491 }
1492
1493 return status;
1494}
1495
5aaca44d
IM		 1496/*
1497 * Set DSP parameters
1498 */
1499static int dspio_set_param(struct hda_codec *codec, int mod_id,
1500 int req, void *data, unsigned int len)
1501{
1502 return dspio_scp(codec, mod_id, req, SCP_SET, data, len, NULL, NULL);
1503}
1504
1505static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
1506 int req, unsigned int data)
1507{
1508 return dspio_set_param(codec, mod_id, req, &data, sizeof(unsigned int));
1509}
1510
d5c21b88
IM		 1511/*
1512 * Allocate a DSP DMA channel via an SCP message
1513 */
01ef7dbf
IM		 1514static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1515{
1516 int status = 0;
1517 unsigned int size = sizeof(dma_chan);
1518
4e76a883 1519 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
01ef7dbf
IM		 1520 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1521 SCP_GET, NULL, 0, dma_chan, &size);
1522
1523 if (status < 0) {
4e76a883 1524 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
01ef7dbf
IM		 1525 return status;
1526 }
1527
1528 if ((*dma_chan + 1) == 0) {
4e76a883 1529 codec_dbg(codec, "no free dma channels to allocate\n");
01ef7dbf
IM		 1530 return -EBUSY;
1531 }
1532
4e76a883
TI		 1533 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1534 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
01ef7dbf
IM		 1535
1536 return status;
1537}
1538
d5c21b88
IM		 1539/*
1540 * Free a DSP DMA via an SCP message
1541 */
01ef7dbf
IM		 1542static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1543{
1544 int status = 0;
1545 unsigned int dummy = 0;
1546
4e76a883
TI		 1547 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
1548 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
01ef7dbf
IM		 1549
1550 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1551 SCP_SET, &dma_chan, sizeof(dma_chan), NULL, &dummy);
1552
1553 if (status < 0) {
4e76a883 1554 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
01ef7dbf
IM		 1555 return status;
1556 }
1557
4e76a883 1558 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
01ef7dbf
IM		 1559
1560 return status;
1561}
1562
1563/*
d5c21b88 1564 * (Re)start the DSP
01ef7dbf
IM		 1565 */
1566static int dsp_set_run_state(struct hda_codec *codec)
1567{
1568 unsigned int dbg_ctrl_reg;
1569 unsigned int halt_state;
1570 int err;
1571
1572 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1573 if (err < 0)
1574 return err;
1575
1576 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1577 DSP_DBGCNTL_STATE_LOBIT;
1578
1579 if (halt_state != 0) {
1580 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1581 DSP_DBGCNTL_SS_MASK);
1582 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1583 dbg_ctrl_reg);
1584 if (err < 0)
1585 return err;
1586
1587 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1588 DSP_DBGCNTL_EXEC_MASK;
1589 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1590 dbg_ctrl_reg);
1591 if (err < 0)
1592 return err;
1593 }
1594
1595 return 0;
1596}
1597
d5c21b88
IM		 1598/*
1599 * Reset the DSP
1600 */
01ef7dbf
IM		 1601static int dsp_reset(struct hda_codec *codec)
1602{
1603 unsigned int res;
1604 int retry = 20;
1605
4e76a883 1606 codec_dbg(codec, "dsp_reset\n");
01ef7dbf
IM		 1607 do {
1608 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
1609 retry--;
1610 } while (res == -EIO && retry);
1611
1612 if (!retry) {
4e76a883 1613 codec_dbg(codec, "dsp_reset timeout\n");
01ef7dbf
IM		 1614 return -EIO;
1615 }
1616
1617 return 0;
1618}
1619
d5c21b88
IM		 1620/*
1621 * Convert chip address to DSP address
1622 */
01ef7dbf
IM		 1623static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
1624 bool *code, bool *yram)
1625{
1626 *code = *yram = false;
1627
1628 if (UC_RANGE(chip_addx, 1)) {
1629 *code = true;
1630 return UC_OFF(chip_addx);
1631 } else if (X_RANGE_ALL(chip_addx, 1)) {
1632 return X_OFF(chip_addx);
1633 } else if (Y_RANGE_ALL(chip_addx, 1)) {
1634 *yram = true;
1635 return Y_OFF(chip_addx);
1636 }
1637
4a8b89f9 1638 return INVALID_CHIP_ADDRESS;
01ef7dbf
IM		 1639}
1640
d5c21b88
IM		 1641/*
1642 * Check if the DSP DMA is active
1643 */
01ef7dbf
IM		 1644static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
1645{
1646 unsigned int dma_chnlstart_reg;
1647
1648 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
1649
1650 return ((dma_chnlstart_reg & (1 <<
1651 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
1652}
1653
1654static int dsp_dma_setup_common(struct hda_codec *codec,
1655 unsigned int chip_addx,
1656 unsigned int dma_chan,
1657 unsigned int port_map_mask,
1658 bool ovly)
1659{
1660 int status = 0;
1661 unsigned int chnl_prop;
1662 unsigned int dsp_addx;
1663 unsigned int active;
1664 bool code, yram;
1665
4e76a883 1666 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
01ef7dbf
IM		 1667
1668 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
4e76a883 1669 codec_dbg(codec, "dma chan num invalid\n");
01ef7dbf
IM		 1670 return -EINVAL;
1671 }
1672
1673 if (dsp_is_dma_active(codec, dma_chan)) {
4e76a883 1674 codec_dbg(codec, "dma already active\n");
01ef7dbf
IM		 1675 return -EBUSY;
1676 }
1677
1678 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1679
1680 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 1681 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 1682 return -ENXIO;
1683 }
1684
1685 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
1686 active = 0;
1687
4e76a883 1688 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
01ef7dbf
IM		 1689
1690 if (ovly) {
1691 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
1692 &chnl_prop);
1693
1694 if (status < 0) {
4e76a883 1695 codec_dbg(codec, "read CHNLPROP Reg fail\n");
01ef7dbf
IM		 1696 return status;
1697 }
4e76a883 1698 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
01ef7dbf
IM		 1699 }
1700
1701 if (!code)
1702 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1703 else
1704 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1705
1706 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
1707
1708 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
1709 if (status < 0) {
4e76a883 1710 codec_dbg(codec, "write CHNLPROP Reg fail\n");
01ef7dbf
IM		 1711 return status;
1712 }
4e76a883 1713 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
01ef7dbf
IM		 1714
1715 if (ovly) {
1716 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
1717 &active);
1718
1719 if (status < 0) {
4e76a883 1720 codec_dbg(codec, "read ACTIVE Reg fail\n");
01ef7dbf
IM		 1721 return status;
1722 }
4e76a883 1723 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
01ef7dbf
IM		 1724 }
1725
1726 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
1727 DSPDMAC_ACTIVE_AAR_MASK;
1728
1729 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
1730 if (status < 0) {
4e76a883 1731 codec_dbg(codec, "write ACTIVE Reg fail\n");
01ef7dbf
IM		 1732 return status;
1733 }
1734
4e76a883 1735 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
01ef7dbf
IM		 1736
1737 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
1738 port_map_mask);
1739 if (status < 0) {
4e76a883 1740 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
01ef7dbf
IM		 1741 return status;
1742 }
4e76a883 1743 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
01ef7dbf
IM		 1744
1745 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
1746 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
1747 if (status < 0) {
4e76a883 1748 codec_dbg(codec, "write IRQCNT Reg fail\n");
01ef7dbf
IM		 1749 return status;
1750 }
4e76a883 1751 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
01ef7dbf 1752
4e76a883 1753 codec_dbg(codec,
01ef7dbf
IM		 1754 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
1755 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
1756 chip_addx, dsp_addx, dma_chan,
1757 port_map_mask, chnl_prop, active);
1758
4e76a883 1759 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
01ef7dbf
IM		 1760
1761 return 0;
1762}
1763
d5c21b88
IM		 1764/*
1765 * Setup the DSP DMA per-transfer-specific registers
1766 */
01ef7dbf
IM		 1767static int dsp_dma_setup(struct hda_codec *codec,
1768 unsigned int chip_addx,
1769 unsigned int count,
1770 unsigned int dma_chan)
1771{
1772 int status = 0;
1773 bool code, yram;
1774 unsigned int dsp_addx;
1775 unsigned int addr_field;
1776 unsigned int incr_field;
1777 unsigned int base_cnt;
1778 unsigned int cur_cnt;
1779 unsigned int dma_cfg = 0;
1780 unsigned int adr_ofs = 0;
1781 unsigned int xfr_cnt = 0;
1782 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
1783 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
1784
4e76a883 1785 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
01ef7dbf
IM		 1786
1787 if (count > max_dma_count) {
4e76a883 1788 codec_dbg(codec, "count too big\n");
01ef7dbf
IM		 1789 return -EINVAL;
1790 }
1791
1792 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1793 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 1794 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 1795 return -ENXIO;
1796 }
1797
4e76a883 1798 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
01ef7dbf
IM		 1799
1800 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
1801 incr_field = 0;
1802
1803 if (!code) {
1804 addr_field <<= 1;
1805 if (yram)
1806 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
1807
1808 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
1809 }
1810
1811 dma_cfg = addr_field + incr_field;
1812 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
1813 dma_cfg);
1814 if (status < 0) {
4e76a883 1815 codec_dbg(codec, "write DMACFG Reg fail\n");
01ef7dbf
IM		 1816 return status;
1817 }
4e76a883 1818 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
01ef7dbf
IM		 1819
1820 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
1821 (code ? 0 : 1));
1822
1823 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
1824 adr_ofs);
1825 if (status < 0) {
4e76a883 1826 codec_dbg(codec, "write DSPADROFS Reg fail\n");
01ef7dbf
IM		 1827 return status;
1828 }
4e76a883 1829 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
01ef7dbf
IM		 1830
1831 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
1832
1833 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
1834
1835 xfr_cnt = base_cnt | cur_cnt;
1836
1837 status = chipio_write(codec,
1838 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
1839 if (status < 0) {
4e76a883 1840 codec_dbg(codec, "write XFRCNT Reg fail\n");
01ef7dbf
IM		 1841 return status;
1842 }
4e76a883 1843 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
01ef7dbf 1844
4e76a883 1845 codec_dbg(codec,
01ef7dbf
IM		 1846 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
1847 "ADROFS=0x%x, XFRCNT=0x%x\n",
1848 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
1849
4e76a883 1850 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
01ef7dbf
IM		 1851
1852 return 0;
1853}
1854
d5c21b88
IM		 1855/*
1856 * Start the DSP DMA
1857 */
01ef7dbf
IM		 1858static int dsp_dma_start(struct hda_codec *codec,
1859 unsigned int dma_chan, bool ovly)
1860{
1861 unsigned int reg = 0;
1862 int status = 0;
1863
4e76a883 1864 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
01ef7dbf
IM		 1865
1866 if (ovly) {
1867 status = chipio_read(codec,
1868 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1869
1870 if (status < 0) {
4e76a883 1871 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 1872 return status;
1873 }
4e76a883 1874 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
01ef7dbf
IM		 1875
1876 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1877 DSPDMAC_CHNLSTART_DIS_MASK);
1878 }
1879
1880 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1881 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
1882 if (status < 0) {
4e76a883 1883 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 1884 return status;
1885 }
4e76a883 1886 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
01ef7dbf
IM		 1887
1888 return status;
1889}
1890
d5c21b88
IM		 1891/*
1892 * Stop the DSP DMA
1893 */
01ef7dbf
IM		 1894static int dsp_dma_stop(struct hda_codec *codec,
1895 unsigned int dma_chan, bool ovly)
1896{
1897 unsigned int reg = 0;
1898 int status = 0;
1899
4e76a883 1900 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
01ef7dbf
IM		 1901
1902 if (ovly) {
1903 status = chipio_read(codec,
1904 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1905
1906 if (status < 0) {
4e76a883 1907 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 1908 return status;
1909 }
4e76a883 1910 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
01ef7dbf
IM		 1911 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1912 DSPDMAC_CHNLSTART_DIS_MASK);
1913 }
1914
1915 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1916 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
1917 if (status < 0) {
4e76a883 1918 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 1919 return status;
1920 }
4e76a883 1921 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
01ef7dbf
IM		 1922
1923 return status;
1924}
1925
d5c21b88
IM		 1926/**
1927 * Allocate router ports
1928 *
1929 * @codec: the HDA codec
1930 * @num_chans: number of channels in the stream
1931 * @ports_per_channel: number of ports per channel
1932 * @start_device: start device
1933 * @port_map: pointer to the port list to hold the allocated ports
1934 *
1935 * Returns zero or a negative error code.
1936 */
01ef7dbf
IM		 1937static int dsp_allocate_router_ports(struct hda_codec *codec,
1938 unsigned int num_chans,
1939 unsigned int ports_per_channel,
1940 unsigned int start_device,
1941 unsigned int *port_map)
1942{
1943 int status = 0;
1944 int res;
1945 u8 val;
1946
1947 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1948 if (status < 0)
1949 return status;
1950
1951 val = start_device << 6;
1952 val |= (ports_per_channel - 1) << 4;
1953 val |= num_chans - 1;
1954
1955 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1956 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
1957 val);
1958
1959 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1960 VENDOR_CHIPIO_PORT_ALLOC_SET,
1961 MEM_CONNID_DSP);
1962
1963 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1964 if (status < 0)
1965 return status;
1966
1967 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1968 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
1969
1970 *port_map = res;
1971
1972 return (res < 0) ? res : 0;
1973}
1974
d5c21b88
IM		 1975/*
1976 * Free router ports
1977 */
01ef7dbf
IM		 1978static int dsp_free_router_ports(struct hda_codec *codec)
1979{
1980 int status = 0;
1981
1982 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1983 if (status < 0)
1984 return status;
1985
1986 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1987 VENDOR_CHIPIO_PORT_FREE_SET,
1988 MEM_CONNID_DSP);
1989
1990 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1991
1992 return status;
1993}
1994
d5c21b88
IM		 1995/*
1996 * Allocate DSP ports for the download stream
1997 */
01ef7dbf
IM		 1998static int dsp_allocate_ports(struct hda_codec *codec,
1999 unsigned int num_chans,
2000 unsigned int rate_multi, unsigned int *port_map)
2001{
2002 int status;
2003
4e76a883 2004 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
01ef7dbf
IM		 2005
2006 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2007 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2008 return -EINVAL;
2009 }
2010
2011 status = dsp_allocate_router_ports(codec, num_chans,
2012 rate_multi, 0, port_map);
2013
4e76a883 2014 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
01ef7dbf
IM		 2015
2016 return status;
2017}
2018
01ef7dbf
IM		 2019static int dsp_allocate_ports_format(struct hda_codec *codec,
2020 const unsigned short fmt,
2021 unsigned int *port_map)
2022{
2023 int status;
2024 unsigned int num_chans;
2025
2026 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2027 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2028 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2029
2030 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2031 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2032 return -EINVAL;
2033 }
2034
2035 num_chans = get_hdafmt_chs(fmt) + 1;
2036
2037 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2038
2039 return status;
2040}
2041
d5c21b88
IM		 2042/*
2043 * free DSP ports
2044 */
2045static int dsp_free_ports(struct hda_codec *codec)
2046{
2047 int status;
2048
4e76a883 2049 codec_dbg(codec, " dsp_free_ports() -- begin\n");
d5c21b88
IM		 2050
2051 status = dsp_free_router_ports(codec);
2052 if (status < 0) {
4e76a883 2053 codec_dbg(codec, "free router ports fail\n");
d5c21b88
IM		 2054 return status;
2055 }
4e76a883 2056 codec_dbg(codec, " dsp_free_ports() -- complete\n");
d5c21b88
IM		 2057
2058 return status;
2059}
2060
01ef7dbf
IM		 2061/*
2062 * HDA DMA engine stuffs for DSP code download
2063 */
2064struct dma_engine {
2065 struct hda_codec *codec;
2066 unsigned short m_converter_format;
2067 struct snd_dma_buffer *dmab;
2068 unsigned int buf_size;
2069};
2070
2071
2072enum dma_state {
2073 DMA_STATE_STOP = 0,
2074 DMA_STATE_RUN = 1
2075};
2076
6194b99d 2077static int dma_convert_to_hda_format(struct hda_codec *codec,
e97249dd
IM		 2078 unsigned int sample_rate,
2079 unsigned short channels,
01ef7dbf
IM		 2080 unsigned short *hda_format)
2081{
2082 unsigned int format_val;
2083
b7d023e1
TI		 2084 format_val = snd_hdac_calc_stream_format(sample_rate,
2085 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
01ef7dbf
IM		 2086
2087 if (hda_format)
2088 *hda_format = (unsigned short)format_val;
2089
2090 return 0;
2091}
2092
d5c21b88
IM		 2093/*
2094 * Reset DMA for DSP download
2095 */
01ef7dbf
IM		 2096static int dma_reset(struct dma_engine *dma)
2097{
2098 struct hda_codec *codec = dma->codec;
2099 struct ca0132_spec *spec = codec->spec;
2100 int status;
2101
b3667bd7 2102 if (dma->dmab->area)
01ef7dbf
IM		 2103 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2104
2105 status = snd_hda_codec_load_dsp_prepare(codec,
2106 dma->m_converter_format,
2107 dma->buf_size,
2108 dma->dmab);
2109 if (status < 0)
2110 return status;
2111 spec->dsp_stream_id = status;
2112 return 0;
2113}
2114
2115static int dma_set_state(struct dma_engine *dma, enum dma_state state)
95c6e9cb 2116{
01ef7dbf
IM		 2117 bool cmd;
2118
01ef7dbf
IM		 2119 switch (state) {
2120 case DMA_STATE_STOP:
2121 cmd = false;
2122 break;
2123 case DMA_STATE_RUN:
2124 cmd = true;
2125 break;
2126 default:
c41999a2
DH		 2127 return 0;
2128 }
01ef7dbf
IM		 2129
2130 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2131 return 0;
95c6e9cb
IM		 2132}
2133
01ef7dbf
IM		 2134static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2135{
2136 return dma->dmab->bytes;
2137}
95c6e9cb 2138
01ef7dbf
IM		 2139static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2140{
2141 return dma->dmab->area;
2142}
95c6e9cb 2143
01ef7dbf
IM		 2144static int dma_xfer(struct dma_engine *dma,
2145 const unsigned int *data,
2146 unsigned int count)
2147{
2148 memcpy(dma->dmab->area, data, count);
2149 return 0;
2150}
95c6e9cb 2151
01ef7dbf
IM		 2152static void dma_get_converter_format(
2153 struct dma_engine *dma,
2154 unsigned short *format)
2155{
2156 if (format)
2157 *format = dma->m_converter_format;
2158}
95c6e9cb 2159
01ef7dbf 2160static unsigned int dma_get_stream_id(struct dma_engine *dma)
95c6e9cb 2161{
01ef7dbf 2162 struct ca0132_spec *spec = dma->codec->spec;
95c6e9cb 2163
01ef7dbf 2164 return spec->dsp_stream_id;
95c6e9cb
IM		 2165}
2166
01ef7dbf
IM		 2167struct dsp_image_seg {
2168 u32 magic;
2169 u32 chip_addr;
2170 u32 count;
2171 u32 data[0];
2172};
2173
2174static const u32 g_magic_value = 0x4c46584d;
2175static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2176
2177static bool is_valid(const struct dsp_image_seg *p)
95c6e9cb 2178{
01ef7dbf
IM		 2179 return p->magic == g_magic_value;
2180}
95c6e9cb 2181
01ef7dbf
IM		 2182static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2183{
2184 return g_chip_addr_magic_value == p->chip_addr;
2185}
95c6e9cb 2186
01ef7dbf
IM		 2187static bool is_last(const struct dsp_image_seg *p)
2188{
2189 return p->count == 0;
2190}
95c6e9cb 2191
01ef7dbf
IM		 2192static size_t dsp_sizeof(const struct dsp_image_seg *p)
2193{
2194 return sizeof(*p) + p->count*sizeof(u32);
2195}
2196
2197static const struct dsp_image_seg *get_next_seg_ptr(
2198 const struct dsp_image_seg *p)
2199{
2200 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
95c6e9cb
IM		 2201}
2202
2203/*
01ef7dbf 2204 * CA0132 chip DSP transfer stuffs. For DSP download.
95c6e9cb 2205 */
8ae3124b 2206#define INVALID_DMA_CHANNEL (~0U)
95c6e9cb 2207
d5c21b88
IM		 2208/*
2209 * Program a list of address/data pairs via the ChipIO widget.
2210 * The segment data is in the format of successive pairs of words.
2211 * These are repeated as indicated by the segment's count field.
2212 */
01ef7dbf
IM		 2213static int dspxfr_hci_write(struct hda_codec *codec,
2214 const struct dsp_image_seg *fls)
95c6e9cb 2215{
01ef7dbf
IM		 2216 int status;
2217 const u32 *data;
2218 unsigned int count;
95c6e9cb 2219
01ef7dbf 2220 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
4e76a883 2221 codec_dbg(codec, "hci_write invalid params\n");
01ef7dbf 2222 return -EINVAL;
95c6e9cb
IM		 2223 }
2224
01ef7dbf
IM		 2225 count = fls->count;
2226 data = (u32 *)(fls->data);
2227 while (count >= 2) {
2228 status = chipio_write(codec, data[0], data[1]);
2229 if (status < 0) {
4e76a883 2230 codec_dbg(codec, "hci_write chipio failed\n");
01ef7dbf
IM		 2231 return status;
2232 }
2233 count -= 2;
2234 data += 2;
2235 }
2236 return 0;
95c6e9cb
IM		 2237}
2238
d5c21b88
IM		 2239/**
2240 * Write a block of data into DSP code or data RAM using pre-allocated
2241 * DMA engine.
2242 *
2243 * @codec: the HDA codec
2244 * @fls: pointer to a fast load image
2245 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2246 * no relocation
2247 * @dma_engine: pointer to DMA engine to be used for DSP download
2248 * @dma_chan: The number of DMA channels used for DSP download
2249 * @port_map_mask: port mapping
2250 * @ovly: TRUE if overlay format is required
2251 *
2252 * Returns zero or a negative error code.
2253 */
01ef7dbf
IM		 2254static int dspxfr_one_seg(struct hda_codec *codec,
2255 const struct dsp_image_seg *fls,
2256 unsigned int reloc,
2257 struct dma_engine *dma_engine,
2258 unsigned int dma_chan,
2259 unsigned int port_map_mask,
2260 bool ovly)
95c6e9cb 2261{
406261ce 2262 int status = 0;
01ef7dbf
IM		 2263 bool comm_dma_setup_done = false;
2264 const unsigned int *data;
2265 unsigned int chip_addx;
2266 unsigned int words_to_write;
2267 unsigned int buffer_size_words;
2268 unsigned char *buffer_addx;
2269 unsigned short hda_format;
2270 unsigned int sample_rate_div;
2271 unsigned int sample_rate_mul;
2272 unsigned int num_chans;
2273 unsigned int hda_frame_size_words;
2274 unsigned int remainder_words;
2275 const u32 *data_remainder;
2276 u32 chip_addx_remainder;
2277 unsigned int run_size_words;
2278 const struct dsp_image_seg *hci_write = NULL;
6d67530e
IM		 2279 unsigned long timeout;
2280 bool dma_active;
01ef7dbf
IM		 2281
2282 if (fls == NULL)
2283 return -EINVAL;
2284 if (is_hci_prog_list_seg(fls)) {
2285 hci_write = fls;
2286 fls = get_next_seg_ptr(fls);
2287 }
95c6e9cb 2288
01ef7dbf 2289 if (hci_write && (!fls || is_last(fls))) {
4e76a883 2290 codec_dbg(codec, "hci_write\n");
01ef7dbf
IM		 2291 return dspxfr_hci_write(codec, hci_write);
2292 }
95c6e9cb 2293
01ef7dbf 2294 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
4e76a883 2295 codec_dbg(codec, "Invalid Params\n");
01ef7dbf 2296 return -EINVAL;
95c6e9cb
IM		 2297 }
2298
01ef7dbf
IM		 2299 data = fls->data;
2300 chip_addx = fls->chip_addr,
2301 words_to_write = fls->count;
2302
2303 if (!words_to_write)
2304 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2305 if (reloc)
2306 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2307
2308 if (!UC_RANGE(chip_addx, words_to_write) &&
2309 !X_RANGE_ALL(chip_addx, words_to_write) &&
2310 !Y_RANGE_ALL(chip_addx, words_to_write)) {
4e76a883 2311 codec_dbg(codec, "Invalid chip_addx Params\n");
01ef7dbf 2312 return -EINVAL;
95c6e9cb
IM		 2313 }
2314
01ef7dbf
IM		 2315 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2316 sizeof(u32);
2317
2318 buffer_addx = dma_get_buffer_addr(dma_engine);
2319
2320 if (buffer_addx == NULL) {
4e76a883 2321 codec_dbg(codec, "dma_engine buffer NULL\n");
01ef7dbf
IM		 2322 return -EINVAL;
2323 }
2324
2325 dma_get_converter_format(dma_engine, &hda_format);
2326 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2327 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2328 num_chans = get_hdafmt_chs(hda_format) + 1;
2329
2330 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2331 (num_chans * sample_rate_mul / sample_rate_div));
2332
3bc085a1 2333 if (hda_frame_size_words == 0) {
4e76a883 2334 codec_dbg(codec, "frmsz zero\n");
3bc085a1
XW		 2335 return -EINVAL;
2336 }
2337
01ef7dbf
IM		 2338 buffer_size_words = min(buffer_size_words,
2339 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2340 65536 : 32768));
2341 buffer_size_words -= buffer_size_words % hda_frame_size_words;
4e76a883 2342 codec_dbg(codec,
01ef7dbf
IM		 2343 "chpadr=0x%08x frmsz=%u nchan=%u "
2344 "rate_mul=%u div=%u bufsz=%u\n",
2345 chip_addx, hda_frame_size_words, num_chans,
2346 sample_rate_mul, sample_rate_div, buffer_size_words);
2347
3bc085a1 2348 if (buffer_size_words < hda_frame_size_words) {
4e76a883 2349 codec_dbg(codec, "dspxfr_one_seg:failed\n");
01ef7dbf
IM		 2350 return -EINVAL;
2351 }
2352
2353 remainder_words = words_to_write % hda_frame_size_words;
2354 data_remainder = data;
2355 chip_addx_remainder = chip_addx;
2356
2357 data += remainder_words;
2358 chip_addx += remainder_words*sizeof(u32);
2359 words_to_write -= remainder_words;
2360
2361 while (words_to_write != 0) {
2362 run_size_words = min(buffer_size_words, words_to_write);
4e76a883 2363 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
01ef7dbf
IM		 2364 words_to_write, run_size_words, remainder_words);
2365 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2366 if (!comm_dma_setup_done) {
2367 status = dsp_dma_stop(codec, dma_chan, ovly);
2368 if (status < 0)
425a7880 2369 return status;
01ef7dbf
IM		 2370 status = dsp_dma_setup_common(codec, chip_addx,
2371 dma_chan, port_map_mask, ovly);
2372 if (status < 0)
2373 return status;
2374 comm_dma_setup_done = true;
2375 }
2376
2377 status = dsp_dma_setup(codec, chip_addx,
2378 run_size_words, dma_chan);
2379 if (status < 0)
2380 return status;
2381 status = dsp_dma_start(codec, dma_chan, ovly);
2382 if (status < 0)
2383 return status;
2384 if (!dsp_is_dma_active(codec, dma_chan)) {
4e76a883 2385 codec_dbg(codec, "dspxfr:DMA did not start\n");
01ef7dbf
IM		 2386 return -EIO;
2387 }
2388 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2389 if (status < 0)
2390 return status;
2391 if (remainder_words != 0) {
2392 status = chipio_write_multiple(codec,
2393 chip_addx_remainder,
2394 data_remainder,
2395 remainder_words);
b3667bd7
TI		 2396 if (status < 0)
2397 return status;
01ef7dbf
IM		 2398 remainder_words = 0;
2399 }
2400 if (hci_write) {
2401 status = dspxfr_hci_write(codec, hci_write);
b3667bd7
TI		 2402 if (status < 0)
2403 return status;
01ef7dbf
IM		 2404 hci_write = NULL;
2405 }
6d67530e
IM		 2406
2407 timeout = jiffies + msecs_to_jiffies(2000);
2408 do {
2409 dma_active = dsp_is_dma_active(codec, dma_chan);
2410 if (!dma_active)
01ef7dbf 2411 break;
6d67530e
IM		 2412 msleep(20);
2413 } while (time_before(jiffies, timeout));
2414 if (dma_active)
2415 break;
2416
4e76a883 2417 codec_dbg(codec, "+++++ DMA complete\n");
01ef7dbf 2418 dma_set_state(dma_engine, DMA_STATE_STOP);
b3667bd7 2419 status = dma_reset(dma_engine);
01ef7dbf
IM		 2420
2421 if (status < 0)
2422 return status;
2423
2424 data += run_size_words;
2425 chip_addx += run_size_words*sizeof(u32);
2426 words_to_write -= run_size_words;
2427 }
2428
2429 if (remainder_words != 0) {
2430 status = chipio_write_multiple(codec, chip_addx_remainder,
2431 data_remainder, remainder_words);
2432 }
2433
2434 return status;
95c6e9cb
IM		 2435}
2436
d5c21b88
IM		 2437/**
2438 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2439 *
2440 * @codec: the HDA codec
2441 * @fls_data: pointer to a fast load image
2442 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2443 * no relocation
e97249dd 2444 * @sample_rate: sampling rate of the stream used for DSP download
e60b2c7f 2445 * @channels: channels of the stream used for DSP download
d5c21b88
IM		 2446 * @ovly: TRUE if overlay format is required
2447 *
2448 * Returns zero or a negative error code.
2449 */
01ef7dbf
IM		 2450static int dspxfr_image(struct hda_codec *codec,
2451 const struct dsp_image_seg *fls_data,
e97249dd
IM		 2452 unsigned int reloc,
2453 unsigned int sample_rate,
2454 unsigned short channels,
01ef7dbf 2455 bool ovly)
95c6e9cb
IM		 2456{
2457 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 2458 int status;
2459 unsigned short hda_format = 0;
2460 unsigned int response;
2461 unsigned char stream_id = 0;
2462 struct dma_engine *dma_engine;
2463 unsigned int dma_chan;
2464 unsigned int port_map_mask;
2465
2466 if (fls_data == NULL)
2467 return -EINVAL;
2468
2469 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
549e8292
TI		 2470 if (!dma_engine)
2471 return -ENOMEM;
95c6e9cb 2472
01ef7dbf
IM		 2473 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2474 if (!dma_engine->dmab) {
549e8292
TI		 2475 kfree(dma_engine);
2476 return -ENOMEM;
01ef7dbf 2477 }
95c6e9cb 2478
01ef7dbf 2479 dma_engine->codec = codec;
6194b99d 2480 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
01ef7dbf
IM		 2481 dma_engine->m_converter_format = hda_format;
2482 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2483 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2484
8ae3124b 2485 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
01ef7dbf
IM		 2486
2487 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2488 hda_format, &response);
2489
2490 if (status < 0) {
4e76a883 2491 codec_dbg(codec, "set converter format fail\n");
01ef7dbf
IM		 2492 goto exit;
2493 }
2494
2495 status = snd_hda_codec_load_dsp_prepare(codec,
2496 dma_engine->m_converter_format,
2497 dma_engine->buf_size,
2498 dma_engine->dmab);
2499 if (status < 0)
95c6e9cb 2500 goto exit;
01ef7dbf
IM		 2501 spec->dsp_stream_id = status;
2502
2503 if (ovly) {
2504 status = dspio_alloc_dma_chan(codec, &dma_chan);
2505 if (status < 0) {
4e76a883 2506 codec_dbg(codec, "alloc dmachan fail\n");
8ae3124b 2507 dma_chan = INVALID_DMA_CHANNEL;
01ef7dbf
IM		 2508 goto exit;
2509 }
2510 }
95c6e9cb 2511
01ef7dbf
IM		 2512 port_map_mask = 0;
2513 status = dsp_allocate_ports_format(codec, hda_format,
2514 &port_map_mask);
2515 if (status < 0) {
4e76a883 2516 codec_dbg(codec, "alloc ports fail\n");
01ef7dbf
IM		 2517 goto exit;
2518 }
2519
2520 stream_id = dma_get_stream_id(dma_engine);
2521 status = codec_set_converter_stream_channel(codec,
2522 WIDGET_CHIP_CTRL, stream_id, 0, &response);
2523 if (status < 0) {
4e76a883 2524 codec_dbg(codec, "set stream chan fail\n");
01ef7dbf
IM		 2525 goto exit;
2526 }
2527
2528 while ((fls_data != NULL) && !is_last(fls_data)) {
2529 if (!is_valid(fls_data)) {
4e76a883 2530 codec_dbg(codec, "FLS check fail\n");
01ef7dbf
IM		 2531 status = -EINVAL;
2532 goto exit;
2533 }
2534 status = dspxfr_one_seg(codec, fls_data, reloc,
2535 dma_engine, dma_chan,
2536 port_map_mask, ovly);
2537 if (status < 0)
2538 break;
2539
2540 if (is_hci_prog_list_seg(fls_data))
2541 fls_data = get_next_seg_ptr(fls_data);
2542
2543 if ((fls_data != NULL) && !is_last(fls_data))
2544 fls_data = get_next_seg_ptr(fls_data);
2545 }
2546
2547 if (port_map_mask != 0)
2548 status = dsp_free_ports(codec);
2549
2550 if (status < 0)
95c6e9cb
IM		 2551 goto exit;
2552
01ef7dbf
IM		 2553 status = codec_set_converter_stream_channel(codec,
2554 WIDGET_CHIP_CTRL, 0, 0, &response);
2555
95c6e9cb 2556exit:
01ef7dbf
IM		 2557 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2558 dspio_free_dma_chan(codec, dma_chan);
2559
b3667bd7 2560 if (dma_engine->dmab->area)
01ef7dbf
IM		 2561 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2562 kfree(dma_engine->dmab);
2563 kfree(dma_engine);
2564
2565 return status;
95c6e9cb
IM		 2566}
2567
2568/*
01ef7dbf 2569 * CA0132 DSP download stuffs.
95c6e9cb 2570 */
01ef7dbf 2571static void dspload_post_setup(struct hda_codec *codec)
95c6e9cb 2572{
4e76a883 2573 codec_dbg(codec, "---- dspload_post_setup ------\n");
95c6e9cb 2574
01ef7dbf
IM		 2575 /*set DSP speaker to 2.0 configuration*/
2576 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2577 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
95c6e9cb 2578
01ef7dbf
IM		 2579 /*update write pointer*/
2580 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2581}
95c6e9cb 2582
d5c21b88 2583/**
e60b2c7f 2584 * dspload_image - Download DSP from a DSP Image Fast Load structure.
d5c21b88
IM		 2585 *
2586 * @codec: the HDA codec
2587 * @fls: pointer to a fast load image
2588 * @ovly: TRUE if overlay format is required
2589 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2590 * no relocation
2591 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2592 * @router_chans: number of audio router channels to be allocated (0 means use
2593 * internal defaults; max is 32)
2594 *
e60b2c7f
TI		 2595 * Download DSP from a DSP Image Fast Load structure. This structure is a
2596 * linear, non-constant sized element array of structures, each of which
2597 * contain the count of the data to be loaded, the data itself, and the
2598 * corresponding starting chip address of the starting data location.
d5c21b88
IM		 2599 * Returns zero or a negative error code.
2600 */
01ef7dbf
IM		 2601static int dspload_image(struct hda_codec *codec,
2602 const struct dsp_image_seg *fls,
2603 bool ovly,
2604 unsigned int reloc,
2605 bool autostart,
2606 int router_chans)
2607{
2608 int status = 0;
e97249dd
IM		 2609 unsigned int sample_rate;
2610 unsigned short channels;
01ef7dbf 2611
4e76a883 2612 codec_dbg(codec, "---- dspload_image begin ------\n");
01ef7dbf
IM		 2613 if (router_chans == 0) {
2614 if (!ovly)
2615 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
2616 else
2617 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
2618 }
95c6e9cb 2619
e97249dd
IM		 2620 sample_rate = 48000;
2621 channels = (unsigned short)router_chans;
01ef7dbf 2622
e97249dd
IM		 2623 while (channels > 16) {
2624 sample_rate *= 2;
2625 channels /= 2;
01ef7dbf
IM		 2626 }
2627
01ef7dbf 2628 do {
4e76a883 2629 codec_dbg(codec, "Ready to program DMA\n");
01ef7dbf
IM		 2630 if (!ovly)
2631 status = dsp_reset(codec);
2632
2633 if (status < 0)
2634 break;
2635
4e76a883 2636 codec_dbg(codec, "dsp_reset() complete\n");
e97249dd
IM		 2637 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
2638 ovly);
01ef7dbf
IM		 2639
2640 if (status < 0)
2641 break;
2642
4e76a883 2643 codec_dbg(codec, "dspxfr_image() complete\n");
01ef7dbf
IM		 2644 if (autostart && !ovly) {
2645 dspload_post_setup(codec);
2646 status = dsp_set_run_state(codec);
2647 }
2648
4e76a883 2649 codec_dbg(codec, "LOAD FINISHED\n");
01ef7dbf
IM		 2650 } while (0);
2651
2652 return status;
2653}
2654
f664417e 2655#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf
IM		 2656static bool dspload_is_loaded(struct hda_codec *codec)
2657{
2658 unsigned int data = 0;
2659 int status = 0;
2660
2661 status = chipio_read(codec, 0x40004, &data);
2662 if ((status < 0) || (data != 1))
2663 return false;
2664
2665 return true;
2666}
f664417e
TI		 2667#else
2668#define dspload_is_loaded(codec) false
2669#endif
01ef7dbf
IM		 2670
2671static bool dspload_wait_loaded(struct hda_codec *codec)
2672{
6d67530e 2673 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
01ef7dbf
IM		 2674
2675 do {
01ef7dbf 2676 if (dspload_is_loaded(codec)) {
d9684bb5 2677 codec_info(codec, "ca0132 DSP downloaded and running\n");
01ef7dbf
IM		 2678 return true;
2679 }
6d67530e
IM		 2680 msleep(20);
2681 } while (time_before(jiffies, timeout));
01ef7dbf 2682
d9684bb5 2683 codec_err(codec, "ca0132 failed to download DSP\n");
01ef7dbf 2684 return false;
95c6e9cb
IM		 2685}
2686
825315bc
IM		 2687/*
2688 * PCM callbacks
2689 */
95c6e9cb
IM		 2690static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2691 struct hda_codec *codec,
2692 unsigned int stream_tag,
2693 unsigned int format,
2694 struct snd_pcm_substream *substream)
2695{
2696 struct ca0132_spec *spec = codec->spec;
825315bc 2697
28fba950 2698 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
825315bc
IM		 2699
2700 return 0;
95c6e9cb
IM		 2701}
2702
2703static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2704 struct hda_codec *codec,
2705 struct snd_pcm_substream *substream)
2706{
2707 struct ca0132_spec *spec = codec->spec;
825315bc
IM		 2708
2709 if (spec->dsp_state == DSP_DOWNLOADING)
2710 return 0;
2711
2712 /*If Playback effects are on, allow stream some time to flush
2713 *effects tail*/
2714 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
2715 msleep(50);
2716
28fba950 2717 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
825315bc
IM		 2718
2719 return 0;
95c6e9cb
IM		 2720}
2721
e8412ca4
DR		 2722static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
2723 struct hda_codec *codec,
2724 struct snd_pcm_substream *substream)
2725{
2726 struct ca0132_spec *spec = codec->spec;
2727 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
2728 struct snd_pcm_runtime *runtime = substream->runtime;
2729
2730 if (spec->dsp_state != DSP_DOWNLOADED)
2731 return 0;
2732
2733 /* Add latency if playback enhancement and either effect is enabled. */
2734 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
2735 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
2736 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
2737 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
2738 }
2739
2740 /* Applying Speaker EQ adds latency as well. */
2741 if (spec->cur_out_type == SPEAKER_OUT)
2742 latency += DSP_SPEAKER_OUT_LATENCY;
2743
2744 return (latency * runtime->rate) / 1000;
2745}
2746
95c6e9cb
IM		 2747/*
2748 * Digital out
2749 */
27ebeb0b
TI		 2750static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
2751 struct hda_codec *codec,
2752 struct snd_pcm_substream *substream)
95c6e9cb
IM		 2753{
2754 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2755 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
95c6e9cb
IM		 2756}
2757
27ebeb0b 2758static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
95c6e9cb
IM		 2759 struct hda_codec *codec,
2760 unsigned int stream_tag,
2761 unsigned int format,
2762 struct snd_pcm_substream *substream)
2763{
2764 struct ca0132_spec *spec = codec->spec;
27ebeb0b
TI		 2765 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2766 stream_tag, format, substream);
95c6e9cb
IM		 2767}
2768
27ebeb0b 2769static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
95c6e9cb 2770 struct hda_codec *codec,
95c6e9cb
IM		 2771 struct snd_pcm_substream *substream)
2772{
2773 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2774 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
95c6e9cb
IM		 2775}
2776
27ebeb0b
TI		 2777static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
2778 struct hda_codec *codec,
2779 struct snd_pcm_substream *substream)
95c6e9cb
IM		 2780{
2781 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2782 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
95c6e9cb
IM		 2783}
2784
825315bc
IM		 2785/*
2786 * Analog capture
2787 */
2788static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
2789 struct hda_codec *codec,
2790 unsigned int stream_tag,
2791 unsigned int format,
2792 struct snd_pcm_substream *substream)
2793{
13c12dbe 2794 snd_hda_codec_setup_stream(codec, hinfo->nid,
28fba950 2795 stream_tag, 0, format);
825315bc
IM		 2796
2797 return 0;
2798}
2799
2800static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
2801 struct hda_codec *codec,
2802 struct snd_pcm_substream *substream)
2803{
2804 struct ca0132_spec *spec = codec->spec;
2805
2806 if (spec->dsp_state == DSP_DOWNLOADING)
2807 return 0;
2808
28fba950 2809 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
825315bc
IM		 2810 return 0;
2811}
2812
e8412ca4
DR		 2813static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
2814 struct hda_codec *codec,
2815 struct snd_pcm_substream *substream)
2816{
2817 struct ca0132_spec *spec = codec->spec;
2818 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
2819 struct snd_pcm_runtime *runtime = substream->runtime;
2820
2821 if (spec->dsp_state != DSP_DOWNLOADED)
2822 return 0;
2823
2824 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
2825 latency += DSP_CRYSTAL_VOICE_LATENCY;
2826
2827 return (latency * runtime->rate) / 1000;
2828}
2829
e90f29e4
IM		 2830/*
2831 * Controls stuffs.
2832 */
2833
2834/*
2835 * Mixer controls helpers.
2836 */
2837#define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
2838 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2839 .name = xname, \
2840 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2841 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2842 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
2843 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
2844 .info = ca0132_volume_info, \
2845 .get = ca0132_volume_get, \
2846 .put = ca0132_volume_put, \
2847 .tlv = { .c = ca0132_volume_tlv }, \
2848 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2849
2850#define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
2851 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2852 .name = xname, \
2853 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2854 .info = snd_hda_mixer_amp_switch_info, \
2855 .get = ca0132_switch_get, \
2856 .put = ca0132_switch_put, \
2857 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2858
2859/* stereo */
2860#define CA0132_CODEC_VOL(xname, nid, dir) \
2861 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
2862#define CA0132_CODEC_MUTE(xname, nid, dir) \
2863 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
2864
44f0c978
IM		 2865/* The followings are for tuning of products */
2866#ifdef ENABLE_TUNING_CONTROLS
2867
2868static unsigned int voice_focus_vals_lookup[] = {
28690x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
28700x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
28710x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
28720x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
28730x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
28740x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
28750x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
28760x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
28770x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
28780x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
28790x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
28800x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
28810x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
28820x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
28830x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
28840x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
28850x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
28860x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
28870x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
28880x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
28890x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
28900x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
28910x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
28920x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
28930x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
28940x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
28950x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
2896};
2897
2898static unsigned int mic_svm_vals_lookup[] = {
28990x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
29000x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
29010x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
29020x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
29030x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
29040x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
29050x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
29060x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
29070x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
29080x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
29090x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
29100x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
29110x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
29120x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
29130x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
29140x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
29150x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
2916};
2917
2918static unsigned int equalizer_vals_lookup[] = {
29190xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
29200xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
29210xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
29220xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
29230x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
29240x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
29250x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
29260x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
29270x41C00000
2928};
2929
2930static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
2931 unsigned int *lookup, int idx)
2932{
2933 int i = 0;
2934
2935 for (i = 0; i < TUNING_CTLS_COUNT; i++)
2936 if (nid == ca0132_tuning_ctls[i].nid)
2937 break;
2938
2939 snd_hda_power_up(codec);
2940 dspio_set_param(codec, ca0132_tuning_ctls[i].mid,
2941 ca0132_tuning_ctls[i].req,
2942 &(lookup[idx]), sizeof(unsigned int));
2943 snd_hda_power_down(codec);
2944
2945 return 1;
2946}
2947
2948static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
2949 struct snd_ctl_elem_value *ucontrol)
2950{
2951 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2952 struct ca0132_spec *spec = codec->spec;
2953 hda_nid_t nid = get_amp_nid(kcontrol);
2954 long *valp = ucontrol->value.integer.value;
2955 int idx = nid - TUNING_CTL_START_NID;
2956
2957 *valp = spec->cur_ctl_vals[idx];
2958 return 0;
2959}
2960
2961static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
2962 struct snd_ctl_elem_info *uinfo)
2963{
2964 int chs = get_amp_channels(kcontrol);
2965 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2966 uinfo->count = chs == 3 ? 2 : 1;
2967 uinfo->value.integer.min = 20;
2968 uinfo->value.integer.max = 180;
2969 uinfo->value.integer.step = 1;
2970
2971 return 0;
2972}
2973
2974static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
2975 struct snd_ctl_elem_value *ucontrol)
2976{
2977 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2978 struct ca0132_spec *spec = codec->spec;
2979 hda_nid_t nid = get_amp_nid(kcontrol);
2980 long *valp = ucontrol->value.integer.value;
2981 int idx;
2982
2983 idx = nid - TUNING_CTL_START_NID;
2984 /* any change? */
2985 if (spec->cur_ctl_vals[idx] == *valp)
2986 return 0;
2987
2988 spec->cur_ctl_vals[idx] = *valp;
2989
2990 idx = *valp - 20;
2991 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
2992
2993 return 1;
2994}
2995
2996static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
2997 struct snd_ctl_elem_info *uinfo)
2998{
2999 int chs = get_amp_channels(kcontrol);
3000 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3001 uinfo->count = chs == 3 ? 2 : 1;
3002 uinfo->value.integer.min = 0;
3003 uinfo->value.integer.max = 100;
3004 uinfo->value.integer.step = 1;
3005
3006 return 0;
3007}
3008
3009static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3010 struct snd_ctl_elem_value *ucontrol)
3011{
3012 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3013 struct ca0132_spec *spec = codec->spec;
3014 hda_nid_t nid = get_amp_nid(kcontrol);
3015 long *valp = ucontrol->value.integer.value;
3016 int idx;
3017
3018 idx = nid - TUNING_CTL_START_NID;
3019 /* any change? */
3020 if (spec->cur_ctl_vals[idx] == *valp)
3021 return 0;
3022
3023 spec->cur_ctl_vals[idx] = *valp;
3024
3025 idx = *valp;
3026 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3027
3028 return 0;
3029}
3030
3031static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3032 struct snd_ctl_elem_info *uinfo)
3033{
3034 int chs = get_amp_channels(kcontrol);
3035 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3036 uinfo->count = chs == 3 ? 2 : 1;
3037 uinfo->value.integer.min = 0;
3038 uinfo->value.integer.max = 48;
3039 uinfo->value.integer.step = 1;
3040
3041 return 0;
3042}
3043
3044static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3045 struct snd_ctl_elem_value *ucontrol)
3046{
3047 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3048 struct ca0132_spec *spec = codec->spec;
3049 hda_nid_t nid = get_amp_nid(kcontrol);
3050 long *valp = ucontrol->value.integer.value;
3051 int idx;
3052
3053 idx = nid - TUNING_CTL_START_NID;
3054 /* any change? */
3055 if (spec->cur_ctl_vals[idx] == *valp)
3056 return 0;
3057
3058 spec->cur_ctl_vals[idx] = *valp;
3059
3060 idx = *valp;
3061 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3062
3063 return 1;
3064}
3065
3066static const DECLARE_TLV_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3067static const DECLARE_TLV_DB_SCALE(eq_db_scale, -2400, 100, 0);
3068
3069static int add_tuning_control(struct hda_codec *codec,
3070 hda_nid_t pnid, hda_nid_t nid,
3071 const char *name, int dir)
3072{
975cc02a 3073 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
44f0c978
IM		 3074 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3075 struct snd_kcontrol_new knew =
3076 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3077
3078 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3079 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3080 knew.tlv.c = 0;
3081 knew.tlv.p = 0;
3082 switch (pnid) {
3083 case VOICE_FOCUS:
3084 knew.info = voice_focus_ctl_info;
3085 knew.get = tuning_ctl_get;
3086 knew.put = voice_focus_ctl_put;
3087 knew.tlv.p = voice_focus_db_scale;
3088 break;
3089 case MIC_SVM:
3090 knew.info = mic_svm_ctl_info;
3091 knew.get = tuning_ctl_get;
3092 knew.put = mic_svm_ctl_put;
3093 break;
3094 case EQUALIZER:
3095 knew.info = equalizer_ctl_info;
3096 knew.get = tuning_ctl_get;
3097 knew.put = equalizer_ctl_put;
3098 knew.tlv.p = eq_db_scale;
3099 break;
3100 default:
3101 return 0;
3102 }
3103 knew.private_value =
3104 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3105 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3106 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3107}
3108
3109static int add_tuning_ctls(struct hda_codec *codec)
3110{
3111 int i;
3112 int err;
3113
3114 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3115 err = add_tuning_control(codec,
3116 ca0132_tuning_ctls[i].parent_nid,
3117 ca0132_tuning_ctls[i].nid,
3118 ca0132_tuning_ctls[i].name,
3119 ca0132_tuning_ctls[i].direct);
3120 if (err < 0)
3121 return err;
3122 }
3123
3124 return 0;
3125}
3126
3127static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3128{
3129 struct ca0132_spec *spec = codec->spec;
3130 int i;
3131
3132 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
3133 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3134 /* SVM level defaults to 0.74. */
3135 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3136
3137 /* EQ defaults to 0dB. */
3138 for (i = 2; i < TUNING_CTLS_COUNT; i++)
3139 spec->cur_ctl_vals[i] = 24;
3140}
3141#endif /*ENABLE_TUNING_CONTROLS*/
3142
5aaca44d
IM		 3143/*
3144 * Select the active output.
3145 * If autodetect is enabled, output will be selected based on jack detection.
3146 * If jack inserted, headphone will be selected, else built-in speakers
3147 * If autodetect is disabled, output will be selected based on selection.
3148 */
3149static int ca0132_select_out(struct hda_codec *codec)
3150{
3151 struct ca0132_spec *spec = codec->spec;
3152 unsigned int pin_ctl;
3153 int jack_present;
3154 int auto_jack;
3155 unsigned int tmp;
3156 int err;
3157
4e76a883 3158 codec_dbg(codec, "ca0132_select_out\n");
5aaca44d 3159
664c7155 3160 snd_hda_power_up_pm(codec);
5aaca44d
IM		 3161
3162 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3163
3164 if (auto_jack)
fe14f39e 3165 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
5aaca44d
IM		 3166 else
3167 jack_present =
3168 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3169
3170 if (jack_present)
3171 spec->cur_out_type = HEADPHONE_OUT;
3172 else
3173 spec->cur_out_type = SPEAKER_OUT;
3174
3175 if (spec->cur_out_type == SPEAKER_OUT) {
4e76a883 3176 codec_dbg(codec, "ca0132_select_out speaker\n");
5aaca44d
IM		 3177 /*speaker out config*/
3178 tmp = FLOAT_ONE;
3179 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3180 if (err < 0)
3181 goto exit;
3182 /*enable speaker EQ*/
3183 tmp = FLOAT_ONE;
3184 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3185 if (err < 0)
3186 goto exit;
3187
3188 /* Setup EAPD */
3189 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3190 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3191 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3192 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3193 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3194 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3195 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3196 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3197
3198 /* disable headphone node */
3199 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3200 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3201 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3202 pin_ctl & ~PIN_HP);
5aaca44d
IM		 3203 /* enable speaker node */
3204 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3205 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3206 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3207 pin_ctl | PIN_OUT);
5aaca44d 3208 } else {
4e76a883 3209 codec_dbg(codec, "ca0132_select_out hp\n");
5aaca44d
IM		 3210 /*headphone out config*/
3211 tmp = FLOAT_ZERO;
3212 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3213 if (err < 0)
3214 goto exit;
3215 /*disable speaker EQ*/
3216 tmp = FLOAT_ZERO;
3217 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3218 if (err < 0)
3219 goto exit;
3220
3221 /* Setup EAPD */
3222 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3223 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3224 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3225 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3226 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3227 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3228 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3229 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3230
3231 /* disable speaker*/
3232 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3233 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3234 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3235 pin_ctl & ~PIN_HP);
5aaca44d
IM		 3236 /* enable headphone*/
3237 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3238 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3239 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3240 pin_ctl | PIN_HP);
5aaca44d
IM		 3241 }
3242
3243exit:
664c7155 3244 snd_hda_power_down_pm(codec);
5aaca44d
IM		 3245
3246 return err < 0 ? err : 0;
3247}
3248
993884f6
CCC		 3249static void ca0132_unsol_hp_delayed(struct work_struct *work)
3250{
3251 struct ca0132_spec *spec = container_of(
3252 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
f8fb1170
TI		 3253 struct hda_jack_tbl *jack;
3254
993884f6 3255 ca0132_select_out(spec->codec);
d5c016b5 3256 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
f8fb1170
TI		 3257 if (jack) {
3258 jack->block_report = 0;
3259 snd_hda_jack_report_sync(spec->codec);
3260 }
993884f6
CCC		 3261}
3262
5aaca44d
IM		 3263static void ca0132_set_dmic(struct hda_codec *codec, int enable);
3264static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
3265static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
3266
3267/*
3268 * Select the active VIP source
3269 */
3270static int ca0132_set_vipsource(struct hda_codec *codec, int val)
3271{
3272 struct ca0132_spec *spec = codec->spec;
3273 unsigned int tmp;
3274
e8f1bd5d 3275 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 3276 return 0;
3277
3278 /* if CrystalVoice if off, vipsource should be 0 */
3279 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
3280 (val == 0)) {
3281 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
3282 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
3283 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
3284 if (spec->cur_mic_type == DIGITAL_MIC)
3285 tmp = FLOAT_TWO;
3286 else
3287 tmp = FLOAT_ONE;
3288 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3289 tmp = FLOAT_ZERO;
3290 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3291 } else {
3292 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
3293 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
3294 if (spec->cur_mic_type == DIGITAL_MIC)
3295 tmp = FLOAT_TWO;
3296 else
3297 tmp = FLOAT_ONE;
3298 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3299 tmp = FLOAT_ONE;
3300 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3301 msleep(20);
3302 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
3303 }
3304
3305 return 1;
3306}
3307
3308/*
3309 * Select the active microphone.
3310 * If autodetect is enabled, mic will be selected based on jack detection.
3311 * If jack inserted, ext.mic will be selected, else built-in mic
3312 * If autodetect is disabled, mic will be selected based on selection.
3313 */
3314static int ca0132_select_mic(struct hda_codec *codec)
3315{
3316 struct ca0132_spec *spec = codec->spec;
3317 int jack_present;
3318 int auto_jack;
3319
4e76a883 3320 codec_dbg(codec, "ca0132_select_mic\n");
5aaca44d 3321
664c7155 3322 snd_hda_power_up_pm(codec);
5aaca44d
IM		 3323
3324 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3325
3326 if (auto_jack)
fe14f39e 3327 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
5aaca44d
IM		 3328 else
3329 jack_present =
3330 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
3331
3332 if (jack_present)
3333 spec->cur_mic_type = LINE_MIC_IN;
3334 else
3335 spec->cur_mic_type = DIGITAL_MIC;
3336
3337 if (spec->cur_mic_type == DIGITAL_MIC) {
3338 /* enable digital Mic */
3339 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
3340 ca0132_set_dmic(codec, 1);
3341 ca0132_mic_boost_set(codec, 0);
3342 /* set voice focus */
3343 ca0132_effects_set(codec, VOICE_FOCUS,
3344 spec->effects_switch
3345 [VOICE_FOCUS - EFFECT_START_NID]);
3346 } else {
3347 /* disable digital Mic */
3348 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
3349 ca0132_set_dmic(codec, 0);
3350 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
3351 /* disable voice focus */
3352 ca0132_effects_set(codec, VOICE_FOCUS, 0);
3353 }
3354
664c7155 3355 snd_hda_power_down_pm(codec);
5aaca44d
IM		 3356
3357 return 0;
3358}
3359
a7e76271
IM		 3360/*
3361 * Check if VNODE settings take effect immediately.
3362 */
3363static bool ca0132_is_vnode_effective(struct hda_codec *codec,
3364 hda_nid_t vnid,
3365 hda_nid_t *shared_nid)
3366{
3367 struct ca0132_spec *spec = codec->spec;
3368 hda_nid_t nid;
a7e76271
IM		 3369
3370 switch (vnid) {
3371 case VNID_SPK:
3372 nid = spec->shared_out_nid;
a7e76271
IM		 3373 break;
3374 case VNID_MIC:
3375 nid = spec->shared_mic_nid;
a7e76271
IM		 3376 break;
3377 default:
9a0869f4 3378 return false;
a7e76271
IM		 3379 }
3380
9a0869f4 3381 if (shared_nid)
a7e76271
IM		 3382 *shared_nid = nid;
3383
9a0869f4 3384 return true;
a7e76271
IM		 3385}
3386
3387/*
3388* The following functions are control change helpers.
3389* They return 0 if no changed. Return 1 if changed.
3390*/
3391static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
3392{
3393 struct ca0132_spec *spec = codec->spec;
3394 unsigned int tmp;
3395
3396 /* based on CrystalVoice state to enable VoiceFX. */
3397 if (enable) {
3398 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
3399 FLOAT_ONE : FLOAT_ZERO;
3400 } else {
3401 tmp = FLOAT_ZERO;
3402 }
3403
3404 dspio_set_uint_param(codec, ca0132_voicefx.mid,
3405 ca0132_voicefx.reqs[0], tmp);
3406
3407 return 1;
3408}
3409
5aaca44d
IM		 3410/*
3411 * Set the effects parameters
3412 */
3413static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
3414{
3415 struct ca0132_spec *spec = codec->spec;
3416 unsigned int on;
3417 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3418 int err = 0;
3419 int idx = nid - EFFECT_START_NID;
3420
3421 if ((idx < 0) || (idx >= num_fx))
3422 return 0; /* no changed */
3423
3424 /* for out effect, qualify with PE */
3425 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
3426 /* if PE if off, turn off out effects. */
3427 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3428 val = 0;
3429 }
3430
3431 /* for in effect, qualify with CrystalVoice */
3432 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
3433 /* if CrystalVoice if off, turn off in effects. */
3434 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3435 val = 0;
3436
3437 /* Voice Focus applies to 2-ch Mic, Digital Mic */
3438 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
3439 val = 0;
3440 }
3441
4e76a883 3442 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5aaca44d
IM		 3443 nid, val);
3444
3445 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
3446 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
3447 ca0132_effects[idx].reqs[0], on);
3448
3449 if (err < 0)
3450 return 0; /* no changed */
3451
3452 return 1;
3453}
3454
a7e76271
IM		 3455/*
3456 * Turn on/off Playback Enhancements
3457 */
3458static int ca0132_pe_switch_set(struct hda_codec *codec)
3459{
3460 struct ca0132_spec *spec = codec->spec;
3461 hda_nid_t nid;
3462 int i, ret = 0;
3463
4e76a883 3464 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
a7e76271
IM		 3465 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
3466
3467 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
3468 nid = OUT_EFFECT_START_NID;
3469 /* PE affects all out effects */
3470 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
3471 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3472
3473 return ret;
3474}
3475
5aaca44d
IM		 3476/* Check if Mic1 is streaming, if so, stop streaming */
3477static int stop_mic1(struct hda_codec *codec)
3478{
3479 struct ca0132_spec *spec = codec->spec;
3480 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
3481 AC_VERB_GET_CONV, 0);
3482 if (oldval != 0)
3483 snd_hda_codec_write(codec, spec->adcs[0], 0,
3484 AC_VERB_SET_CHANNEL_STREAMID,
3485 0);
3486 return oldval;
3487}
3488
3489/* Resume Mic1 streaming if it was stopped. */
3490static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
3491{
3492 struct ca0132_spec *spec = codec->spec;
3493 /* Restore the previous stream and channel */
3494 if (oldval != 0)
3495 snd_hda_codec_write(codec, spec->adcs[0], 0,
3496 AC_VERB_SET_CHANNEL_STREAMID,
3497 oldval);
3498}
3499
3500/*
a7e76271 3501 * Turn on/off CrystalVoice
5aaca44d 3502 */
a7e76271
IM		 3503static int ca0132_cvoice_switch_set(struct hda_codec *codec)
3504{
3505 struct ca0132_spec *spec = codec->spec;
3506 hda_nid_t nid;
3507 int i, ret = 0;
3508 unsigned int oldval;
3509
4e76a883 3510 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
a7e76271
IM		 3511 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
3512
3513 i = IN_EFFECT_START_NID - EFFECT_START_NID;
3514 nid = IN_EFFECT_START_NID;
3515 /* CrystalVoice affects all in effects */
3516 for (; nid < IN_EFFECT_END_NID; nid++, i++)
3517 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3518
3519 /* including VoiceFX */
3520 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
3521
3522 /* set correct vipsource */
3523 oldval = stop_mic1(codec);
3524 ret |= ca0132_set_vipsource(codec, 1);
3525 resume_mic1(codec, oldval);
3526 return ret;
3527}
3528
5aaca44d
IM		 3529static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
3530{
3531 struct ca0132_spec *spec = codec->spec;
3532 int ret = 0;
3533
3534 if (val) /* on */
3535 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3536 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
3537 else /* off */
3538 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3539 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
3540
3541 return ret;
3542}
3543
a7e76271
IM		 3544static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
3545 struct snd_ctl_elem_value *ucontrol)
95c6e9cb 3546{
a7e76271
IM		 3547 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3548 hda_nid_t nid = get_amp_nid(kcontrol);
3549 hda_nid_t shared_nid = 0;
3550 bool effective;
3551 int ret = 0;
95c6e9cb 3552 struct ca0132_spec *spec = codec->spec;
a7e76271 3553 int auto_jack;
95c6e9cb 3554
a7e76271
IM		 3555 if (nid == VNID_HP_SEL) {
3556 auto_jack =
3557 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3558 if (!auto_jack)
3559 ca0132_select_out(codec);
3560 return 1;
3561 }
95c6e9cb 3562
a7e76271
IM		 3563 if (nid == VNID_AMIC1_SEL) {
3564 auto_jack =
3565 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3566 if (!auto_jack)
3567 ca0132_select_mic(codec);
3568 return 1;
3569 }
95c6e9cb 3570
a7e76271
IM		 3571 if (nid == VNID_HP_ASEL) {
3572 ca0132_select_out(codec);
3573 return 1;
3574 }
95c6e9cb 3575
a7e76271
IM		 3576 if (nid == VNID_AMIC1_ASEL) {
3577 ca0132_select_mic(codec);
3578 return 1;
95c6e9cb 3579 }
a7e76271
IM		 3580
3581 /* if effective conditions, then update hw immediately. */
3582 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3583 if (effective) {
3584 int dir = get_amp_direction(kcontrol);
3585 int ch = get_amp_channels(kcontrol);
3586 unsigned long pval;
3587
3588 mutex_lock(&codec->control_mutex);
3589 pval = kcontrol->private_value;
3590 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3591 0, dir);
3592 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
3593 kcontrol->private_value = pval;
3594 mutex_unlock(&codec->control_mutex);
95c6e9cb 3595 }
95c6e9cb 3596
a7e76271 3597 return ret;
95c6e9cb 3598}
a7e76271 3599/* End of control change helpers. */
95c6e9cb 3600
a7e76271
IM		 3601static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
3602 struct snd_ctl_elem_info *uinfo)
3603{
3604 unsigned int items = sizeof(ca0132_voicefx_presets)
3605 / sizeof(struct ct_voicefx_preset);
3606
3607 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3608 uinfo->count = 1;
3609 uinfo->value.enumerated.items = items;
3610 if (uinfo->value.enumerated.item >= items)
3611 uinfo->value.enumerated.item = items - 1;
3612 strcpy(uinfo->value.enumerated.name,
3613 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
3614 return 0;
3615}
95c6e9cb 3616
a7e76271 3617static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3618 struct snd_ctl_elem_value *ucontrol)
3619{
3620 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3621 struct ca0132_spec *spec = codec->spec;
95c6e9cb 3622
a7e76271 3623 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
95c6e9cb
IM		 3624 return 0;
3625}
3626
a7e76271 3627static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3628 struct snd_ctl_elem_value *ucontrol)
3629{
3630 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3631 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3632 int i, err = 0;
3633 int sel = ucontrol->value.enumerated.item[0];
3634 unsigned int items = sizeof(ca0132_voicefx_presets)
3635 / sizeof(struct ct_voicefx_preset);
95c6e9cb 3636
a7e76271 3637 if (sel >= items)
95c6e9cb
IM		 3638 return 0;
3639
4e76a883 3640 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
a7e76271 3641 sel, ca0132_voicefx_presets[sel].name);
95c6e9cb 3642
a7e76271
IM		 3643 /*
3644 * Idx 0 is default.
3645 * Default needs to qualify with CrystalVoice state.
3646 */
3647 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
3648 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
3649 ca0132_voicefx.reqs[i],
3650 ca0132_voicefx_presets[sel].vals[i]);
3651 if (err < 0)
3652 break;
3653 }
95c6e9cb 3654
a7e76271
IM		 3655 if (err >= 0) {
3656 spec->voicefx_val = sel;
3657 /* enable voice fx */
3658 ca0132_voicefx_set(codec, (sel ? 1 : 0));
3659 }
95c6e9cb 3660
a7e76271 3661 return 1;
95c6e9cb
IM		 3662}
3663
a7e76271
IM		 3664static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
3665 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 3666{
3667 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3668 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3669 hda_nid_t nid = get_amp_nid(kcontrol);
3670 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 3671 long *valp = ucontrol->value.integer.value;
3672
a7e76271
IM		 3673 /* vnode */
3674 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3675 if (ch & 1) {
3676 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
3677 valp++;
3678 }
3679 if (ch & 2) {
3680 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
3681 valp++;
3682 }
3683 return 0;
3684 }
3685
3686 /* effects, include PE and CrystalVoice */
3687 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
3688 *valp = spec->effects_switch[nid - EFFECT_START_NID];
3689 return 0;
3690 }
3691
3692 /* mic boost */
3693 if (nid == spec->input_pins[0]) {
3694 *valp = spec->cur_mic_boost;
3695 return 0;
3696 }
3697
95c6e9cb
IM		 3698 return 0;
3699}
3700
a7e76271
IM		 3701static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
3702 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 3703{
3704 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3705 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3706 hda_nid_t nid = get_amp_nid(kcontrol);
3707 int ch = get_amp_channels(kcontrol);
95c6e9cb 3708 long *valp = ucontrol->value.integer.value;
a7e76271 3709 int changed = 1;
95c6e9cb 3710
4e76a883 3711 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
a7e76271 3712 nid, *valp);
95c6e9cb
IM		 3713
3714 snd_hda_power_up(codec);
a7e76271
IM		 3715 /* vnode */
3716 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3717 if (ch & 1) {
3718 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
3719 valp++;
3720 }
3721 if (ch & 2) {
3722 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
3723 valp++;
3724 }
3725 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
3726 goto exit;
3727 }
95c6e9cb 3728
a7e76271
IM		 3729 /* PE */
3730 if (nid == PLAY_ENHANCEMENT) {
3731 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3732 changed = ca0132_pe_switch_set(codec);
b97f6bfd 3733 goto exit;
a7e76271 3734 }
95c6e9cb 3735
a7e76271
IM		 3736 /* CrystalVoice */
3737 if (nid == CRYSTAL_VOICE) {
3738 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3739 changed = ca0132_cvoice_switch_set(codec);
b97f6bfd 3740 goto exit;
a7e76271 3741 }
95c6e9cb 3742
a7e76271
IM		 3743 /* out and in effects */
3744 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
3745 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
3746 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3747 changed = ca0132_effects_set(codec, nid, *valp);
3748 goto exit;
3749 }
3750
3751 /* mic boost */
3752 if (nid == spec->input_pins[0]) {
3753 spec->cur_mic_boost = *valp;
3754
3755 /* Mic boost does not apply to Digital Mic */
3756 if (spec->cur_mic_type != DIGITAL_MIC)
3757 changed = ca0132_mic_boost_set(codec, *valp);
3758 goto exit;
3759 }
95c6e9cb 3760
a7e76271 3761exit:
95c6e9cb 3762 snd_hda_power_down(codec);
a7e76271 3763 return changed;
95c6e9cb
IM		 3764}
3765
a7e76271
IM		 3766/*
3767 * Volume related
3768 */
3769static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
3770 struct snd_ctl_elem_info *uinfo)
3771{
3772 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3773 struct ca0132_spec *spec = codec->spec;
3774 hda_nid_t nid = get_amp_nid(kcontrol);
3775 int ch = get_amp_channels(kcontrol);
3776 int dir = get_amp_direction(kcontrol);
3777 unsigned long pval;
3778 int err;
3779
3780 switch (nid) {
3781 case VNID_SPK:
3782 /* follow shared_out info */
3783 nid = spec->shared_out_nid;
3784 mutex_lock(&codec->control_mutex);
3785 pval = kcontrol->private_value;
3786 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3787 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3788 kcontrol->private_value = pval;
3789 mutex_unlock(&codec->control_mutex);
3790 break;
3791 case VNID_MIC:
3792 /* follow shared_mic info */
3793 nid = spec->shared_mic_nid;
3794 mutex_lock(&codec->control_mutex);
3795 pval = kcontrol->private_value;
3796 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3797 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3798 kcontrol->private_value = pval;
3799 mutex_unlock(&codec->control_mutex);
3800 break;
3801 default:
3802 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3803 }
3804 return err;
3805}
3806
3807static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3808 struct snd_ctl_elem_value *ucontrol)
3809{
3810 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3811 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3812 hda_nid_t nid = get_amp_nid(kcontrol);
3813 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 3814 long *valp = ucontrol->value.integer.value;
3815
a7e76271
IM		 3816 /* store the left and right volume */
3817 if (ch & 1) {
3818 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
3819 valp++;
3820 }
3821 if (ch & 2) {
3822 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
3823 valp++;
3824 }
95c6e9cb
IM		 3825 return 0;
3826}
3827
a7e76271 3828static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3829 struct snd_ctl_elem_value *ucontrol)
3830{
3831 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3832 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3833 hda_nid_t nid = get_amp_nid(kcontrol);
3834 int ch = get_amp_channels(kcontrol);
95c6e9cb 3835 long *valp = ucontrol->value.integer.value;
a7e76271
IM		 3836 hda_nid_t shared_nid = 0;
3837 bool effective;
3838 int changed = 1;
3839
3840 /* store the left and right volume */
3841 if (ch & 1) {
3842 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
3843 valp++;
3844 }
3845 if (ch & 2) {
3846 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
3847 valp++;
3848 }
95c6e9cb 3849
a7e76271
IM		 3850 /* if effective conditions, then update hw immediately. */
3851 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3852 if (effective) {
3853 int dir = get_amp_direction(kcontrol);
3854 unsigned long pval;
3855
3856 snd_hda_power_up(codec);
3857 mutex_lock(&codec->control_mutex);
3858 pval = kcontrol->private_value;
3859 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3860 0, dir);
3861 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
3862 kcontrol->private_value = pval;
3863 mutex_unlock(&codec->control_mutex);
3864 snd_hda_power_down(codec);
3865 }
95c6e9cb 3866
a7e76271 3867 return changed;
95c6e9cb
IM		 3868}
3869
a7e76271
IM		 3870static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
3871 unsigned int size, unsigned int __user *tlv)
95c6e9cb 3872{
a7e76271
IM		 3873 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3874 struct ca0132_spec *spec = codec->spec;
3875 hda_nid_t nid = get_amp_nid(kcontrol);
3876 int ch = get_amp_channels(kcontrol);
3877 int dir = get_amp_direction(kcontrol);
3878 unsigned long pval;
3879 int err;
3880
3881 switch (nid) {
3882 case VNID_SPK:
3883 /* follow shared_out tlv */
3884 nid = spec->shared_out_nid;
3885 mutex_lock(&codec->control_mutex);
3886 pval = kcontrol->private_value;
3887 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3888 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3889 kcontrol->private_value = pval;
3890 mutex_unlock(&codec->control_mutex);
3891 break;
3892 case VNID_MIC:
3893 /* follow shared_mic tlv */
3894 nid = spec->shared_mic_nid;
3895 mutex_lock(&codec->control_mutex);
3896 pval = kcontrol->private_value;
3897 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3898 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3899 kcontrol->private_value = pval;
3900 mutex_unlock(&codec->control_mutex);
3901 break;
3902 default:
3903 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3904 }
3905 return err;
95c6e9cb
IM		 3906}
3907
a7e76271
IM		 3908static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
3909 const char *pfx, int dir)
95c6e9cb 3910{
975cc02a 3911 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
a7e76271 3912 int type = dir ? HDA_INPUT : HDA_OUTPUT;
95c6e9cb 3913 struct snd_kcontrol_new knew =
a7e76271
IM		 3914 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
3915 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
95c6e9cb
IM		 3916 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3917}
3918
a7e76271 3919static int add_voicefx(struct hda_codec *codec)
95c6e9cb
IM		 3920{
3921 struct snd_kcontrol_new knew =
a7e76271
IM		 3922 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
3923 VOICEFX, 1, 0, HDA_INPUT);
3924 knew.info = ca0132_voicefx_info;
3925 knew.get = ca0132_voicefx_get;
3926 knew.put = ca0132_voicefx_put;
3927 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
95c6e9cb
IM		 3928}
3929
a7e76271
IM		 3930/*
3931 * When changing Node IDs for Mixer Controls below, make sure to update
3932 * Node IDs in ca0132_config() as well.
3933 */
3934static struct snd_kcontrol_new ca0132_mixer[] = {
3935 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
3936 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
3937 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
3938 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
3939 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
3940 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
3941 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
3942 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
3943 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
3944 0x12, 1, HDA_INPUT),
3945 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
3946 VNID_HP_SEL, 1, HDA_OUTPUT),
3947 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
3948 VNID_AMIC1_SEL, 1, HDA_INPUT),
3949 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
3950 VNID_HP_ASEL, 1, HDA_OUTPUT),
3951 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
3952 VNID_AMIC1_ASEL, 1, HDA_INPUT),
3953 { } /* end */
3954};
3955
e90f29e4
IM		 3956static int ca0132_build_controls(struct hda_codec *codec)
3957{
3958 struct ca0132_spec *spec = codec->spec;
3959 int i, num_fx;
3960 int err = 0;
3961
3962 /* Add Mixer controls */
3963 for (i = 0; i < spec->num_mixers; i++) {
3964 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
3965 if (err < 0)
3966 return err;
3967 }
3968
3969 /* Add in and out effects controls.
3970 * VoiceFX, PE and CrystalVoice are added separately.
3971 */
3972 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3973 for (i = 0; i < num_fx; i++) {
3974 err = add_fx_switch(codec, ca0132_effects[i].nid,
3975 ca0132_effects[i].name,
3976 ca0132_effects[i].direct);
3977 if (err < 0)
3978 return err;
3979 }
3980
3981 err = add_fx_switch(codec, PLAY_ENHANCEMENT, "PlayEnhancement", 0);
3982 if (err < 0)
3983 return err;
3984
3985 err = add_fx_switch(codec, CRYSTAL_VOICE, "CrystalVoice", 1);
3986 if (err < 0)
3987 return err;
3988
3989 add_voicefx(codec);
3990
3991#ifdef ENABLE_TUNING_CONTROLS
3992 add_tuning_ctls(codec);
3993#endif
3994
3995 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
3996 if (err < 0)
3997 return err;
3998
3999 if (spec->dig_out) {
4000 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
4001 spec->dig_out);
4002 if (err < 0)
4003 return err;
4004 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
4005 if (err < 0)
4006 return err;
4007 /* spec->multiout.share_spdif = 1; */
4008 }
4009
4010 if (spec->dig_in) {
4011 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
4012 if (err < 0)
4013 return err;
4014 }
4015 return 0;
4016}
4017
a7e76271 4018/*
e90f29e4 4019 * PCM
a7e76271 4020 */
071f1344 4021static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
a7e76271
IM		 4022 .substreams = 1,
4023 .channels_min = 2,
825315bc 4024 .channels_max = 6,
a7e76271 4025 .ops = {
a7e76271 4026 .prepare = ca0132_playback_pcm_prepare,
e8412ca4
DR		 4027 .cleanup = ca0132_playback_pcm_cleanup,
4028 .get_delay = ca0132_playback_pcm_delay,
a7e76271
IM		 4029 },
4030};
4031
071f1344 4032static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
a7e76271
IM		 4033 .substreams = 1,
4034 .channels_min = 2,
4035 .channels_max = 2,
825315bc
IM		 4036 .ops = {
4037 .prepare = ca0132_capture_pcm_prepare,
e8412ca4
DR		 4038 .cleanup = ca0132_capture_pcm_cleanup,
4039 .get_delay = ca0132_capture_pcm_delay,
825315bc 4040 },
a7e76271
IM		 4041};
4042
071f1344 4043static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
a7e76271
IM		 4044 .substreams = 1,
4045 .channels_min = 2,
4046 .channels_max = 2,
4047 .ops = {
4048 .open = ca0132_dig_playback_pcm_open,
4049 .close = ca0132_dig_playback_pcm_close,
4050 .prepare = ca0132_dig_playback_pcm_prepare,
4051 .cleanup = ca0132_dig_playback_pcm_cleanup
4052 },
4053};
4054
071f1344 4055static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
a7e76271
IM		 4056 .substreams = 1,
4057 .channels_min = 2,
4058 .channels_max = 2,
4059};
4060
4061static int ca0132_build_pcms(struct hda_codec *codec)
95c6e9cb
IM		 4062{
4063 struct ca0132_spec *spec = codec->spec;
bbbc7e85 4064 struct hda_pcm *info;
a7e76271 4065
bbbc7e85
TI		 4066 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
4067 if (!info)
4068 return -ENOMEM;
a7e76271
IM		 4069 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
4070 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
4071 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
4072 spec->multiout.max_channels;
4073 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
825315bc 4074 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
a7e76271 4075 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
a7e76271 4076
bbbc7e85
TI		 4077 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
4078 if (!info)
4079 return -ENOMEM;
825315bc
IM		 4080 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4081 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4082 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
825315bc 4083
bbbc7e85
TI		 4084 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
4085 if (!info)
4086 return -ENOMEM;
825315bc
IM		 4087 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4088 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4089 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
825315bc 4090
a7e76271
IM		 4091 if (!spec->dig_out && !spec->dig_in)
4092 return 0;
4093
bbbc7e85
TI		 4094 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
4095 if (!info)
4096 return -ENOMEM;
a7e76271
IM		 4097 info->pcm_type = HDA_PCM_TYPE_SPDIF;
4098 if (spec->dig_out) {
4099 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
4100 ca0132_pcm_digital_playback;
4101 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
4102 }
4103 if (spec->dig_in) {
4104 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
4105 ca0132_pcm_digital_capture;
4106 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
4107 }
95c6e9cb 4108
a7e76271 4109 return 0;
95c6e9cb
IM		 4110}
4111
441aa6a0
IM		 4112static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
4113{
4114 if (pin) {
a0c041cb 4115 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
441aa6a0
IM		 4116 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
4117 snd_hda_codec_write(codec, pin, 0,
4118 AC_VERB_SET_AMP_GAIN_MUTE,
4119 AMP_OUT_UNMUTE);
4120 }
4121 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
4122 snd_hda_codec_write(codec, dac, 0,
4123 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
4124}
4125
4126static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
4127{
4128 if (pin) {
a0c041cb 4129 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
441aa6a0
IM		 4130 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
4131 snd_hda_codec_write(codec, pin, 0,
4132 AC_VERB_SET_AMP_GAIN_MUTE,
4133 AMP_IN_UNMUTE(0));
4134 }
4135 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
4136 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
4137 AMP_IN_UNMUTE(0));
4138
4139 /* init to 0 dB and unmute. */
4140 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4141 HDA_AMP_VOLMASK, 0x5a);
4142 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4143 HDA_AMP_MUTE, 0);
4144 }
4145}
4146
5aaca44d
IM		 4147static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
4148{
4149 unsigned int caps;
4150
4151 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
4152 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
4153 snd_hda_override_amp_caps(codec, nid, dir, caps);
4154}
4155
4156/*
4157 * Switch between Digital built-in mic and analog mic.
4158 */
4159static void ca0132_set_dmic(struct hda_codec *codec, int enable)
4160{
4161 struct ca0132_spec *spec = codec->spec;
4162 unsigned int tmp;
4163 u8 val;
4164 unsigned int oldval;
4165
4e76a883 4166 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
5aaca44d
IM		 4167
4168 oldval = stop_mic1(codec);
4169 ca0132_set_vipsource(codec, 0);
4170 if (enable) {
4171 /* set DMic input as 2-ch */
4172 tmp = FLOAT_TWO;
4173 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4174
4175 val = spec->dmic_ctl;
4176 val |= 0x80;
4177 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4178 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4179
4180 if (!(spec->dmic_ctl & 0x20))
4181 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
4182 } else {
4183 /* set AMic input as mono */
4184 tmp = FLOAT_ONE;
4185 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4186
4187 val = spec->dmic_ctl;
4188 /* clear bit7 and bit5 to disable dmic */
4189 val &= 0x5f;
4190 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4191 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4192
4193 if (!(spec->dmic_ctl & 0x20))
4194 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
4195 }
4196 ca0132_set_vipsource(codec, 1);
4197 resume_mic1(codec, oldval);
4198}
4199
4200/*
4201 * Initialization for Digital Mic.
4202 */
4203static void ca0132_init_dmic(struct hda_codec *codec)
4204{
4205 struct ca0132_spec *spec = codec->spec;
4206 u8 val;
4207
4208 /* Setup Digital Mic here, but don't enable.
4209 * Enable based on jack detect.
4210 */
4211
4212 /* MCLK uses MPIO1, set to enable.
4213 * Bit 2-0: MPIO select
4214 * Bit 3: set to disable
4215 * Bit 7-4: reserved
4216 */
4217 val = 0x01;
4218 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4219 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
4220
4221 /* Data1 uses MPIO3. Data2 not use
4222 * Bit 2-0: Data1 MPIO select
4223 * Bit 3: set disable Data1
4224 * Bit 6-4: Data2 MPIO select
4225 * Bit 7: set disable Data2
4226 */
4227 val = 0x83;
4228 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4229 VENDOR_CHIPIO_DMIC_PIN_SET, val);
4230
4231 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
4232 * Bit 3-0: Channel mask
4233 * Bit 4: set for 48KHz, clear for 32KHz
4234 * Bit 5: mode
4235 * Bit 6: set to select Data2, clear for Data1
4236 * Bit 7: set to enable DMic, clear for AMic
4237 */
4238 val = 0x23;
4239 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
4240 spec->dmic_ctl = val;
4241 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4242 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4243}
4244
4245/*
4246 * Initialization for Analog Mic 2
4247 */
4248static void ca0132_init_analog_mic2(struct hda_codec *codec)
4249{
4250 struct ca0132_spec *spec = codec->spec;
4251
4252 mutex_lock(&spec->chipio_mutex);
4253 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4254 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
4255 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4256 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4257 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4258 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4259 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4260 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
4261 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4262 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4263 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4264 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4265 mutex_unlock(&spec->chipio_mutex);
4266}
4267
4268static void ca0132_refresh_widget_caps(struct hda_codec *codec)
4269{
4270 struct ca0132_spec *spec = codec->spec;
4271 int i;
5aaca44d 4272
4e76a883 4273 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
7639a06c 4274 snd_hda_codec_update_widgets(codec);
5aaca44d
IM		 4275
4276 for (i = 0; i < spec->multiout.num_dacs; i++)
4277 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
4278
4279 for (i = 0; i < spec->num_outputs; i++)
4280 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
4281
4282 for (i = 0; i < spec->num_inputs; i++) {
4283 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
4284 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
4285 }
4286}
4287
4288/*
4289 * Setup default parameters for DSP
4290 */
4291static void ca0132_setup_defaults(struct hda_codec *codec)
4292{
e8f1bd5d 4293 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 4294 unsigned int tmp;
4295 int num_fx;
4296 int idx, i;
4297
e8f1bd5d 4298 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 4299 return;
4300
4301 /* out, in effects + voicefx */
4302 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
4303 for (idx = 0; idx < num_fx; idx++) {
4304 for (i = 0; i <= ca0132_effects[idx].params; i++) {
4305 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4306 ca0132_effects[idx].reqs[i],
4307 ca0132_effects[idx].def_vals[i]);
4308 }
4309 }
4310
4311 /*remove DSP headroom*/
4312 tmp = FLOAT_ZERO;
4313 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
4314
4315 /*set speaker EQ bypass attenuation*/
4316 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
4317
4318 /* set AMic1 and AMic2 as mono mic */
4319 tmp = FLOAT_ONE;
4320 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4321 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
4322
4323 /* set AMic1 as CrystalVoice input */
4324 tmp = FLOAT_ONE;
4325 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4326
4327 /* set WUH source */
4328 tmp = FLOAT_TWO;
4329 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
4330}
4331
4332/*
4333 * Initialization of flags in chip
4334 */
4335static void ca0132_init_flags(struct hda_codec *codec)
4336{
4337 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
4338 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
4339 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
4340 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
4341 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
4342 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
4343}
4344
4345/*
4346 * Initialization of parameters in chip
4347 */
4348static void ca0132_init_params(struct hda_codec *codec)
4349{
4350 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
4351 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
4352}
95c6e9cb 4353
e90f29e4
IM		 4354static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
4355{
4356 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
4357 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
4358 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
4359 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
4360 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
4361 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
4362
406261ce
IM		 4363 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4364 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
e90f29e4
IM		 4365 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
4366}
4367
4368static bool ca0132_download_dsp_images(struct hda_codec *codec)
4369{
4370 bool dsp_loaded = false;
4371 const struct dsp_image_seg *dsp_os_image;
15e4ba66 4372 const struct firmware *fw_entry;
e90f29e4 4373
6efdd851 4374 if (request_firmware(&fw_entry, EFX_FILE, codec->card->dev) != 0)
e90f29e4
IM		 4375 return false;
4376
15e4ba66 4377 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
d1d28500 4378 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
d9684bb5 4379 codec_err(codec, "ca0132 DSP load image failed\n");
d1d28500
DR		 4380 goto exit_download;
4381 }
4382
e90f29e4
IM		 4383 dsp_loaded = dspload_wait_loaded(codec);
4384
d1d28500 4385exit_download:
15e4ba66
TI		 4386 release_firmware(fw_entry);
4387
e90f29e4
IM		 4388 return dsp_loaded;
4389}
4390
4391static void ca0132_download_dsp(struct hda_codec *codec)
4392{
4393 struct ca0132_spec *spec = codec->spec;
4394
9a0869f4
TI		 4395#ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
4396 return; /* NOP */
4397#endif
e90f29e4 4398
e24aa0a4
TI		 4399 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
4400 return; /* don't retry failures */
4401
b714a710
DR		 4402 chipio_enable_clocks(codec);
4403 spec->dsp_state = DSP_DOWNLOADING;
4404 if (!ca0132_download_dsp_images(codec))
4405 spec->dsp_state = DSP_DOWNLOAD_FAILED;
4406 else
4407 spec->dsp_state = DSP_DOWNLOADED;
e90f29e4
IM		 4408
4409 if (spec->dsp_state == DSP_DOWNLOADED)
4410 ca0132_set_dsp_msr(codec, true);
4411}
4412
f8fb1170
TI		 4413static void ca0132_process_dsp_response(struct hda_codec *codec,
4414 struct hda_jack_callback *callback)
e90f29e4
IM		 4415{
4416 struct ca0132_spec *spec = codec->spec;
4417
4e76a883 4418 codec_dbg(codec, "ca0132_process_dsp_response\n");
e90f29e4
IM		 4419 if (spec->wait_scp) {
4420 if (dspio_get_response_data(codec) >= 0)
4421 spec->wait_scp = 0;
4422 }
4423
4424 dspio_clear_response_queue(codec);
4425}
4426
f8fb1170 4427static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
e90f29e4 4428{
993884f6 4429 struct ca0132_spec *spec = codec->spec;
2ebab40e 4430 struct hda_jack_tbl *tbl;
e90f29e4 4431
f8fb1170
TI		 4432 /* Delay enabling the HP amp, to let the mic-detection
4433 * state machine run.
4434 */
4435 cancel_delayed_work_sync(&spec->unsol_hp_work);
2f35c630 4436 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
2ebab40e
TI		 4437 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
4438 if (tbl)
4439 tbl->block_report = 1;
f8fb1170
TI		 4440}
4441
4442static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
4443{
4444 ca0132_select_mic(codec);
4445}
4446
4447static void ca0132_init_unsol(struct hda_codec *codec)
4448{
d5c016b5
GM		 4449 struct ca0132_spec *spec = codec->spec;
4450 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
4451 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
f8fb1170
TI		 4452 amic_callback);
4453 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
4454 ca0132_process_dsp_response);
e90f29e4
IM		 4455}
4456
5aaca44d
IM		 4457/*
4458 * Verbs tables.
4459 */
4460
4461/* Sends before DSP download. */
4462static struct hda_verb ca0132_base_init_verbs[] = {
4463 /*enable ct extension*/
4464 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
5aaca44d
IM		 4465 {}
4466};
4467
4468/* Send at exit. */
4469static struct hda_verb ca0132_base_exit_verbs[] = {
4470 /*set afg to D3*/
4471 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
4472 /*disable ct extension*/
4473 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
4474 {}
4475};
4476
4477/* Other verbs tables. Sends after DSP download. */
4478static struct hda_verb ca0132_init_verbs0[] = {
4479 /* chip init verbs */
4480 {0x15, 0x70D, 0xF0},
4481 {0x15, 0x70E, 0xFE},
4482 {0x15, 0x707, 0x75},
4483 {0x15, 0x707, 0xD3},
4484 {0x15, 0x707, 0x09},
4485 {0x15, 0x707, 0x53},
4486 {0x15, 0x707, 0xD4},
4487 {0x15, 0x707, 0xEF},
4488 {0x15, 0x707, 0x75},
4489 {0x15, 0x707, 0xD3},
4490 {0x15, 0x707, 0x09},
4491 {0x15, 0x707, 0x02},
4492 {0x15, 0x707, 0x37},
4493 {0x15, 0x707, 0x78},
4494 {0x15, 0x53C, 0xCE},
4495 {0x15, 0x575, 0xC9},
4496 {0x15, 0x53D, 0xCE},
4497 {0x15, 0x5B7, 0xC9},
4498 {0x15, 0x70D, 0xE8},
4499 {0x15, 0x70E, 0xFE},
4500 {0x15, 0x707, 0x02},
4501 {0x15, 0x707, 0x68},
4502 {0x15, 0x707, 0x62},
4503 {0x15, 0x53A, 0xCE},
4504 {0x15, 0x546, 0xC9},
4505 {0x15, 0x53B, 0xCE},
4506 {0x15, 0x5E8, 0xC9},
4507 {0x15, 0x717, 0x0D},
4508 {0x15, 0x718, 0x20},
4509 {}
4510};
4511
95c6e9cb
IM		 4512static void ca0132_init_chip(struct hda_codec *codec)
4513{
4514 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 4515 int num_fx;
4516 int i;
4517 unsigned int on;
95c6e9cb
IM		 4518
4519 mutex_init(&spec->chipio_mutex);
5aaca44d
IM		 4520
4521 spec->cur_out_type = SPEAKER_OUT;
4522 spec->cur_mic_type = DIGITAL_MIC;
4523 spec->cur_mic_boost = 0;
4524
4525 for (i = 0; i < VNODES_COUNT; i++) {
4526 spec->vnode_lvol[i] = 0x5a;
4527 spec->vnode_rvol[i] = 0x5a;
4528 spec->vnode_lswitch[i] = 0;
4529 spec->vnode_rswitch[i] = 0;
4530 }
4531
4532 /*
4533 * Default states for effects are in ca0132_effects[].
4534 */
4535 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4536 for (i = 0; i < num_fx; i++) {
4537 on = (unsigned int)ca0132_effects[i].reqs[0];
4538 spec->effects_switch[i] = on ? 1 : 0;
4539 }
4540
4541 spec->voicefx_val = 0;
4542 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
4543 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
4544
44f0c978
IM		 4545#ifdef ENABLE_TUNING_CONTROLS
4546 ca0132_init_tuning_defaults(codec);
4547#endif
95c6e9cb
IM		 4548}
4549
4550static void ca0132_exit_chip(struct hda_codec *codec)
4551{
4552 /* put any chip cleanup stuffs here. */
5aaca44d
IM		 4553
4554 if (dspload_is_loaded(codec))
4555 dsp_reset(codec);
95c6e9cb
IM		 4556}
4557
4558static int ca0132_init(struct hda_codec *codec)
4559{
4560 struct ca0132_spec *spec = codec->spec;
4561 struct auto_pin_cfg *cfg = &spec->autocfg;
4562 int i;
4563
e24aa0a4
TI		 4564 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
4565 spec->dsp_state = DSP_DOWNLOAD_INIT;
4a8b89f9 4566 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
5aaca44d 4567
664c7155 4568 snd_hda_power_up_pm(codec);
5aaca44d 4569
f8fb1170
TI		 4570 ca0132_init_unsol(codec);
4571
5aaca44d
IM		 4572 ca0132_init_params(codec);
4573 ca0132_init_flags(codec);
4574 snd_hda_sequence_write(codec, spec->base_init_verbs);
01ef7dbf 4575 ca0132_download_dsp(codec);
5aaca44d
IM		 4576 ca0132_refresh_widget_caps(codec);
4577 ca0132_setup_defaults(codec);
4578 ca0132_init_analog_mic2(codec);
4579 ca0132_init_dmic(codec);
4580
4581 for (i = 0; i < spec->num_outputs; i++)
4582 init_output(codec, spec->out_pins[i], spec->dacs[0]);
01ef7dbf 4583
95c6e9cb
IM		 4584 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
4585
4586 for (i = 0; i < spec->num_inputs; i++)
4587 init_input(codec, spec->input_pins[i], spec->adcs[i]);
4588
4589 init_input(codec, cfg->dig_in_pin, spec->dig_in);
4590
d5c016b5
GM		 4591 snd_hda_sequence_write(codec, spec->chip_init_verbs);
4592 snd_hda_sequence_write(codec, spec->spec_init_verbs);
5aaca44d
IM		 4593
4594 ca0132_select_out(codec);
4595 ca0132_select_mic(codec);
4596
a73d511c
IM		 4597 snd_hda_jack_report_sync(codec);
4598
664c7155 4599 snd_hda_power_down_pm(codec);
95c6e9cb
IM		 4600
4601 return 0;
4602}
4603
95c6e9cb
IM		 4604static void ca0132_free(struct hda_codec *codec)
4605{
5aaca44d
IM		 4606 struct ca0132_spec *spec = codec->spec;
4607
993884f6 4608 cancel_delayed_work_sync(&spec->unsol_hp_work);
5aaca44d
IM		 4609 snd_hda_power_up(codec);
4610 snd_hda_sequence_write(codec, spec->base_exit_verbs);
95c6e9cb 4611 ca0132_exit_chip(codec);
5aaca44d 4612 snd_hda_power_down(codec);
d5c016b5 4613 kfree(spec->spec_init_verbs);
95c6e9cb
IM		 4614 kfree(codec->spec);
4615}
4616
071f1344 4617static const struct hda_codec_ops ca0132_patch_ops = {
95c6e9cb
IM		 4618 .build_controls = ca0132_build_controls,
4619 .build_pcms = ca0132_build_pcms,
4620 .init = ca0132_init,
4621 .free = ca0132_free,
f8fb1170 4622 .unsol_event = snd_hda_jack_unsol_event,
95c6e9cb
IM		 4623};
4624
441aa6a0
IM		 4625static void ca0132_config(struct hda_codec *codec)
4626{
4627 struct ca0132_spec *spec = codec->spec;
4628 struct auto_pin_cfg *cfg = &spec->autocfg;
4629
4630 spec->dacs[0] = 0x2;
4631 spec->dacs[1] = 0x3;
4632 spec->dacs[2] = 0x4;
4633
4634 spec->multiout.dac_nids = spec->dacs;
4635 spec->multiout.num_dacs = 3;
4636 spec->multiout.max_channels = 2;
4637
d5c016b5
GM		 4638 if (spec->quirk == QUIRK_ALIENWARE) {
4639 codec_dbg(codec, "ca0132_config: QUIRK_ALIENWARE applied.\n");
fe14f39e
TI		 4640 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
4641
4642 spec->num_outputs = 2;
4643 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 4644 spec->out_pins[1] = 0x0f;
fe14f39e
TI		 4645 spec->shared_out_nid = 0x2;
4646 spec->unsol_tag_hp = 0x0f;
4647
4648 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4649 spec->adcs[1] = 0x8; /* analog mic2 */
4650 spec->adcs[2] = 0xa; /* what u hear */
4651
4652 spec->num_inputs = 3;
4653 spec->input_pins[0] = 0x12;
4654 spec->input_pins[1] = 0x11;
4655 spec->input_pins[2] = 0x13;
4656 spec->shared_mic_nid = 0x7;
4657 spec->unsol_tag_amic1 = 0x11;
4658 } else {
4659 spec->num_outputs = 2;
4660 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 4661 spec->out_pins[1] = 0x10; /* headphone out */
fe14f39e
TI		 4662 spec->shared_out_nid = 0x2;
4663 spec->unsol_tag_hp = spec->out_pins[1];
4664
4665 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4666 spec->adcs[1] = 0x8; /* analog mic2 */
4667 spec->adcs[2] = 0xa; /* what u hear */
4668
4669 spec->num_inputs = 3;
4670 spec->input_pins[0] = 0x12;
4671 spec->input_pins[1] = 0x11;
4672 spec->input_pins[2] = 0x13;
4673 spec->shared_mic_nid = 0x7;
4674 spec->unsol_tag_amic1 = spec->input_pins[0];
4675
4676 /* SPDIF I/O */
4677 spec->dig_out = 0x05;
4678 spec->multiout.dig_out_nid = spec->dig_out;
4679 cfg->dig_out_pins[0] = 0x0c;
4680 cfg->dig_outs = 1;
4681 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
4682 spec->dig_in = 0x09;
4683 cfg->dig_in_pin = 0x0e;
4684 cfg->dig_in_type = HDA_PCM_TYPE_SPDIF;
d5c016b5 4685 }
441aa6a0
IM		 4686}
4687
d5c016b5
GM		 4688static int ca0132_prepare_verbs(struct hda_codec *codec)
4689{
4690/* Verbs + terminator (an empty element) */
4691#define NUM_SPEC_VERBS 4
4692 struct ca0132_spec *spec = codec->spec;
4693
4694 spec->chip_init_verbs = ca0132_init_verbs0;
4695 spec->spec_init_verbs = kzalloc(sizeof(struct hda_verb) * NUM_SPEC_VERBS, GFP_KERNEL);
4696 if (!spec->spec_init_verbs)
4697 return -ENOMEM;
4698
4699 /* HP jack autodetection */
4700 spec->spec_init_verbs[0].nid = spec->unsol_tag_hp;
4701 spec->spec_init_verbs[0].param = AC_VERB_SET_UNSOLICITED_ENABLE;
4702 spec->spec_init_verbs[0].verb = AC_USRSP_EN | spec->unsol_tag_hp;
4703
4704 /* MIC1 jack autodetection */
4705 spec->spec_init_verbs[1].nid = spec->unsol_tag_amic1;
4706 spec->spec_init_verbs[1].param = AC_VERB_SET_UNSOLICITED_ENABLE;
4707 spec->spec_init_verbs[1].verb = AC_USRSP_EN | spec->unsol_tag_amic1;
4708
4709 /* config EAPD */
4710 spec->spec_init_verbs[2].nid = 0x0b;
4711 spec->spec_init_verbs[2].param = 0x78D;
4712 spec->spec_init_verbs[2].verb = 0x00;
4713
4714 /* Previously commented configuration */
4715 /*
4716 spec->spec_init_verbs[3].nid = 0x0b;
4717 spec->spec_init_verbs[3].param = AC_VERB_SET_EAPD_BTLENABLE;
4718 spec->spec_init_verbs[3].verb = 0x02;
4719
4720 spec->spec_init_verbs[4].nid = 0x10;
4721 spec->spec_init_verbs[4].param = 0x78D;
4722 spec->spec_init_verbs[4].verb = 0x02;
4723
4724 spec->spec_init_verbs[5].nid = 0x10;
4725 spec->spec_init_verbs[5].param = AC_VERB_SET_EAPD_BTLENABLE;
4726 spec->spec_init_verbs[5].verb = 0x02;
4727 */
4728
4729 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
4730 return 0;
4731}
4732
95c6e9cb
IM		 4733static int patch_ca0132(struct hda_codec *codec)
4734{
4735 struct ca0132_spec *spec;
a73d511c 4736 int err;
d5c016b5 4737 const struct snd_pci_quirk *quirk;
95c6e9cb 4738
4e76a883 4739 codec_dbg(codec, "patch_ca0132\n");
95c6e9cb
IM		 4740
4741 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
4742 if (!spec)
4743 return -ENOMEM;
4744 codec->spec = spec;
993884f6 4745 spec->codec = codec;
95c6e9cb 4746
225068ab
TI		 4747 codec->patch_ops = ca0132_patch_ops;
4748 codec->pcm_format_first = 1;
4749 codec->no_sticky_stream = 1;
4750
d5c016b5
GM		 4751 /* Detect codec quirk */
4752 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
4753 if (quirk)
4754 spec->quirk = quirk->value;
4755 else
4756 spec->quirk = QUIRK_NONE;
4757
e24aa0a4 4758 spec->dsp_state = DSP_DOWNLOAD_INIT;
a7e76271
IM		 4759 spec->num_mixers = 1;
4760 spec->mixers[0] = ca0132_mixer;
4761
5aaca44d
IM		 4762 spec->base_init_verbs = ca0132_base_init_verbs;
4763 spec->base_exit_verbs = ca0132_base_exit_verbs;
5aaca44d 4764
993884f6
CCC		 4765 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
4766
95c6e9cb
IM		 4767 ca0132_init_chip(codec);
4768
4769 ca0132_config(codec);
4770
d5c016b5
GM		 4771 err = ca0132_prepare_verbs(codec);
4772 if (err < 0)
4773 return err;
4774
a73d511c
IM		 4775 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
4776 if (err < 0)
4777 return err;
4778
95c6e9cb
IM		 4779 return 0;
4780}
4781
4782/*
4783 * patch entries
4784 */
b9a94a9c
TI		 4785static struct hda_device_id snd_hda_id_ca0132[] = {
4786 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
95c6e9cb
IM		 4787 {} /* terminator */
4788};
b9a94a9c 4789MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
95c6e9cb
IM		 4790
4791MODULE_LICENSE("GPL");
406261ce 4792MODULE_DESCRIPTION("Creative Sound Core3D codec");
95c6e9cb 4793
d8a766a1 4794static struct hda_codec_driver ca0132_driver = {
b9a94a9c 4795 .id = snd_hda_id_ca0132,
95c6e9cb
IM		 4796};
4797
d8a766a1 4798module_hda_codec_driver(ca0132_driver);
Linux kernel - Deliverables
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