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ALSA: hda - hdmi: Set infoframe and channel mapping even without sink
[deliverable/linux.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
5a613584 9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
079d88cc
WF		 10 *
11 * Authors:
12 * Wu Fengguang <wfg@linux.intel.com>
13 *
14 * Maintained by:
15 * Wu Fengguang <wfg@linux.intel.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 * for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
84eb01be
TI		 32#include <linux/init.h>
33#include <linux/delay.h>
34#include <linux/slab.h>
65a77217 35#include <linux/module.h>
84eb01be 36#include <sound/core.h>
07acecc1 37#include <sound/jack.h>
433968da 38#include <sound/asoundef.h>
d45e6889 39#include <sound/tlv.h>
84eb01be
TI		 40#include "hda_codec.h"
41#include "hda_local.h"
1835a0f9 42#include "hda_jack.h"
84eb01be 43
0ebaa24c
TI		 44static bool static_hdmi_pcm;
45module_param(static_hdmi_pcm, bool, 0644);
46MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
47
fb87fa3a 48#define is_haswell(codec) ((codec)->vendor_id == 0x80862807)
75dcbe4d
ML		 49#define is_broadwell(codec) ((codec)->vendor_id == 0x80862808)
50#define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec))
51
02383854 52#define is_valleyview(codec) ((codec)->vendor_id == 0x80862882)
fb87fa3a 53
384a48d7
SW		 54struct hdmi_spec_per_cvt {
55 hda_nid_t cvt_nid;
56 int assigned;
57 unsigned int channels_min;
58 unsigned int channels_max;
59 u32 rates;
60 u64 formats;
61 unsigned int maxbps;
62};
079d88cc 63
4eea3091
TI		 64/* max. connections to a widget */
65#define HDA_MAX_CONNECTIONS 32
66
384a48d7
SW		 67struct hdmi_spec_per_pin {
68 hda_nid_t pin_nid;
69 int num_mux_nids;
70 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
2df6742f 71 int mux_idx;
1df5a06a 72 hda_nid_t cvt_nid;
744626da
WF		 73
74 struct hda_codec *codec;
384a48d7 75 struct hdmi_eld sink_eld;
a4e9a38b 76 struct mutex lock;
744626da 77 struct delayed_work work;
92c69e79 78 struct snd_kcontrol *eld_ctl;
c6e8453e 79 int repoll_count;
b054087d
TI		 80 bool setup; /* the stream has been set up by prepare callback */
81 int channels; /* current number of channels */
1a6003b5 82 bool non_pcm;
d45e6889
TI		 83 bool chmap_set; /* channel-map override by ALSA API? */
84 unsigned char chmap[8]; /* ALSA API channel-map */
bce0d2a8 85 char pcm_name[8]; /* filled in build_pcm callbacks */
a4e9a38b
TI		 86#ifdef CONFIG_PROC_FS
87 struct snd_info_entry *proc_entry;
88#endif
384a48d7 89};
079d88cc 90
307229d2
AH		 91struct cea_channel_speaker_allocation;
92
93/* operations used by generic code that can be overridden by patches */
94struct hdmi_ops {
95 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
96 unsigned char *buf, int *eld_size);
97
98 /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
99 int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
100 int asp_slot);
101 int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
102 int asp_slot, int channel);
103
104 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
105 int ca, int active_channels, int conn_type);
106
107 /* enable/disable HBR (HD passthrough) */
108 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
109
110 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
111 hda_nid_t pin_nid, u32 stream_tag, int format);
112
113 /* Helpers for producing the channel map TLVs. These can be overridden
114 * for devices that have non-standard mapping requirements. */
115 int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap,
116 int channels);
117 void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap,
118 unsigned int *chmap, int channels);
119
120 /* check that the user-given chmap is supported */
121 int (*chmap_validate)(int ca, int channels, unsigned char *chmap);
122};
123
384a48d7
SW		 124struct hdmi_spec {
125 int num_cvts;
bce0d2a8
TI		 126 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
127 hda_nid_t cvt_nids[4]; /* only for haswell fix */
079d88cc 128
384a48d7 129 int num_pins;
bce0d2a8
TI		 130 struct snd_array pins; /* struct hdmi_spec_per_pin */
131 struct snd_array pcm_rec; /* struct hda_pcm */
d45e6889 132 unsigned int channels_max; /* max over all cvts */
079d88cc 133
4bd038f9 134 struct hdmi_eld temp_eld;
307229d2 135 struct hdmi_ops ops;
75fae117
SW		 136
137 bool dyn_pin_out;
138
079d88cc 139 /*
5a613584 140 * Non-generic VIA/NVIDIA specific
079d88cc
WF		 141 */
142 struct hda_multi_out multiout;
d0b1252d 143 struct hda_pcm_stream pcm_playback;
079d88cc
WF		 144};
145
146
147struct hdmi_audio_infoframe {
148 u8 type; /* 0x84 */
149 u8 ver; /* 0x01 */
150 u8 len; /* 0x0a */
151
53d7d69d
WF		 152 u8 checksum;
153
079d88cc
WF		 154 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
155 u8 SS01_SF24;
156 u8 CXT04;
157 u8 CA;
158 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 159};
160
161struct dp_audio_infoframe {
162 u8 type; /* 0x84 */
163 u8 len; /* 0x1b */
164 u8 ver; /* 0x11 << 2 */
165
166 u8 CC02_CT47; /* match with HDMI infoframe from this on */
167 u8 SS01_SF24;
168 u8 CXT04;
169 u8 CA;
170 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 171};
172
2b203dbb
TI		 173union audio_infoframe {
174 struct hdmi_audio_infoframe hdmi;
175 struct dp_audio_infoframe dp;
176 u8 bytes[0];
177};
178
079d88cc
WF		 179/*
180 * CEA speaker placement:
181 *
182 * FLH FCH FRH
183 * FLW FL FLC FC FRC FR FRW
184 *
185 * LFE
186 * TC
187 *
188 * RL RLC RC RRC RR
189 *
190 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
191 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
192 */
193enum cea_speaker_placement {
194 FL = (1 << 0), /* Front Left */
195 FC = (1 << 1), /* Front Center */
196 FR = (1 << 2), /* Front Right */
197 FLC = (1 << 3), /* Front Left Center */
198 FRC = (1 << 4), /* Front Right Center */
199 RL = (1 << 5), /* Rear Left */
200 RC = (1 << 6), /* Rear Center */
201 RR = (1 << 7), /* Rear Right */
202 RLC = (1 << 8), /* Rear Left Center */
203 RRC = (1 << 9), /* Rear Right Center */
204 LFE = (1 << 10), /* Low Frequency Effect */
205 FLW = (1 << 11), /* Front Left Wide */
206 FRW = (1 << 12), /* Front Right Wide */
207 FLH = (1 << 13), /* Front Left High */
208 FCH = (1 << 14), /* Front Center High */
209 FRH = (1 << 15), /* Front Right High */
210 TC = (1 << 16), /* Top Center */
211};
212
213/*
214 * ELD SA bits in the CEA Speaker Allocation data block
215 */
216static int eld_speaker_allocation_bits[] = {
217 [0] = FL | FR,
218 [1] = LFE,
219 [2] = FC,
220 [3] = RL | RR,
221 [4] = RC,
222 [5] = FLC | FRC,
223 [6] = RLC | RRC,
224 /* the following are not defined in ELD yet */
225 [7] = FLW | FRW,
226 [8] = FLH | FRH,
227 [9] = TC,
228 [10] = FCH,
229};
230
231struct cea_channel_speaker_allocation {
232 int ca_index;
233 int speakers[8];
234
235 /* derived values, just for convenience */
236 int channels;
237 int spk_mask;
238};
239
240/*
241 * ALSA sequence is:
242 *
243 * surround40 surround41 surround50 surround51 surround71
244 * ch0 front left = = = =
245 * ch1 front right = = = =
246 * ch2 rear left = = = =
247 * ch3 rear right = = = =
248 * ch4 LFE center center center
249 * ch5 LFE LFE
250 * ch6 side left
251 * ch7 side right
252 *
253 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
254 */
255static int hdmi_channel_mapping[0x32][8] = {
256 /* stereo */
257 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
258 /* 2.1 */
259 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
260 /* Dolby Surround */
261 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
262 /* surround40 */
263 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
264 /* 4ch */
265 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
266 /* surround41 */
9396d317 267 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 268 /* surround50 */
269 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
270 /* surround51 */
271 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
272 /* 7.1 */
273 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
274};
275
276/*
277 * This is an ordered list!
278 *
279 * The preceding ones have better chances to be selected by
53d7d69d 280 * hdmi_channel_allocation().
079d88cc
WF		 281 */
282static struct cea_channel_speaker_allocation channel_allocations[] = {
283/* channel: 7 6 5 4 3 2 1 0 */
284{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
285 /* 2.1 */
286{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
287 /* Dolby Surround */
288{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
289 /* surround40 */
290{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
291 /* surround41 */
292{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
293 /* surround50 */
294{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
295 /* surround51 */
296{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
297 /* 6.1 */
298{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
299 /* surround71 */
300{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
301
302{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
303{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
304{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
305{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
306{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
307{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
308{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
309{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
310{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
311{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
312{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
313{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
314{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
315{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
316{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
317{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
318{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
319{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
320{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
321{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
322{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
323{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
324{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
325{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
326{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
327{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
328{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
329{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
330{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
331{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
332{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
333{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
334{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
335{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
336{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
337{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
338{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
339{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
340{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
341{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
342{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
343};
344
345
346/*
347 * HDMI routines
348 */
349
bce0d2a8
TI		 350#define get_pin(spec, idx) \
351 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
352#define get_cvt(spec, idx) \
353 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
354#define get_pcm_rec(spec, idx) \
355 ((struct hda_pcm *)snd_array_elem(&spec->pcm_rec, idx))
356
4e76a883 357static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc 358{
4e76a883 359 struct hdmi_spec *spec = codec->spec;
384a48d7 360 int pin_idx;
079d88cc 361
384a48d7 362 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 363 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
384a48d7 364 return pin_idx;
079d88cc 365
4e76a883 366 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
384a48d7
SW		 367 return -EINVAL;
368}
369
4e76a883 370static int hinfo_to_pin_index(struct hda_codec *codec,
384a48d7
SW		 371 struct hda_pcm_stream *hinfo)
372{
4e76a883 373 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 374 int pin_idx;
375
376 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 377 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
384a48d7
SW		 378 return pin_idx;
379
4e76a883 380 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
384a48d7
SW		 381 return -EINVAL;
382}
383
4e76a883 384static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
384a48d7 385{
4e76a883 386 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 387 int cvt_idx;
388
389 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
bce0d2a8 390 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
384a48d7
SW		 391 return cvt_idx;
392
4e76a883 393 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 394 return -EINVAL;
395}
396
14bc52b8
PLB		 397static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
398 struct snd_ctl_elem_info *uinfo)
399{
400 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 401 struct hdmi_spec *spec = codec->spec;
a4e9a38b 402 struct hdmi_spec_per_pin *per_pin;
68e03de9 403 struct hdmi_eld *eld;
14bc52b8
PLB		 404 int pin_idx;
405
14bc52b8
PLB		 406 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
407
408 pin_idx = kcontrol->private_value;
a4e9a38b
TI		 409 per_pin = get_pin(spec, pin_idx);
410 eld = &per_pin->sink_eld;
68e03de9 411
a4e9a38b 412 mutex_lock(&per_pin->lock);
68e03de9 413 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
a4e9a38b 414 mutex_unlock(&per_pin->lock);
14bc52b8
PLB		 415
416 return 0;
417}
418
419static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
420 struct snd_ctl_elem_value *ucontrol)
421{
422 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 423 struct hdmi_spec *spec = codec->spec;
a4e9a38b 424 struct hdmi_spec_per_pin *per_pin;
68e03de9 425 struct hdmi_eld *eld;
14bc52b8
PLB		 426 int pin_idx;
427
14bc52b8 428 pin_idx = kcontrol->private_value;
a4e9a38b
TI		 429 per_pin = get_pin(spec, pin_idx);
430 eld = &per_pin->sink_eld;
68e03de9 431
a4e9a38b 432 mutex_lock(&per_pin->lock);
68e03de9 433 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
a4e9a38b 434 mutex_unlock(&per_pin->lock);
68e03de9
DH		 435 snd_BUG();
436 return -EINVAL;
437 }
438
439 memset(ucontrol->value.bytes.data, 0,
440 ARRAY_SIZE(ucontrol->value.bytes.data));
441 if (eld->eld_valid)
442 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
443 eld->eld_size);
a4e9a38b 444 mutex_unlock(&per_pin->lock);
14bc52b8
PLB		 445
446 return 0;
447}
448
449static struct snd_kcontrol_new eld_bytes_ctl = {
450 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
451 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
452 .name = "ELD",
453 .info = hdmi_eld_ctl_info,
454 .get = hdmi_eld_ctl_get,
455};
456
457static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
458 int device)
459{
460 struct snd_kcontrol *kctl;
461 struct hdmi_spec *spec = codec->spec;
462 int err;
463
464 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
465 if (!kctl)
466 return -ENOMEM;
467 kctl->private_value = pin_idx;
468 kctl->id.device = device;
469
bce0d2a8 470 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
14bc52b8
PLB		 471 if (err < 0)
472 return err;
473
bce0d2a8 474 get_pin(spec, pin_idx)->eld_ctl = kctl;
14bc52b8
PLB		 475 return 0;
476}
477
079d88cc
WF		 478#ifdef BE_PARANOID
479static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
480 int *packet_index, int *byte_index)
481{
482 int val;
483
484 val = snd_hda_codec_read(codec, pin_nid, 0,
485 AC_VERB_GET_HDMI_DIP_INDEX, 0);
486
487 *packet_index = val >> 5;
488 *byte_index = val & 0x1f;
489}
490#endif
491
492static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
493 int packet_index, int byte_index)
494{
495 int val;
496
497 val = (packet_index << 5) | (byte_index & 0x1f);
498
499 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
500}
501
502static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
503 unsigned char val)
504{
505 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
506}
507
384a48d7 508static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc 509{
75fae117
SW		 510 struct hdmi_spec *spec = codec->spec;
511 int pin_out;
512
079d88cc
WF		 513 /* Unmute */
514 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
515 snd_hda_codec_write(codec, pin_nid, 0,
516 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
75fae117
SW		 517
518 if (spec->dyn_pin_out)
519 /* Disable pin out until stream is active */
520 pin_out = 0;
521 else
522 /* Enable pin out: some machines with GM965 gets broken output
523 * when the pin is disabled or changed while using with HDMI
524 */
525 pin_out = PIN_OUT;
526
079d88cc 527 snd_hda_codec_write(codec, pin_nid, 0,
75fae117 528 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
079d88cc
WF		 529}
530
384a48d7 531static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc 532{
384a48d7 533 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
079d88cc
WF		 534 AC_VERB_GET_CVT_CHAN_COUNT, 0);
535}
536
537static void hdmi_set_channel_count(struct hda_codec *codec,
384a48d7 538 hda_nid_t cvt_nid, int chs)
079d88cc 539{
384a48d7
SW		 540 if (chs != hdmi_get_channel_count(codec, cvt_nid))
541 snd_hda_codec_write(codec, cvt_nid, 0,
079d88cc
WF		 542 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
543}
544
a4e9a38b
TI		 545/*
546 * ELD proc files
547 */
548
549#ifdef CONFIG_PROC_FS
550static void print_eld_info(struct snd_info_entry *entry,
551 struct snd_info_buffer *buffer)
552{
553 struct hdmi_spec_per_pin *per_pin = entry->private_data;
554
555 mutex_lock(&per_pin->lock);
556 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
557 mutex_unlock(&per_pin->lock);
558}
559
560static void write_eld_info(struct snd_info_entry *entry,
561 struct snd_info_buffer *buffer)
562{
563 struct hdmi_spec_per_pin *per_pin = entry->private_data;
564
565 mutex_lock(&per_pin->lock);
566 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
567 mutex_unlock(&per_pin->lock);
568}
569
570static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
571{
572 char name[32];
573 struct hda_codec *codec = per_pin->codec;
574 struct snd_info_entry *entry;
575 int err;
576
577 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
578 err = snd_card_proc_new(codec->bus->card, name, &entry);
579 if (err < 0)
580 return err;
581
582 snd_info_set_text_ops(entry, per_pin, print_eld_info);
583 entry->c.text.write = write_eld_info;
584 entry->mode |= S_IWUSR;
585 per_pin->proc_entry = entry;
586
587 return 0;
588}
589
590static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
591{
592 if (!per_pin->codec->bus->shutdown && per_pin->proc_entry) {
593 snd_device_free(per_pin->codec->bus->card, per_pin->proc_entry);
594 per_pin->proc_entry = NULL;
595 }
596}
597#else
b55447a7
TI		 598static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
599 int index)
a4e9a38b
TI		 600{
601 return 0;
602}
b55447a7 603static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
a4e9a38b
TI		 604{
605}
606#endif
079d88cc
WF		 607
608/*
609 * Channel mapping routines
610 */
611
612/*
613 * Compute derived values in channel_allocations[].
614 */
615static void init_channel_allocations(void)
616{
617 int i, j;
618 struct cea_channel_speaker_allocation *p;
619
620 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
621 p = channel_allocations + i;
622 p->channels = 0;
623 p->spk_mask = 0;
624 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
625 if (p->speakers[j]) {
626 p->channels++;
627 p->spk_mask |= p->speakers[j];
628 }
629 }
630}
631
72357c78
WX		 632static int get_channel_allocation_order(int ca)
633{
634 int i;
635
636 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
637 if (channel_allocations[i].ca_index == ca)
638 break;
639 }
640 return i;
641}
642
079d88cc
WF		 643/*
644 * The transformation takes two steps:
645 *
646 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
647 * spk_mask => (channel_allocations[]) => ai->CA
648 *
649 * TODO: it could select the wrong CA from multiple candidates.
650*/
384a48d7 651static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
079d88cc 652{
079d88cc 653 int i;
53d7d69d 654 int ca = 0;
079d88cc 655 int spk_mask = 0;
079d88cc
WF		 656 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
657
658 /*
659 * CA defaults to 0 for basic stereo audio
660 */
661 if (channels <= 2)
662 return 0;
663
079d88cc
WF		 664 /*
665 * expand ELD's speaker allocation mask
666 *
667 * ELD tells the speaker mask in a compact(paired) form,
668 * expand ELD's notions to match the ones used by Audio InfoFrame.
669 */
670 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
1613d6b4 671 if (eld->info.spk_alloc & (1 << i))
079d88cc
WF		 672 spk_mask |= eld_speaker_allocation_bits[i];
673 }
674
675 /* search for the first working match in the CA table */
676 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
677 if (channels == channel_allocations[i].channels &&
678 (spk_mask & channel_allocations[i].spk_mask) ==
679 channel_allocations[i].spk_mask) {
53d7d69d 680 ca = channel_allocations[i].ca_index;
079d88cc
WF		 681 break;
682 }
683 }
684
18e39186
AH		 685 if (!ca) {
686 /* if there was no match, select the regular ALSA channel
687 * allocation with the matching number of channels */
688 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
689 if (channels == channel_allocations[i].channels) {
690 ca = channel_allocations[i].ca_index;
691 break;
692 }
693 }
694 }
695
1613d6b4 696 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
2abbf439 697 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 698 ca, channels, buf);
079d88cc 699
53d7d69d 700 return ca;
079d88cc
WF		 701}
702
703static void hdmi_debug_channel_mapping(struct hda_codec *codec,
704 hda_nid_t pin_nid)
705{
706#ifdef CONFIG_SND_DEBUG_VERBOSE
307229d2 707 struct hdmi_spec *spec = codec->spec;
079d88cc 708 int i;
307229d2 709 int channel;
079d88cc
WF		 710
711 for (i = 0; i < 8; i++) {
307229d2 712 channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i);
4e76a883 713 codec_dbg(codec, "HDMI: ASP channel %d => slot %d\n",
307229d2 714 channel, i);
079d88cc
WF		 715 }
716#endif
717}
718
d45e6889 719static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
079d88cc 720 hda_nid_t pin_nid,
433968da 721 bool non_pcm,
53d7d69d 722 int ca)
079d88cc 723{
307229d2 724 struct hdmi_spec *spec = codec->spec;
90f28002 725 struct cea_channel_speaker_allocation *ch_alloc;
079d88cc 726 int i;
079d88cc 727 int err;
72357c78 728 int order;
433968da 729 int non_pcm_mapping[8];
079d88cc 730
72357c78 731 order = get_channel_allocation_order(ca);
90f28002 732 ch_alloc = &channel_allocations[order];
433968da 733
079d88cc 734 if (hdmi_channel_mapping[ca][1] == 0) {
90f28002
AH		 735 int hdmi_slot = 0;
736 /* fill actual channel mappings in ALSA channel (i) order */
737 for (i = 0; i < ch_alloc->channels; i++) {
738 while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
739 hdmi_slot++; /* skip zero slots */
740
741 hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
742 }
743 /* fill the rest of the slots with ALSA channel 0xf */
744 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
745 if (!ch_alloc->speakers[7 - hdmi_slot])
746 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
079d88cc
WF		 747 }
748
433968da 749 if (non_pcm) {
90f28002 750 for (i = 0; i < ch_alloc->channels; i++)
11f7c52d 751 non_pcm_mapping[i] = (i << 4) | i;
433968da 752 for (; i < 8; i++)
11f7c52d 753 non_pcm_mapping[i] = (0xf << 4) | i;
433968da
WX		 754 }
755
079d88cc 756 for (i = 0; i < 8; i++) {
307229d2
AH		 757 int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i];
758 int hdmi_slot = slotsetup & 0x0f;
759 int channel = (slotsetup & 0xf0) >> 4;
760 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel);
079d88cc 761 if (err) {
4e76a883 762 codec_dbg(codec, "HDMI: channel mapping failed\n");
079d88cc
WF		 763 break;
764 }
765 }
079d88cc
WF		 766}
767
d45e6889
TI		 768struct channel_map_table {
769 unsigned char map; /* ALSA API channel map position */
d45e6889
TI		 770 int spk_mask; /* speaker position bit mask */
771};
772
773static struct channel_map_table map_tables[] = {
a5b7d510
AH		 774 { SNDRV_CHMAP_FL, FL },
775 { SNDRV_CHMAP_FR, FR },
776 { SNDRV_CHMAP_RL, RL },
777 { SNDRV_CHMAP_RR, RR },
778 { SNDRV_CHMAP_LFE, LFE },
779 { SNDRV_CHMAP_FC, FC },
780 { SNDRV_CHMAP_RLC, RLC },
781 { SNDRV_CHMAP_RRC, RRC },
782 { SNDRV_CHMAP_RC, RC },
783 { SNDRV_CHMAP_FLC, FLC },
784 { SNDRV_CHMAP_FRC, FRC },
94908a39
AH		 785 { SNDRV_CHMAP_TFL, FLH },
786 { SNDRV_CHMAP_TFR, FRH },
a5b7d510
AH		 787 { SNDRV_CHMAP_FLW, FLW },
788 { SNDRV_CHMAP_FRW, FRW },
789 { SNDRV_CHMAP_TC, TC },
94908a39 790 { SNDRV_CHMAP_TFC, FCH },
d45e6889
TI		 791 {} /* terminator */
792};
793
794/* from ALSA API channel position to speaker bit mask */
795static int to_spk_mask(unsigned char c)
796{
797 struct channel_map_table *t = map_tables;
798 for (; t->map; t++) {
799 if (t->map == c)
800 return t->spk_mask;
801 }
802 return 0;
803}
804
805/* from ALSA API channel position to CEA slot */
a5b7d510 806static int to_cea_slot(int ordered_ca, unsigned char pos)
d45e6889 807{
a5b7d510
AH		 808 int mask = to_spk_mask(pos);
809 int i;
d45e6889 810
a5b7d510
AH		 811 if (mask) {
812 for (i = 0; i < 8; i++) {
813 if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
814 return i;
815 }
d45e6889 816 }
a5b7d510
AH		 817
818 return -1;
d45e6889
TI		 819}
820
821/* from speaker bit mask to ALSA API channel position */
822static int spk_to_chmap(int spk)
823{
824 struct channel_map_table *t = map_tables;
825 for (; t->map; t++) {
826 if (t->spk_mask == spk)
827 return t->map;
828 }
829 return 0;
830}
831
a5b7d510
AH		 832/* from CEA slot to ALSA API channel position */
833static int from_cea_slot(int ordered_ca, unsigned char slot)
834{
835 int mask = channel_allocations[ordered_ca].speakers[7 - slot];
836
837 return spk_to_chmap(mask);
838}
839
d45e6889
TI		 840/* get the CA index corresponding to the given ALSA API channel map */
841static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
842{
843 int i, spks = 0, spk_mask = 0;
844
845 for (i = 0; i < chs; i++) {
846 int mask = to_spk_mask(map[i]);
847 if (mask) {
848 spk_mask |= mask;
849 spks++;
850 }
851 }
852
853 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
854 if ((chs == channel_allocations[i].channels ||
855 spks == channel_allocations[i].channels) &&
856 (spk_mask & channel_allocations[i].spk_mask) ==
857 channel_allocations[i].spk_mask)
858 return channel_allocations[i].ca_index;
859 }
860 return -1;
861}
862
863/* set up the channel slots for the given ALSA API channel map */
864static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
865 hda_nid_t pin_nid,
a5b7d510
AH		 866 int chs, unsigned char *map,
867 int ca)
d45e6889 868{
307229d2 869 struct hdmi_spec *spec = codec->spec;
a5b7d510 870 int ordered_ca = get_channel_allocation_order(ca);
11f7c52d
AH		 871 int alsa_pos, hdmi_slot;
872 int assignments[8] = {[0 ... 7] = 0xf};
873
874 for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
875
a5b7d510 876 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
11f7c52d
AH		 877
878 if (hdmi_slot < 0)
879 continue; /* unassigned channel */
880
881 assignments[hdmi_slot] = alsa_pos;
882 }
883
884 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
307229d2 885 int err;
11f7c52d 886
307229d2
AH		 887 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot,
888 assignments[hdmi_slot]);
d45e6889
TI		 889 if (err)
890 return -EINVAL;
891 }
892 return 0;
893}
894
895/* store ALSA API channel map from the current default map */
896static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
897{
898 int i;
56cac413 899 int ordered_ca = get_channel_allocation_order(ca);
d45e6889 900 for (i = 0; i < 8; i++) {
56cac413 901 if (i < channel_allocations[ordered_ca].channels)
a5b7d510 902 map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
d45e6889
TI		 903 else
904 map[i] = 0;
905 }
906}
907
908static void hdmi_setup_channel_mapping(struct hda_codec *codec,
909 hda_nid_t pin_nid, bool non_pcm, int ca,
20608731
AH		 910 int channels, unsigned char *map,
911 bool chmap_set)
d45e6889 912{
20608731 913 if (!non_pcm && chmap_set) {
d45e6889 914 hdmi_manual_setup_channel_mapping(codec, pin_nid,
a5b7d510 915 channels, map, ca);
d45e6889
TI		 916 } else {
917 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
918 hdmi_setup_fake_chmap(map, ca);
919 }
980b2495
AH		 920
921 hdmi_debug_channel_mapping(codec, pin_nid);
d45e6889 922}
079d88cc 923
307229d2
AH		 924static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
925 int asp_slot, int channel)
926{
927 return snd_hda_codec_write(codec, pin_nid, 0,
928 AC_VERB_SET_HDMI_CHAN_SLOT,
929 (channel << 4) | asp_slot);
930}
931
932static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
933 int asp_slot)
934{
935 return (snd_hda_codec_read(codec, pin_nid, 0,
936 AC_VERB_GET_HDMI_CHAN_SLOT,
937 asp_slot) & 0xf0) >> 4;
938}
939
079d88cc
WF		 940/*
941 * Audio InfoFrame routines
942 */
943
944/*
945 * Enable Audio InfoFrame Transmission
946 */
947static void hdmi_start_infoframe_trans(struct hda_codec *codec,
948 hda_nid_t pin_nid)
949{
950 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
951 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
952 AC_DIPXMIT_BEST);
953}
954
955/*
956 * Disable Audio InfoFrame Transmission
957 */
958static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
959 hda_nid_t pin_nid)
960{
961 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
962 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
963 AC_DIPXMIT_DISABLE);
964}
965
966static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
967{
968#ifdef CONFIG_SND_DEBUG_VERBOSE
969 int i;
970 int size;
971
972 size = snd_hdmi_get_eld_size(codec, pin_nid);
4e76a883 973 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
079d88cc
WF		 974
975 for (i = 0; i < 8; i++) {
976 size = snd_hda_codec_read(codec, pin_nid, 0,
977 AC_VERB_GET_HDMI_DIP_SIZE, i);
4e76a883 978 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
079d88cc
WF		 979 }
980#endif
981}
982
983static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
984{
985#ifdef BE_PARANOID
986 int i, j;
987 int size;
988 int pi, bi;
989 for (i = 0; i < 8; i++) {
990 size = snd_hda_codec_read(codec, pin_nid, 0,
991 AC_VERB_GET_HDMI_DIP_SIZE, i);
992 if (size == 0)
993 continue;
994
995 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
996 for (j = 1; j < 1000; j++) {
997 hdmi_write_dip_byte(codec, pin_nid, 0x0);
998 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
999 if (pi != i)
4e76a883 1000 codec_dbg(codec, "dip index %d: %d != %d\n",
079d88cc
WF		 1001 bi, pi, i);
1002 if (bi == 0) /* byte index wrapped around */
1003 break;
1004 }
4e76a883 1005 codec_dbg(codec,
079d88cc
WF		 1006 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
1007 i, size, j);
1008 }
1009#endif
1010}
1011
53d7d69d 1012static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 1013{
53d7d69d 1014 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 1015 u8 sum = 0;
1016 int i;
1017
53d7d69d 1018 hdmi_ai->checksum = 0;
079d88cc 1019
53d7d69d 1020 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 1021 sum += bytes[i];
1022
53d7d69d 1023 hdmi_ai->checksum = -sum;
079d88cc
WF		 1024}
1025
1026static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
1027 hda_nid_t pin_nid,
53d7d69d 1028 u8 *dip, int size)
079d88cc 1029{
079d88cc
WF		 1030 int i;
1031
1032 hdmi_debug_dip_size(codec, pin_nid);
1033 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
1034
079d88cc 1035 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 1036 for (i = 0; i < size; i++)
1037 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 1038}
1039
1040static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 1041 u8 *dip, int size)
079d88cc 1042{
079d88cc
WF		 1043 u8 val;
1044 int i;
1045
1046 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
1047 != AC_DIPXMIT_BEST)
1048 return false;
1049
1050 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 1051 for (i = 0; i < size; i++) {
079d88cc
WF		 1052 val = snd_hda_codec_read(codec, pin_nid, 0,
1053 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 1054 if (val != dip[i])
079d88cc
WF		 1055 return false;
1056 }
1057
1058 return true;
1059}
1060
307229d2
AH		 1061static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
1062 hda_nid_t pin_nid,
1063 int ca, int active_channels,
1064 int conn_type)
1065{
1066 union audio_infoframe ai;
1067
caaf5ef9 1068 memset(&ai, 0, sizeof(ai));
307229d2
AH		 1069 if (conn_type == 0) { /* HDMI */
1070 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
1071
1072 hdmi_ai->type = 0x84;
1073 hdmi_ai->ver = 0x01;
1074 hdmi_ai->len = 0x0a;
1075 hdmi_ai->CC02_CT47 = active_channels - 1;
1076 hdmi_ai->CA = ca;
1077 hdmi_checksum_audio_infoframe(hdmi_ai);
1078 } else if (conn_type == 1) { /* DisplayPort */
1079 struct dp_audio_infoframe *dp_ai = &ai.dp;
1080
1081 dp_ai->type = 0x84;
1082 dp_ai->len = 0x1b;
1083 dp_ai->ver = 0x11 << 2;
1084 dp_ai->CC02_CT47 = active_channels - 1;
1085 dp_ai->CA = ca;
1086 } else {
4e76a883 1087 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
307229d2
AH		 1088 pin_nid);
1089 return;
1090 }
1091
1092 /*
1093 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
1094 * sizeof(*dp_ai) to avoid partial match/update problems when
1095 * the user switches between HDMI/DP monitors.
1096 */
1097 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
1098 sizeof(ai))) {
4e76a883
TI		 1099 codec_dbg(codec,
1100 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
307229d2
AH		 1101 pin_nid,
1102 active_channels, ca);
1103 hdmi_stop_infoframe_trans(codec, pin_nid);
1104 hdmi_fill_audio_infoframe(codec, pin_nid,
1105 ai.bytes, sizeof(ai));
1106 hdmi_start_infoframe_trans(codec, pin_nid);
1107 }
1108}
1109
b054087d
TI		 1110static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
1111 struct hdmi_spec_per_pin *per_pin,
1112 bool non_pcm)
079d88cc 1113{
307229d2 1114 struct hdmi_spec *spec = codec->spec;
384a48d7 1115 hda_nid_t pin_nid = per_pin->pin_nid;
b054087d 1116 int channels = per_pin->channels;
1df5a06a 1117 int active_channels;
384a48d7 1118 struct hdmi_eld *eld;
1df5a06a 1119 int ca, ordered_ca;
079d88cc 1120
b054087d
TI		 1121 if (!channels)
1122 return;
1123
75dcbe4d 1124 if (is_haswell_plus(codec))
58f7d28d
ML		 1125 snd_hda_codec_write(codec, pin_nid, 0,
1126 AC_VERB_SET_AMP_GAIN_MUTE,
1127 AMP_OUT_UNMUTE);
1128
bce0d2a8 1129 eld = &per_pin->sink_eld;
079d88cc 1130
d45e6889
TI		 1131 if (!non_pcm && per_pin->chmap_set)
1132 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
1133 else
1134 ca = hdmi_channel_allocation(eld, channels);
1135 if (ca < 0)
1136 ca = 0;
384a48d7 1137
1df5a06a
AH		 1138 ordered_ca = get_channel_allocation_order(ca);
1139 active_channels = channel_allocations[ordered_ca].channels;
1140
1141 hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
1142
39edac70
AH		 1143 /*
1144 * always configure channel mapping, it may have been changed by the
1145 * user in the meantime
1146 */
1147 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
1148 channels, per_pin->chmap,
1149 per_pin->chmap_set);
1150
307229d2
AH		 1151 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
1152 eld->info.conn_type);
433968da 1153
1a6003b5 1154 per_pin->non_pcm = non_pcm;
079d88cc
WF		 1155}
1156
079d88cc
WF		 1157/*
1158 * Unsolicited events
1159 */
1160
efe47108 1161static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 1162
20ce9029 1163static void jack_callback(struct hda_codec *codec, struct hda_jack_tbl *jack)
079d88cc
WF		 1164{
1165 struct hdmi_spec *spec = codec->spec;
4e76a883 1166 int pin_idx = pin_nid_to_pin_index(codec, jack->nid);
20ce9029
DH		 1167 if (pin_idx < 0)
1168 return;
1169
1170 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
1171 snd_hda_jack_report_sync(codec);
1172}
1173
1174static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1175{
3a93897e 1176 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
3a93897e 1177 struct hda_jack_tbl *jack;
2e59e5ab 1178 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
3a93897e
TI		 1179
1180 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1181 if (!jack)
1182 return;
3a93897e 1183 jack->jack_dirty = 1;
079d88cc 1184
4e76a883 1185 codec_dbg(codec,
2e59e5ab 1186 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
20ce9029 1187 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
fae3d88a 1188 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 1189
20ce9029 1190 jack_callback(codec, jack);
079d88cc
WF		 1191}
1192
1193static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1194{
1195 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1196 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1197 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1198 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1199
4e76a883 1200 codec_info(codec,
e9ea8e8f 1201 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 1202 codec->addr,
079d88cc
WF		 1203 tag,
1204 subtag,
1205 cp_state,
1206 cp_ready);
1207
1208 /* TODO */
1209 if (cp_state)
1210 ;
1211 if (cp_ready)
1212 ;
1213}
1214
1215
1216static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1217{
079d88cc
WF		 1218 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1219 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1220
3a93897e 1221 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
4e76a883 1222 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
079d88cc
WF		 1223 return;
1224 }
1225
1226 if (subtag == 0)
1227 hdmi_intrinsic_event(codec, res);
1228 else
1229 hdmi_non_intrinsic_event(codec, res);
1230}
1231
58f7d28d 1232static void haswell_verify_D0(struct hda_codec *codec,
53b434f0 1233 hda_nid_t cvt_nid, hda_nid_t nid)
83f26ad2 1234{
58f7d28d 1235 int pwr;
83f26ad2 1236
53b434f0
WX		 1237 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1238 * thus pins could only choose converter 0 for use. Make sure the
1239 * converters are in correct power state */
fd678cac 1240 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
53b434f0
WX		 1241 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1242
fd678cac 1243 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
83f26ad2
DH		 1244 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1245 AC_PWRST_D0);
1246 msleep(40);
1247 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1248 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
4e76a883 1249 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
83f26ad2 1250 }
83f26ad2
DH		 1251}
1252
079d88cc
WF		 1253/*
1254 * Callbacks
1255 */
1256
92f10b3f
TI		 1257/* HBR should be Non-PCM, 8 channels */
1258#define is_hbr_format(format) \
1259 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1260
307229d2
AH		 1261static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
1262 bool hbr)
079d88cc 1263{
307229d2 1264 int pinctl, new_pinctl;
83f26ad2 1265
384a48d7
SW		 1266 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1267 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 1268 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1269
13122e6e
AH		 1270 if (pinctl < 0)
1271 return hbr ? -EINVAL : 0;
1272
ea87d1c4 1273 new_pinctl = pinctl & ~AC_PINCTL_EPT;
307229d2 1274 if (hbr)
ea87d1c4
AH		 1275 new_pinctl |= AC_PINCTL_EPT_HBR;
1276 else
1277 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1278
4e76a883
TI		 1279 codec_dbg(codec,
1280 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
384a48d7 1281 pin_nid,
ea87d1c4
AH		 1282 pinctl == new_pinctl ? "" : "new-",
1283 new_pinctl);
1284
1285 if (pinctl != new_pinctl)
384a48d7 1286 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 1287 AC_VERB_SET_PIN_WIDGET_CONTROL,
1288 new_pinctl);
307229d2
AH		 1289 } else if (hbr)
1290 return -EINVAL;
ea87d1c4 1291
307229d2
AH		 1292 return 0;
1293}
1294
1295static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1296 hda_nid_t pin_nid, u32 stream_tag, int format)
1297{
1298 struct hdmi_spec *spec = codec->spec;
1299 int err;
1300
75dcbe4d 1301 if (is_haswell_plus(codec))
307229d2
AH		 1302 haswell_verify_D0(codec, cvt_nid, pin_nid);
1303
1304 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
1305
1306 if (err) {
4e76a883 1307 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
307229d2 1308 return err;
ea87d1c4 1309 }
079d88cc 1310
384a48d7 1311 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 1312 return 0;
079d88cc
WF		 1313}
1314
7ef166b8
WX		 1315static int hdmi_choose_cvt(struct hda_codec *codec,
1316 int pin_idx, int *cvt_id, int *mux_id)
bbbe3390
TI		 1317{
1318 struct hdmi_spec *spec = codec->spec;
384a48d7 1319 struct hdmi_spec_per_pin *per_pin;
384a48d7 1320 struct hdmi_spec_per_cvt *per_cvt = NULL;
7ef166b8 1321 int cvt_idx, mux_idx = 0;
bbbe3390 1322
bce0d2a8 1323 per_pin = get_pin(spec, pin_idx);
384a48d7
SW		 1324
1325 /* Dynamically assign converter to stream */
1326 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
bce0d2a8 1327 per_cvt = get_cvt(spec, cvt_idx);
bbbe3390 1328
384a48d7
SW		 1329 /* Must not already be assigned */
1330 if (per_cvt->assigned)
1331 continue;
1332 /* Must be in pin's mux's list of converters */
1333 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1334 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1335 break;
1336 /* Not in mux list */
1337 if (mux_idx == per_pin->num_mux_nids)
1338 continue;
1339 break;
1340 }
7ef166b8 1341
384a48d7
SW		 1342 /* No free converters */
1343 if (cvt_idx == spec->num_cvts)
1344 return -ENODEV;
1345
2df6742f
ML		 1346 per_pin->mux_idx = mux_idx;
1347
7ef166b8
WX		 1348 if (cvt_id)
1349 *cvt_id = cvt_idx;
1350 if (mux_id)
1351 *mux_id = mux_idx;
1352
1353 return 0;
1354}
1355
2df6742f
ML		 1356/* Assure the pin select the right convetor */
1357static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1358 struct hdmi_spec_per_pin *per_pin)
1359{
1360 hda_nid_t pin_nid = per_pin->pin_nid;
1361 int mux_idx, curr;
1362
1363 mux_idx = per_pin->mux_idx;
1364 curr = snd_hda_codec_read(codec, pin_nid, 0,
1365 AC_VERB_GET_CONNECT_SEL, 0);
1366 if (curr != mux_idx)
1367 snd_hda_codec_write_cache(codec, pin_nid, 0,
1368 AC_VERB_SET_CONNECT_SEL,
1369 mux_idx);
1370}
1371
300016b9
ML		 1372/* Intel HDMI workaround to fix audio routing issue:
1373 * For some Intel display codecs, pins share the same connection list.
1374 * So a conveter can be selected by multiple pins and playback on any of these
1375 * pins will generate sound on the external display, because audio flows from
1376 * the same converter to the display pipeline. Also muting one pin may make
1377 * other pins have no sound output.
1378 * So this function assures that an assigned converter for a pin is not selected
1379 * by any other pins.
1380 */
1381static void intel_not_share_assigned_cvt(struct hda_codec *codec,
f82d7d16 1382 hda_nid_t pin_nid, int mux_idx)
7ef166b8
WX		 1383{
1384 struct hdmi_spec *spec = codec->spec;
f82d7d16
ML		 1385 hda_nid_t nid, end_nid;
1386 int cvt_idx, curr;
1387 struct hdmi_spec_per_cvt *per_cvt;
7ef166b8 1388
f82d7d16
ML		 1389 /* configure all pins, including "no physical connection" ones */
1390 end_nid = codec->start_nid + codec->num_nodes;
1391 for (nid = codec->start_nid; nid < end_nid; nid++) {
1392 unsigned int wid_caps = get_wcaps(codec, nid);
1393 unsigned int wid_type = get_wcaps_type(wid_caps);
1394
1395 if (wid_type != AC_WID_PIN)
1396 continue;
7ef166b8 1397
f82d7d16 1398 if (nid == pin_nid)
7ef166b8
WX		 1399 continue;
1400
f82d7d16 1401 curr = snd_hda_codec_read(codec, nid, 0,
7ef166b8 1402 AC_VERB_GET_CONNECT_SEL, 0);
f82d7d16
ML		 1403 if (curr != mux_idx)
1404 continue;
7ef166b8 1405
f82d7d16
ML		 1406 /* choose an unassigned converter. The conveters in the
1407 * connection list are in the same order as in the codec.
1408 */
1409 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1410 per_cvt = get_cvt(spec, cvt_idx);
1411 if (!per_cvt->assigned) {
4e76a883
TI		 1412 codec_dbg(codec,
1413 "choose cvt %d for pin nid %d\n",
f82d7d16
ML		 1414 cvt_idx, nid);
1415 snd_hda_codec_write_cache(codec, nid, 0,
7ef166b8 1416 AC_VERB_SET_CONNECT_SEL,
f82d7d16
ML		 1417 cvt_idx);
1418 break;
1419 }
7ef166b8
WX		 1420 }
1421 }
1422}
1423
1424/*
1425 * HDA PCM callbacks
1426 */
1427static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1428 struct hda_codec *codec,
1429 struct snd_pcm_substream *substream)
1430{
1431 struct hdmi_spec *spec = codec->spec;
1432 struct snd_pcm_runtime *runtime = substream->runtime;
1433 int pin_idx, cvt_idx, mux_idx = 0;
1434 struct hdmi_spec_per_pin *per_pin;
1435 struct hdmi_eld *eld;
1436 struct hdmi_spec_per_cvt *per_cvt = NULL;
1437 int err;
1438
1439 /* Validate hinfo */
4e76a883 1440 pin_idx = hinfo_to_pin_index(codec, hinfo);
7ef166b8
WX		 1441 if (snd_BUG_ON(pin_idx < 0))
1442 return -EINVAL;
1443 per_pin = get_pin(spec, pin_idx);
1444 eld = &per_pin->sink_eld;
1445
1446 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1447 if (err < 0)
1448 return err;
1449
1450 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1451 /* Claim converter */
1452 per_cvt->assigned = 1;
1df5a06a 1453 per_pin->cvt_nid = per_cvt->cvt_nid;
384a48d7
SW		 1454 hinfo->nid = per_cvt->cvt_nid;
1455
bddee96b 1456 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
384a48d7
SW		 1457 AC_VERB_SET_CONNECT_SEL,
1458 mux_idx);
7ef166b8
WX		 1459
1460 /* configure unused pins to choose other converters */
75dcbe4d 1461 if (is_haswell_plus(codec) || is_valleyview(codec))
300016b9 1462 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
7ef166b8 1463
384a48d7 1464 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
bbbe3390 1465
2def8172 1466 /* Initially set the converter's capabilities */
384a48d7
SW		 1467 hinfo->channels_min = per_cvt->channels_min;
1468 hinfo->channels_max = per_cvt->channels_max;
1469 hinfo->rates = per_cvt->rates;
1470 hinfo->formats = per_cvt->formats;
1471 hinfo->maxbps = per_cvt->maxbps;
2def8172 1472
384a48d7 1473 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 1474 if (!static_hdmi_pcm && eld->eld_valid) {
1613d6b4 1475 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
bbbe3390 1476 if (hinfo->channels_min > hinfo->channels_max ||
2ad779b7
TI		 1477 !hinfo->rates || !hinfo->formats) {
1478 per_cvt->assigned = 0;
1479 hinfo->nid = 0;
1480 snd_hda_spdif_ctls_unassign(codec, pin_idx);
bbbe3390 1481 return -ENODEV;
2ad779b7 1482 }
bbbe3390 1483 }
2def8172
SW		 1484
1485 /* Store the updated parameters */
639cef0e
TI		 1486 runtime->hw.channels_min = hinfo->channels_min;
1487 runtime->hw.channels_max = hinfo->channels_max;
1488 runtime->hw.formats = hinfo->formats;
1489 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 1490
1491 snd_pcm_hw_constraint_step(substream->runtime, 0,
1492 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 1493 return 0;
1494}
1495
079d88cc
WF		 1496/*
1497 * HDA/HDMI auto parsing
1498 */
384a48d7 1499static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 1500{
1501 struct hdmi_spec *spec = codec->spec;
bce0d2a8 1502 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1503 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 1504
1505 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
4e76a883
TI		 1506 codec_warn(codec,
1507 "HDMI: pin %d wcaps %#x does not support connection list\n",
079d88cc
WF		 1508 pin_nid, get_wcaps(codec, pin_nid));
1509 return -EINVAL;
1510 }
1511
384a48d7
SW		 1512 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1513 per_pin->mux_nids,
1514 HDA_MAX_CONNECTIONS);
079d88cc
WF		 1515
1516 return 0;
1517}
1518
efe47108 1519static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
079d88cc 1520{
464837a7 1521 struct hda_jack_tbl *jack;
744626da 1522 struct hda_codec *codec = per_pin->codec;
4bd038f9
DH		 1523 struct hdmi_spec *spec = codec->spec;
1524 struct hdmi_eld *eld = &spec->temp_eld;
1525 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
744626da 1526 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 1527 /*
1528 * Always execute a GetPinSense verb here, even when called from
1529 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1530 * response's PD bit is not the real PD value, but indicates that
1531 * the real PD value changed. An older version of the HD-audio
1532 * specification worked this way. Hence, we just ignore the data in
1533 * the unsolicited response to avoid custom WARs.
1534 */
da4a7a39 1535 int present;
4bd038f9
DH		 1536 bool update_eld = false;
1537 bool eld_changed = false;
efe47108 1538 bool ret;
079d88cc 1539
da4a7a39
DH		 1540 snd_hda_power_up(codec);
1541 present = snd_hda_pin_sense(codec, pin_nid);
1542
a4e9a38b 1543 mutex_lock(&per_pin->lock);
4bd038f9
DH		 1544 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1545 if (pin_eld->monitor_present)
1546 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1547 else
1548 eld->eld_valid = false;
079d88cc 1549
4e76a883 1550 codec_dbg(codec,
384a48d7 1551 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
10250911 1552 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
5d44f927 1553
4bd038f9 1554 if (eld->eld_valid) {
307229d2 1555 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1613d6b4 1556 &eld->eld_size) < 0)
4bd038f9 1557 eld->eld_valid = false;
1613d6b4
DH		 1558 else {
1559 memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
1560 if (snd_hdmi_parse_eld(&eld->info, eld->eld_buffer,
1561 eld->eld_size) < 0)
4bd038f9 1562 eld->eld_valid = false;
1613d6b4
DH		 1563 }
1564
4bd038f9 1565 if (eld->eld_valid) {
1613d6b4 1566 snd_hdmi_show_eld(&eld->info);
4bd038f9 1567 update_eld = true;
1613d6b4 1568 }
c6e8453e 1569 else if (repoll) {
744626da
WF		 1570 queue_delayed_work(codec->bus->workq,
1571 &per_pin->work,
1572 msecs_to_jiffies(300));
cbbaa603 1573 goto unlock;
744626da
WF		 1574 }
1575 }
4bd038f9 1576
92c69e79 1577 if (pin_eld->eld_valid && !eld->eld_valid) {
4bd038f9 1578 update_eld = true;
92c69e79
DH		 1579 eld_changed = true;
1580 }
4bd038f9 1581 if (update_eld) {
b054087d 1582 bool old_eld_valid = pin_eld->eld_valid;
4bd038f9 1583 pin_eld->eld_valid = eld->eld_valid;
92c69e79
DH		 1584 eld_changed = pin_eld->eld_size != eld->eld_size ||
1585 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
4bd038f9
DH		 1586 eld->eld_size) != 0;
1587 if (eld_changed)
1588 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1589 eld->eld_size);
1590 pin_eld->eld_size = eld->eld_size;
1591 pin_eld->info = eld->info;
b054087d 1592
7342017f
AH		 1593 /*
1594 * Re-setup pin and infoframe. This is needed e.g. when
1595 * - sink is first plugged-in (infoframe is not set up if !monitor_present)
1596 * - transcoder can change during stream playback on Haswell
b054087d 1597 */
7342017f 1598 if (eld->eld_valid && !old_eld_valid && per_pin->setup)
b054087d
TI		 1599 hdmi_setup_audio_infoframe(codec, per_pin,
1600 per_pin->non_pcm);
4bd038f9 1601 }
92c69e79
DH		 1602
1603 if (eld_changed)
1604 snd_ctl_notify(codec->bus->card,
1605 SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
1606 &per_pin->eld_ctl->id);
cbbaa603 1607 unlock:
aff747eb 1608 ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid;
464837a7
DH		 1609
1610 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1611 if (jack)
1612 jack->block_report = !ret;
1613
a4e9a38b 1614 mutex_unlock(&per_pin->lock);
da4a7a39 1615 snd_hda_power_down(codec);
efe47108 1616 return ret;
079d88cc
WF		 1617}
1618
744626da
WF		 1619static void hdmi_repoll_eld(struct work_struct *work)
1620{
1621 struct hdmi_spec_per_pin *per_pin =
1622 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1623
c6e8453e
WF		 1624 if (per_pin->repoll_count++ > 6)
1625 per_pin->repoll_count = 0;
1626
efe47108
TI		 1627 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1628 snd_hda_jack_report_sync(per_pin->codec);
744626da
WF		 1629}
1630
c88d4e84
TI		 1631static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1632 hda_nid_t nid);
1633
079d88cc
WF		 1634static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1635{
1636 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1637 unsigned int caps, config;
1638 int pin_idx;
1639 struct hdmi_spec_per_pin *per_pin;
07acecc1 1640 int err;
079d88cc 1641
efc2f8de 1642 caps = snd_hda_query_pin_caps(codec, pin_nid);
384a48d7
SW		 1643 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1644 return 0;
1645
efc2f8de 1646 config = snd_hda_codec_get_pincfg(codec, pin_nid);
384a48d7
SW		 1647 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1648 return 0;
1649
75dcbe4d 1650 if (is_haswell_plus(codec))
c88d4e84
TI		 1651 intel_haswell_fixup_connect_list(codec, pin_nid);
1652
384a48d7 1653 pin_idx = spec->num_pins;
bce0d2a8
TI		 1654 per_pin = snd_array_new(&spec->pins);
1655 if (!per_pin)
1656 return -ENOMEM;
384a48d7
SW		 1657
1658 per_pin->pin_nid = pin_nid;
1a6003b5 1659 per_pin->non_pcm = false;
079d88cc 1660
384a48d7
SW		 1661 err = hdmi_read_pin_conn(codec, pin_idx);
1662 if (err < 0)
1663 return err;
079d88cc 1664
079d88cc
WF		 1665 spec->num_pins++;
1666
384a48d7 1667 return 0;
079d88cc
WF		 1668}
1669
384a48d7 1670static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1671{
1672 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1673 struct hdmi_spec_per_cvt *per_cvt;
1674 unsigned int chans;
1675 int err;
079d88cc 1676
384a48d7
SW		 1677 chans = get_wcaps(codec, cvt_nid);
1678 chans = get_wcaps_channels(chans);
1679
bce0d2a8
TI		 1680 per_cvt = snd_array_new(&spec->cvts);
1681 if (!per_cvt)
1682 return -ENOMEM;
384a48d7
SW		 1683
1684 per_cvt->cvt_nid = cvt_nid;
1685 per_cvt->channels_min = 2;
d45e6889 1686 if (chans <= 16) {
384a48d7 1687 per_cvt->channels_max = chans;
d45e6889
TI		 1688 if (chans > spec->channels_max)
1689 spec->channels_max = chans;
1690 }
384a48d7
SW		 1691
1692 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1693 &per_cvt->rates,
1694 &per_cvt->formats,
1695 &per_cvt->maxbps);
1696 if (err < 0)
1697 return err;
1698
bce0d2a8
TI		 1699 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1700 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1701 spec->num_cvts++;
079d88cc
WF		 1702
1703 return 0;
1704}
1705
1706static int hdmi_parse_codec(struct hda_codec *codec)
1707{
1708 hda_nid_t nid;
1709 int i, nodes;
1710
1711 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
1712 if (!nid || nodes < 0) {
4e76a883 1713 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
079d88cc
WF		 1714 return -EINVAL;
1715 }
1716
1717 for (i = 0; i < nodes; i++, nid++) {
1718 unsigned int caps;
1719 unsigned int type;
1720
efc2f8de 1721 caps = get_wcaps(codec, nid);
079d88cc
WF		 1722 type = get_wcaps_type(caps);
1723
1724 if (!(caps & AC_WCAP_DIGITAL))
1725 continue;
1726
1727 switch (type) {
1728 case AC_WID_AUD_OUT:
384a48d7 1729 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1730 break;
1731 case AC_WID_PIN:
3eaead57 1732 hdmi_add_pin(codec, nid);
079d88cc
WF		 1733 break;
1734 }
1735 }
1736
079d88cc
WF		 1737 return 0;
1738}
1739
84eb01be
TI		 1740/*
1741 */
1a6003b5
TI		 1742static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1743{
1744 struct hda_spdif_out *spdif;
1745 bool non_pcm;
1746
1747 mutex_lock(&codec->spdif_mutex);
1748 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1749 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1750 mutex_unlock(&codec->spdif_mutex);
1751 return non_pcm;
1752}
1753
1754
84eb01be
TI		 1755/*
1756 * HDMI callbacks
1757 */
1758
1759static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1760 struct hda_codec *codec,
1761 unsigned int stream_tag,
1762 unsigned int format,
1763 struct snd_pcm_substream *substream)
1764{
384a48d7
SW		 1765 hda_nid_t cvt_nid = hinfo->nid;
1766 struct hdmi_spec *spec = codec->spec;
4e76a883 1767 int pin_idx = hinfo_to_pin_index(codec, hinfo);
b054087d
TI		 1768 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1769 hda_nid_t pin_nid = per_pin->pin_nid;
1a6003b5 1770 bool non_pcm;
75fae117 1771 int pinctl;
1a6003b5 1772
2df6742f
ML		 1773 if (is_haswell_plus(codec) || is_valleyview(codec)) {
1774 /* Verify pin:cvt selections to avoid silent audio after S3.
1775 * After S3, the audio driver restores pin:cvt selections
1776 * but this can happen before gfx is ready and such selection
1777 * is overlooked by HW. Thus multiple pins can share a same
1778 * default convertor and mute control will affect each other,
1779 * which can cause a resumed audio playback become silent
1780 * after S3.
1781 */
1782 intel_verify_pin_cvt_connect(codec, per_pin);
1783 intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx);
1784 }
1785
1a6003b5 1786 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
a4e9a38b 1787 mutex_lock(&per_pin->lock);
b054087d
TI		 1788 per_pin->channels = substream->runtime->channels;
1789 per_pin->setup = true;
384a48d7 1790
b054087d 1791 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
a4e9a38b 1792 mutex_unlock(&per_pin->lock);
84eb01be 1793
75fae117
SW		 1794 if (spec->dyn_pin_out) {
1795 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1796 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1797 snd_hda_codec_write(codec, pin_nid, 0,
1798 AC_VERB_SET_PIN_WIDGET_CONTROL,
1799 pinctl | PIN_OUT);
1800 }
1801
307229d2 1802 return spec->ops.setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
84eb01be
TI		 1803}
1804
8dfaa573
TI		 1805static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1806 struct hda_codec *codec,
1807 struct snd_pcm_substream *substream)
1808{
1809 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1810 return 0;
1811}
1812
f2ad24fa
TI		 1813static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1814 struct hda_codec *codec,
1815 struct snd_pcm_substream *substream)
384a48d7
SW		 1816{
1817 struct hdmi_spec *spec = codec->spec;
1818 int cvt_idx, pin_idx;
1819 struct hdmi_spec_per_cvt *per_cvt;
1820 struct hdmi_spec_per_pin *per_pin;
75fae117 1821 int pinctl;
384a48d7 1822
384a48d7 1823 if (hinfo->nid) {
4e76a883 1824 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
384a48d7
SW		 1825 if (snd_BUG_ON(cvt_idx < 0))
1826 return -EINVAL;
bce0d2a8 1827 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1828
1829 snd_BUG_ON(!per_cvt->assigned);
1830 per_cvt->assigned = 0;
1831 hinfo->nid = 0;
1832
4e76a883 1833 pin_idx = hinfo_to_pin_index(codec, hinfo);
384a48d7
SW		 1834 if (snd_BUG_ON(pin_idx < 0))
1835 return -EINVAL;
bce0d2a8 1836 per_pin = get_pin(spec, pin_idx);
384a48d7 1837
75fae117
SW		 1838 if (spec->dyn_pin_out) {
1839 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1840 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1841 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1842 AC_VERB_SET_PIN_WIDGET_CONTROL,
1843 pinctl & ~PIN_OUT);
1844 }
1845
384a48d7 1846 snd_hda_spdif_ctls_unassign(codec, pin_idx);
cbbaa603 1847
a4e9a38b 1848 mutex_lock(&per_pin->lock);
d45e6889
TI		 1849 per_pin->chmap_set = false;
1850 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
b054087d
TI		 1851
1852 per_pin->setup = false;
1853 per_pin->channels = 0;
a4e9a38b 1854 mutex_unlock(&per_pin->lock);
384a48d7 1855 }
d45e6889 1856
384a48d7
SW		 1857 return 0;
1858}
1859
1860static const struct hda_pcm_ops generic_ops = {
1861 .open = hdmi_pcm_open,
f2ad24fa 1862 .close = hdmi_pcm_close,
384a48d7 1863 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 1864 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 1865};
1866
d45e6889
TI		 1867/*
1868 * ALSA API channel-map control callbacks
1869 */
1870static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1871 struct snd_ctl_elem_info *uinfo)
1872{
1873 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1874 struct hda_codec *codec = info->private_data;
1875 struct hdmi_spec *spec = codec->spec;
1876 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1877 uinfo->count = spec->channels_max;
1878 uinfo->value.integer.min = 0;
1879 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1880 return 0;
1881}
1882
307229d2
AH		 1883static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
1884 int channels)
1885{
1886 /* If the speaker allocation matches the channel count, it is OK.*/
1887 if (cap->channels != channels)
1888 return -1;
1889
1890 /* all channels are remappable freely */
1891 return SNDRV_CTL_TLVT_CHMAP_VAR;
1892}
1893
1894static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
1895 unsigned int *chmap, int channels)
1896{
1897 int count = 0;
1898 int c;
1899
1900 for (c = 7; c >= 0; c--) {
1901 int spk = cap->speakers[c];
1902 if (!spk)
1903 continue;
1904
1905 chmap[count++] = spk_to_chmap(spk);
1906 }
1907
1908 WARN_ON(count != channels);
1909}
1910
d45e6889
TI		 1911static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1912 unsigned int size, unsigned int __user *tlv)
1913{
1914 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1915 struct hda_codec *codec = info->private_data;
1916 struct hdmi_spec *spec = codec->spec;
d45e6889
TI		 1917 unsigned int __user *dst;
1918 int chs, count = 0;
1919
1920 if (size < 8)
1921 return -ENOMEM;
1922 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1923 return -EFAULT;
1924 size -= 8;
1925 dst = tlv + 2;
498dab3a 1926 for (chs = 2; chs <= spec->channels_max; chs++) {
307229d2 1927 int i;
d45e6889
TI		 1928 struct cea_channel_speaker_allocation *cap;
1929 cap = channel_allocations;
1930 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1931 int chs_bytes = chs * 4;
307229d2
AH		 1932 int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs);
1933 unsigned int tlv_chmap[8];
1934
1935 if (type < 0)
d45e6889 1936 continue;
d45e6889
TI		 1937 if (size < 8)
1938 return -ENOMEM;
307229d2 1939 if (put_user(type, dst) ||
d45e6889
TI		 1940 put_user(chs_bytes, dst + 1))
1941 return -EFAULT;
1942 dst += 2;
1943 size -= 8;
1944 count += 8;
1945 if (size < chs_bytes)
1946 return -ENOMEM;
1947 size -= chs_bytes;
1948 count += chs_bytes;
307229d2
AH		 1949 spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs);
1950 if (copy_to_user(dst, tlv_chmap, chs_bytes))
1951 return -EFAULT;
1952 dst += chs;
d45e6889
TI		 1953 }
1954 }
1955 if (put_user(count, tlv + 1))
1956 return -EFAULT;
1957 return 0;
1958}
1959
1960static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
1961 struct snd_ctl_elem_value *ucontrol)
1962{
1963 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1964 struct hda_codec *codec = info->private_data;
1965 struct hdmi_spec *spec = codec->spec;
1966 int pin_idx = kcontrol->private_value;
bce0d2a8 1967 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1968 int i;
1969
1970 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
1971 ucontrol->value.integer.value[i] = per_pin->chmap[i];
1972 return 0;
1973}
1974
1975static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
1976 struct snd_ctl_elem_value *ucontrol)
1977{
1978 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1979 struct hda_codec *codec = info->private_data;
1980 struct hdmi_spec *spec = codec->spec;
1981 int pin_idx = kcontrol->private_value;
bce0d2a8 1982 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1983 unsigned int ctl_idx;
1984 struct snd_pcm_substream *substream;
1985 unsigned char chmap[8];
307229d2 1986 int i, err, ca, prepared = 0;
d45e6889
TI		 1987
1988 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
1989 substream = snd_pcm_chmap_substream(info, ctl_idx);
1990 if (!substream || !substream->runtime)
6f54c361 1991 return 0; /* just for avoiding error from alsactl restore */
d45e6889
TI		 1992 switch (substream->runtime->status->state) {
1993 case SNDRV_PCM_STATE_OPEN:
1994 case SNDRV_PCM_STATE_SETUP:
1995 break;
1996 case SNDRV_PCM_STATE_PREPARED:
1997 prepared = 1;
1998 break;
1999 default:
2000 return -EBUSY;
2001 }
2002 memset(chmap, 0, sizeof(chmap));
2003 for (i = 0; i < ARRAY_SIZE(chmap); i++)
2004 chmap[i] = ucontrol->value.integer.value[i];
2005 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
2006 return 0;
2007 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
2008 if (ca < 0)
2009 return -EINVAL;
307229d2
AH		 2010 if (spec->ops.chmap_validate) {
2011 err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap);
2012 if (err)
2013 return err;
2014 }
a4e9a38b 2015 mutex_lock(&per_pin->lock);
d45e6889
TI		 2016 per_pin->chmap_set = true;
2017 memcpy(per_pin->chmap, chmap, sizeof(chmap));
2018 if (prepared)
b054087d 2019 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
a4e9a38b 2020 mutex_unlock(&per_pin->lock);
d45e6889
TI		 2021
2022 return 0;
2023}
2024
84eb01be
TI		 2025static int generic_hdmi_build_pcms(struct hda_codec *codec)
2026{
2027 struct hdmi_spec *spec = codec->spec;
384a48d7 2028 int pin_idx;
84eb01be 2029
384a48d7
SW		 2030 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2031 struct hda_pcm *info;
84eb01be 2032 struct hda_pcm_stream *pstr;
bce0d2a8
TI		 2033 struct hdmi_spec_per_pin *per_pin;
2034
2035 per_pin = get_pin(spec, pin_idx);
2036 sprintf(per_pin->pcm_name, "HDMI %d", pin_idx);
2037 info = snd_array_new(&spec->pcm_rec);
2038 if (!info)
2039 return -ENOMEM;
2040 info->name = per_pin->pcm_name;
84eb01be 2041 info->pcm_type = HDA_PCM_TYPE_HDMI;
d45e6889 2042 info->own_chmap = true;
384a48d7 2043
84eb01be 2044 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 2045 pstr->substreams = 1;
2046 pstr->ops = generic_ops;
2047 /* other pstr fields are set in open */
84eb01be
TI		 2048 }
2049
384a48d7 2050 codec->num_pcms = spec->num_pins;
bce0d2a8 2051 codec->pcm_info = spec->pcm_rec.list;
384a48d7 2052
84eb01be
TI		 2053 return 0;
2054}
2055
0b6c49b5
DH		 2056static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
2057{
31ef2257 2058 char hdmi_str[32] = "HDMI/DP";
0b6c49b5 2059 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2060 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2061 int pcmdev = get_pcm_rec(spec, pin_idx)->device;
0b6c49b5 2062
31ef2257
TI		 2063 if (pcmdev > 0)
2064 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
30efd8de
DH		 2065 if (!is_jack_detectable(codec, per_pin->pin_nid))
2066 strncat(hdmi_str, " Phantom",
2067 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
0b6c49b5 2068
31ef2257 2069 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0);
0b6c49b5
DH		 2070}
2071
84eb01be
TI		 2072static int generic_hdmi_build_controls(struct hda_codec *codec)
2073{
2074 struct hdmi_spec *spec = codec->spec;
2075 int err;
384a48d7 2076 int pin_idx;
84eb01be 2077
384a48d7 2078 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2079 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
0b6c49b5
DH		 2080
2081 err = generic_hdmi_build_jack(codec, pin_idx);
2082 if (err < 0)
2083 return err;
2084
dcda5806
TI		 2085 err = snd_hda_create_dig_out_ctls(codec,
2086 per_pin->pin_nid,
2087 per_pin->mux_nids[0],
2088 HDA_PCM_TYPE_HDMI);
84eb01be
TI		 2089 if (err < 0)
2090 return err;
384a48d7 2091 snd_hda_spdif_ctls_unassign(codec, pin_idx);
14bc52b8
PLB		 2092
2093 /* add control for ELD Bytes */
bce0d2a8
TI		 2094 err = hdmi_create_eld_ctl(codec, pin_idx,
2095 get_pcm_rec(spec, pin_idx)->device);
14bc52b8
PLB		 2096
2097 if (err < 0)
2098 return err;
31ef2257 2099
82b1d73f 2100 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 2101 }
2102
d45e6889
TI		 2103 /* add channel maps */
2104 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2105 struct snd_pcm_chmap *chmap;
2106 struct snd_kcontrol *kctl;
2107 int i;
2ca320e2
TI		 2108
2109 if (!codec->pcm_info[pin_idx].pcm)
2110 break;
d45e6889
TI		 2111 err = snd_pcm_add_chmap_ctls(codec->pcm_info[pin_idx].pcm,
2112 SNDRV_PCM_STREAM_PLAYBACK,
2113 NULL, 0, pin_idx, &chmap);
2114 if (err < 0)
2115 return err;
2116 /* override handlers */
2117 chmap->private_data = codec;
2118 kctl = chmap->kctl;
2119 for (i = 0; i < kctl->count; i++)
2120 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
2121 kctl->info = hdmi_chmap_ctl_info;
2122 kctl->get = hdmi_chmap_ctl_get;
2123 kctl->put = hdmi_chmap_ctl_put;
2124 kctl->tlv.c = hdmi_chmap_ctl_tlv;
2125 }
2126
84eb01be
TI		 2127 return 0;
2128}
2129
8b8d654b 2130static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 2131{
2132 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2133 int pin_idx;
2134
2135 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2136 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2137
744626da 2138 per_pin->codec = codec;
a4e9a38b 2139 mutex_init(&per_pin->lock);
744626da 2140 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
a4e9a38b 2141 eld_proc_new(per_pin, pin_idx);
84eb01be 2142 }
8b8d654b
TI		 2143 return 0;
2144}
2145
2146static int generic_hdmi_init(struct hda_codec *codec)
2147{
2148 struct hdmi_spec *spec = codec->spec;
2149 int pin_idx;
2150
2151 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2152 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
8b8d654b
TI		 2153 hda_nid_t pin_nid = per_pin->pin_nid;
2154
2155 hdmi_init_pin(codec, pin_nid);
20ce9029
DH		 2156 snd_hda_jack_detect_enable_callback(codec, pin_nid, pin_nid,
2157 codec->jackpoll_interval > 0 ? jack_callback : NULL);
8b8d654b 2158 }
84eb01be
TI		 2159 return 0;
2160}
2161
bce0d2a8
TI		 2162static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2163{
2164 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2165 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2166 snd_array_init(&spec->pcm_rec, sizeof(struct hda_pcm), nums);
2167}
2168
2169static void hdmi_array_free(struct hdmi_spec *spec)
2170{
2171 snd_array_free(&spec->pins);
2172 snd_array_free(&spec->cvts);
2173 snd_array_free(&spec->pcm_rec);
2174}
2175
84eb01be
TI		 2176static void generic_hdmi_free(struct hda_codec *codec)
2177{
2178 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2179 int pin_idx;
2180
2181 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2182 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2183
744626da 2184 cancel_delayed_work(&per_pin->work);
a4e9a38b 2185 eld_proc_free(per_pin);
384a48d7 2186 }
84eb01be 2187
744626da 2188 flush_workqueue(codec->bus->workq);
bce0d2a8 2189 hdmi_array_free(spec);
84eb01be
TI		 2190 kfree(spec);
2191}
2192
28cb72e5
WX		 2193#ifdef CONFIG_PM
2194static int generic_hdmi_resume(struct hda_codec *codec)
2195{
2196 struct hdmi_spec *spec = codec->spec;
2197 int pin_idx;
2198
2199 generic_hdmi_init(codec);
2200 snd_hda_codec_resume_amp(codec);
2201 snd_hda_codec_resume_cache(codec);
2202
2203 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2204 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2205 hdmi_present_sense(per_pin, 1);
2206 }
2207 return 0;
2208}
2209#endif
2210
fb79e1e0 2211static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 2212 .init = generic_hdmi_init,
2213 .free = generic_hdmi_free,
2214 .build_pcms = generic_hdmi_build_pcms,
2215 .build_controls = generic_hdmi_build_controls,
2216 .unsol_event = hdmi_unsol_event,
28cb72e5
WX		 2217#ifdef CONFIG_PM
2218 .resume = generic_hdmi_resume,
2219#endif
84eb01be
TI		 2220};
2221
307229d2
AH		 2222static const struct hdmi_ops generic_standard_hdmi_ops = {
2223 .pin_get_eld = snd_hdmi_get_eld,
2224 .pin_get_slot_channel = hdmi_pin_get_slot_channel,
2225 .pin_set_slot_channel = hdmi_pin_set_slot_channel,
2226 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2227 .pin_hbr_setup = hdmi_pin_hbr_setup,
2228 .setup_stream = hdmi_setup_stream,
2229 .chmap_cea_alloc_validate_get_type = hdmi_chmap_cea_alloc_validate_get_type,
2230 .cea_alloc_to_tlv_chmap = hdmi_cea_alloc_to_tlv_chmap,
2231};
2232
6ffe168f 2233
c88d4e84
TI		 2234static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2235 hda_nid_t nid)
2236{
2237 struct hdmi_spec *spec = codec->spec;
2238 hda_nid_t conns[4];
2239 int nconns;
6ffe168f 2240
c88d4e84
TI		 2241 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2242 if (nconns == spec->num_cvts &&
2243 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
6ffe168f
ML		 2244 return;
2245
c88d4e84 2246 /* override pins connection list */
4e76a883 2247 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
c88d4e84 2248 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
6ffe168f
ML		 2249}
2250
1611a9c9
ML		 2251#define INTEL_VENDOR_NID 0x08
2252#define INTEL_GET_VENDOR_VERB 0xf81
2253#define INTEL_SET_VENDOR_VERB 0x781
2254#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2255#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2256
2257static void intel_haswell_enable_all_pins(struct hda_codec *codec,
17df3f55 2258 bool update_tree)
1611a9c9
ML		 2259{
2260 unsigned int vendor_param;
2261
1611a9c9
ML		 2262 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2263 INTEL_GET_VENDOR_VERB, 0);
2264 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2265 return;
2266
2267 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2268 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2269 INTEL_SET_VENDOR_VERB, vendor_param);
2270 if (vendor_param == -1)
2271 return;
2272
17df3f55
TI		 2273 if (update_tree)
2274 snd_hda_codec_update_widgets(codec);
1611a9c9
ML		 2275}
2276
c88d4e84
TI		 2277static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2278{
2279 unsigned int vendor_param;
2280
2281 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2282 INTEL_GET_VENDOR_VERB, 0);
2283 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2284 return;
2285
2286 /* enable DP1.2 mode */
2287 vendor_param |= INTEL_EN_DP12;
2288 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2289 INTEL_SET_VENDOR_VERB, vendor_param);
2290}
2291
17df3f55
TI		 2292/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2293 * Otherwise you may get severe h/w communication errors.
2294 */
2295static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2296 unsigned int power_state)
2297{
2298 if (power_state == AC_PWRST_D0) {
2299 intel_haswell_enable_all_pins(codec, false);
2300 intel_haswell_fixup_enable_dp12(codec);
2301 }
c88d4e84 2302
17df3f55
TI		 2303 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2304 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2305}
6ffe168f 2306
84eb01be
TI		 2307static int patch_generic_hdmi(struct hda_codec *codec)
2308{
2309 struct hdmi_spec *spec;
84eb01be
TI		 2310
2311 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2312 if (spec == NULL)
2313 return -ENOMEM;
2314
307229d2 2315 spec->ops = generic_standard_hdmi_ops;
84eb01be 2316 codec->spec = spec;
bce0d2a8 2317 hdmi_array_init(spec, 4);
6ffe168f 2318
75dcbe4d 2319 if (is_haswell_plus(codec)) {
17df3f55 2320 intel_haswell_enable_all_pins(codec, true);
c88d4e84 2321 intel_haswell_fixup_enable_dp12(codec);
17df3f55 2322 }
6ffe168f 2323
5b8620bb
ML		 2324 if (is_haswell(codec) || is_valleyview(codec)) {
2325 codec->depop_delay = 0;
2326 }
2327
84eb01be
TI		 2328 if (hdmi_parse_codec(codec) < 0) {
2329 codec->spec = NULL;
2330 kfree(spec);
2331 return -EINVAL;
2332 }
2333 codec->patch_ops = generic_hdmi_patch_ops;
75dcbe4d 2334 if (is_haswell_plus(codec)) {
17df3f55 2335 codec->patch_ops.set_power_state = haswell_set_power_state;
5dc989bd
ML		 2336 codec->dp_mst = true;
2337 }
17df3f55 2338
8b8d654b 2339 generic_hdmi_init_per_pins(codec);
84eb01be 2340
84eb01be
TI		 2341 init_channel_allocations();
2342
2343 return 0;
2344}
2345
3aaf8980
SW		 2346/*
2347 * Shared non-generic implementations
2348 */
2349
2350static int simple_playback_build_pcms(struct hda_codec *codec)
2351{
2352 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2353 struct hda_pcm *info;
8ceb332d
TI		 2354 unsigned int chans;
2355 struct hda_pcm_stream *pstr;
bce0d2a8 2356 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2357
bce0d2a8
TI		 2358 per_cvt = get_cvt(spec, 0);
2359 chans = get_wcaps(codec, per_cvt->cvt_nid);
8ceb332d 2360 chans = get_wcaps_channels(chans);
3aaf8980 2361
bce0d2a8
TI		 2362 info = snd_array_new(&spec->pcm_rec);
2363 if (!info)
2364 return -ENOMEM;
2365 info->name = get_pin(spec, 0)->pcm_name;
2366 sprintf(info->name, "HDMI 0");
8ceb332d
TI		 2367 info->pcm_type = HDA_PCM_TYPE_HDMI;
2368 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2369 *pstr = spec->pcm_playback;
bce0d2a8 2370 pstr->nid = per_cvt->cvt_nid;
8ceb332d
TI		 2371 if (pstr->channels_max <= 2 && chans && chans <= 16)
2372 pstr->channels_max = chans;
3aaf8980 2373
bce0d2a8
TI		 2374 codec->num_pcms = 1;
2375 codec->pcm_info = info;
2376
3aaf8980
SW		 2377 return 0;
2378}
2379
4b6ace9e
TI		 2380/* unsolicited event for jack sensing */
2381static void simple_hdmi_unsol_event(struct hda_codec *codec,
2382 unsigned int res)
2383{
9dd8cf12 2384 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 2385 snd_hda_jack_report_sync(codec);
2386}
2387
2388/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2389 * as long as spec->pins[] is set correctly
2390 */
2391#define simple_hdmi_build_jack generic_hdmi_build_jack
2392
3aaf8980
SW		 2393static int simple_playback_build_controls(struct hda_codec *codec)
2394{
2395 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2396 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2397 int err;
3aaf8980 2398
bce0d2a8 2399 per_cvt = get_cvt(spec, 0);
c9a6338a
AH		 2400 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2401 per_cvt->cvt_nid,
2402 HDA_PCM_TYPE_HDMI);
8ceb332d
TI		 2403 if (err < 0)
2404 return err;
2405 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 2406}
2407
4f0110ce
TI		 2408static int simple_playback_init(struct hda_codec *codec)
2409{
2410 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2411 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2412 hda_nid_t pin = per_pin->pin_nid;
8ceb332d
TI		 2413
2414 snd_hda_codec_write(codec, pin, 0,
2415 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2416 /* some codecs require to unmute the pin */
2417 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2418 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2419 AMP_OUT_UNMUTE);
2420 snd_hda_jack_detect_enable(codec, pin, pin);
4f0110ce
TI		 2421 return 0;
2422}
2423
3aaf8980
SW		 2424static void simple_playback_free(struct hda_codec *codec)
2425{
2426 struct hdmi_spec *spec = codec->spec;
2427
bce0d2a8 2428 hdmi_array_free(spec);
3aaf8980
SW		 2429 kfree(spec);
2430}
2431
84eb01be
TI		 2432/*
2433 * Nvidia specific implementations
2434 */
2435
2436#define Nv_VERB_SET_Channel_Allocation 0xF79
2437#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2438#define Nv_VERB_SET_Audio_Protection_On 0xF98
2439#define Nv_VERB_SET_Audio_Protection_Off 0xF99
2440
2441#define nvhdmi_master_con_nid_7x 0x04
2442#define nvhdmi_master_pin_nid_7x 0x05
2443
fb79e1e0 2444static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 2445 /*front, rear, clfe, rear_surr */
2446 0x6, 0x8, 0xa, 0xc,
2447};
2448
ceaa86ba
TI		 2449static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2450 /* set audio protect on */
2451 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2452 /* enable digital output on pin widget */
2453 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2454 {} /* terminator */
2455};
2456
2457static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 2458 /* set audio protect on */
2459 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2460 /* enable digital output on pin widget */
2461 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2462 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2463 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2464 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2465 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2466 {} /* terminator */
2467};
2468
2469#ifdef LIMITED_RATE_FMT_SUPPORT
2470/* support only the safe format and rate */
2471#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2472#define SUPPORTED_MAXBPS 16
2473#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2474#else
2475/* support all rates and formats */
2476#define SUPPORTED_RATES \
2477 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2478 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2479 SNDRV_PCM_RATE_192000)
2480#define SUPPORTED_MAXBPS 24
2481#define SUPPORTED_FORMATS \
2482 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2483#endif
2484
ceaa86ba
TI		 2485static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2486{
2487 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2488 return 0;
2489}
2490
2491static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 2492{
ceaa86ba 2493 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 2494 return 0;
2495}
2496
393004b2
ND		 2497static unsigned int channels_2_6_8[] = {
2498 2, 6, 8
2499};
2500
2501static unsigned int channels_2_8[] = {
2502 2, 8
2503};
2504
2505static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2506 .count = ARRAY_SIZE(channels_2_6_8),
2507 .list = channels_2_6_8,
2508 .mask = 0,
2509};
2510
2511static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2512 .count = ARRAY_SIZE(channels_2_8),
2513 .list = channels_2_8,
2514 .mask = 0,
2515};
2516
84eb01be
TI		 2517static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2518 struct hda_codec *codec,
2519 struct snd_pcm_substream *substream)
2520{
2521 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 2522 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2523
2524 switch (codec->preset->id) {
2525 case 0x10de0002:
2526 case 0x10de0003:
2527 case 0x10de0005:
2528 case 0x10de0006:
2529 hw_constraints_channels = &hw_constraints_2_8_channels;
2530 break;
2531 case 0x10de0007:
2532 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2533 break;
2534 default:
2535 break;
2536 }
2537
2538 if (hw_constraints_channels != NULL) {
2539 snd_pcm_hw_constraint_list(substream->runtime, 0,
2540 SNDRV_PCM_HW_PARAM_CHANNELS,
2541 hw_constraints_channels);
ad09fc9d
TI		 2542 } else {
2543 snd_pcm_hw_constraint_step(substream->runtime, 0,
2544 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 2545 }
2546
84eb01be
TI		 2547 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2548}
2549
2550static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2551 struct hda_codec *codec,
2552 struct snd_pcm_substream *substream)
2553{
2554 struct hdmi_spec *spec = codec->spec;
2555 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2556}
2557
2558static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2559 struct hda_codec *codec,
2560 unsigned int stream_tag,
2561 unsigned int format,
2562 struct snd_pcm_substream *substream)
2563{
2564 struct hdmi_spec *spec = codec->spec;
2565 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2566 stream_tag, format, substream);
2567}
2568
d0b1252d
TI		 2569static const struct hda_pcm_stream simple_pcm_playback = {
2570 .substreams = 1,
2571 .channels_min = 2,
2572 .channels_max = 2,
2573 .ops = {
2574 .open = simple_playback_pcm_open,
2575 .close = simple_playback_pcm_close,
2576 .prepare = simple_playback_pcm_prepare
2577 },
2578};
2579
2580static const struct hda_codec_ops simple_hdmi_patch_ops = {
2581 .build_controls = simple_playback_build_controls,
2582 .build_pcms = simple_playback_build_pcms,
2583 .init = simple_playback_init,
2584 .free = simple_playback_free,
250e41ac 2585 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 2586};
2587
2588static int patch_simple_hdmi(struct hda_codec *codec,
2589 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2590{
2591 struct hdmi_spec *spec;
bce0d2a8
TI		 2592 struct hdmi_spec_per_cvt *per_cvt;
2593 struct hdmi_spec_per_pin *per_pin;
d0b1252d
TI		 2594
2595 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2596 if (!spec)
2597 return -ENOMEM;
2598
2599 codec->spec = spec;
bce0d2a8 2600 hdmi_array_init(spec, 1);
d0b1252d
TI		 2601
2602 spec->multiout.num_dacs = 0; /* no analog */
2603 spec->multiout.max_channels = 2;
2604 spec->multiout.dig_out_nid = cvt_nid;
2605 spec->num_cvts = 1;
2606 spec->num_pins = 1;
bce0d2a8
TI		 2607 per_pin = snd_array_new(&spec->pins);
2608 per_cvt = snd_array_new(&spec->cvts);
2609 if (!per_pin || !per_cvt) {
2610 simple_playback_free(codec);
2611 return -ENOMEM;
2612 }
2613 per_cvt->cvt_nid = cvt_nid;
2614 per_pin->pin_nid = pin_nid;
d0b1252d
TI		 2615 spec->pcm_playback = simple_pcm_playback;
2616
2617 codec->patch_ops = simple_hdmi_patch_ops;
2618
2619 return 0;
2620}
2621
1f348522
AP		 2622static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2623 int channels)
2624{
2625 unsigned int chanmask;
2626 int chan = channels ? (channels - 1) : 1;
2627
2628 switch (channels) {
2629 default:
2630 case 0:
2631 case 2:
2632 chanmask = 0x00;
2633 break;
2634 case 4:
2635 chanmask = 0x08;
2636 break;
2637 case 6:
2638 chanmask = 0x0b;
2639 break;
2640 case 8:
2641 chanmask = 0x13;
2642 break;
2643 }
2644
2645 /* Set the audio infoframe channel allocation and checksum fields. The
2646 * channel count is computed implicitly by the hardware. */
2647 snd_hda_codec_write(codec, 0x1, 0,
2648 Nv_VERB_SET_Channel_Allocation, chanmask);
2649
2650 snd_hda_codec_write(codec, 0x1, 0,
2651 Nv_VERB_SET_Info_Frame_Checksum,
2652 (0x71 - chan - chanmask));
2653}
2654
84eb01be
TI		 2655static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2656 struct hda_codec *codec,
2657 struct snd_pcm_substream *substream)
2658{
2659 struct hdmi_spec *spec = codec->spec;
2660 int i;
2661
2662 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2663 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2664 for (i = 0; i < 4; i++) {
2665 /* set the stream id */
2666 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2667 AC_VERB_SET_CHANNEL_STREAMID, 0);
2668 /* set the stream format */
2669 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2670 AC_VERB_SET_STREAM_FORMAT, 0);
2671 }
2672
1f348522
AP		 2673 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2674 * streams are disabled. */
2675 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2676
84eb01be
TI		 2677 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2678}
2679
2680static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2681 struct hda_codec *codec,
2682 unsigned int stream_tag,
2683 unsigned int format,
2684 struct snd_pcm_substream *substream)
2685{
2686 int chs;
112daa7a 2687 unsigned int dataDCC2, channel_id;
84eb01be 2688 int i;
7c935976 2689 struct hdmi_spec *spec = codec->spec;
e3245cdd 2690 struct hda_spdif_out *spdif;
bce0d2a8 2691 struct hdmi_spec_per_cvt *per_cvt;
84eb01be
TI		 2692
2693 mutex_lock(&codec->spdif_mutex);
bce0d2a8
TI		 2694 per_cvt = get_cvt(spec, 0);
2695 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
84eb01be
TI		 2696
2697 chs = substream->runtime->channels;
84eb01be 2698
84eb01be
TI		 2699 dataDCC2 = 0x2;
2700
84eb01be 2701 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 2702 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2703 snd_hda_codec_write(codec,
2704 nvhdmi_master_con_nid_7x,
2705 0,
2706 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2707 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2708
2709 /* set the stream id */
2710 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2711 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2712
2713 /* set the stream format */
2714 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2715 AC_VERB_SET_STREAM_FORMAT, format);
2716
2717 /* turn on again (if needed) */
2718 /* enable and set the channel status audio/data flag */
7c935976 2719 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2720 snd_hda_codec_write(codec,
2721 nvhdmi_master_con_nid_7x,
2722 0,
2723 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2724 spdif->ctls & 0xff);
84eb01be
TI		 2725 snd_hda_codec_write(codec,
2726 nvhdmi_master_con_nid_7x,
2727 0,
2728 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2729 }
2730
2731 for (i = 0; i < 4; i++) {
2732 if (chs == 2)
2733 channel_id = 0;
2734 else
2735 channel_id = i * 2;
2736
2737 /* turn off SPDIF once;
2738 *otherwise the IEC958 bits won't be updated
2739 */
2740 if (codec->spdif_status_reset &&
7c935976 2741 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2742 snd_hda_codec_write(codec,
2743 nvhdmi_con_nids_7x[i],
2744 0,
2745 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2746 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2747 /* set the stream id */
2748 snd_hda_codec_write(codec,
2749 nvhdmi_con_nids_7x[i],
2750 0,
2751 AC_VERB_SET_CHANNEL_STREAMID,
2752 (stream_tag << 4) | channel_id);
2753 /* set the stream format */
2754 snd_hda_codec_write(codec,
2755 nvhdmi_con_nids_7x[i],
2756 0,
2757 AC_VERB_SET_STREAM_FORMAT,
2758 format);
2759 /* turn on again (if needed) */
2760 /* enable and set the channel status audio/data flag */
2761 if (codec->spdif_status_reset &&
7c935976 2762 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2763 snd_hda_codec_write(codec,
2764 nvhdmi_con_nids_7x[i],
2765 0,
2766 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2767 spdif->ctls & 0xff);
84eb01be
TI		 2768 snd_hda_codec_write(codec,
2769 nvhdmi_con_nids_7x[i],
2770 0,
2771 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2772 }
2773 }
2774
1f348522 2775 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 2776
2777 mutex_unlock(&codec->spdif_mutex);
2778 return 0;
2779}
2780
fb79e1e0 2781static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 2782 .substreams = 1,
2783 .channels_min = 2,
2784 .channels_max = 8,
2785 .nid = nvhdmi_master_con_nid_7x,
2786 .rates = SUPPORTED_RATES,
2787 .maxbps = SUPPORTED_MAXBPS,
2788 .formats = SUPPORTED_FORMATS,
2789 .ops = {
2790 .open = simple_playback_pcm_open,
2791 .close = nvhdmi_8ch_7x_pcm_close,
2792 .prepare = nvhdmi_8ch_7x_pcm_prepare
2793 },
2794};
2795
84eb01be
TI		 2796static int patch_nvhdmi_2ch(struct hda_codec *codec)
2797{
2798 struct hdmi_spec *spec;
d0b1252d
TI		 2799 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2800 nvhdmi_master_pin_nid_7x);
2801 if (err < 0)
2802 return err;
84eb01be 2803
ceaa86ba 2804 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 2805 /* override the PCM rates, etc, as the codec doesn't give full list */
2806 spec = codec->spec;
2807 spec->pcm_playback.rates = SUPPORTED_RATES;
2808 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2809 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 2810 return 0;
2811}
2812
53775b0d
TI		 2813static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2814{
2815 struct hdmi_spec *spec = codec->spec;
2816 int err = simple_playback_build_pcms(codec);
bce0d2a8
TI		 2817 if (!err) {
2818 struct hda_pcm *info = get_pcm_rec(spec, 0);
2819 info->own_chmap = true;
2820 }
53775b0d
TI		 2821 return err;
2822}
2823
2824static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2825{
2826 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2827 struct hda_pcm *info;
53775b0d
TI		 2828 struct snd_pcm_chmap *chmap;
2829 int err;
2830
2831 err = simple_playback_build_controls(codec);
2832 if (err < 0)
2833 return err;
2834
2835 /* add channel maps */
bce0d2a8
TI		 2836 info = get_pcm_rec(spec, 0);
2837 err = snd_pcm_add_chmap_ctls(info->pcm,
53775b0d
TI		 2838 SNDRV_PCM_STREAM_PLAYBACK,
2839 snd_pcm_alt_chmaps, 8, 0, &chmap);
2840 if (err < 0)
2841 return err;
2842 switch (codec->preset->id) {
2843 case 0x10de0002:
2844 case 0x10de0003:
2845 case 0x10de0005:
2846 case 0x10de0006:
2847 chmap->channel_mask = (1U << 2) | (1U << 8);
2848 break;
2849 case 0x10de0007:
2850 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2851 }
2852 return 0;
2853}
2854
84eb01be
TI		 2855static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2856{
2857 struct hdmi_spec *spec;
2858 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 2859 if (err < 0)
2860 return err;
2861 spec = codec->spec;
2862 spec->multiout.max_channels = 8;
d0b1252d 2863 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 2864 codec->patch_ops.init = nvhdmi_7x_init_8ch;
53775b0d
TI		 2865 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2866 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
1f348522
AP		 2867
2868 /* Initialize the audio infoframe channel mask and checksum to something
2869 * valid */
2870 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2871
84eb01be
TI		 2872 return 0;
2873}
2874
611885bc
AH		 2875/*
2876 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
2877 * - 0x10de0015
2878 * - 0x10de0040
2879 */
2880static int nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
2881 int channels)
2882{
2883 if (cap->ca_index == 0x00 && channels == 2)
2884 return SNDRV_CTL_TLVT_CHMAP_FIXED;
2885
2886 return hdmi_chmap_cea_alloc_validate_get_type(cap, channels);
2887}
2888
2889static int nvhdmi_chmap_validate(int ca, int chs, unsigned char *map)
2890{
2891 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
2892 return -EINVAL;
2893
2894 return 0;
2895}
2896
2897static int patch_nvhdmi(struct hda_codec *codec)
2898{
2899 struct hdmi_spec *spec;
2900 int err;
2901
2902 err = patch_generic_hdmi(codec);
2903 if (err)
2904 return err;
2905
2906 spec = codec->spec;
75fae117 2907 spec->dyn_pin_out = true;
611885bc
AH		 2908
2909 spec->ops.chmap_cea_alloc_validate_get_type =
2910 nvhdmi_chmap_cea_alloc_validate_get_type;
2911 spec->ops.chmap_validate = nvhdmi_chmap_validate;
2912
2913 return 0;
2914}
2915
84eb01be 2916/*
5a613584 2917 * ATI/AMD-specific implementations
84eb01be
TI		 2918 */
2919
5a613584
AH		 2920#define is_amdhdmi_rev3_or_later(codec) \
2921 ((codec)->vendor_id == 0x1002aa01 && ((codec)->revision_id & 0xff00) >= 0x0300)
2922#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
2923
2924/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
2925#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
2926#define ATI_VERB_SET_DOWNMIX_INFO 0x772
2927#define ATI_VERB_SET_MULTICHANNEL_01 0x777
2928#define ATI_VERB_SET_MULTICHANNEL_23 0x778
2929#define ATI_VERB_SET_MULTICHANNEL_45 0x779
2930#define ATI_VERB_SET_MULTICHANNEL_67 0x77a
461cf6b3 2931#define ATI_VERB_SET_HBR_CONTROL 0x77c
5a613584
AH		 2932#define ATI_VERB_SET_MULTICHANNEL_1 0x785
2933#define ATI_VERB_SET_MULTICHANNEL_3 0x786
2934#define ATI_VERB_SET_MULTICHANNEL_5 0x787
2935#define ATI_VERB_SET_MULTICHANNEL_7 0x788
2936#define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
2937#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
2938#define ATI_VERB_GET_DOWNMIX_INFO 0xf72
2939#define ATI_VERB_GET_MULTICHANNEL_01 0xf77
2940#define ATI_VERB_GET_MULTICHANNEL_23 0xf78
2941#define ATI_VERB_GET_MULTICHANNEL_45 0xf79
2942#define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
461cf6b3 2943#define ATI_VERB_GET_HBR_CONTROL 0xf7c
5a613584
AH		 2944#define ATI_VERB_GET_MULTICHANNEL_1 0xf85
2945#define ATI_VERB_GET_MULTICHANNEL_3 0xf86
2946#define ATI_VERB_GET_MULTICHANNEL_5 0xf87
2947#define ATI_VERB_GET_MULTICHANNEL_7 0xf88
2948#define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
2949
84d69e79
AH		 2950/* AMD specific HDA cvt verbs */
2951#define ATI_VERB_SET_RAMP_RATE 0x770
2952#define ATI_VERB_GET_RAMP_RATE 0xf70
2953
5a613584
AH		 2954#define ATI_OUT_ENABLE 0x1
2955
2956#define ATI_MULTICHANNEL_MODE_PAIRED 0
2957#define ATI_MULTICHANNEL_MODE_SINGLE 1
2958
461cf6b3
AH		 2959#define ATI_HBR_CAPABLE 0x01
2960#define ATI_HBR_ENABLE 0x10
2961
89250f84
AH		 2962static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
2963 unsigned char *buf, int *eld_size)
2964{
2965 /* call hda_eld.c ATI/AMD-specific function */
2966 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
2967 is_amdhdmi_rev3_or_later(codec));
2968}
2969
5a613584
AH		 2970static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
2971 int active_channels, int conn_type)
2972{
2973 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
2974}
2975
2976static int atihdmi_paired_swap_fc_lfe(int pos)
2977{
2978 /*
2979 * ATI/AMD have automatic FC/LFE swap built-in
2980 * when in pairwise mapping mode.
2981 */
2982
2983 switch (pos) {
2984 /* see channel_allocations[].speakers[] */
2985 case 2: return 3;
2986 case 3: return 2;
2987 default: break;
2988 }
2989
2990 return pos;
2991}
2992
2993static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map)
2994{
2995 struct cea_channel_speaker_allocation *cap;
2996 int i, j;
2997
2998 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
2999
3000 cap = &channel_allocations[get_channel_allocation_order(ca)];
3001 for (i = 0; i < chs; ++i) {
3002 int mask = to_spk_mask(map[i]);
3003 bool ok = false;
3004 bool companion_ok = false;
3005
3006 if (!mask)
3007 continue;
3008
3009 for (j = 0 + i % 2; j < 8; j += 2) {
3010 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3011 if (cap->speakers[chan_idx] == mask) {
3012 /* channel is in a supported position */
3013 ok = true;
3014
3015 if (i % 2 == 0 && i + 1 < chs) {
3016 /* even channel, check the odd companion */
3017 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3018 int comp_mask_req = to_spk_mask(map[i+1]);
3019 int comp_mask_act = cap->speakers[comp_chan_idx];
3020
3021 if (comp_mask_req == comp_mask_act)
3022 companion_ok = true;
3023 else
3024 return -EINVAL;
3025 }
3026 break;
3027 }
3028 }
3029
3030 if (!ok)
3031 return -EINVAL;
3032
3033 if (companion_ok)
3034 i++; /* companion channel already checked */
3035 }
3036
3037 return 0;
3038}
3039
3040static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3041 int hdmi_slot, int stream_channel)
3042{
3043 int verb;
3044 int ati_channel_setup = 0;
3045
3046 if (hdmi_slot > 7)
3047 return -EINVAL;
3048
3049 if (!has_amd_full_remap_support(codec)) {
3050 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3051
3052 /* In case this is an odd slot but without stream channel, do not
3053 * disable the slot since the corresponding even slot could have a
3054 * channel. In case neither have a channel, the slot pair will be
3055 * disabled when this function is called for the even slot. */
3056 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3057 return 0;
3058
3059 hdmi_slot -= hdmi_slot % 2;
3060
3061 if (stream_channel != 0xf)
3062 stream_channel -= stream_channel % 2;
3063 }
3064
3065 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3066
3067 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3068
3069 if (stream_channel != 0xf)
3070 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3071
3072 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3073}
3074
3075static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3076 int asp_slot)
3077{
3078 bool was_odd = false;
3079 int ati_asp_slot = asp_slot;
3080 int verb;
3081 int ati_channel_setup;
3082
3083 if (asp_slot > 7)
3084 return -EINVAL;
3085
3086 if (!has_amd_full_remap_support(codec)) {
3087 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3088 if (ati_asp_slot % 2 != 0) {
3089 ati_asp_slot -= 1;
3090 was_odd = true;
3091 }
3092 }
3093
3094 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3095
3096 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3097
3098 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3099 return 0xf;
3100
3101 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3102}
84eb01be 3103
5a613584
AH		 3104static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
3105 int channels)
3106{
3107 int c;
3108
3109 /*
3110 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3111 * we need to take that into account (a single channel may take 2
3112 * channel slots if we need to carry a silent channel next to it).
3113 * On Rev3+ AMD codecs this function is not used.
3114 */
3115 int chanpairs = 0;
3116
3117 /* We only produce even-numbered channel count TLVs */
3118 if ((channels % 2) != 0)
3119 return -1;
3120
3121 for (c = 0; c < 7; c += 2) {
3122 if (cap->speakers[c] || cap->speakers[c+1])
3123 chanpairs++;
3124 }
3125
3126 if (chanpairs * 2 != channels)
3127 return -1;
3128
3129 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3130}
3131
3132static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
3133 unsigned int *chmap, int channels)
3134{
3135 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3136 int count = 0;
3137 int c;
3138
3139 for (c = 7; c >= 0; c--) {
3140 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3141 int spk = cap->speakers[chan];
3142 if (!spk) {
3143 /* add N/A channel if the companion channel is occupied */
3144 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3145 chmap[count++] = SNDRV_CHMAP_NA;
3146
3147 continue;
3148 }
3149
3150 chmap[count++] = spk_to_chmap(spk);
3151 }
3152
3153 WARN_ON(count != channels);
3154}
3155
461cf6b3
AH		 3156static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3157 bool hbr)
3158{
3159 int hbr_ctl, hbr_ctl_new;
3160
3161 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
13122e6e 3162 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
461cf6b3
AH		 3163 if (hbr)
3164 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3165 else
3166 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3167
4e76a883
TI		 3168 codec_dbg(codec,
3169 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
461cf6b3
AH		 3170 pin_nid,
3171 hbr_ctl == hbr_ctl_new ? "" : "new-",
3172 hbr_ctl_new);
3173
3174 if (hbr_ctl != hbr_ctl_new)
3175 snd_hda_codec_write(codec, pin_nid, 0,
3176 ATI_VERB_SET_HBR_CONTROL,
3177 hbr_ctl_new);
3178
3179 } else if (hbr)
3180 return -EINVAL;
3181
3182 return 0;
3183}
3184
84d69e79
AH		 3185static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3186 hda_nid_t pin_nid, u32 stream_tag, int format)
3187{
3188
3189 if (is_amdhdmi_rev3_or_later(codec)) {
3190 int ramp_rate = 180; /* default as per AMD spec */
3191 /* disable ramp-up/down for non-pcm as per AMD spec */
3192 if (format & AC_FMT_TYPE_NON_PCM)
3193 ramp_rate = 0;
3194
3195 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3196 }
3197
3198 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3199}
3200
3201
5a613584 3202static int atihdmi_init(struct hda_codec *codec)
84eb01be
TI		 3203{
3204 struct hdmi_spec *spec = codec->spec;
5a613584 3205 int pin_idx, err;
84eb01be 3206
5a613584
AH		 3207 err = generic_hdmi_init(codec);
3208
3209 if (err)
84eb01be 3210 return err;
5a613584
AH		 3211
3212 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3213 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3214
3215 /* make sure downmix information in infoframe is zero */
3216 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3217
3218 /* enable channel-wise remap mode if supported */
3219 if (has_amd_full_remap_support(codec))
3220 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3221 ATI_VERB_SET_MULTICHANNEL_MODE,
3222 ATI_MULTICHANNEL_MODE_SINGLE);
84eb01be 3223 }
5a613584 3224
84eb01be
TI		 3225 return 0;
3226}
3227
84eb01be
TI		 3228static int patch_atihdmi(struct hda_codec *codec)
3229{
3230 struct hdmi_spec *spec;
5a613584
AH		 3231 struct hdmi_spec_per_cvt *per_cvt;
3232 int err, cvt_idx;
3233
3234 err = patch_generic_hdmi(codec);
3235
3236 if (err)
d0b1252d 3237 return err;
5a613584
AH		 3238
3239 codec->patch_ops.init = atihdmi_init;
3240
d0b1252d 3241 spec = codec->spec;
5a613584 3242
89250f84 3243 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
5a613584
AH		 3244 spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3245 spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3246 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
461cf6b3 3247 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
84d69e79 3248 spec->ops.setup_stream = atihdmi_setup_stream;
5a613584
AH		 3249
3250 if (!has_amd_full_remap_support(codec)) {
3251 /* override to ATI/AMD-specific versions with pairwise mapping */
3252 spec->ops.chmap_cea_alloc_validate_get_type =
3253 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3254 spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap;
3255 spec->ops.chmap_validate = atihdmi_paired_chmap_validate;
3256 }
3257
3258 /* ATI/AMD converters do not advertise all of their capabilities */
3259 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3260 per_cvt = get_cvt(spec, cvt_idx);
3261 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3262 per_cvt->rates |= SUPPORTED_RATES;
3263 per_cvt->formats |= SUPPORTED_FORMATS;
3264 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3265 }
3266
3267 spec->channels_max = max(spec->channels_max, 8u);
3268
84eb01be
TI		 3269 return 0;
3270}
3271
3de5ff88
AL		 3272/* VIA HDMI Implementation */
3273#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3274#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3275
3de5ff88
AL		 3276static int patch_via_hdmi(struct hda_codec *codec)
3277{
250e41ac 3278 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 3279}
84eb01be 3280
f0639272
TI		 3281/*
3282 * called from hda_codec.c for generic HDMI support
3283 */
3284int snd_hda_parse_hdmi_codec(struct hda_codec *codec)
3285{
3286 return patch_generic_hdmi(codec);
3287}
2698ea98 3288EXPORT_SYMBOL_GPL(snd_hda_parse_hdmi_codec);
f0639272 3289
84eb01be
TI		 3290/*
3291 * patch entries
3292 */
fb79e1e0 3293static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
84eb01be
TI		 3294{ .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
3295{ .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
3296{ .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
5a613584 3297{ .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_atihdmi },
84eb01be
TI		 3298{ .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
3299{ .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
3300{ .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
3301{ .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3302{ .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3303{ .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3304{ .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3305{ .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
611885bc
AH		 3306{ .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_nvhdmi },
3307{ .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_nvhdmi },
3308{ .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_nvhdmi },
3309{ .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_nvhdmi },
3310{ .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_nvhdmi },
3311{ .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_nvhdmi },
3312{ .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_nvhdmi },
3313{ .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_nvhdmi },
3314{ .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_nvhdmi },
3315{ .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_nvhdmi },
3316{ .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_nvhdmi },
c8900a0f 3317/* 17 is known to be absent */
611885bc
AH		 3318{ .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_nvhdmi },
3319{ .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_nvhdmi },
3320{ .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_nvhdmi },
3321{ .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_nvhdmi },
3322{ .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_nvhdmi },
3323{ .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_nvhdmi },
3324{ .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_nvhdmi },
3325{ .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_nvhdmi },
3326{ .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_nvhdmi },
3327{ .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_nvhdmi },
3328{ .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_nvhdmi },
3329{ .id = 0x10de0060, .name = "GPU 60 HDMI/DP", .patch = patch_nvhdmi },
84eb01be
TI		 3330{ .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
3331{ .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
3de5ff88
AL		 3332{ .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
3333{ .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
3334{ .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
3335{ .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 3336{ .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
3337{ .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
3338{ .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
3339{ .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
3340{ .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
3341{ .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
591e610d 3342{ .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
1c76684d 3343{ .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi },
3adadd28 3344{ .id = 0x80862808, .name = "Broadwell HDMI", .patch = patch_generic_hdmi },
6edc59e6 3345{ .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
cc1a95d9 3346{ .id = 0x80862882, .name = "Valleyview2 HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 3347{ .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
3348{} /* terminator */
3349};
3350
3351MODULE_ALIAS("snd-hda-codec-id:1002793c");
3352MODULE_ALIAS("snd-hda-codec-id:10027919");
3353MODULE_ALIAS("snd-hda-codec-id:1002791a");
3354MODULE_ALIAS("snd-hda-codec-id:1002aa01");
3355MODULE_ALIAS("snd-hda-codec-id:10951390");
3356MODULE_ALIAS("snd-hda-codec-id:10951392");
3357MODULE_ALIAS("snd-hda-codec-id:10de0002");
3358MODULE_ALIAS("snd-hda-codec-id:10de0003");
3359MODULE_ALIAS("snd-hda-codec-id:10de0005");
3360MODULE_ALIAS("snd-hda-codec-id:10de0006");
3361MODULE_ALIAS("snd-hda-codec-id:10de0007");
3362MODULE_ALIAS("snd-hda-codec-id:10de000a");
3363MODULE_ALIAS("snd-hda-codec-id:10de000b");
3364MODULE_ALIAS("snd-hda-codec-id:10de000c");
3365MODULE_ALIAS("snd-hda-codec-id:10de000d");
3366MODULE_ALIAS("snd-hda-codec-id:10de0010");
3367MODULE_ALIAS("snd-hda-codec-id:10de0011");
3368MODULE_ALIAS("snd-hda-codec-id:10de0012");
3369MODULE_ALIAS("snd-hda-codec-id:10de0013");
3370MODULE_ALIAS("snd-hda-codec-id:10de0014");
c8900a0f
RS		 3371MODULE_ALIAS("snd-hda-codec-id:10de0015");
3372MODULE_ALIAS("snd-hda-codec-id:10de0016");
84eb01be
TI		 3373MODULE_ALIAS("snd-hda-codec-id:10de0018");
3374MODULE_ALIAS("snd-hda-codec-id:10de0019");
3375MODULE_ALIAS("snd-hda-codec-id:10de001a");
3376MODULE_ALIAS("snd-hda-codec-id:10de001b");
3377MODULE_ALIAS("snd-hda-codec-id:10de001c");
3378MODULE_ALIAS("snd-hda-codec-id:10de0040");
3379MODULE_ALIAS("snd-hda-codec-id:10de0041");
3380MODULE_ALIAS("snd-hda-codec-id:10de0042");
3381MODULE_ALIAS("snd-hda-codec-id:10de0043");
3382MODULE_ALIAS("snd-hda-codec-id:10de0044");
7ae48b56 3383MODULE_ALIAS("snd-hda-codec-id:10de0051");
d52392b1 3384MODULE_ALIAS("snd-hda-codec-id:10de0060");
84eb01be
TI		 3385MODULE_ALIAS("snd-hda-codec-id:10de0067");
3386MODULE_ALIAS("snd-hda-codec-id:10de8001");
3de5ff88
AL		 3387MODULE_ALIAS("snd-hda-codec-id:11069f80");
3388MODULE_ALIAS("snd-hda-codec-id:11069f81");
3389MODULE_ALIAS("snd-hda-codec-id:11069f84");
3390MODULE_ALIAS("snd-hda-codec-id:11069f85");
84eb01be
TI		 3391MODULE_ALIAS("snd-hda-codec-id:17e80047");
3392MODULE_ALIAS("snd-hda-codec-id:80860054");
3393MODULE_ALIAS("snd-hda-codec-id:80862801");
3394MODULE_ALIAS("snd-hda-codec-id:80862802");
3395MODULE_ALIAS("snd-hda-codec-id:80862803");
3396MODULE_ALIAS("snd-hda-codec-id:80862804");
3397MODULE_ALIAS("snd-hda-codec-id:80862805");
591e610d 3398MODULE_ALIAS("snd-hda-codec-id:80862806");
1c76684d 3399MODULE_ALIAS("snd-hda-codec-id:80862807");
3adadd28 3400MODULE_ALIAS("snd-hda-codec-id:80862808");
6edc59e6 3401MODULE_ALIAS("snd-hda-codec-id:80862880");
cc1a95d9 3402MODULE_ALIAS("snd-hda-codec-id:80862882");
84eb01be
TI		 3403MODULE_ALIAS("snd-hda-codec-id:808629fb");
3404
3405MODULE_LICENSE("GPL");
3406MODULE_DESCRIPTION("HDMI HD-audio codec");
3407MODULE_ALIAS("snd-hda-codec-intelhdmi");
3408MODULE_ALIAS("snd-hda-codec-nvhdmi");
3409MODULE_ALIAS("snd-hda-codec-atihdmi");
3410
3411static struct hda_codec_preset_list intel_list = {
3412 .preset = snd_hda_preset_hdmi,
3413 .owner = THIS_MODULE,
3414};
3415
3416static int __init patch_hdmi_init(void)
3417{
3418 return snd_hda_add_codec_preset(&intel_list);
3419}
3420
3421static void __exit patch_hdmi_exit(void)
3422{
3423 snd_hda_delete_codec_preset(&intel_list);
3424}
3425
3426module_init(patch_hdmi_init)
3427module_exit(patch_hdmi_exit)
Linux kernel - Deliverables
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