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ALSA: hda - hdmi: Tweak debug messages to be more useful
[deliverable/linux.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
079d88cc
WF		 9 *
10 * Authors:
11 * Wu Fengguang <wfg@linux.intel.com>
12 *
13 * Maintained by:
14 * Wu Fengguang <wfg@linux.intel.com>
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the Free
18 * Software Foundation; either version 2 of the License, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful, but
22 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
23 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 * for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software Foundation,
28 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
84eb01be
TI		 31#include <linux/init.h>
32#include <linux/delay.h>
33#include <linux/slab.h>
65a77217 34#include <linux/module.h>
84eb01be 35#include <sound/core.h>
07acecc1 36#include <sound/jack.h>
433968da 37#include <sound/asoundef.h>
d45e6889 38#include <sound/tlv.h>
84eb01be
TI		 39#include "hda_codec.h"
40#include "hda_local.h"
1835a0f9 41#include "hda_jack.h"
84eb01be 42
0ebaa24c
TI		 43static bool static_hdmi_pcm;
44module_param(static_hdmi_pcm, bool, 0644);
45MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
46
fb87fa3a
ML		 47#define is_haswell(codec) ((codec)->vendor_id == 0x80862807)
48
384a48d7
SW		 49struct hdmi_spec_per_cvt {
50 hda_nid_t cvt_nid;
51 int assigned;
52 unsigned int channels_min;
53 unsigned int channels_max;
54 u32 rates;
55 u64 formats;
56 unsigned int maxbps;
57};
079d88cc 58
4eea3091
TI		 59/* max. connections to a widget */
60#define HDA_MAX_CONNECTIONS 32
61
384a48d7
SW		 62struct hdmi_spec_per_pin {
63 hda_nid_t pin_nid;
64 int num_mux_nids;
65 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
1df5a06a 66 hda_nid_t cvt_nid;
744626da
WF		 67
68 struct hda_codec *codec;
384a48d7 69 struct hdmi_eld sink_eld;
744626da 70 struct delayed_work work;
92c69e79 71 struct snd_kcontrol *eld_ctl;
c6e8453e 72 int repoll_count;
b054087d
TI		 73 bool setup; /* the stream has been set up by prepare callback */
74 int channels; /* current number of channels */
1a6003b5 75 bool non_pcm;
d45e6889
TI		 76 bool chmap_set; /* channel-map override by ALSA API? */
77 unsigned char chmap[8]; /* ALSA API channel-map */
bce0d2a8 78 char pcm_name[8]; /* filled in build_pcm callbacks */
384a48d7 79};
079d88cc 80
384a48d7
SW		 81struct hdmi_spec {
82 int num_cvts;
bce0d2a8
TI		 83 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
84 hda_nid_t cvt_nids[4]; /* only for haswell fix */
079d88cc 85
384a48d7 86 int num_pins;
bce0d2a8
TI		 87 struct snd_array pins; /* struct hdmi_spec_per_pin */
88 struct snd_array pcm_rec; /* struct hda_pcm */
d45e6889 89 unsigned int channels_max; /* max over all cvts */
079d88cc 90
4bd038f9 91 struct hdmi_eld temp_eld;
079d88cc 92 /*
384a48d7 93 * Non-generic ATI/NVIDIA specific
079d88cc
WF		 94 */
95 struct hda_multi_out multiout;
d0b1252d 96 struct hda_pcm_stream pcm_playback;
079d88cc
WF		 97};
98
99
100struct hdmi_audio_infoframe {
101 u8 type; /* 0x84 */
102 u8 ver; /* 0x01 */
103 u8 len; /* 0x0a */
104
53d7d69d
WF		 105 u8 checksum;
106
079d88cc
WF		 107 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
108 u8 SS01_SF24;
109 u8 CXT04;
110 u8 CA;
111 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 112};
113
114struct dp_audio_infoframe {
115 u8 type; /* 0x84 */
116 u8 len; /* 0x1b */
117 u8 ver; /* 0x11 << 2 */
118
119 u8 CC02_CT47; /* match with HDMI infoframe from this on */
120 u8 SS01_SF24;
121 u8 CXT04;
122 u8 CA;
123 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 124};
125
2b203dbb
TI		 126union audio_infoframe {
127 struct hdmi_audio_infoframe hdmi;
128 struct dp_audio_infoframe dp;
129 u8 bytes[0];
130};
131
079d88cc
WF		 132/*
133 * CEA speaker placement:
134 *
135 * FLH FCH FRH
136 * FLW FL FLC FC FRC FR FRW
137 *
138 * LFE
139 * TC
140 *
141 * RL RLC RC RRC RR
142 *
143 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
144 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
145 */
146enum cea_speaker_placement {
147 FL = (1 << 0), /* Front Left */
148 FC = (1 << 1), /* Front Center */
149 FR = (1 << 2), /* Front Right */
150 FLC = (1 << 3), /* Front Left Center */
151 FRC = (1 << 4), /* Front Right Center */
152 RL = (1 << 5), /* Rear Left */
153 RC = (1 << 6), /* Rear Center */
154 RR = (1 << 7), /* Rear Right */
155 RLC = (1 << 8), /* Rear Left Center */
156 RRC = (1 << 9), /* Rear Right Center */
157 LFE = (1 << 10), /* Low Frequency Effect */
158 FLW = (1 << 11), /* Front Left Wide */
159 FRW = (1 << 12), /* Front Right Wide */
160 FLH = (1 << 13), /* Front Left High */
161 FCH = (1 << 14), /* Front Center High */
162 FRH = (1 << 15), /* Front Right High */
163 TC = (1 << 16), /* Top Center */
164};
165
166/*
167 * ELD SA bits in the CEA Speaker Allocation data block
168 */
169static int eld_speaker_allocation_bits[] = {
170 [0] = FL | FR,
171 [1] = LFE,
172 [2] = FC,
173 [3] = RL | RR,
174 [4] = RC,
175 [5] = FLC | FRC,
176 [6] = RLC | RRC,
177 /* the following are not defined in ELD yet */
178 [7] = FLW | FRW,
179 [8] = FLH | FRH,
180 [9] = TC,
181 [10] = FCH,
182};
183
184struct cea_channel_speaker_allocation {
185 int ca_index;
186 int speakers[8];
187
188 /* derived values, just for convenience */
189 int channels;
190 int spk_mask;
191};
192
193/*
194 * ALSA sequence is:
195 *
196 * surround40 surround41 surround50 surround51 surround71
197 * ch0 front left = = = =
198 * ch1 front right = = = =
199 * ch2 rear left = = = =
200 * ch3 rear right = = = =
201 * ch4 LFE center center center
202 * ch5 LFE LFE
203 * ch6 side left
204 * ch7 side right
205 *
206 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
207 */
208static int hdmi_channel_mapping[0x32][8] = {
209 /* stereo */
210 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
211 /* 2.1 */
212 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
213 /* Dolby Surround */
214 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
215 /* surround40 */
216 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
217 /* 4ch */
218 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
219 /* surround41 */
9396d317 220 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 221 /* surround50 */
222 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
223 /* surround51 */
224 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
225 /* 7.1 */
226 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
227};
228
229/*
230 * This is an ordered list!
231 *
232 * The preceding ones have better chances to be selected by
53d7d69d 233 * hdmi_channel_allocation().
079d88cc
WF		 234 */
235static struct cea_channel_speaker_allocation channel_allocations[] = {
236/* channel: 7 6 5 4 3 2 1 0 */
237{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
238 /* 2.1 */
239{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
240 /* Dolby Surround */
241{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
242 /* surround40 */
243{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
244 /* surround41 */
245{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
246 /* surround50 */
247{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
248 /* surround51 */
249{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
250 /* 6.1 */
251{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
252 /* surround71 */
253{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
254
255{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
256{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
257{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
258{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
259{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
260{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
261{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
262{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
263{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
264{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
265{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
266{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
267{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
268{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
269{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
270{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
271{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
272{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
273{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
274{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
275{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
276{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
277{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
278{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
279{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
280{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
281{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
282{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
283{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
284{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
285{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
286{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
287{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
288{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
289{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
290{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
291{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
292{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
293{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
294{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
295{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
296};
297
298
299/*
300 * HDMI routines
301 */
302
bce0d2a8
TI		 303#define get_pin(spec, idx) \
304 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
305#define get_cvt(spec, idx) \
306 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
307#define get_pcm_rec(spec, idx) \
308 ((struct hda_pcm *)snd_array_elem(&spec->pcm_rec, idx))
309
384a48d7 310static int pin_nid_to_pin_index(struct hdmi_spec *spec, hda_nid_t pin_nid)
079d88cc 311{
384a48d7 312 int pin_idx;
079d88cc 313
384a48d7 314 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 315 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
384a48d7 316 return pin_idx;
079d88cc 317
384a48d7
SW		 318 snd_printk(KERN_WARNING "HDMI: pin nid %d not registered\n", pin_nid);
319 return -EINVAL;
320}
321
322static int hinfo_to_pin_index(struct hdmi_spec *spec,
323 struct hda_pcm_stream *hinfo)
324{
325 int pin_idx;
326
327 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 328 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
384a48d7
SW		 329 return pin_idx;
330
331 snd_printk(KERN_WARNING "HDMI: hinfo %p not registered\n", hinfo);
332 return -EINVAL;
333}
334
335static int cvt_nid_to_cvt_index(struct hdmi_spec *spec, hda_nid_t cvt_nid)
336{
337 int cvt_idx;
338
339 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
bce0d2a8 340 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
384a48d7
SW		 341 return cvt_idx;
342
343 snd_printk(KERN_WARNING "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 344 return -EINVAL;
345}
346
14bc52b8
PLB		 347static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
348 struct snd_ctl_elem_info *uinfo)
349{
350 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9
DH		 351 struct hdmi_spec *spec = codec->spec;
352 struct hdmi_eld *eld;
14bc52b8
PLB		 353 int pin_idx;
354
14bc52b8
PLB		 355 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
356
357 pin_idx = kcontrol->private_value;
bce0d2a8 358 eld = &get_pin(spec, pin_idx)->sink_eld;
68e03de9 359
4bd038f9 360 mutex_lock(&eld->lock);
68e03de9 361 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
4bd038f9 362 mutex_unlock(&eld->lock);
14bc52b8
PLB		 363
364 return 0;
365}
366
367static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
368 struct snd_ctl_elem_value *ucontrol)
369{
370 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9
DH		 371 struct hdmi_spec *spec = codec->spec;
372 struct hdmi_eld *eld;
14bc52b8
PLB		 373 int pin_idx;
374
14bc52b8 375 pin_idx = kcontrol->private_value;
bce0d2a8 376 eld = &get_pin(spec, pin_idx)->sink_eld;
68e03de9 377
4bd038f9 378 mutex_lock(&eld->lock);
68e03de9 379 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
4bd038f9 380 mutex_unlock(&eld->lock);
68e03de9
DH		 381 snd_BUG();
382 return -EINVAL;
383 }
384
385 memset(ucontrol->value.bytes.data, 0,
386 ARRAY_SIZE(ucontrol->value.bytes.data));
387 if (eld->eld_valid)
388 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
389 eld->eld_size);
4bd038f9 390 mutex_unlock(&eld->lock);
14bc52b8
PLB		 391
392 return 0;
393}
394
395static struct snd_kcontrol_new eld_bytes_ctl = {
396 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
397 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
398 .name = "ELD",
399 .info = hdmi_eld_ctl_info,
400 .get = hdmi_eld_ctl_get,
401};
402
403static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
404 int device)
405{
406 struct snd_kcontrol *kctl;
407 struct hdmi_spec *spec = codec->spec;
408 int err;
409
410 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
411 if (!kctl)
412 return -ENOMEM;
413 kctl->private_value = pin_idx;
414 kctl->id.device = device;
415
bce0d2a8 416 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
14bc52b8
PLB		 417 if (err < 0)
418 return err;
419
bce0d2a8 420 get_pin(spec, pin_idx)->eld_ctl = kctl;
14bc52b8
PLB		 421 return 0;
422}
423
079d88cc
WF		 424#ifdef BE_PARANOID
425static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
426 int *packet_index, int *byte_index)
427{
428 int val;
429
430 val = snd_hda_codec_read(codec, pin_nid, 0,
431 AC_VERB_GET_HDMI_DIP_INDEX, 0);
432
433 *packet_index = val >> 5;
434 *byte_index = val & 0x1f;
435}
436#endif
437
438static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
439 int packet_index, int byte_index)
440{
441 int val;
442
443 val = (packet_index << 5) | (byte_index & 0x1f);
444
445 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
446}
447
448static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
449 unsigned char val)
450{
451 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
452}
453
384a48d7 454static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc
WF		 455{
456 /* Unmute */
457 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
458 snd_hda_codec_write(codec, pin_nid, 0,
459 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
6169b673
TI		 460 /* Enable pin out: some machines with GM965 gets broken output when
461 * the pin is disabled or changed while using with HDMI
462 */
079d88cc 463 snd_hda_codec_write(codec, pin_nid, 0,
6169b673 464 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
079d88cc
WF		 465}
466
384a48d7 467static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc 468{
384a48d7 469 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
079d88cc
WF		 470 AC_VERB_GET_CVT_CHAN_COUNT, 0);
471}
472
473static void hdmi_set_channel_count(struct hda_codec *codec,
384a48d7 474 hda_nid_t cvt_nid, int chs)
079d88cc 475{
384a48d7
SW		 476 if (chs != hdmi_get_channel_count(codec, cvt_nid))
477 snd_hda_codec_write(codec, cvt_nid, 0,
079d88cc
WF		 478 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
479}
480
481
482/*
483 * Channel mapping routines
484 */
485
486/*
487 * Compute derived values in channel_allocations[].
488 */
489static void init_channel_allocations(void)
490{
491 int i, j;
492 struct cea_channel_speaker_allocation *p;
493
494 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
495 p = channel_allocations + i;
496 p->channels = 0;
497 p->spk_mask = 0;
498 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
499 if (p->speakers[j]) {
500 p->channels++;
501 p->spk_mask |= p->speakers[j];
502 }
503 }
504}
505
72357c78
WX		 506static int get_channel_allocation_order(int ca)
507{
508 int i;
509
510 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
511 if (channel_allocations[i].ca_index == ca)
512 break;
513 }
514 return i;
515}
516
079d88cc
WF		 517/*
518 * The transformation takes two steps:
519 *
520 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
521 * spk_mask => (channel_allocations[]) => ai->CA
522 *
523 * TODO: it could select the wrong CA from multiple candidates.
524*/
384a48d7 525static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
079d88cc 526{
079d88cc 527 int i;
53d7d69d 528 int ca = 0;
079d88cc 529 int spk_mask = 0;
079d88cc
WF		 530 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
531
532 /*
533 * CA defaults to 0 for basic stereo audio
534 */
535 if (channels <= 2)
536 return 0;
537
079d88cc
WF		 538 /*
539 * expand ELD's speaker allocation mask
540 *
541 * ELD tells the speaker mask in a compact(paired) form,
542 * expand ELD's notions to match the ones used by Audio InfoFrame.
543 */
544 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
1613d6b4 545 if (eld->info.spk_alloc & (1 << i))
079d88cc
WF		 546 spk_mask |= eld_speaker_allocation_bits[i];
547 }
548
549 /* search for the first working match in the CA table */
550 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
551 if (channels == channel_allocations[i].channels &&
552 (spk_mask & channel_allocations[i].spk_mask) ==
553 channel_allocations[i].spk_mask) {
53d7d69d 554 ca = channel_allocations[i].ca_index;
079d88cc
WF		 555 break;
556 }
557 }
558
18e39186
AH		 559 if (!ca) {
560 /* if there was no match, select the regular ALSA channel
561 * allocation with the matching number of channels */
562 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
563 if (channels == channel_allocations[i].channels) {
564 ca = channel_allocations[i].ca_index;
565 break;
566 }
567 }
568 }
569
1613d6b4 570 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
2abbf439 571 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 572 ca, channels, buf);
079d88cc 573
53d7d69d 574 return ca;
079d88cc
WF		 575}
576
577static void hdmi_debug_channel_mapping(struct hda_codec *codec,
578 hda_nid_t pin_nid)
579{
580#ifdef CONFIG_SND_DEBUG_VERBOSE
581 int i;
582 int slot;
583
584 for (i = 0; i < 8; i++) {
585 slot = snd_hda_codec_read(codec, pin_nid, 0,
586 AC_VERB_GET_HDMI_CHAN_SLOT, i);
587 printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
588 slot >> 4, slot & 0xf);
589 }
590#endif
591}
592
593
d45e6889 594static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
079d88cc 595 hda_nid_t pin_nid,
433968da 596 bool non_pcm,
53d7d69d 597 int ca)
079d88cc 598{
90f28002 599 struct cea_channel_speaker_allocation *ch_alloc;
079d88cc 600 int i;
079d88cc 601 int err;
72357c78 602 int order;
433968da 603 int non_pcm_mapping[8];
079d88cc 604
72357c78 605 order = get_channel_allocation_order(ca);
90f28002 606 ch_alloc = &channel_allocations[order];
433968da 607
079d88cc 608 if (hdmi_channel_mapping[ca][1] == 0) {
90f28002
AH		 609 int hdmi_slot = 0;
610 /* fill actual channel mappings in ALSA channel (i) order */
611 for (i = 0; i < ch_alloc->channels; i++) {
612 while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
613 hdmi_slot++; /* skip zero slots */
614
615 hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
616 }
617 /* fill the rest of the slots with ALSA channel 0xf */
618 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
619 if (!ch_alloc->speakers[7 - hdmi_slot])
620 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
079d88cc
WF		 621 }
622
433968da 623 if (non_pcm) {
90f28002 624 for (i = 0; i < ch_alloc->channels; i++)
11f7c52d 625 non_pcm_mapping[i] = (i << 4) | i;
433968da 626 for (; i < 8; i++)
11f7c52d 627 non_pcm_mapping[i] = (0xf << 4) | i;
433968da
WX		 628 }
629
079d88cc
WF		 630 for (i = 0; i < 8; i++) {
631 err = snd_hda_codec_write(codec, pin_nid, 0,
632 AC_VERB_SET_HDMI_CHAN_SLOT,
433968da 633 non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i]);
079d88cc 634 if (err) {
2abbf439
WF		 635 snd_printdd(KERN_NOTICE
636 "HDMI: channel mapping failed\n");
079d88cc
WF		 637 break;
638 }
639 }
079d88cc
WF		 640}
641
d45e6889
TI		 642struct channel_map_table {
643 unsigned char map; /* ALSA API channel map position */
d45e6889
TI		 644 int spk_mask; /* speaker position bit mask */
645};
646
647static struct channel_map_table map_tables[] = {
a5b7d510
AH		 648 { SNDRV_CHMAP_FL, FL },
649 { SNDRV_CHMAP_FR, FR },
650 { SNDRV_CHMAP_RL, RL },
651 { SNDRV_CHMAP_RR, RR },
652 { SNDRV_CHMAP_LFE, LFE },
653 { SNDRV_CHMAP_FC, FC },
654 { SNDRV_CHMAP_RLC, RLC },
655 { SNDRV_CHMAP_RRC, RRC },
656 { SNDRV_CHMAP_RC, RC },
657 { SNDRV_CHMAP_FLC, FLC },
658 { SNDRV_CHMAP_FRC, FRC },
659 { SNDRV_CHMAP_FLH, FLH },
660 { SNDRV_CHMAP_FRH, FRH },
661 { SNDRV_CHMAP_FLW, FLW },
662 { SNDRV_CHMAP_FRW, FRW },
663 { SNDRV_CHMAP_TC, TC },
664 { SNDRV_CHMAP_FCH, FCH },
d45e6889
TI		 665 {} /* terminator */
666};
667
668/* from ALSA API channel position to speaker bit mask */
669static int to_spk_mask(unsigned char c)
670{
671 struct channel_map_table *t = map_tables;
672 for (; t->map; t++) {
673 if (t->map == c)
674 return t->spk_mask;
675 }
676 return 0;
677}
678
679/* from ALSA API channel position to CEA slot */
a5b7d510 680static int to_cea_slot(int ordered_ca, unsigned char pos)
d45e6889 681{
a5b7d510
AH		 682 int mask = to_spk_mask(pos);
683 int i;
d45e6889 684
a5b7d510
AH		 685 if (mask) {
686 for (i = 0; i < 8; i++) {
687 if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
688 return i;
689 }
d45e6889 690 }
a5b7d510
AH		 691
692 return -1;
d45e6889
TI		 693}
694
695/* from speaker bit mask to ALSA API channel position */
696static int spk_to_chmap(int spk)
697{
698 struct channel_map_table *t = map_tables;
699 for (; t->map; t++) {
700 if (t->spk_mask == spk)
701 return t->map;
702 }
703 return 0;
704}
705
a5b7d510
AH		 706/* from CEA slot to ALSA API channel position */
707static int from_cea_slot(int ordered_ca, unsigned char slot)
708{
709 int mask = channel_allocations[ordered_ca].speakers[7 - slot];
710
711 return spk_to_chmap(mask);
712}
713
d45e6889
TI		 714/* get the CA index corresponding to the given ALSA API channel map */
715static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
716{
717 int i, spks = 0, spk_mask = 0;
718
719 for (i = 0; i < chs; i++) {
720 int mask = to_spk_mask(map[i]);
721 if (mask) {
722 spk_mask |= mask;
723 spks++;
724 }
725 }
726
727 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
728 if ((chs == channel_allocations[i].channels ||
729 spks == channel_allocations[i].channels) &&
730 (spk_mask & channel_allocations[i].spk_mask) ==
731 channel_allocations[i].spk_mask)
732 return channel_allocations[i].ca_index;
733 }
734 return -1;
735}
736
737/* set up the channel slots for the given ALSA API channel map */
738static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
739 hda_nid_t pin_nid,
a5b7d510
AH		 740 int chs, unsigned char *map,
741 int ca)
d45e6889 742{
a5b7d510 743 int ordered_ca = get_channel_allocation_order(ca);
11f7c52d
AH		 744 int alsa_pos, hdmi_slot;
745 int assignments[8] = {[0 ... 7] = 0xf};
746
747 for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
748
a5b7d510 749 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
11f7c52d
AH		 750
751 if (hdmi_slot < 0)
752 continue; /* unassigned channel */
753
754 assignments[hdmi_slot] = alsa_pos;
755 }
756
757 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
d45e6889 758 int val, err;
11f7c52d
AH		 759
760 val = (assignments[hdmi_slot] << 4) | hdmi_slot;
d45e6889
TI		 761 err = snd_hda_codec_write(codec, pin_nid, 0,
762 AC_VERB_SET_HDMI_CHAN_SLOT, val);
763 if (err)
764 return -EINVAL;
765 }
766 return 0;
767}
768
769/* store ALSA API channel map from the current default map */
770static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
771{
772 int i;
56cac413 773 int ordered_ca = get_channel_allocation_order(ca);
d45e6889 774 for (i = 0; i < 8; i++) {
56cac413 775 if (i < channel_allocations[ordered_ca].channels)
a5b7d510 776 map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
d45e6889
TI		 777 else
778 map[i] = 0;
779 }
780}
781
782static void hdmi_setup_channel_mapping(struct hda_codec *codec,
783 hda_nid_t pin_nid, bool non_pcm, int ca,
20608731
AH		 784 int channels, unsigned char *map,
785 bool chmap_set)
d45e6889 786{
20608731 787 if (!non_pcm && chmap_set) {
d45e6889 788 hdmi_manual_setup_channel_mapping(codec, pin_nid,
a5b7d510 789 channels, map, ca);
d45e6889
TI		 790 } else {
791 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
792 hdmi_setup_fake_chmap(map, ca);
793 }
980b2495
AH		 794
795 hdmi_debug_channel_mapping(codec, pin_nid);
d45e6889 796}
079d88cc
WF		 797
798/*
799 * Audio InfoFrame routines
800 */
801
802/*
803 * Enable Audio InfoFrame Transmission
804 */
805static void hdmi_start_infoframe_trans(struct hda_codec *codec,
806 hda_nid_t pin_nid)
807{
808 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
809 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
810 AC_DIPXMIT_BEST);
811}
812
813/*
814 * Disable Audio InfoFrame Transmission
815 */
816static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
817 hda_nid_t pin_nid)
818{
819 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
820 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
821 AC_DIPXMIT_DISABLE);
822}
823
824static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
825{
826#ifdef CONFIG_SND_DEBUG_VERBOSE
827 int i;
828 int size;
829
830 size = snd_hdmi_get_eld_size(codec, pin_nid);
831 printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
832
833 for (i = 0; i < 8; i++) {
834 size = snd_hda_codec_read(codec, pin_nid, 0,
835 AC_VERB_GET_HDMI_DIP_SIZE, i);
836 printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
837 }
838#endif
839}
840
841static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
842{
843#ifdef BE_PARANOID
844 int i, j;
845 int size;
846 int pi, bi;
847 for (i = 0; i < 8; i++) {
848 size = snd_hda_codec_read(codec, pin_nid, 0,
849 AC_VERB_GET_HDMI_DIP_SIZE, i);
850 if (size == 0)
851 continue;
852
853 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
854 for (j = 1; j < 1000; j++) {
855 hdmi_write_dip_byte(codec, pin_nid, 0x0);
856 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
857 if (pi != i)
858 snd_printd(KERN_INFO "dip index %d: %d != %d\n",
859 bi, pi, i);
860 if (bi == 0) /* byte index wrapped around */
861 break;
862 }
863 snd_printd(KERN_INFO
864 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
865 i, size, j);
866 }
867#endif
868}
869
53d7d69d 870static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 871{
53d7d69d 872 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 873 u8 sum = 0;
874 int i;
875
53d7d69d 876 hdmi_ai->checksum = 0;
079d88cc 877
53d7d69d 878 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 879 sum += bytes[i];
880
53d7d69d 881 hdmi_ai->checksum = -sum;
079d88cc
WF		 882}
883
884static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
885 hda_nid_t pin_nid,
53d7d69d 886 u8 *dip, int size)
079d88cc 887{
079d88cc
WF		 888 int i;
889
890 hdmi_debug_dip_size(codec, pin_nid);
891 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
892
079d88cc 893 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 894 for (i = 0; i < size; i++)
895 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 896}
897
898static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 899 u8 *dip, int size)
079d88cc 900{
079d88cc
WF		 901 u8 val;
902 int i;
903
904 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
905 != AC_DIPXMIT_BEST)
906 return false;
907
908 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 909 for (i = 0; i < size; i++) {
079d88cc
WF		 910 val = snd_hda_codec_read(codec, pin_nid, 0,
911 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 912 if (val != dip[i])
079d88cc
WF		 913 return false;
914 }
915
916 return true;
917}
918
b054087d
TI		 919static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
920 struct hdmi_spec_per_pin *per_pin,
921 bool non_pcm)
079d88cc 922{
384a48d7 923 hda_nid_t pin_nid = per_pin->pin_nid;
b054087d 924 int channels = per_pin->channels;
1df5a06a 925 int active_channels;
384a48d7 926 struct hdmi_eld *eld;
1df5a06a 927 int ca, ordered_ca;
2b203dbb 928 union audio_infoframe ai;
079d88cc 929
b054087d
TI		 930 if (!channels)
931 return;
932
58f7d28d
ML		 933 if (is_haswell(codec))
934 snd_hda_codec_write(codec, pin_nid, 0,
935 AC_VERB_SET_AMP_GAIN_MUTE,
936 AMP_OUT_UNMUTE);
937
bce0d2a8 938 eld = &per_pin->sink_eld;
384a48d7
SW		 939 if (!eld->monitor_present)
940 return;
079d88cc 941
d45e6889
TI		 942 if (!non_pcm && per_pin->chmap_set)
943 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
944 else
945 ca = hdmi_channel_allocation(eld, channels);
946 if (ca < 0)
947 ca = 0;
384a48d7 948
1df5a06a
AH		 949 ordered_ca = get_channel_allocation_order(ca);
950 active_channels = channel_allocations[ordered_ca].channels;
951
952 hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
953
384a48d7 954 memset(&ai, 0, sizeof(ai));
1613d6b4 955 if (eld->info.conn_type == 0) { /* HDMI */
384a48d7
SW		 956 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
957
958 hdmi_ai->type = 0x84;
959 hdmi_ai->ver = 0x01;
960 hdmi_ai->len = 0x0a;
1df5a06a 961 hdmi_ai->CC02_CT47 = active_channels - 1;
384a48d7
SW		 962 hdmi_ai->CA = ca;
963 hdmi_checksum_audio_infoframe(hdmi_ai);
1613d6b4 964 } else if (eld->info.conn_type == 1) { /* DisplayPort */
384a48d7
SW		 965 struct dp_audio_infoframe *dp_ai = &ai.dp;
966
967 dp_ai->type = 0x84;
968 dp_ai->len = 0x1b;
969 dp_ai->ver = 0x11 << 2;
1df5a06a 970 dp_ai->CC02_CT47 = active_channels - 1;
384a48d7
SW		 971 dp_ai->CA = ca;
972 } else {
973 snd_printd("HDMI: unknown connection type at pin %d\n",
974 pin_nid);
975 return;
976 }
53d7d69d 977
384a48d7
SW		 978 /*
979 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
980 * sizeof(*dp_ai) to avoid partial match/update problems when
981 * the user switches between HDMI/DP monitors.
982 */
983 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
984 sizeof(ai))) {
985 snd_printdd("hdmi_setup_audio_infoframe: "
980b2495 986 "pin=%d channels=%d ca=0x%02x\n",
384a48d7 987 pin_nid,
980b2495 988 active_channels, ca);
d45e6889 989 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
20608731
AH		 990 channels, per_pin->chmap,
991 per_pin->chmap_set);
384a48d7
SW		 992 hdmi_stop_infoframe_trans(codec, pin_nid);
993 hdmi_fill_audio_infoframe(codec, pin_nid,
994 ai.bytes, sizeof(ai));
995 hdmi_start_infoframe_trans(codec, pin_nid);
2d7e887c
WX		 996 } else {
997 /* For non-pcm audio switch, setup new channel mapping
998 * accordingly */
1a6003b5 999 if (per_pin->non_pcm != non_pcm)
d45e6889 1000 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
20608731
AH		 1001 channels, per_pin->chmap,
1002 per_pin->chmap_set);
079d88cc 1003 }
433968da 1004
1a6003b5 1005 per_pin->non_pcm = non_pcm;
079d88cc
WF		 1006}
1007
1008
1009/*
1010 * Unsolicited events
1011 */
1012
c6e8453e 1013static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 1014
079d88cc
WF		 1015static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1016{
1017 struct hdmi_spec *spec = codec->spec;
3a93897e
TI		 1018 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1019 int pin_nid;
384a48d7 1020 int pin_idx;
3a93897e 1021 struct hda_jack_tbl *jack;
2e59e5ab 1022 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
3a93897e
TI		 1023
1024 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1025 if (!jack)
1026 return;
1027 pin_nid = jack->nid;
1028 jack->jack_dirty = 1;
079d88cc 1029
fae3d88a 1030 _snd_printd(SND_PR_VERBOSE,
2e59e5ab
ML		 1031 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
1032 codec->addr, pin_nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
fae3d88a 1033 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 1034
384a48d7
SW		 1035 pin_idx = pin_nid_to_pin_index(spec, pin_nid);
1036 if (pin_idx < 0)
079d88cc
WF		 1037 return;
1038
bce0d2a8 1039 hdmi_present_sense(get_pin(spec, pin_idx), 1);
01a61e12 1040 snd_hda_jack_report_sync(codec);
079d88cc
WF		 1041}
1042
1043static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1044{
1045 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1046 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1047 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1048 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1049
1050 printk(KERN_INFO
e9ea8e8f 1051 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 1052 codec->addr,
079d88cc
WF		 1053 tag,
1054 subtag,
1055 cp_state,
1056 cp_ready);
1057
1058 /* TODO */
1059 if (cp_state)
1060 ;
1061 if (cp_ready)
1062 ;
1063}
1064
1065
1066static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1067{
079d88cc
WF		 1068 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1069 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1070
3a93897e 1071 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
079d88cc
WF		 1072 snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
1073 return;
1074 }
1075
1076 if (subtag == 0)
1077 hdmi_intrinsic_event(codec, res);
1078 else
1079 hdmi_non_intrinsic_event(codec, res);
1080}
1081
58f7d28d 1082static void haswell_verify_D0(struct hda_codec *codec,
53b434f0 1083 hda_nid_t cvt_nid, hda_nid_t nid)
83f26ad2 1084{
58f7d28d 1085 int pwr;
83f26ad2 1086
53b434f0
WX		 1087 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1088 * thus pins could only choose converter 0 for use. Make sure the
1089 * converters are in correct power state */
fd678cac 1090 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
53b434f0
WX		 1091 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1092
fd678cac 1093 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
83f26ad2
DH		 1094 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1095 AC_PWRST_D0);
1096 msleep(40);
1097 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1098 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
1099 snd_printd("Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
1100 }
83f26ad2
DH		 1101}
1102
079d88cc
WF		 1103/*
1104 * Callbacks
1105 */
1106
92f10b3f
TI		 1107/* HBR should be Non-PCM, 8 channels */
1108#define is_hbr_format(format) \
1109 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1110
384a48d7
SW		 1111static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1112 hda_nid_t pin_nid, u32 stream_tag, int format)
079d88cc 1113{
ea87d1c4
AH		 1114 int pinctl;
1115 int new_pinctl = 0;
ea87d1c4 1116
fb87fa3a 1117 if (is_haswell(codec))
58f7d28d 1118 haswell_verify_D0(codec, cvt_nid, pin_nid);
83f26ad2 1119
384a48d7
SW		 1120 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1121 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 1122 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1123
1124 new_pinctl = pinctl & ~AC_PINCTL_EPT;
92f10b3f 1125 if (is_hbr_format(format))
ea87d1c4
AH		 1126 new_pinctl |= AC_PINCTL_EPT_HBR;
1127 else
1128 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1129
1130 snd_printdd("hdmi_setup_stream: "
1131 "NID=0x%x, %spinctl=0x%x\n",
384a48d7 1132 pin_nid,
ea87d1c4
AH		 1133 pinctl == new_pinctl ? "" : "new-",
1134 new_pinctl);
1135
1136 if (pinctl != new_pinctl)
384a48d7 1137 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 1138 AC_VERB_SET_PIN_WIDGET_CONTROL,
1139 new_pinctl);
ea87d1c4 1140
384a48d7 1141 }
92f10b3f 1142 if (is_hbr_format(format) && !new_pinctl) {
ea87d1c4
AH		 1143 snd_printdd("hdmi_setup_stream: HBR is not supported\n");
1144 return -EINVAL;
1145 }
079d88cc 1146
384a48d7 1147 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 1148 return 0;
079d88cc
WF		 1149}
1150
7ef166b8
WX		 1151static int hdmi_choose_cvt(struct hda_codec *codec,
1152 int pin_idx, int *cvt_id, int *mux_id)
bbbe3390
TI		 1153{
1154 struct hdmi_spec *spec = codec->spec;
384a48d7 1155 struct hdmi_spec_per_pin *per_pin;
384a48d7 1156 struct hdmi_spec_per_cvt *per_cvt = NULL;
7ef166b8 1157 int cvt_idx, mux_idx = 0;
bbbe3390 1158
bce0d2a8 1159 per_pin = get_pin(spec, pin_idx);
384a48d7
SW		 1160
1161 /* Dynamically assign converter to stream */
1162 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
bce0d2a8 1163 per_cvt = get_cvt(spec, cvt_idx);
bbbe3390 1164
384a48d7
SW		 1165 /* Must not already be assigned */
1166 if (per_cvt->assigned)
1167 continue;
1168 /* Must be in pin's mux's list of converters */
1169 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1170 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1171 break;
1172 /* Not in mux list */
1173 if (mux_idx == per_pin->num_mux_nids)
1174 continue;
1175 break;
1176 }
7ef166b8 1177
384a48d7
SW		 1178 /* No free converters */
1179 if (cvt_idx == spec->num_cvts)
1180 return -ENODEV;
1181
7ef166b8
WX		 1182 if (cvt_id)
1183 *cvt_id = cvt_idx;
1184 if (mux_id)
1185 *mux_id = mux_idx;
1186
1187 return 0;
1188}
1189
1190static void haswell_config_cvts(struct hda_codec *codec,
f82d7d16 1191 hda_nid_t pin_nid, int mux_idx)
7ef166b8
WX		 1192{
1193 struct hdmi_spec *spec = codec->spec;
f82d7d16
ML		 1194 hda_nid_t nid, end_nid;
1195 int cvt_idx, curr;
1196 struct hdmi_spec_per_cvt *per_cvt;
7ef166b8 1197
f82d7d16
ML		 1198 /* configure all pins, including "no physical connection" ones */
1199 end_nid = codec->start_nid + codec->num_nodes;
1200 for (nid = codec->start_nid; nid < end_nid; nid++) {
1201 unsigned int wid_caps = get_wcaps(codec, nid);
1202 unsigned int wid_type = get_wcaps_type(wid_caps);
1203
1204 if (wid_type != AC_WID_PIN)
1205 continue;
7ef166b8 1206
f82d7d16 1207 if (nid == pin_nid)
7ef166b8
WX		 1208 continue;
1209
f82d7d16 1210 curr = snd_hda_codec_read(codec, nid, 0,
7ef166b8 1211 AC_VERB_GET_CONNECT_SEL, 0);
f82d7d16
ML		 1212 if (curr != mux_idx)
1213 continue;
7ef166b8 1214
f82d7d16
ML		 1215 /* choose an unassigned converter. The conveters in the
1216 * connection list are in the same order as in the codec.
1217 */
1218 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1219 per_cvt = get_cvt(spec, cvt_idx);
1220 if (!per_cvt->assigned) {
1221 snd_printdd("choose cvt %d for pin nid %d\n",
1222 cvt_idx, nid);
1223 snd_hda_codec_write_cache(codec, nid, 0,
7ef166b8 1224 AC_VERB_SET_CONNECT_SEL,
f82d7d16
ML		 1225 cvt_idx);
1226 break;
1227 }
7ef166b8
WX		 1228 }
1229 }
1230}
1231
1232/*
1233 * HDA PCM callbacks
1234 */
1235static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1236 struct hda_codec *codec,
1237 struct snd_pcm_substream *substream)
1238{
1239 struct hdmi_spec *spec = codec->spec;
1240 struct snd_pcm_runtime *runtime = substream->runtime;
1241 int pin_idx, cvt_idx, mux_idx = 0;
1242 struct hdmi_spec_per_pin *per_pin;
1243 struct hdmi_eld *eld;
1244 struct hdmi_spec_per_cvt *per_cvt = NULL;
1245 int err;
1246
1247 /* Validate hinfo */
1248 pin_idx = hinfo_to_pin_index(spec, hinfo);
1249 if (snd_BUG_ON(pin_idx < 0))
1250 return -EINVAL;
1251 per_pin = get_pin(spec, pin_idx);
1252 eld = &per_pin->sink_eld;
1253
1254 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1255 if (err < 0)
1256 return err;
1257
1258 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1259 /* Claim converter */
1260 per_cvt->assigned = 1;
1df5a06a 1261 per_pin->cvt_nid = per_cvt->cvt_nid;
384a48d7
SW		 1262 hinfo->nid = per_cvt->cvt_nid;
1263
bddee96b 1264 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
384a48d7
SW		 1265 AC_VERB_SET_CONNECT_SEL,
1266 mux_idx);
7ef166b8
WX		 1267
1268 /* configure unused pins to choose other converters */
fb87fa3a 1269 if (is_haswell(codec))
f82d7d16 1270 haswell_config_cvts(codec, per_pin->pin_nid, mux_idx);
7ef166b8 1271
384a48d7 1272 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
bbbe3390 1273
2def8172 1274 /* Initially set the converter's capabilities */
384a48d7
SW		 1275 hinfo->channels_min = per_cvt->channels_min;
1276 hinfo->channels_max = per_cvt->channels_max;
1277 hinfo->rates = per_cvt->rates;
1278 hinfo->formats = per_cvt->formats;
1279 hinfo->maxbps = per_cvt->maxbps;
2def8172 1280
384a48d7 1281 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 1282 if (!static_hdmi_pcm && eld->eld_valid) {
1613d6b4 1283 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
bbbe3390 1284 if (hinfo->channels_min > hinfo->channels_max ||
2ad779b7
TI		 1285 !hinfo->rates || !hinfo->formats) {
1286 per_cvt->assigned = 0;
1287 hinfo->nid = 0;
1288 snd_hda_spdif_ctls_unassign(codec, pin_idx);
bbbe3390 1289 return -ENODEV;
2ad779b7 1290 }
bbbe3390 1291 }
2def8172
SW		 1292
1293 /* Store the updated parameters */
639cef0e
TI		 1294 runtime->hw.channels_min = hinfo->channels_min;
1295 runtime->hw.channels_max = hinfo->channels_max;
1296 runtime->hw.formats = hinfo->formats;
1297 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 1298
1299 snd_pcm_hw_constraint_step(substream->runtime, 0,
1300 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 1301 return 0;
1302}
1303
079d88cc
WF		 1304/*
1305 * HDA/HDMI auto parsing
1306 */
384a48d7 1307static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 1308{
1309 struct hdmi_spec *spec = codec->spec;
bce0d2a8 1310 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1311 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 1312
1313 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1314 snd_printk(KERN_WARNING
1315 "HDMI: pin %d wcaps %#x "
1316 "does not support connection list\n",
1317 pin_nid, get_wcaps(codec, pin_nid));
1318 return -EINVAL;
1319 }
1320
384a48d7
SW		 1321 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1322 per_pin->mux_nids,
1323 HDA_MAX_CONNECTIONS);
079d88cc
WF		 1324
1325 return 0;
1326}
1327
c6e8453e 1328static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
079d88cc 1329{
744626da 1330 struct hda_codec *codec = per_pin->codec;
4bd038f9
DH		 1331 struct hdmi_spec *spec = codec->spec;
1332 struct hdmi_eld *eld = &spec->temp_eld;
1333 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
744626da 1334 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 1335 /*
1336 * Always execute a GetPinSense verb here, even when called from
1337 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1338 * response's PD bit is not the real PD value, but indicates that
1339 * the real PD value changed. An older version of the HD-audio
1340 * specification worked this way. Hence, we just ignore the data in
1341 * the unsolicited response to avoid custom WARs.
1342 */
079d88cc 1343 int present = snd_hda_pin_sense(codec, pin_nid);
4bd038f9
DH		 1344 bool update_eld = false;
1345 bool eld_changed = false;
079d88cc 1346
4bd038f9
DH		 1347 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1348 if (pin_eld->monitor_present)
1349 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1350 else
1351 eld->eld_valid = false;
079d88cc 1352
fae3d88a 1353 _snd_printd(SND_PR_VERBOSE,
384a48d7 1354 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
10250911 1355 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
5d44f927 1356
4bd038f9 1357 if (eld->eld_valid) {
1613d6b4
DH		 1358 if (snd_hdmi_get_eld(codec, pin_nid, eld->eld_buffer,
1359 &eld->eld_size) < 0)
4bd038f9 1360 eld->eld_valid = false;
1613d6b4
DH		 1361 else {
1362 memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
1363 if (snd_hdmi_parse_eld(&eld->info, eld->eld_buffer,
1364 eld->eld_size) < 0)
4bd038f9 1365 eld->eld_valid = false;
1613d6b4
DH		 1366 }
1367
4bd038f9 1368 if (eld->eld_valid) {
1613d6b4 1369 snd_hdmi_show_eld(&eld->info);
4bd038f9 1370 update_eld = true;
1613d6b4 1371 }
c6e8453e 1372 else if (repoll) {
744626da
WF		 1373 queue_delayed_work(codec->bus->workq,
1374 &per_pin->work,
1375 msecs_to_jiffies(300));
4bd038f9 1376 return;
744626da
WF		 1377 }
1378 }
4bd038f9
DH		 1379
1380 mutex_lock(&pin_eld->lock);
92c69e79 1381 if (pin_eld->eld_valid && !eld->eld_valid) {
4bd038f9 1382 update_eld = true;
92c69e79
DH		 1383 eld_changed = true;
1384 }
4bd038f9 1385 if (update_eld) {
b054087d 1386 bool old_eld_valid = pin_eld->eld_valid;
4bd038f9 1387 pin_eld->eld_valid = eld->eld_valid;
92c69e79
DH		 1388 eld_changed = pin_eld->eld_size != eld->eld_size ||
1389 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
4bd038f9
DH		 1390 eld->eld_size) != 0;
1391 if (eld_changed)
1392 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1393 eld->eld_size);
1394 pin_eld->eld_size = eld->eld_size;
1395 pin_eld->info = eld->info;
b054087d
TI		 1396
1397 /* Haswell-specific workaround: re-setup when the transcoder is
1398 * changed during the stream playback
1399 */
fb87fa3a 1400 if (is_haswell(codec) &&
58f7d28d 1401 eld->eld_valid && !old_eld_valid && per_pin->setup)
b054087d
TI		 1402 hdmi_setup_audio_infoframe(codec, per_pin,
1403 per_pin->non_pcm);
4bd038f9
DH		 1404 }
1405 mutex_unlock(&pin_eld->lock);
92c69e79
DH		 1406
1407 if (eld_changed)
1408 snd_ctl_notify(codec->bus->card,
1409 SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
1410 &per_pin->eld_ctl->id);
079d88cc
WF		 1411}
1412
744626da
WF		 1413static void hdmi_repoll_eld(struct work_struct *work)
1414{
1415 struct hdmi_spec_per_pin *per_pin =
1416 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1417
c6e8453e
WF		 1418 if (per_pin->repoll_count++ > 6)
1419 per_pin->repoll_count = 0;
1420
1421 hdmi_present_sense(per_pin, per_pin->repoll_count);
744626da
WF		 1422}
1423
c88d4e84
TI		 1424static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1425 hda_nid_t nid);
1426
079d88cc
WF		 1427static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1428{
1429 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1430 unsigned int caps, config;
1431 int pin_idx;
1432 struct hdmi_spec_per_pin *per_pin;
07acecc1 1433 int err;
079d88cc 1434
efc2f8de 1435 caps = snd_hda_query_pin_caps(codec, pin_nid);
384a48d7
SW		 1436 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1437 return 0;
1438
efc2f8de 1439 config = snd_hda_codec_get_pincfg(codec, pin_nid);
384a48d7
SW		 1440 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1441 return 0;
1442
fb87fa3a 1443 if (is_haswell(codec))
c88d4e84
TI		 1444 intel_haswell_fixup_connect_list(codec, pin_nid);
1445
384a48d7 1446 pin_idx = spec->num_pins;
bce0d2a8
TI		 1447 per_pin = snd_array_new(&spec->pins);
1448 if (!per_pin)
1449 return -ENOMEM;
384a48d7
SW		 1450
1451 per_pin->pin_nid = pin_nid;
1a6003b5 1452 per_pin->non_pcm = false;
079d88cc 1453
384a48d7
SW		 1454 err = hdmi_read_pin_conn(codec, pin_idx);
1455 if (err < 0)
1456 return err;
079d88cc 1457
079d88cc
WF		 1458 spec->num_pins++;
1459
384a48d7 1460 return 0;
079d88cc
WF		 1461}
1462
384a48d7 1463static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1464{
1465 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1466 struct hdmi_spec_per_cvt *per_cvt;
1467 unsigned int chans;
1468 int err;
079d88cc 1469
384a48d7
SW		 1470 chans = get_wcaps(codec, cvt_nid);
1471 chans = get_wcaps_channels(chans);
1472
bce0d2a8
TI		 1473 per_cvt = snd_array_new(&spec->cvts);
1474 if (!per_cvt)
1475 return -ENOMEM;
384a48d7
SW		 1476
1477 per_cvt->cvt_nid = cvt_nid;
1478 per_cvt->channels_min = 2;
d45e6889 1479 if (chans <= 16) {
384a48d7 1480 per_cvt->channels_max = chans;
d45e6889
TI		 1481 if (chans > spec->channels_max)
1482 spec->channels_max = chans;
1483 }
384a48d7
SW		 1484
1485 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1486 &per_cvt->rates,
1487 &per_cvt->formats,
1488 &per_cvt->maxbps);
1489 if (err < 0)
1490 return err;
1491
bce0d2a8
TI		 1492 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1493 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1494 spec->num_cvts++;
079d88cc
WF		 1495
1496 return 0;
1497}
1498
1499static int hdmi_parse_codec(struct hda_codec *codec)
1500{
1501 hda_nid_t nid;
1502 int i, nodes;
1503
1504 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
1505 if (!nid || nodes < 0) {
1506 snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
1507 return -EINVAL;
1508 }
1509
1510 for (i = 0; i < nodes; i++, nid++) {
1511 unsigned int caps;
1512 unsigned int type;
1513
efc2f8de 1514 caps = get_wcaps(codec, nid);
079d88cc
WF		 1515 type = get_wcaps_type(caps);
1516
1517 if (!(caps & AC_WCAP_DIGITAL))
1518 continue;
1519
1520 switch (type) {
1521 case AC_WID_AUD_OUT:
384a48d7 1522 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1523 break;
1524 case AC_WID_PIN:
3eaead57 1525 hdmi_add_pin(codec, nid);
079d88cc
WF		 1526 break;
1527 }
1528 }
1529
c9adeefd
DH		 1530#ifdef CONFIG_PM
1531 /* We're seeing some problems with unsolicited hot plug events on
1532 * PantherPoint after S3, if this is not enabled */
1533 if (codec->vendor_id == 0x80862806)
1534 codec->bus->power_keep_link_on = 1;
079d88cc
WF		 1535 /*
1536 * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
1537 * can be lost and presence sense verb will become inaccurate if the
1538 * HDA link is powered off at hot plug or hw initialization time.
1539 */
c9adeefd 1540 else if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) &
079d88cc
WF		 1541 AC_PWRST_EPSS))
1542 codec->bus->power_keep_link_on = 1;
1543#endif
1544
1545 return 0;
1546}
1547
84eb01be
TI		 1548/*
1549 */
1a6003b5
TI		 1550static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1551{
1552 struct hda_spdif_out *spdif;
1553 bool non_pcm;
1554
1555 mutex_lock(&codec->spdif_mutex);
1556 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1557 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1558 mutex_unlock(&codec->spdif_mutex);
1559 return non_pcm;
1560}
1561
1562
84eb01be
TI		 1563/*
1564 * HDMI callbacks
1565 */
1566
1567static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1568 struct hda_codec *codec,
1569 unsigned int stream_tag,
1570 unsigned int format,
1571 struct snd_pcm_substream *substream)
1572{
384a48d7
SW		 1573 hda_nid_t cvt_nid = hinfo->nid;
1574 struct hdmi_spec *spec = codec->spec;
1575 int pin_idx = hinfo_to_pin_index(spec, hinfo);
b054087d
TI		 1576 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1577 hda_nid_t pin_nid = per_pin->pin_nid;
1a6003b5
TI		 1578 bool non_pcm;
1579
1580 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
b054087d
TI		 1581 per_pin->channels = substream->runtime->channels;
1582 per_pin->setup = true;
384a48d7 1583
b054087d 1584 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
84eb01be 1585
384a48d7 1586 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
84eb01be
TI		 1587}
1588
8dfaa573
TI		 1589static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1590 struct hda_codec *codec,
1591 struct snd_pcm_substream *substream)
1592{
1593 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1594 return 0;
1595}
1596
f2ad24fa
TI		 1597static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1598 struct hda_codec *codec,
1599 struct snd_pcm_substream *substream)
384a48d7
SW		 1600{
1601 struct hdmi_spec *spec = codec->spec;
1602 int cvt_idx, pin_idx;
1603 struct hdmi_spec_per_cvt *per_cvt;
1604 struct hdmi_spec_per_pin *per_pin;
384a48d7 1605
384a48d7
SW		 1606 if (hinfo->nid) {
1607 cvt_idx = cvt_nid_to_cvt_index(spec, hinfo->nid);
1608 if (snd_BUG_ON(cvt_idx < 0))
1609 return -EINVAL;
bce0d2a8 1610 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1611
1612 snd_BUG_ON(!per_cvt->assigned);
1613 per_cvt->assigned = 0;
1614 hinfo->nid = 0;
1615
1616 pin_idx = hinfo_to_pin_index(spec, hinfo);
1617 if (snd_BUG_ON(pin_idx < 0))
1618 return -EINVAL;
bce0d2a8 1619 per_pin = get_pin(spec, pin_idx);
384a48d7 1620
384a48d7 1621 snd_hda_spdif_ctls_unassign(codec, pin_idx);
d45e6889
TI		 1622 per_pin->chmap_set = false;
1623 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
b054087d
TI		 1624
1625 per_pin->setup = false;
1626 per_pin->channels = 0;
384a48d7 1627 }
d45e6889 1628
384a48d7
SW		 1629 return 0;
1630}
1631
1632static const struct hda_pcm_ops generic_ops = {
1633 .open = hdmi_pcm_open,
f2ad24fa 1634 .close = hdmi_pcm_close,
384a48d7 1635 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 1636 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 1637};
1638
d45e6889
TI		 1639/*
1640 * ALSA API channel-map control callbacks
1641 */
1642static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1643 struct snd_ctl_elem_info *uinfo)
1644{
1645 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1646 struct hda_codec *codec = info->private_data;
1647 struct hdmi_spec *spec = codec->spec;
1648 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1649 uinfo->count = spec->channels_max;
1650 uinfo->value.integer.min = 0;
1651 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1652 return 0;
1653}
1654
1655static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1656 unsigned int size, unsigned int __user *tlv)
1657{
1658 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1659 struct hda_codec *codec = info->private_data;
1660 struct hdmi_spec *spec = codec->spec;
d45e6889
TI		 1661 unsigned int __user *dst;
1662 int chs, count = 0;
1663
1664 if (size < 8)
1665 return -ENOMEM;
1666 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1667 return -EFAULT;
1668 size -= 8;
1669 dst = tlv + 2;
498dab3a 1670 for (chs = 2; chs <= spec->channels_max; chs++) {
d45e6889
TI		 1671 int i, c;
1672 struct cea_channel_speaker_allocation *cap;
1673 cap = channel_allocations;
1674 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1675 int chs_bytes = chs * 4;
1676 if (cap->channels != chs)
1677 continue;
d45e6889
TI		 1678 if (size < 8)
1679 return -ENOMEM;
1680 if (put_user(SNDRV_CTL_TLVT_CHMAP_VAR, dst) ||
1681 put_user(chs_bytes, dst + 1))
1682 return -EFAULT;
1683 dst += 2;
1684 size -= 8;
1685 count += 8;
1686 if (size < chs_bytes)
1687 return -ENOMEM;
1688 size -= chs_bytes;
1689 count += chs_bytes;
1690 for (c = 7; c >= 0; c--) {
1691 int spk = cap->speakers[c];
1692 if (!spk)
1693 continue;
1694 if (put_user(spk_to_chmap(spk), dst))
1695 return -EFAULT;
1696 dst++;
1697 }
1698 }
1699 }
1700 if (put_user(count, tlv + 1))
1701 return -EFAULT;
1702 return 0;
1703}
1704
1705static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
1706 struct snd_ctl_elem_value *ucontrol)
1707{
1708 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1709 struct hda_codec *codec = info->private_data;
1710 struct hdmi_spec *spec = codec->spec;
1711 int pin_idx = kcontrol->private_value;
bce0d2a8 1712 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1713 int i;
1714
1715 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
1716 ucontrol->value.integer.value[i] = per_pin->chmap[i];
1717 return 0;
1718}
1719
1720static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
1721 struct snd_ctl_elem_value *ucontrol)
1722{
1723 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1724 struct hda_codec *codec = info->private_data;
1725 struct hdmi_spec *spec = codec->spec;
1726 int pin_idx = kcontrol->private_value;
bce0d2a8 1727 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1728 unsigned int ctl_idx;
1729 struct snd_pcm_substream *substream;
1730 unsigned char chmap[8];
1731 int i, ca, prepared = 0;
1732
1733 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
1734 substream = snd_pcm_chmap_substream(info, ctl_idx);
1735 if (!substream || !substream->runtime)
6f54c361 1736 return 0; /* just for avoiding error from alsactl restore */
d45e6889
TI		 1737 switch (substream->runtime->status->state) {
1738 case SNDRV_PCM_STATE_OPEN:
1739 case SNDRV_PCM_STATE_SETUP:
1740 break;
1741 case SNDRV_PCM_STATE_PREPARED:
1742 prepared = 1;
1743 break;
1744 default:
1745 return -EBUSY;
1746 }
1747 memset(chmap, 0, sizeof(chmap));
1748 for (i = 0; i < ARRAY_SIZE(chmap); i++)
1749 chmap[i] = ucontrol->value.integer.value[i];
1750 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
1751 return 0;
1752 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
1753 if (ca < 0)
1754 return -EINVAL;
1755 per_pin->chmap_set = true;
1756 memcpy(per_pin->chmap, chmap, sizeof(chmap));
1757 if (prepared)
b054087d 1758 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
d45e6889
TI		 1759
1760 return 0;
1761}
1762
84eb01be
TI		 1763static int generic_hdmi_build_pcms(struct hda_codec *codec)
1764{
1765 struct hdmi_spec *spec = codec->spec;
384a48d7 1766 int pin_idx;
84eb01be 1767
384a48d7
SW		 1768 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1769 struct hda_pcm *info;
84eb01be 1770 struct hda_pcm_stream *pstr;
bce0d2a8
TI		 1771 struct hdmi_spec_per_pin *per_pin;
1772
1773 per_pin = get_pin(spec, pin_idx);
1774 sprintf(per_pin->pcm_name, "HDMI %d", pin_idx);
1775 info = snd_array_new(&spec->pcm_rec);
1776 if (!info)
1777 return -ENOMEM;
1778 info->name = per_pin->pcm_name;
84eb01be 1779 info->pcm_type = HDA_PCM_TYPE_HDMI;
d45e6889 1780 info->own_chmap = true;
384a48d7 1781
84eb01be 1782 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 1783 pstr->substreams = 1;
1784 pstr->ops = generic_ops;
1785 /* other pstr fields are set in open */
84eb01be
TI		 1786 }
1787
384a48d7 1788 codec->num_pcms = spec->num_pins;
bce0d2a8 1789 codec->pcm_info = spec->pcm_rec.list;
384a48d7 1790
84eb01be
TI		 1791 return 0;
1792}
1793
0b6c49b5
DH		 1794static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
1795{
31ef2257 1796 char hdmi_str[32] = "HDMI/DP";
0b6c49b5 1797 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 1798 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1799 int pcmdev = get_pcm_rec(spec, pin_idx)->device;
0b6c49b5 1800
31ef2257
TI		 1801 if (pcmdev > 0)
1802 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
30efd8de
DH		 1803 if (!is_jack_detectable(codec, per_pin->pin_nid))
1804 strncat(hdmi_str, " Phantom",
1805 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
0b6c49b5 1806
31ef2257 1807 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0);
0b6c49b5
DH		 1808}
1809
84eb01be
TI		 1810static int generic_hdmi_build_controls(struct hda_codec *codec)
1811{
1812 struct hdmi_spec *spec = codec->spec;
1813 int err;
384a48d7 1814 int pin_idx;
84eb01be 1815
384a48d7 1816 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1817 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
0b6c49b5
DH		 1818
1819 err = generic_hdmi_build_jack(codec, pin_idx);
1820 if (err < 0)
1821 return err;
1822
dcda5806
TI		 1823 err = snd_hda_create_dig_out_ctls(codec,
1824 per_pin->pin_nid,
1825 per_pin->mux_nids[0],
1826 HDA_PCM_TYPE_HDMI);
84eb01be
TI		 1827 if (err < 0)
1828 return err;
384a48d7 1829 snd_hda_spdif_ctls_unassign(codec, pin_idx);
14bc52b8
PLB		 1830
1831 /* add control for ELD Bytes */
bce0d2a8
TI		 1832 err = hdmi_create_eld_ctl(codec, pin_idx,
1833 get_pcm_rec(spec, pin_idx)->device);
14bc52b8
PLB		 1834
1835 if (err < 0)
1836 return err;
31ef2257 1837
82b1d73f 1838 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 1839 }
1840
d45e6889
TI		 1841 /* add channel maps */
1842 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1843 struct snd_pcm_chmap *chmap;
1844 struct snd_kcontrol *kctl;
1845 int i;
2ca320e2
TI		 1846
1847 if (!codec->pcm_info[pin_idx].pcm)
1848 break;
d45e6889
TI		 1849 err = snd_pcm_add_chmap_ctls(codec->pcm_info[pin_idx].pcm,
1850 SNDRV_PCM_STREAM_PLAYBACK,
1851 NULL, 0, pin_idx, &chmap);
1852 if (err < 0)
1853 return err;
1854 /* override handlers */
1855 chmap->private_data = codec;
1856 kctl = chmap->kctl;
1857 for (i = 0; i < kctl->count; i++)
1858 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
1859 kctl->info = hdmi_chmap_ctl_info;
1860 kctl->get = hdmi_chmap_ctl_get;
1861 kctl->put = hdmi_chmap_ctl_put;
1862 kctl->tlv.c = hdmi_chmap_ctl_tlv;
1863 }
1864
84eb01be
TI		 1865 return 0;
1866}
1867
8b8d654b 1868static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 1869{
1870 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1871 int pin_idx;
1872
1873 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1874 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1875 struct hdmi_eld *eld = &per_pin->sink_eld;
84eb01be 1876
744626da 1877 per_pin->codec = codec;
4bd038f9 1878 mutex_init(&eld->lock);
744626da 1879 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
384a48d7 1880 snd_hda_eld_proc_new(codec, eld, pin_idx);
84eb01be 1881 }
8b8d654b
TI		 1882 return 0;
1883}
1884
1885static int generic_hdmi_init(struct hda_codec *codec)
1886{
1887 struct hdmi_spec *spec = codec->spec;
1888 int pin_idx;
1889
1890 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1891 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
8b8d654b
TI		 1892 hda_nid_t pin_nid = per_pin->pin_nid;
1893
1894 hdmi_init_pin(codec, pin_nid);
1895 snd_hda_jack_detect_enable(codec, pin_nid, pin_nid);
1896 }
84eb01be
TI		 1897 return 0;
1898}
1899
bce0d2a8
TI		 1900static void hdmi_array_init(struct hdmi_spec *spec, int nums)
1901{
1902 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
1903 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
1904 snd_array_init(&spec->pcm_rec, sizeof(struct hda_pcm), nums);
1905}
1906
1907static void hdmi_array_free(struct hdmi_spec *spec)
1908{
1909 snd_array_free(&spec->pins);
1910 snd_array_free(&spec->cvts);
1911 snd_array_free(&spec->pcm_rec);
1912}
1913
84eb01be
TI		 1914static void generic_hdmi_free(struct hda_codec *codec)
1915{
1916 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1917 int pin_idx;
1918
1919 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1920 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1921 struct hdmi_eld *eld = &per_pin->sink_eld;
84eb01be 1922
744626da 1923 cancel_delayed_work(&per_pin->work);
384a48d7
SW		 1924 snd_hda_eld_proc_free(codec, eld);
1925 }
84eb01be 1926
744626da 1927 flush_workqueue(codec->bus->workq);
bce0d2a8 1928 hdmi_array_free(spec);
84eb01be
TI		 1929 kfree(spec);
1930}
1931
28cb72e5
WX		 1932#ifdef CONFIG_PM
1933static int generic_hdmi_resume(struct hda_codec *codec)
1934{
1935 struct hdmi_spec *spec = codec->spec;
1936 int pin_idx;
1937
1938 generic_hdmi_init(codec);
1939 snd_hda_codec_resume_amp(codec);
1940 snd_hda_codec_resume_cache(codec);
1941
1942 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1943 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1944 hdmi_present_sense(per_pin, 1);
1945 }
1946 return 0;
1947}
1948#endif
1949
fb79e1e0 1950static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 1951 .init = generic_hdmi_init,
1952 .free = generic_hdmi_free,
1953 .build_pcms = generic_hdmi_build_pcms,
1954 .build_controls = generic_hdmi_build_controls,
1955 .unsol_event = hdmi_unsol_event,
28cb72e5
WX		 1956#ifdef CONFIG_PM
1957 .resume = generic_hdmi_resume,
1958#endif
84eb01be
TI		 1959};
1960
6ffe168f 1961
c88d4e84
TI		 1962static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1963 hda_nid_t nid)
1964{
1965 struct hdmi_spec *spec = codec->spec;
1966 hda_nid_t conns[4];
1967 int nconns;
6ffe168f 1968
c88d4e84
TI		 1969 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
1970 if (nconns == spec->num_cvts &&
1971 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
6ffe168f
ML		 1972 return;
1973
c88d4e84
TI		 1974 /* override pins connection list */
1975 snd_printdd("hdmi: haswell: override pin connection 0x%x\n", nid);
1976 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
6ffe168f
ML		 1977}
1978
1611a9c9
ML		 1979#define INTEL_VENDOR_NID 0x08
1980#define INTEL_GET_VENDOR_VERB 0xf81
1981#define INTEL_SET_VENDOR_VERB 0x781
1982#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
1983#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
1984
1985static void intel_haswell_enable_all_pins(struct hda_codec *codec,
17df3f55 1986 bool update_tree)
1611a9c9
ML		 1987{
1988 unsigned int vendor_param;
1989
1611a9c9
ML		 1990 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
1991 INTEL_GET_VENDOR_VERB, 0);
1992 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
1993 return;
1994
1995 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
1996 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
1997 INTEL_SET_VENDOR_VERB, vendor_param);
1998 if (vendor_param == -1)
1999 return;
2000
17df3f55
TI		 2001 if (update_tree)
2002 snd_hda_codec_update_widgets(codec);
1611a9c9
ML		 2003}
2004
c88d4e84
TI		 2005static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2006{
2007 unsigned int vendor_param;
2008
2009 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2010 INTEL_GET_VENDOR_VERB, 0);
2011 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2012 return;
2013
2014 /* enable DP1.2 mode */
2015 vendor_param |= INTEL_EN_DP12;
2016 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2017 INTEL_SET_VENDOR_VERB, vendor_param);
2018}
2019
17df3f55
TI		 2020/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2021 * Otherwise you may get severe h/w communication errors.
2022 */
2023static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2024 unsigned int power_state)
2025{
2026 if (power_state == AC_PWRST_D0) {
2027 intel_haswell_enable_all_pins(codec, false);
2028 intel_haswell_fixup_enable_dp12(codec);
2029 }
c88d4e84 2030
17df3f55
TI		 2031 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2032 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2033}
6ffe168f 2034
84eb01be
TI		 2035static int patch_generic_hdmi(struct hda_codec *codec)
2036{
2037 struct hdmi_spec *spec;
84eb01be
TI		 2038
2039 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2040 if (spec == NULL)
2041 return -ENOMEM;
2042
2043 codec->spec = spec;
bce0d2a8 2044 hdmi_array_init(spec, 4);
6ffe168f 2045
fb87fa3a 2046 if (is_haswell(codec)) {
17df3f55 2047 intel_haswell_enable_all_pins(codec, true);
c88d4e84 2048 intel_haswell_fixup_enable_dp12(codec);
17df3f55 2049 }
6ffe168f 2050
84eb01be
TI		 2051 if (hdmi_parse_codec(codec) < 0) {
2052 codec->spec = NULL;
2053 kfree(spec);
2054 return -EINVAL;
2055 }
2056 codec->patch_ops = generic_hdmi_patch_ops;
fb87fa3a 2057 if (is_haswell(codec)) {
17df3f55 2058 codec->patch_ops.set_power_state = haswell_set_power_state;
5dc989bd
ML		 2059 codec->dp_mst = true;
2060 }
17df3f55 2061
8b8d654b 2062 generic_hdmi_init_per_pins(codec);
84eb01be 2063
84eb01be
TI		 2064 init_channel_allocations();
2065
2066 return 0;
2067}
2068
3aaf8980
SW		 2069/*
2070 * Shared non-generic implementations
2071 */
2072
2073static int simple_playback_build_pcms(struct hda_codec *codec)
2074{
2075 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2076 struct hda_pcm *info;
8ceb332d
TI		 2077 unsigned int chans;
2078 struct hda_pcm_stream *pstr;
bce0d2a8 2079 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2080
bce0d2a8
TI		 2081 per_cvt = get_cvt(spec, 0);
2082 chans = get_wcaps(codec, per_cvt->cvt_nid);
8ceb332d 2083 chans = get_wcaps_channels(chans);
3aaf8980 2084
bce0d2a8
TI		 2085 info = snd_array_new(&spec->pcm_rec);
2086 if (!info)
2087 return -ENOMEM;
2088 info->name = get_pin(spec, 0)->pcm_name;
2089 sprintf(info->name, "HDMI 0");
8ceb332d
TI		 2090 info->pcm_type = HDA_PCM_TYPE_HDMI;
2091 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2092 *pstr = spec->pcm_playback;
bce0d2a8 2093 pstr->nid = per_cvt->cvt_nid;
8ceb332d
TI		 2094 if (pstr->channels_max <= 2 && chans && chans <= 16)
2095 pstr->channels_max = chans;
3aaf8980 2096
bce0d2a8
TI		 2097 codec->num_pcms = 1;
2098 codec->pcm_info = info;
2099
3aaf8980
SW		 2100 return 0;
2101}
2102
4b6ace9e
TI		 2103/* unsolicited event for jack sensing */
2104static void simple_hdmi_unsol_event(struct hda_codec *codec,
2105 unsigned int res)
2106{
9dd8cf12 2107 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 2108 snd_hda_jack_report_sync(codec);
2109}
2110
2111/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2112 * as long as spec->pins[] is set correctly
2113 */
2114#define simple_hdmi_build_jack generic_hdmi_build_jack
2115
3aaf8980
SW		 2116static int simple_playback_build_controls(struct hda_codec *codec)
2117{
2118 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2119 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2120 int err;
3aaf8980 2121
bce0d2a8
TI		 2122 per_cvt = get_cvt(spec, 0);
2123 err = snd_hda_create_spdif_out_ctls(codec, per_cvt->cvt_nid,
2124 per_cvt->cvt_nid);
8ceb332d
TI		 2125 if (err < 0)
2126 return err;
2127 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 2128}
2129
4f0110ce
TI		 2130static int simple_playback_init(struct hda_codec *codec)
2131{
2132 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2133 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2134 hda_nid_t pin = per_pin->pin_nid;
8ceb332d
TI		 2135
2136 snd_hda_codec_write(codec, pin, 0,
2137 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2138 /* some codecs require to unmute the pin */
2139 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2140 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2141 AMP_OUT_UNMUTE);
2142 snd_hda_jack_detect_enable(codec, pin, pin);
4f0110ce
TI		 2143 return 0;
2144}
2145
3aaf8980
SW		 2146static void simple_playback_free(struct hda_codec *codec)
2147{
2148 struct hdmi_spec *spec = codec->spec;
2149
bce0d2a8 2150 hdmi_array_free(spec);
3aaf8980
SW		 2151 kfree(spec);
2152}
2153
84eb01be
TI		 2154/*
2155 * Nvidia specific implementations
2156 */
2157
2158#define Nv_VERB_SET_Channel_Allocation 0xF79
2159#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2160#define Nv_VERB_SET_Audio_Protection_On 0xF98
2161#define Nv_VERB_SET_Audio_Protection_Off 0xF99
2162
2163#define nvhdmi_master_con_nid_7x 0x04
2164#define nvhdmi_master_pin_nid_7x 0x05
2165
fb79e1e0 2166static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 2167 /*front, rear, clfe, rear_surr */
2168 0x6, 0x8, 0xa, 0xc,
2169};
2170
ceaa86ba
TI		 2171static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2172 /* set audio protect on */
2173 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2174 /* enable digital output on pin widget */
2175 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2176 {} /* terminator */
2177};
2178
2179static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 2180 /* set audio protect on */
2181 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2182 /* enable digital output on pin widget */
2183 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2184 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2185 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2186 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2187 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2188 {} /* terminator */
2189};
2190
2191#ifdef LIMITED_RATE_FMT_SUPPORT
2192/* support only the safe format and rate */
2193#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2194#define SUPPORTED_MAXBPS 16
2195#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2196#else
2197/* support all rates and formats */
2198#define SUPPORTED_RATES \
2199 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2200 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2201 SNDRV_PCM_RATE_192000)
2202#define SUPPORTED_MAXBPS 24
2203#define SUPPORTED_FORMATS \
2204 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2205#endif
2206
ceaa86ba
TI		 2207static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2208{
2209 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2210 return 0;
2211}
2212
2213static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 2214{
ceaa86ba 2215 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 2216 return 0;
2217}
2218
393004b2
ND		 2219static unsigned int channels_2_6_8[] = {
2220 2, 6, 8
2221};
2222
2223static unsigned int channels_2_8[] = {
2224 2, 8
2225};
2226
2227static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2228 .count = ARRAY_SIZE(channels_2_6_8),
2229 .list = channels_2_6_8,
2230 .mask = 0,
2231};
2232
2233static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2234 .count = ARRAY_SIZE(channels_2_8),
2235 .list = channels_2_8,
2236 .mask = 0,
2237};
2238
84eb01be
TI		 2239static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2240 struct hda_codec *codec,
2241 struct snd_pcm_substream *substream)
2242{
2243 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 2244 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2245
2246 switch (codec->preset->id) {
2247 case 0x10de0002:
2248 case 0x10de0003:
2249 case 0x10de0005:
2250 case 0x10de0006:
2251 hw_constraints_channels = &hw_constraints_2_8_channels;
2252 break;
2253 case 0x10de0007:
2254 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2255 break;
2256 default:
2257 break;
2258 }
2259
2260 if (hw_constraints_channels != NULL) {
2261 snd_pcm_hw_constraint_list(substream->runtime, 0,
2262 SNDRV_PCM_HW_PARAM_CHANNELS,
2263 hw_constraints_channels);
ad09fc9d
TI		 2264 } else {
2265 snd_pcm_hw_constraint_step(substream->runtime, 0,
2266 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 2267 }
2268
84eb01be
TI		 2269 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2270}
2271
2272static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2273 struct hda_codec *codec,
2274 struct snd_pcm_substream *substream)
2275{
2276 struct hdmi_spec *spec = codec->spec;
2277 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2278}
2279
2280static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2281 struct hda_codec *codec,
2282 unsigned int stream_tag,
2283 unsigned int format,
2284 struct snd_pcm_substream *substream)
2285{
2286 struct hdmi_spec *spec = codec->spec;
2287 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2288 stream_tag, format, substream);
2289}
2290
d0b1252d
TI		 2291static const struct hda_pcm_stream simple_pcm_playback = {
2292 .substreams = 1,
2293 .channels_min = 2,
2294 .channels_max = 2,
2295 .ops = {
2296 .open = simple_playback_pcm_open,
2297 .close = simple_playback_pcm_close,
2298 .prepare = simple_playback_pcm_prepare
2299 },
2300};
2301
2302static const struct hda_codec_ops simple_hdmi_patch_ops = {
2303 .build_controls = simple_playback_build_controls,
2304 .build_pcms = simple_playback_build_pcms,
2305 .init = simple_playback_init,
2306 .free = simple_playback_free,
250e41ac 2307 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 2308};
2309
2310static int patch_simple_hdmi(struct hda_codec *codec,
2311 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2312{
2313 struct hdmi_spec *spec;
bce0d2a8
TI		 2314 struct hdmi_spec_per_cvt *per_cvt;
2315 struct hdmi_spec_per_pin *per_pin;
d0b1252d
TI		 2316
2317 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2318 if (!spec)
2319 return -ENOMEM;
2320
2321 codec->spec = spec;
bce0d2a8 2322 hdmi_array_init(spec, 1);
d0b1252d
TI		 2323
2324 spec->multiout.num_dacs = 0; /* no analog */
2325 spec->multiout.max_channels = 2;
2326 spec->multiout.dig_out_nid = cvt_nid;
2327 spec->num_cvts = 1;
2328 spec->num_pins = 1;
bce0d2a8
TI		 2329 per_pin = snd_array_new(&spec->pins);
2330 per_cvt = snd_array_new(&spec->cvts);
2331 if (!per_pin || !per_cvt) {
2332 simple_playback_free(codec);
2333 return -ENOMEM;
2334 }
2335 per_cvt->cvt_nid = cvt_nid;
2336 per_pin->pin_nid = pin_nid;
d0b1252d
TI		 2337 spec->pcm_playback = simple_pcm_playback;
2338
2339 codec->patch_ops = simple_hdmi_patch_ops;
2340
2341 return 0;
2342}
2343
1f348522
AP		 2344static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2345 int channels)
2346{
2347 unsigned int chanmask;
2348 int chan = channels ? (channels - 1) : 1;
2349
2350 switch (channels) {
2351 default:
2352 case 0:
2353 case 2:
2354 chanmask = 0x00;
2355 break;
2356 case 4:
2357 chanmask = 0x08;
2358 break;
2359 case 6:
2360 chanmask = 0x0b;
2361 break;
2362 case 8:
2363 chanmask = 0x13;
2364 break;
2365 }
2366
2367 /* Set the audio infoframe channel allocation and checksum fields. The
2368 * channel count is computed implicitly by the hardware. */
2369 snd_hda_codec_write(codec, 0x1, 0,
2370 Nv_VERB_SET_Channel_Allocation, chanmask);
2371
2372 snd_hda_codec_write(codec, 0x1, 0,
2373 Nv_VERB_SET_Info_Frame_Checksum,
2374 (0x71 - chan - chanmask));
2375}
2376
84eb01be
TI		 2377static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2378 struct hda_codec *codec,
2379 struct snd_pcm_substream *substream)
2380{
2381 struct hdmi_spec *spec = codec->spec;
2382 int i;
2383
2384 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2385 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2386 for (i = 0; i < 4; i++) {
2387 /* set the stream id */
2388 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2389 AC_VERB_SET_CHANNEL_STREAMID, 0);
2390 /* set the stream format */
2391 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2392 AC_VERB_SET_STREAM_FORMAT, 0);
2393 }
2394
1f348522
AP		 2395 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2396 * streams are disabled. */
2397 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2398
84eb01be
TI		 2399 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2400}
2401
2402static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2403 struct hda_codec *codec,
2404 unsigned int stream_tag,
2405 unsigned int format,
2406 struct snd_pcm_substream *substream)
2407{
2408 int chs;
112daa7a 2409 unsigned int dataDCC2, channel_id;
84eb01be 2410 int i;
7c935976 2411 struct hdmi_spec *spec = codec->spec;
e3245cdd 2412 struct hda_spdif_out *spdif;
bce0d2a8 2413 struct hdmi_spec_per_cvt *per_cvt;
84eb01be
TI		 2414
2415 mutex_lock(&codec->spdif_mutex);
bce0d2a8
TI		 2416 per_cvt = get_cvt(spec, 0);
2417 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
84eb01be
TI		 2418
2419 chs = substream->runtime->channels;
84eb01be 2420
84eb01be
TI		 2421 dataDCC2 = 0x2;
2422
84eb01be 2423 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 2424 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2425 snd_hda_codec_write(codec,
2426 nvhdmi_master_con_nid_7x,
2427 0,
2428 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2429 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2430
2431 /* set the stream id */
2432 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2433 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2434
2435 /* set the stream format */
2436 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2437 AC_VERB_SET_STREAM_FORMAT, format);
2438
2439 /* turn on again (if needed) */
2440 /* enable and set the channel status audio/data flag */
7c935976 2441 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2442 snd_hda_codec_write(codec,
2443 nvhdmi_master_con_nid_7x,
2444 0,
2445 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2446 spdif->ctls & 0xff);
84eb01be
TI		 2447 snd_hda_codec_write(codec,
2448 nvhdmi_master_con_nid_7x,
2449 0,
2450 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2451 }
2452
2453 for (i = 0; i < 4; i++) {
2454 if (chs == 2)
2455 channel_id = 0;
2456 else
2457 channel_id = i * 2;
2458
2459 /* turn off SPDIF once;
2460 *otherwise the IEC958 bits won't be updated
2461 */
2462 if (codec->spdif_status_reset &&
7c935976 2463 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2464 snd_hda_codec_write(codec,
2465 nvhdmi_con_nids_7x[i],
2466 0,
2467 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2468 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2469 /* set the stream id */
2470 snd_hda_codec_write(codec,
2471 nvhdmi_con_nids_7x[i],
2472 0,
2473 AC_VERB_SET_CHANNEL_STREAMID,
2474 (stream_tag << 4) | channel_id);
2475 /* set the stream format */
2476 snd_hda_codec_write(codec,
2477 nvhdmi_con_nids_7x[i],
2478 0,
2479 AC_VERB_SET_STREAM_FORMAT,
2480 format);
2481 /* turn on again (if needed) */
2482 /* enable and set the channel status audio/data flag */
2483 if (codec->spdif_status_reset &&
7c935976 2484 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2485 snd_hda_codec_write(codec,
2486 nvhdmi_con_nids_7x[i],
2487 0,
2488 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2489 spdif->ctls & 0xff);
84eb01be
TI		 2490 snd_hda_codec_write(codec,
2491 nvhdmi_con_nids_7x[i],
2492 0,
2493 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2494 }
2495 }
2496
1f348522 2497 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 2498
2499 mutex_unlock(&codec->spdif_mutex);
2500 return 0;
2501}
2502
fb79e1e0 2503static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 2504 .substreams = 1,
2505 .channels_min = 2,
2506 .channels_max = 8,
2507 .nid = nvhdmi_master_con_nid_7x,
2508 .rates = SUPPORTED_RATES,
2509 .maxbps = SUPPORTED_MAXBPS,
2510 .formats = SUPPORTED_FORMATS,
2511 .ops = {
2512 .open = simple_playback_pcm_open,
2513 .close = nvhdmi_8ch_7x_pcm_close,
2514 .prepare = nvhdmi_8ch_7x_pcm_prepare
2515 },
2516};
2517
84eb01be
TI		 2518static int patch_nvhdmi_2ch(struct hda_codec *codec)
2519{
2520 struct hdmi_spec *spec;
d0b1252d
TI		 2521 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2522 nvhdmi_master_pin_nid_7x);
2523 if (err < 0)
2524 return err;
84eb01be 2525
ceaa86ba 2526 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 2527 /* override the PCM rates, etc, as the codec doesn't give full list */
2528 spec = codec->spec;
2529 spec->pcm_playback.rates = SUPPORTED_RATES;
2530 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2531 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 2532 return 0;
2533}
2534
53775b0d
TI		 2535static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2536{
2537 struct hdmi_spec *spec = codec->spec;
2538 int err = simple_playback_build_pcms(codec);
bce0d2a8
TI		 2539 if (!err) {
2540 struct hda_pcm *info = get_pcm_rec(spec, 0);
2541 info->own_chmap = true;
2542 }
53775b0d
TI		 2543 return err;
2544}
2545
2546static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2547{
2548 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2549 struct hda_pcm *info;
53775b0d
TI		 2550 struct snd_pcm_chmap *chmap;
2551 int err;
2552
2553 err = simple_playback_build_controls(codec);
2554 if (err < 0)
2555 return err;
2556
2557 /* add channel maps */
bce0d2a8
TI		 2558 info = get_pcm_rec(spec, 0);
2559 err = snd_pcm_add_chmap_ctls(info->pcm,
53775b0d
TI		 2560 SNDRV_PCM_STREAM_PLAYBACK,
2561 snd_pcm_alt_chmaps, 8, 0, &chmap);
2562 if (err < 0)
2563 return err;
2564 switch (codec->preset->id) {
2565 case 0x10de0002:
2566 case 0x10de0003:
2567 case 0x10de0005:
2568 case 0x10de0006:
2569 chmap->channel_mask = (1U << 2) | (1U << 8);
2570 break;
2571 case 0x10de0007:
2572 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2573 }
2574 return 0;
2575}
2576
84eb01be
TI		 2577static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2578{
2579 struct hdmi_spec *spec;
2580 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 2581 if (err < 0)
2582 return err;
2583 spec = codec->spec;
2584 spec->multiout.max_channels = 8;
d0b1252d 2585 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 2586 codec->patch_ops.init = nvhdmi_7x_init_8ch;
53775b0d
TI		 2587 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2588 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
1f348522
AP		 2589
2590 /* Initialize the audio infoframe channel mask and checksum to something
2591 * valid */
2592 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2593
84eb01be
TI		 2594 return 0;
2595}
2596
2597/*
2598 * ATI-specific implementations
2599 *
2600 * FIXME: we may omit the whole this and use the generic code once after
2601 * it's confirmed to work.
2602 */
2603
2604#define ATIHDMI_CVT_NID 0x02 /* audio converter */
2605#define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */
2606
2607static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2608 struct hda_codec *codec,
2609 unsigned int stream_tag,
2610 unsigned int format,
2611 struct snd_pcm_substream *substream)
2612{
2613 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2614 struct hdmi_spec_per_cvt *per_cvt = get_cvt(spec, 0);
84eb01be
TI		 2615 int chans = substream->runtime->channels;
2616 int i, err;
2617
2618 err = simple_playback_pcm_prepare(hinfo, codec, stream_tag, format,
2619 substream);
2620 if (err < 0)
2621 return err;
bce0d2a8 2622 snd_hda_codec_write(codec, per_cvt->cvt_nid, 0,
384a48d7 2623 AC_VERB_SET_CVT_CHAN_COUNT, chans - 1);
84eb01be
TI		 2624 /* FIXME: XXX */
2625 for (i = 0; i < chans; i++) {
bce0d2a8 2626 snd_hda_codec_write(codec, per_cvt->cvt_nid, 0,
84eb01be
TI		 2627 AC_VERB_SET_HDMI_CHAN_SLOT,
2628 (i << 4) | i);
2629 }
2630 return 0;
2631}
2632
84eb01be
TI		 2633static int patch_atihdmi(struct hda_codec *codec)
2634{
2635 struct hdmi_spec *spec;
d0b1252d
TI		 2636 int err = patch_simple_hdmi(codec, ATIHDMI_CVT_NID, ATIHDMI_PIN_NID);
2637 if (err < 0)
2638 return err;
2639 spec = codec->spec;
2640 spec->pcm_playback.ops.prepare = atihdmi_playback_pcm_prepare;
84eb01be
TI		 2641 return 0;
2642}
2643
3de5ff88
AL		 2644/* VIA HDMI Implementation */
2645#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
2646#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
2647
3de5ff88
AL		 2648static int patch_via_hdmi(struct hda_codec *codec)
2649{
250e41ac 2650 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 2651}
84eb01be
TI		 2652
2653/*
2654 * patch entries
2655 */
fb79e1e0 2656static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
84eb01be
TI		 2657{ .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
2658{ .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
2659{ .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
36e9c135 2660{ .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 2661{ .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
2662{ .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
2663{ .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
2664{ .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2665{ .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2666{ .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2667{ .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2668{ .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
5d44f927
SW		 2669{ .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_generic_hdmi },
2670{ .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_generic_hdmi },
2671{ .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_generic_hdmi },
2672{ .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_generic_hdmi },
2673{ .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_generic_hdmi },
2674{ .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_generic_hdmi },
2675{ .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_generic_hdmi },
2676{ .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_generic_hdmi },
2677{ .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_generic_hdmi },
2678{ .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_generic_hdmi },
2679{ .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_generic_hdmi },
c8900a0f 2680/* 17 is known to be absent */
5d44f927
SW		 2681{ .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_generic_hdmi },
2682{ .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_generic_hdmi },
2683{ .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_generic_hdmi },
2684{ .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_generic_hdmi },
2685{ .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_generic_hdmi },
2686{ .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_generic_hdmi },
2687{ .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_generic_hdmi },
2688{ .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_generic_hdmi },
2689{ .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_generic_hdmi },
2690{ .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_generic_hdmi },
7ae48b56 2691{ .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_generic_hdmi },
d52392b1 2692{ .id = 0x10de0060, .name = "GPU 60 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 2693{ .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
2694{ .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
3de5ff88
AL		 2695{ .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
2696{ .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
2697{ .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
2698{ .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 2699{ .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
2700{ .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
2701{ .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
2702{ .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
2703{ .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
2704{ .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
591e610d 2705{ .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
1c76684d 2706{ .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi },
6edc59e6 2707{ .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 2708{ .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
2709{} /* terminator */
2710};
2711
2712MODULE_ALIAS("snd-hda-codec-id:1002793c");
2713MODULE_ALIAS("snd-hda-codec-id:10027919");
2714MODULE_ALIAS("snd-hda-codec-id:1002791a");
2715MODULE_ALIAS("snd-hda-codec-id:1002aa01");
2716MODULE_ALIAS("snd-hda-codec-id:10951390");
2717MODULE_ALIAS("snd-hda-codec-id:10951392");
2718MODULE_ALIAS("snd-hda-codec-id:10de0002");
2719MODULE_ALIAS("snd-hda-codec-id:10de0003");
2720MODULE_ALIAS("snd-hda-codec-id:10de0005");
2721MODULE_ALIAS("snd-hda-codec-id:10de0006");
2722MODULE_ALIAS("snd-hda-codec-id:10de0007");
2723MODULE_ALIAS("snd-hda-codec-id:10de000a");
2724MODULE_ALIAS("snd-hda-codec-id:10de000b");
2725MODULE_ALIAS("snd-hda-codec-id:10de000c");
2726MODULE_ALIAS("snd-hda-codec-id:10de000d");
2727MODULE_ALIAS("snd-hda-codec-id:10de0010");
2728MODULE_ALIAS("snd-hda-codec-id:10de0011");
2729MODULE_ALIAS("snd-hda-codec-id:10de0012");
2730MODULE_ALIAS("snd-hda-codec-id:10de0013");
2731MODULE_ALIAS("snd-hda-codec-id:10de0014");
c8900a0f
RS		 2732MODULE_ALIAS("snd-hda-codec-id:10de0015");
2733MODULE_ALIAS("snd-hda-codec-id:10de0016");
84eb01be
TI		 2734MODULE_ALIAS("snd-hda-codec-id:10de0018");
2735MODULE_ALIAS("snd-hda-codec-id:10de0019");
2736MODULE_ALIAS("snd-hda-codec-id:10de001a");
2737MODULE_ALIAS("snd-hda-codec-id:10de001b");
2738MODULE_ALIAS("snd-hda-codec-id:10de001c");
2739MODULE_ALIAS("snd-hda-codec-id:10de0040");
2740MODULE_ALIAS("snd-hda-codec-id:10de0041");
2741MODULE_ALIAS("snd-hda-codec-id:10de0042");
2742MODULE_ALIAS("snd-hda-codec-id:10de0043");
2743MODULE_ALIAS("snd-hda-codec-id:10de0044");
7ae48b56 2744MODULE_ALIAS("snd-hda-codec-id:10de0051");
d52392b1 2745MODULE_ALIAS("snd-hda-codec-id:10de0060");
84eb01be
TI		 2746MODULE_ALIAS("snd-hda-codec-id:10de0067");
2747MODULE_ALIAS("snd-hda-codec-id:10de8001");
3de5ff88
AL		 2748MODULE_ALIAS("snd-hda-codec-id:11069f80");
2749MODULE_ALIAS("snd-hda-codec-id:11069f81");
2750MODULE_ALIAS("snd-hda-codec-id:11069f84");
2751MODULE_ALIAS("snd-hda-codec-id:11069f85");
84eb01be
TI		 2752MODULE_ALIAS("snd-hda-codec-id:17e80047");
2753MODULE_ALIAS("snd-hda-codec-id:80860054");
2754MODULE_ALIAS("snd-hda-codec-id:80862801");
2755MODULE_ALIAS("snd-hda-codec-id:80862802");
2756MODULE_ALIAS("snd-hda-codec-id:80862803");
2757MODULE_ALIAS("snd-hda-codec-id:80862804");
2758MODULE_ALIAS("snd-hda-codec-id:80862805");
591e610d 2759MODULE_ALIAS("snd-hda-codec-id:80862806");
1c76684d 2760MODULE_ALIAS("snd-hda-codec-id:80862807");
6edc59e6 2761MODULE_ALIAS("snd-hda-codec-id:80862880");
84eb01be
TI		 2762MODULE_ALIAS("snd-hda-codec-id:808629fb");
2763
2764MODULE_LICENSE("GPL");
2765MODULE_DESCRIPTION("HDMI HD-audio codec");
2766MODULE_ALIAS("snd-hda-codec-intelhdmi");
2767MODULE_ALIAS("snd-hda-codec-nvhdmi");
2768MODULE_ALIAS("snd-hda-codec-atihdmi");
2769
2770static struct hda_codec_preset_list intel_list = {
2771 .preset = snd_hda_preset_hdmi,
2772 .owner = THIS_MODULE,
2773};
2774
2775static int __init patch_hdmi_init(void)
2776{
2777 return snd_hda_add_codec_preset(&intel_list);
2778}
2779
2780static void __exit patch_hdmi_exit(void)
2781{
2782 snd_hda_delete_codec_preset(&intel_list);
2783}
2784
2785module_init(patch_hdmi_init)
2786module_exit(patch_hdmi_exit)
Linux kernel - Deliverables
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