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Merge remote-tracking branch 'ftrace/for-next'
[deliverable/linux.git] / sound / soc / codecs / rt286.c
CommitLineData
07cf7cba
BL		 1/*
2 * rt286.c -- RT286 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
6c67cde2 20#include <linux/dmi.h>
07cf7cba
BL		 21#include <linux/acpi.h>
22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29#include <sound/jack.h>
30#include <linux/workqueue.h>
31#include <sound/rt286.h>
07cf7cba 32
bc08f96b 33#include "rl6347a.h"
07cf7cba
BL		 34#include "rt286.h"
35
36#define RT286_VENDOR_ID 0x10ec0286
3ab888db 37#define RT288_VENDOR_ID 0x10ec0288
07cf7cba
BL		 38
39struct rt286_priv {
dc6d84c6 40 struct reg_default *index_cache;
bc08f96b 41 int index_cache_size;
07cf7cba 42 struct regmap *regmap;
6879db76 43 struct snd_soc_codec *codec;
07cf7cba
BL		 44 struct rt286_platform_data pdata;
45 struct i2c_client *i2c;
46 struct snd_soc_jack *jack;
47 struct delayed_work jack_detect_work;
48 int sys_clk;
6879db76 49 int clk_id;
07cf7cba
BL		 50};
51
c418a84a 52static const struct reg_default rt286_index_def[] = {
07cf7cba
BL		 53 { 0x01, 0xaaaa },
54 { 0x02, 0x8aaa },
55 { 0x03, 0x0002 },
56 { 0x04, 0xaf01 },
57 { 0x08, 0x000d },
58 { 0x09, 0xd810 },
b7a29767 59 { 0x0a, 0x0120 },
07cf7cba 60 { 0x0b, 0x0000 },
bc6c4e45 61 { 0x0d, 0x2800 },
07cf7cba
BL		 62 { 0x0f, 0x0000 },
63 { 0x19, 0x0a17 },
64 { 0x20, 0x0020 },
65 { 0x33, 0x0208 },
66 { 0x49, 0x0004 },
67 { 0x4f, 0x50e9 },
b7a29767 68 { 0x50, 0x2000 },
07cf7cba 69 { 0x63, 0x2902 },
bc6c4e45
BL		 70 { 0x67, 0x1111 },
71 { 0x68, 0x1016 },
72 { 0x69, 0x273f },
07cf7cba
BL		 73};
74#define INDEX_CACHE_SIZE ARRAY_SIZE(rt286_index_def)
75
76static const struct reg_default rt286_reg[] = {
77 { 0x00170500, 0x00000400 },
78 { 0x00220000, 0x00000031 },
79 { 0x00239000, 0x0000007f },
80 { 0x0023a000, 0x0000007f },
81 { 0x00270500, 0x00000400 },
82 { 0x00370500, 0x00000400 },
83 { 0x00870500, 0x00000400 },
84 { 0x00920000, 0x00000031 },
85 { 0x00935000, 0x000000c3 },
86 { 0x00936000, 0x000000c3 },
87 { 0x00970500, 0x00000400 },
88 { 0x00b37000, 0x00000097 },
89 { 0x00b37200, 0x00000097 },
90 { 0x00b37300, 0x00000097 },
91 { 0x00c37000, 0x00000000 },
92 { 0x00c37100, 0x00000080 },
93 { 0x01270500, 0x00000400 },
94 { 0x01370500, 0x00000400 },
95 { 0x01371f00, 0x411111f0 },
96 { 0x01439000, 0x00000080 },
97 { 0x0143a000, 0x00000080 },
98 { 0x01470700, 0x00000000 },
99 { 0x01470500, 0x00000400 },
100 { 0x01470c00, 0x00000000 },
101 { 0x01470100, 0x00000000 },
102 { 0x01837000, 0x00000000 },
103 { 0x01870500, 0x00000400 },
104 { 0x02050000, 0x00000000 },
105 { 0x02139000, 0x00000080 },
106 { 0x0213a000, 0x00000080 },
107 { 0x02170100, 0x00000000 },
108 { 0x02170500, 0x00000400 },
109 { 0x02170700, 0x00000000 },
110 { 0x02270100, 0x00000000 },
111 { 0x02370100, 0x00000000 },
07cf7cba
BL		 112 { 0x01870700, 0x00000020 },
113 { 0x00830000, 0x000000c3 },
114 { 0x00930000, 0x000000c3 },
115 { 0x01270700, 0x00000000 },
116};
117
118static bool rt286_volatile_register(struct device *dev, unsigned int reg)
119{
120 switch (reg) {
121 case 0 ... 0xff:
122 case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
123 case RT286_GET_HP_SENSE:
124 case RT286_GET_MIC1_SENSE:
125 case RT286_PROC_COEF:
126 return true;
127 default:
128 return false;
129 }
130
131
132}
133
134static bool rt286_readable_register(struct device *dev, unsigned int reg)
135{
136 switch (reg) {
137 case 0 ... 0xff:
138 case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
139 case RT286_GET_HP_SENSE:
140 case RT286_GET_MIC1_SENSE:
141 case RT286_SET_AUDIO_POWER:
142 case RT286_SET_HPO_POWER:
143 case RT286_SET_SPK_POWER:
144 case RT286_SET_DMIC1_POWER:
145 case RT286_SPK_MUX:
146 case RT286_HPO_MUX:
147 case RT286_ADC0_MUX:
148 case RT286_ADC1_MUX:
149 case RT286_SET_MIC1:
150 case RT286_SET_PIN_HPO:
151 case RT286_SET_PIN_SPK:
152 case RT286_SET_PIN_DMIC1:
153 case RT286_SPK_EAPD:
154 case RT286_SET_AMP_GAIN_HPO:
155 case RT286_SET_DMIC2_DEFAULT:
156 case RT286_DACL_GAIN:
157 case RT286_DACR_GAIN:
158 case RT286_ADCL_GAIN:
159 case RT286_ADCR_GAIN:
160 case RT286_MIC_GAIN:
161 case RT286_SPOL_GAIN:
162 case RT286_SPOR_GAIN:
163 case RT286_HPOL_GAIN:
164 case RT286_HPOR_GAIN:
165 case RT286_F_DAC_SWITCH:
166 case RT286_F_RECMIX_SWITCH:
167 case RT286_REC_MIC_SWITCH:
168 case RT286_REC_I2S_SWITCH:
169 case RT286_REC_LINE_SWITCH:
170 case RT286_REC_BEEP_SWITCH:
171 case RT286_DAC_FORMAT:
172 case RT286_ADC_FORMAT:
173 case RT286_COEF_INDEX:
174 case RT286_PROC_COEF:
175 case RT286_SET_AMP_GAIN_ADC_IN1:
176 case RT286_SET_AMP_GAIN_ADC_IN2:
177 case RT286_SET_POWER(RT286_DAC_OUT1):
178 case RT286_SET_POWER(RT286_DAC_OUT2):
179 case RT286_SET_POWER(RT286_ADC_IN1):
180 case RT286_SET_POWER(RT286_ADC_IN2):
181 case RT286_SET_POWER(RT286_DMIC2):
182 case RT286_SET_POWER(RT286_MIC1):
183 return true;
184 default:
185 return false;
186 }
187}
188
81f3dfe1 189#ifdef CONFIG_PM
07cf7cba
BL		 190static void rt286_index_sync(struct snd_soc_codec *codec)
191{
192 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
193 int i;
194
195 for (i = 0; i < INDEX_CACHE_SIZE; i++) {
196 snd_soc_write(codec, rt286->index_cache[i].reg,
197 rt286->index_cache[i].def);
198 }
199}
81f3dfe1 200#endif
07cf7cba
BL		 201
202static int rt286_support_power_controls[] = {
203 RT286_DAC_OUT1,
204 RT286_DAC_OUT2,
205 RT286_ADC_IN1,
206 RT286_ADC_IN2,
207 RT286_MIC1,
208 RT286_DMIC1,
209 RT286_DMIC2,
210 RT286_SPK_OUT,
211 RT286_HP_OUT,
212};
213#define RT286_POWER_REG_LEN ARRAY_SIZE(rt286_support_power_controls)
214
90f601ef 215static int rt286_jack_detect(struct rt286_priv *rt286, bool *hp, bool *mic)
07cf7cba 216{
b1cd8457 217 struct snd_soc_dapm_context *dapm;
07cf7cba 218 unsigned int val, buf;
07cf7cba
BL		 219
220 *hp = false;
221 *mic = false;
222
28d1ad09
BL		 223 if (!rt286->codec)
224 return -EINVAL;
b1cd8457
LPC		 225
226 dapm = snd_soc_codec_get_dapm(rt286->codec);
227
07cf7cba 228 if (rt286->pdata.cbj_en) {
90f601ef 229 regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
07cf7cba
BL		 230 *hp = buf & 0x80000000;
231 if (*hp) {
232 /* power on HV,VERF */
90f601ef 233 regmap_update_bits(rt286->regmap,
6879db76
BL		 234 RT286_DC_GAIN, 0x200, 0x200);
235
b1cd8457
LPC		 236 snd_soc_dapm_force_enable_pin(dapm, "HV");
237 snd_soc_dapm_force_enable_pin(dapm, "VREF");
07cf7cba 238 /* power LDO1 */
b1cd8457
LPC		 239 snd_soc_dapm_force_enable_pin(dapm, "LDO1");
240 snd_soc_dapm_sync(dapm);
07cf7cba 241
6879db76
BL		 242 regmap_write(rt286->regmap, RT286_SET_MIC1, 0x24);
243 msleep(50);
07cf7cba 244
6879db76
BL		 245 regmap_update_bits(rt286->regmap,
246 RT286_CBJ_CTRL1, 0xfcc0, 0xd400);
247 msleep(300);
248 regmap_read(rt286->regmap, RT286_CBJ_CTRL2, &val);
07cf7cba 249
6879db76 250 if (0x0070 == (val & 0x0070)) {
07cf7cba 251 *mic = true;
07cf7cba 252 } else {
6879db76
BL		 253 regmap_update_bits(rt286->regmap,
254 RT286_CBJ_CTRL1, 0xfcc0, 0xe400);
255 msleep(300);
256 regmap_read(rt286->regmap,
257 RT286_CBJ_CTRL2, &val);
258 if (0x0070 == (val & 0x0070))
259 *mic = true;
260 else
261 *mic = false;
07cf7cba 262 }
90f601ef 263 regmap_update_bits(rt286->regmap,
6879db76 264 RT286_DC_GAIN, 0x200, 0x0);
07cf7cba 265
6879db76 266 } else {
07cf7cba 267 *mic = false;
6879db76 268 regmap_write(rt286->regmap, RT286_SET_MIC1, 0x20);
6d514c72
BL		 269 regmap_update_bits(rt286->regmap,
270 RT286_CBJ_CTRL1, 0x0400, 0x0000);
07cf7cba
BL		 271 }
272 } else {
90f601ef 273 regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
07cf7cba 274 *hp = buf & 0x80000000;
90f601ef 275 regmap_read(rt286->regmap, RT286_GET_MIC1_SENSE, &buf);
07cf7cba
BL		 276 *mic = buf & 0x80000000;
277 }
278
b1cd8457
LPC		 279 snd_soc_dapm_disable_pin(dapm, "HV");
280 snd_soc_dapm_disable_pin(dapm, "VREF");
6879db76 281 if (!*hp)
b1cd8457
LPC		 282 snd_soc_dapm_disable_pin(dapm, "LDO1");
283 snd_soc_dapm_sync(dapm);
6879db76 284
07cf7cba
BL		 285 return 0;
286}
287
288static void rt286_jack_detect_work(struct work_struct *work)
289{
290 struct rt286_priv *rt286 =
291 container_of(work, struct rt286_priv, jack_detect_work.work);
292 int status = 0;
293 bool hp = false;
294 bool mic = false;
295
90f601ef 296 rt286_jack_detect(rt286, &hp, &mic);
07cf7cba
BL		 297
298 if (hp == true)
299 status |= SND_JACK_HEADPHONE;
300
301 if (mic == true)
302 status |= SND_JACK_MICROPHONE;
303
304 snd_soc_jack_report(rt286->jack, status,
305 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
306}
307
308int rt286_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
309{
b1cd8457 310 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
07cf7cba
BL		 311 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
312
313 rt286->jack = jack;
314
e2cef68d
JY		 315 if (jack) {
316 /* enable IRQ */
5af76d5c 317 if (rt286->jack->status & SND_JACK_HEADPHONE)
b1cd8457 318 snd_soc_dapm_force_enable_pin(dapm, "LDO1");
e2cef68d
JY		 319 regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x2, 0x2);
320 /* Send an initial empty report */
321 snd_soc_jack_report(rt286->jack, rt286->jack->status,
322 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
323 } else {
324 /* disable IRQ */
325 regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x2, 0x0);
b1cd8457 326 snd_soc_dapm_disable_pin(dapm, "LDO1");
e2cef68d 327 }
b1cd8457 328 snd_soc_dapm_sync(dapm);
07cf7cba
BL		 329
330 return 0;
331}
332EXPORT_SYMBOL_GPL(rt286_mic_detect);
333
6879db76
BL		 334static int is_mclk_mode(struct snd_soc_dapm_widget *source,
335 struct snd_soc_dapm_widget *sink)
336{
76f17f18
LPC		 337 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
338 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
6879db76
BL		 339
340 if (rt286->clk_id == RT286_SCLK_S_MCLK)
341 return 1;
342 else
343 return 0;
344}
345
07cf7cba
BL		 346static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0);
347static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
348
349static const struct snd_kcontrol_new rt286_snd_controls[] = {
350 SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT286_DACL_GAIN,
351 RT286_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv),
54d96a40
BL		 352 SOC_DOUBLE_R("ADC0 Capture Switch", RT286_ADCL_GAIN,
353 RT286_ADCR_GAIN, 7, 1, 1),
07cf7cba
BL		 354 SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT286_ADCL_GAIN,
355 RT286_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv),
356 SOC_SINGLE_TLV("AMIC Volume", RT286_MIC_GAIN,
357 0, 0x3, 0, mic_vol_tlv),
358 SOC_DOUBLE_R("Speaker Playback Switch", RT286_SPOL_GAIN,
359 RT286_SPOR_GAIN, RT286_MUTE_SFT, 1, 1),
360};
361
362/* Digital Mixer */
363static const struct snd_kcontrol_new rt286_front_mix[] = {
364 SOC_DAPM_SINGLE("DAC Switch", RT286_F_DAC_SWITCH,
365 RT286_MUTE_SFT, 1, 1),
366 SOC_DAPM_SINGLE("RECMIX Switch", RT286_F_RECMIX_SWITCH,
367 RT286_MUTE_SFT, 1, 1),
368};
369
370/* Analog Input Mixer */
371static const struct snd_kcontrol_new rt286_rec_mix[] = {
372 SOC_DAPM_SINGLE("Mic1 Switch", RT286_REC_MIC_SWITCH,
373 RT286_MUTE_SFT, 1, 1),
374 SOC_DAPM_SINGLE("I2S Switch", RT286_REC_I2S_SWITCH,
375 RT286_MUTE_SFT, 1, 1),
376 SOC_DAPM_SINGLE("Line1 Switch", RT286_REC_LINE_SWITCH,
377 RT286_MUTE_SFT, 1, 1),
378 SOC_DAPM_SINGLE("Beep Switch", RT286_REC_BEEP_SWITCH,
379 RT286_MUTE_SFT, 1, 1),
380};
381
382static const struct snd_kcontrol_new spo_enable_control =
383 SOC_DAPM_SINGLE("Switch", RT286_SET_PIN_SPK,
384 RT286_SET_PIN_SFT, 1, 0);
385
386static const struct snd_kcontrol_new hpol_enable_control =
387 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOL_GAIN,
388 RT286_MUTE_SFT, 1, 1);
389
390static const struct snd_kcontrol_new hpor_enable_control =
391 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOR_GAIN,
392 RT286_MUTE_SFT, 1, 1);
393
394/* ADC0 source */
395static const char * const rt286_adc_src[] = {
396 "Mic", "RECMIX", "Dmic"
397};
398
399static const int rt286_adc_values[] = {
400 0, 4, 5,
401};
402
403static SOC_VALUE_ENUM_SINGLE_DECL(
404 rt286_adc0_enum, RT286_ADC0_MUX, RT286_ADC_SEL_SFT,
405 RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
406
407static const struct snd_kcontrol_new rt286_adc0_mux =
408 SOC_DAPM_ENUM("ADC 0 source", rt286_adc0_enum);
409
410static SOC_VALUE_ENUM_SINGLE_DECL(
411 rt286_adc1_enum, RT286_ADC1_MUX, RT286_ADC_SEL_SFT,
412 RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
413
414static const struct snd_kcontrol_new rt286_adc1_mux =
415 SOC_DAPM_ENUM("ADC 1 source", rt286_adc1_enum);
416
417static const char * const rt286_dac_src[] = {
418 "Front", "Surround"
419};
420/* HP-OUT source */
421static SOC_ENUM_SINGLE_DECL(rt286_hpo_enum, RT286_HPO_MUX,
422 0, rt286_dac_src);
423
424static const struct snd_kcontrol_new rt286_hpo_mux =
425SOC_DAPM_ENUM("HPO source", rt286_hpo_enum);
426
427/* SPK-OUT source */
428static SOC_ENUM_SINGLE_DECL(rt286_spo_enum, RT286_SPK_MUX,
429 0, rt286_dac_src);
430
431static const struct snd_kcontrol_new rt286_spo_mux =
432SOC_DAPM_ENUM("SPO source", rt286_spo_enum);
433
434static int rt286_spk_event(struct snd_soc_dapm_widget *w,
435 struct snd_kcontrol *kcontrol, int event)
436{
76f17f18 437 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
07cf7cba
BL		 438
439 switch (event) {
440 case SND_SOC_DAPM_POST_PMU:
441 snd_soc_write(codec,
442 RT286_SPK_EAPD, RT286_SET_EAPD_HIGH);
443 break;
444 case SND_SOC_DAPM_PRE_PMD:
445 snd_soc_write(codec,
446 RT286_SPK_EAPD, RT286_SET_EAPD_LOW);
447 break;
448
449 default:
450 return 0;
451 }
452
453 return 0;
454}
455
456static int rt286_set_dmic1_event(struct snd_soc_dapm_widget *w,
457 struct snd_kcontrol *kcontrol, int event)
458{
76f17f18 459 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
07cf7cba
BL		 460
461 switch (event) {
462 case SND_SOC_DAPM_POST_PMU:
463 snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0x20);
464 break;
465 case SND_SOC_DAPM_PRE_PMD:
466 snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0);
467 break;
468 default:
469 return 0;
470 }
471
472 return 0;
473}
474
6879db76
BL		 475static int rt286_ldo2_event(struct snd_soc_dapm_widget *w,
476 struct snd_kcontrol *kcontrol, int event)
477{
76f17f18 478 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
6879db76
BL		 479
480 switch (event) {
481 case SND_SOC_DAPM_POST_PMU:
482 snd_soc_update_bits(codec, RT286_POWER_CTRL2, 0x38, 0x08);
483 break;
484 case SND_SOC_DAPM_PRE_PMD:
485 snd_soc_update_bits(codec, RT286_POWER_CTRL2, 0x38, 0x30);
486 break;
487 default:
488 return 0;
489 }
490
491 return 0;
492}
493
494static int rt286_mic1_event(struct snd_soc_dapm_widget *w,
495 struct snd_kcontrol *kcontrol, int event)
496{
76f17f18 497 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
6879db76
BL		 498
499 switch (event) {
500 case SND_SOC_DAPM_PRE_PMU:
501 snd_soc_update_bits(codec,
502 RT286_A_BIAS_CTRL3, 0xc000, 0x8000);
503 snd_soc_update_bits(codec,
504 RT286_A_BIAS_CTRL2, 0xc000, 0x8000);
505 break;
506 case SND_SOC_DAPM_POST_PMD:
507 snd_soc_update_bits(codec,
508 RT286_A_BIAS_CTRL3, 0xc000, 0x0000);
509 snd_soc_update_bits(codec,
510 RT286_A_BIAS_CTRL2, 0xc000, 0x0000);
511 break;
512 default:
513 return 0;
514 }
515
516 return 0;
517}
518
07cf7cba 519static const struct snd_soc_dapm_widget rt286_dapm_widgets[] = {
6879db76
BL		 520 SND_SOC_DAPM_SUPPLY_S("HV", 1, RT286_POWER_CTRL1,
521 12, 1, NULL, 0),
522 SND_SOC_DAPM_SUPPLY("VREF", RT286_POWER_CTRL1,
6d514c72 523 0, 1, NULL, 0),
6879db76
BL		 524 SND_SOC_DAPM_SUPPLY_S("LDO1", 1, RT286_POWER_CTRL2,
525 2, 0, NULL, 0),
526 SND_SOC_DAPM_SUPPLY_S("LDO2", 2, RT286_POWER_CTRL1,
527 13, 1, rt286_ldo2_event, SND_SOC_DAPM_PRE_PMD |
528 SND_SOC_DAPM_POST_PMU),
529 SND_SOC_DAPM_SUPPLY("MCLK MODE", RT286_PLL_CTRL1,
530 5, 0, NULL, 0),
531 SND_SOC_DAPM_SUPPLY("MIC1 Input Buffer", SND_SOC_NOPM,
532 0, 0, rt286_mic1_event, SND_SOC_DAPM_PRE_PMU |
533 SND_SOC_DAPM_POST_PMD),
534
07cf7cba
BL		 535 /* Input Lines */
536 SND_SOC_DAPM_INPUT("DMIC1 Pin"),
537 SND_SOC_DAPM_INPUT("DMIC2 Pin"),
538 SND_SOC_DAPM_INPUT("MIC1"),
539 SND_SOC_DAPM_INPUT("LINE1"),
540 SND_SOC_DAPM_INPUT("Beep"),
541
542 /* DMIC */
543 SND_SOC_DAPM_PGA_E("DMIC1", RT286_SET_POWER(RT286_DMIC1), 0, 1,
544 NULL, 0, rt286_set_dmic1_event,
545 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
546 SND_SOC_DAPM_PGA("DMIC2", RT286_SET_POWER(RT286_DMIC2), 0, 1,
547 NULL, 0),
548 SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM,
549 0, 0, NULL, 0),
550
551 /* REC Mixer */
552 SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0,
553 rt286_rec_mix, ARRAY_SIZE(rt286_rec_mix)),
554
555 /* ADCs */
556 SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0),
557 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
558
559 /* ADC Mux */
54d96a40
BL		 560 SND_SOC_DAPM_MUX("ADC 0 Mux", RT286_SET_POWER(RT286_ADC_IN1), 0, 1,
561 &rt286_adc0_mux),
562 SND_SOC_DAPM_MUX("ADC 1 Mux", RT286_SET_POWER(RT286_ADC_IN2), 0, 1,
563 &rt286_adc1_mux),
07cf7cba
BL		 564
565 /* Audio Interface */
566 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
567 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
568 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
569 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
570
571 /* Output Side */
572 /* DACs */
573 SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0),
574 SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0),
575
576 /* Output Mux */
577 SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt286_spo_mux),
578 SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt286_hpo_mux),
579
580 SND_SOC_DAPM_SUPPLY("HP Power", RT286_SET_PIN_HPO,
581 RT286_SET_PIN_SFT, 0, NULL, 0),
582
583 /* Output Mixer */
584 SND_SOC_DAPM_MIXER("Front", RT286_SET_POWER(RT286_DAC_OUT1), 0, 1,
585 rt286_front_mix, ARRAY_SIZE(rt286_front_mix)),
586 SND_SOC_DAPM_PGA("Surround", RT286_SET_POWER(RT286_DAC_OUT2), 0, 1,
587 NULL, 0),
588
589 /* Output Pga */
590 SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0,
591 &spo_enable_control, rt286_spk_event,
592 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
593 SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0,
594 &hpol_enable_control),
595 SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0,
596 &hpor_enable_control),
597
598 /* Output Lines */
599 SND_SOC_DAPM_OUTPUT("SPOL"),
600 SND_SOC_DAPM_OUTPUT("SPOR"),
601 SND_SOC_DAPM_OUTPUT("HPO Pin"),
602 SND_SOC_DAPM_OUTPUT("SPDIF"),
603};
604
605static const struct snd_soc_dapm_route rt286_dapm_routes[] = {
6879db76
BL		 606 {"ADC 0", NULL, "MCLK MODE", is_mclk_mode},
607 {"ADC 1", NULL, "MCLK MODE", is_mclk_mode},
608 {"Front", NULL, "MCLK MODE", is_mclk_mode},
609 {"Surround", NULL, "MCLK MODE", is_mclk_mode},
610
611 {"HP Power", NULL, "LDO1"},
612 {"HP Power", NULL, "LDO2"},
613
614 {"MIC1", NULL, "LDO1"},
615 {"MIC1", NULL, "LDO2"},
616 {"MIC1", NULL, "HV"},
617 {"MIC1", NULL, "VREF"},
618 {"MIC1", NULL, "MIC1 Input Buffer"},
619
620 {"SPO", NULL, "LDO1"},
621 {"SPO", NULL, "LDO2"},
622 {"SPO", NULL, "HV"},
623 {"SPO", NULL, "VREF"},
624
07cf7cba
BL		 625 {"DMIC1", NULL, "DMIC1 Pin"},
626 {"DMIC2", NULL, "DMIC2 Pin"},
627 {"DMIC1", NULL, "DMIC Receiver"},
628 {"DMIC2", NULL, "DMIC Receiver"},
629
630 {"RECMIX", "Beep Switch", "Beep"},
631 {"RECMIX", "Line1 Switch", "LINE1"},
632 {"RECMIX", "Mic1 Switch", "MIC1"},
633
634 {"ADC 0 Mux", "Dmic", "DMIC1"},
635 {"ADC 0 Mux", "RECMIX", "RECMIX"},
636 {"ADC 0 Mux", "Mic", "MIC1"},
637 {"ADC 1 Mux", "Dmic", "DMIC2"},
638 {"ADC 1 Mux", "RECMIX", "RECMIX"},
639 {"ADC 1 Mux", "Mic", "MIC1"},
640
641 {"ADC 0", NULL, "ADC 0 Mux"},
642 {"ADC 1", NULL, "ADC 1 Mux"},
643
644 {"AIF1TX", NULL, "ADC 0"},
645 {"AIF2TX", NULL, "ADC 1"},
646
647 {"DAC 0", NULL, "AIF1RX"},
648 {"DAC 1", NULL, "AIF2RX"},
649
650 {"Front", "DAC Switch", "DAC 0"},
651 {"Front", "RECMIX Switch", "RECMIX"},
652
653 {"Surround", NULL, "DAC 1"},
654
655 {"SPK Mux", "Front", "Front"},
656 {"SPK Mux", "Surround", "Surround"},
657
658 {"HPO Mux", "Front", "Front"},
659 {"HPO Mux", "Surround", "Surround"},
660
661 {"SPO", "Switch", "SPK Mux"},
662 {"HPO L", "Switch", "HPO Mux"},
663 {"HPO R", "Switch", "HPO Mux"},
664 {"HPO L", NULL, "HP Power"},
665 {"HPO R", NULL, "HP Power"},
666
667 {"SPOL", NULL, "SPO"},
668 {"SPOR", NULL, "SPO"},
669 {"HPO Pin", NULL, "HPO L"},
670 {"HPO Pin", NULL, "HPO R"},
671};
672
673static int rt286_hw_params(struct snd_pcm_substream *substream,
674 struct snd_pcm_hw_params *params,
675 struct snd_soc_dai *dai)
676{
677 struct snd_soc_codec *codec = dai->codec;
678 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
679 unsigned int val = 0;
680 int d_len_code;
681
682 switch (params_rate(params)) {
683 /* bit 14 0:48K 1:44.1K */
684 case 44100:
685 val |= 0x4000;
686 break;
687 case 48000:
688 break;
689 default:
690 dev_err(codec->dev, "Unsupported sample rate %d\n",
691 params_rate(params));
692 return -EINVAL;
693 }
694 switch (rt286->sys_clk) {
695 case 12288000:
696 case 24576000:
697 if (params_rate(params) != 48000) {
698 dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n",
699 params_rate(params), rt286->sys_clk);
700 return -EINVAL;
701 }
702 break;
703 case 11289600:
704 case 22579200:
705 if (params_rate(params) != 44100) {
706 dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n",
707 params_rate(params), rt286->sys_clk);
708 return -EINVAL;
709 }
710 break;
711 }
712
713 if (params_channels(params) <= 16) {
714 /* bit 3:0 Number of Channel */
715 val |= (params_channels(params) - 1);
716 } else {
717 dev_err(codec->dev, "Unsupported channels %d\n",
718 params_channels(params));
719 return -EINVAL;
720 }
721
722 d_len_code = 0;
723 switch (params_width(params)) {
724 /* bit 6:4 Bits per Sample */
725 case 16:
726 d_len_code = 0;
727 val |= (0x1 << 4);
728 break;
729 case 32:
730 d_len_code = 2;
731 val |= (0x4 << 4);
732 break;
733 case 20:
734 d_len_code = 1;
735 val |= (0x2 << 4);
736 break;
737 case 24:
738 d_len_code = 2;
739 val |= (0x3 << 4);
740 break;
741 case 8:
742 d_len_code = 3;
743 break;
744 default:
745 return -EINVAL;
746 }
747
748 snd_soc_update_bits(codec,
749 RT286_I2S_CTRL1, 0x0018, d_len_code << 3);
750 dev_dbg(codec->dev, "format val = 0x%x\n", val);
751
45437fa5
BL		 752 snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x407f, val);
753 snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x407f, val);
07cf7cba
BL		 754
755 return 0;
756}
757
758static int rt286_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
759{
760 struct snd_soc_codec *codec = dai->codec;
761
762 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
763 case SND_SOC_DAIFMT_CBM_CFM:
764 snd_soc_update_bits(codec,
765 RT286_I2S_CTRL1, 0x800, 0x800);
766 break;
767 case SND_SOC_DAIFMT_CBS_CFS:
768 snd_soc_update_bits(codec,
769 RT286_I2S_CTRL1, 0x800, 0x0);
770 break;
771 default:
772 return -EINVAL;
773 }
774
775 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
776 case SND_SOC_DAIFMT_I2S:
777 snd_soc_update_bits(codec,
778 RT286_I2S_CTRL1, 0x300, 0x0);
779 break;
780 case SND_SOC_DAIFMT_LEFT_J:
781 snd_soc_update_bits(codec,
782 RT286_I2S_CTRL1, 0x300, 0x1 << 8);
783 break;
784 case SND_SOC_DAIFMT_DSP_A:
785 snd_soc_update_bits(codec,
786 RT286_I2S_CTRL1, 0x300, 0x2 << 8);
787 break;
788 case SND_SOC_DAIFMT_DSP_B:
789 snd_soc_update_bits(codec,
790 RT286_I2S_CTRL1, 0x300, 0x3 << 8);
791 break;
792 default:
793 return -EINVAL;
794 }
795 /* bit 15 Stream Type 0:PCM 1:Non-PCM */
796 snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x8000, 0);
797 snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x8000, 0);
798
799 return 0;
800}
801
802static int rt286_set_dai_sysclk(struct snd_soc_dai *dai,
803 int clk_id, unsigned int freq, int dir)
804{
805 struct snd_soc_codec *codec = dai->codec;
806 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
807
808 dev_dbg(codec->dev, "%s freq=%d\n", __func__, freq);
809
810 if (RT286_SCLK_S_MCLK == clk_id) {
811 snd_soc_update_bits(codec,
812 RT286_I2S_CTRL2, 0x0100, 0x0);
813 snd_soc_update_bits(codec,
814 RT286_PLL_CTRL1, 0x20, 0x20);
815 } else {
816 snd_soc_update_bits(codec,
817 RT286_I2S_CTRL2, 0x0100, 0x0100);
818 snd_soc_update_bits(codec,
819 RT286_PLL_CTRL, 0x4, 0x4);
820 snd_soc_update_bits(codec,
821 RT286_PLL_CTRL1, 0x20, 0x0);
822 }
823
824 switch (freq) {
825 case 19200000:
826 if (RT286_SCLK_S_MCLK == clk_id) {
827 dev_err(codec->dev, "Should not use MCLK\n");
828 return -EINVAL;
829 }
830 snd_soc_update_bits(codec,
831 RT286_I2S_CTRL2, 0x40, 0x40);
832 break;
833 case 24000000:
834 if (RT286_SCLK_S_MCLK == clk_id) {
835 dev_err(codec->dev, "Should not use MCLK\n");
836 return -EINVAL;
837 }
838 snd_soc_update_bits(codec,
839 RT286_I2S_CTRL2, 0x40, 0x0);
840 break;
841 case 12288000:
842 case 11289600:
843 snd_soc_update_bits(codec,
844 RT286_I2S_CTRL2, 0x8, 0x0);
845 snd_soc_update_bits(codec,
846 RT286_CLK_DIV, 0xfc1e, 0x0004);
847 break;
848 case 24576000:
849 case 22579200:
850 snd_soc_update_bits(codec,
851 RT286_I2S_CTRL2, 0x8, 0x8);
852 snd_soc_update_bits(codec,
853 RT286_CLK_DIV, 0xfc1e, 0x5406);
854 break;
855 default:
856 dev_err(codec->dev, "Unsupported system clock\n");
857 return -EINVAL;
858 }
859
860 rt286->sys_clk = freq;
6879db76 861 rt286->clk_id = clk_id;
07cf7cba
BL		 862
863 return 0;
864}
865
866static int rt286_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
867{
868 struct snd_soc_codec *codec = dai->codec;
869
870 dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio);
871 if (50 == ratio)
872 snd_soc_update_bits(codec,
873 RT286_I2S_CTRL1, 0x1000, 0x1000);
874 else
875 snd_soc_update_bits(codec,
876 RT286_I2S_CTRL1, 0x1000, 0x0);
877
878
879 return 0;
880}
881
882static int rt286_set_bias_level(struct snd_soc_codec *codec,
883 enum snd_soc_bias_level level)
884{
885 switch (level) {
886 case SND_SOC_BIAS_PREPARE:
b1cd8457 887 if (SND_SOC_BIAS_STANDBY == snd_soc_codec_get_bias_level(codec)) {
07cf7cba
BL		 888 snd_soc_write(codec,
889 RT286_SET_AUDIO_POWER, AC_PWRST_D0);
bc6c4e45
BL		 890 snd_soc_update_bits(codec,
891 RT286_DC_GAIN, 0x200, 0x200);
892 }
893 break;
894
895 case SND_SOC_BIAS_ON:
896 mdelay(10);
6879db76
BL		 897 snd_soc_update_bits(codec,
898 RT286_DC_GAIN, 0x200, 0x0);
899
07cf7cba
BL		 900 break;
901
902 case SND_SOC_BIAS_STANDBY:
903 snd_soc_write(codec,
904 RT286_SET_AUDIO_POWER, AC_PWRST_D3);
905 break;
906
907 default:
908 break;
909 }
07cf7cba
BL		 910
911 return 0;
912}
913
914static irqreturn_t rt286_irq(int irq, void *data)
915{
916 struct rt286_priv *rt286 = data;
917 bool hp = false;
918 bool mic = false;
919 int status = 0;
920
90f601ef 921 rt286_jack_detect(rt286, &hp, &mic);
07cf7cba
BL		 922
923 /* Clear IRQ */
90f601ef 924 regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x1, 0x1);
07cf7cba
BL		 925
926 if (hp == true)
927 status |= SND_JACK_HEADPHONE;
928
929 if (mic == true)
930 status |= SND_JACK_MICROPHONE;
931
932 snd_soc_jack_report(rt286->jack, status,
933 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
934
935 pm_wakeup_event(&rt286->i2c->dev, 300);
936
937 return IRQ_HANDLED;
938}
939
940static int rt286_probe(struct snd_soc_codec *codec)
941{
942 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
07cf7cba 943
6879db76 944 rt286->codec = codec;
90f601ef
BL		 945
946 if (rt286->i2c->irq) {
947 regmap_update_bits(rt286->regmap,
948 RT286_IRQ_CTRL, 0x2, 0x2);
949
950 INIT_DELAYED_WORK(&rt286->jack_detect_work,
951 rt286_jack_detect_work);
952 schedule_delayed_work(&rt286->jack_detect_work,
953 msecs_to_jiffies(1250));
954 }
07cf7cba 955
07cf7cba
BL		 956 return 0;
957}
958
959static int rt286_remove(struct snd_soc_codec *codec)
960{
961 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
962
963 cancel_delayed_work_sync(&rt286->jack_detect_work);
964
965 return 0;
966}
967
968#ifdef CONFIG_PM
969static int rt286_suspend(struct snd_soc_codec *codec)
970{
971 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
972
973 regcache_cache_only(rt286->regmap, true);
974 regcache_mark_dirty(rt286->regmap);
975
976 return 0;
977}
978
979static int rt286_resume(struct snd_soc_codec *codec)
980{
981 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
982
983 regcache_cache_only(rt286->regmap, false);
984 rt286_index_sync(codec);
985 regcache_sync(rt286->regmap);
986
987 return 0;
988}
989#else
990#define rt286_suspend NULL
991#define rt286_resume NULL
992#endif
993
994#define RT286_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
995#define RT286_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
996 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
997
998static const struct snd_soc_dai_ops rt286_aif_dai_ops = {
999 .hw_params = rt286_hw_params,
1000 .set_fmt = rt286_set_dai_fmt,
1001 .set_sysclk = rt286_set_dai_sysclk,
1002 .set_bclk_ratio = rt286_set_bclk_ratio,
1003};
1004
1005static struct snd_soc_dai_driver rt286_dai[] = {
1006 {
1007 .name = "rt286-aif1",
1008 .id = RT286_AIF1,
1009 .playback = {
1010 .stream_name = "AIF1 Playback",
1011 .channels_min = 1,
1012 .channels_max = 2,
1013 .rates = RT286_STEREO_RATES,
1014 .formats = RT286_FORMATS,
1015 },
1016 .capture = {
1017 .stream_name = "AIF1 Capture",
1018 .channels_min = 1,
1019 .channels_max = 2,
1020 .rates = RT286_STEREO_RATES,
1021 .formats = RT286_FORMATS,
1022 },
1023 .ops = &rt286_aif_dai_ops,
1024 .symmetric_rates = 1,
1025 },
1026 {
1027 .name = "rt286-aif2",
1028 .id = RT286_AIF2,
1029 .playback = {
1030 .stream_name = "AIF2 Playback",
1031 .channels_min = 1,
1032 .channels_max = 2,
1033 .rates = RT286_STEREO_RATES,
1034 .formats = RT286_FORMATS,
1035 },
1036 .capture = {
1037 .stream_name = "AIF2 Capture",
1038 .channels_min = 1,
1039 .channels_max = 2,
1040 .rates = RT286_STEREO_RATES,
1041 .formats = RT286_FORMATS,
1042 },
1043 .ops = &rt286_aif_dai_ops,
1044 .symmetric_rates = 1,
1045 },
1046
1047};
1048
1049static struct snd_soc_codec_driver soc_codec_dev_rt286 = {
1050 .probe = rt286_probe,
1051 .remove = rt286_remove,
1052 .suspend = rt286_suspend,
1053 .resume = rt286_resume,
1054 .set_bias_level = rt286_set_bias_level,
1055 .idle_bias_off = true,
a6a505dd
KM		 1056 .component_driver = {
1057 .controls = rt286_snd_controls,
1058 .num_controls = ARRAY_SIZE(rt286_snd_controls),
1059 .dapm_widgets = rt286_dapm_widgets,
1060 .num_dapm_widgets = ARRAY_SIZE(rt286_dapm_widgets),
1061 .dapm_routes = rt286_dapm_routes,
1062 .num_dapm_routes = ARRAY_SIZE(rt286_dapm_routes),
1063 },
07cf7cba
BL		 1064};
1065
1066static const struct regmap_config rt286_regmap = {
1067 .reg_bits = 32,
1068 .val_bits = 32,
1069 .max_register = 0x02370100,
1070 .volatile_reg = rt286_volatile_register,
1071 .readable_reg = rt286_readable_register,
bc08f96b
OC		 1072 .reg_write = rl6347a_hw_write,
1073 .reg_read = rl6347a_hw_read,
07cf7cba
BL		 1074 .cache_type = REGCACHE_RBTREE,
1075 .reg_defaults = rt286_reg,
1076 .num_reg_defaults = ARRAY_SIZE(rt286_reg),
1077};
1078
1079static const struct i2c_device_id rt286_i2c_id[] = {
1080 {"rt286", 0},
3ab888db 1081 {"rt288", 0},
07cf7cba
BL		 1082 {}
1083};
1084MODULE_DEVICE_TABLE(i2c, rt286_i2c_id);
1085
1086static const struct acpi_device_id rt286_acpi_match[] = {
1087 { "INT343A", 0 },
1088 {},
1089};
1090MODULE_DEVICE_TABLE(acpi, rt286_acpi_match);
1091
a5afdc5b 1092static const struct dmi_system_id force_combo_jack_table[] = {
6c67cde2
BL		 1093 {
1094 .ident = "Intel Wilson Beach",
1095 .matches = {
1096 DMI_MATCH(DMI_BOARD_NAME, "Wilson Beach SDS")
1097 }
1098 },
166765ea
VK		 1099 {
1100 .ident = "Intel Skylake RVP",
1101 .matches = {
1102 DMI_MATCH(DMI_PRODUCT_NAME, "Skylake Client platform")
1103 }
1104 },
d06de6d9
VK		 1105 {
1106 .ident = "Intel Kabylake RVP",
1107 .matches = {
1108 DMI_MATCH(DMI_PRODUCT_NAME, "Kabylake Client platform")
1109 }
1110 },
1111
6c67cde2
BL		 1112 { }
1113};
1114
a5afdc5b 1115static const struct dmi_system_id dmi_dell_dino[] = {
2cc3f234
BL		 1116 {
1117 .ident = "Dell Dino",
1118 .matches = {
1119 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
a4ee5561 1120 DMI_MATCH(DMI_PRODUCT_NAME, "XPS 13 9343")
2cc3f234
BL		 1121 }
1122 },
1123 { }
1124};
1125
07cf7cba
BL		 1126static int rt286_i2c_probe(struct i2c_client *i2c,
1127 const struct i2c_device_id *id)
1128{
1129 struct rt286_platform_data *pdata = dev_get_platdata(&i2c->dev);
1130 struct rt286_priv *rt286;
143526ee 1131 int i, ret, val;
07cf7cba
BL		 1132
1133 rt286 = devm_kzalloc(&i2c->dev, sizeof(*rt286),
1134 GFP_KERNEL);
1135 if (NULL == rt286)
1136 return -ENOMEM;
1137
1138 rt286->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt286_regmap);
1139 if (IS_ERR(rt286->regmap)) {
1140 ret = PTR_ERR(rt286->regmap);
1141 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1142 ret);
1143 return ret;
1144 }
1145
143526ee
BL		 1146 ret = regmap_read(rt286->regmap,
1147 RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &val);
1148 if (ret != 0) {
1149 dev_err(&i2c->dev, "I2C error %d\n", ret);
1150 return ret;
1151 }
1152 if (val != RT286_VENDOR_ID && val != RT288_VENDOR_ID) {
4b21768a 1153 dev_err(&i2c->dev,
e608aaef 1154 "Device with ID register %#x is not rt286\n", val);
4b21768a
BL		 1155 return -ENODEV;
1156 }
1157
dc6d84c6
AL		 1158 rt286->index_cache = devm_kmemdup(&i2c->dev, rt286_index_def,
1159 sizeof(rt286_index_def), GFP_KERNEL);
1160 if (!rt286->index_cache)
1161 return -ENOMEM;
1162
bc08f96b 1163 rt286->index_cache_size = INDEX_CACHE_SIZE;
07cf7cba
BL		 1164 rt286->i2c = i2c;
1165 i2c_set_clientdata(i2c, rt286);
1166
d53d59ec
BL		 1167 /* restore codec default */
1168 for (i = 0; i < INDEX_CACHE_SIZE; i++)
1169 regmap_write(rt286->regmap, rt286->index_cache[i].reg,
1170 rt286->index_cache[i].def);
1171 for (i = 0; i < ARRAY_SIZE(rt286_reg); i++)
1172 regmap_write(rt286->regmap, rt286_reg[i].reg,
1173 rt286_reg[i].def);
1174
07cf7cba
BL		 1175 if (pdata)
1176 rt286->pdata = *pdata;
1177
2cc3f234
BL		 1178 if (dmi_check_system(force_combo_jack_table) ||
1179 dmi_check_system(dmi_dell_dino))
6c67cde2
BL		 1180 rt286->pdata.cbj_en = true;
1181
61a414c4
BL		 1182 regmap_write(rt286->regmap, RT286_SET_AUDIO_POWER, AC_PWRST_D3);
1183
1184 for (i = 0; i < RT286_POWER_REG_LEN; i++)
1185 regmap_write(rt286->regmap,
1186 RT286_SET_POWER(rt286_support_power_controls[i]),
1187 AC_PWRST_D1);
1188
1189 if (!rt286->pdata.cbj_en) {
1190 regmap_write(rt286->regmap, RT286_CBJ_CTRL2, 0x0000);
1191 regmap_write(rt286->regmap, RT286_MIC1_DET_CTRL, 0x0816);
61a414c4
BL		 1192 regmap_update_bits(rt286->regmap,
1193 RT286_CBJ_CTRL1, 0xf000, 0xb000);
1194 } else {
1195 regmap_update_bits(rt286->regmap,
1196 RT286_CBJ_CTRL1, 0xf000, 0x5000);
1197 }
1198
1199 mdelay(10);
1200
1201 if (!rt286->pdata.gpio2_en)
1202 regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0x4000);
1203 else
1204 regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0);
1205
1206 mdelay(10);
1207
6879db76 1208 regmap_write(rt286->regmap, RT286_MISC_CTRL1, 0x0000);
f8c101bc 1209 /* Power down LDO, VREF */
6879db76
BL		 1210 regmap_update_bits(rt286->regmap, RT286_POWER_CTRL2, 0xc, 0x0);
1211 regmap_update_bits(rt286->regmap, RT286_POWER_CTRL1, 0x1001, 0x1001);
61a414c4 1212
f8c101bc 1213 /* Set depop parameter */
bc6c4e45
BL		 1214 regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL2, 0x403a, 0x401a);
1215 regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL3, 0xf777, 0x4737);
1216 regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL4, 0x00ff, 0x003f);
1217
2cc3f234
BL		 1218 if (dmi_check_system(dmi_dell_dino)) {
1219 regmap_update_bits(rt286->regmap,
1220 RT286_SET_GPIO_MASK, 0x40, 0x40);
1221 regmap_update_bits(rt286->regmap,
1222 RT286_SET_GPIO_DIRECTION, 0x40, 0x40);
1223 regmap_update_bits(rt286->regmap,
1224 RT286_SET_GPIO_DATA, 0x40, 0x40);
1225 regmap_update_bits(rt286->regmap,
1226 RT286_GPIO_CTRL, 0xc, 0x8);
1227 }
1228
61a414c4 1229 if (rt286->i2c->irq) {
61a414c4
BL		 1230 ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq,
1231 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt286", rt286);
1232 if (ret != 0) {
1233 dev_err(&i2c->dev,
1234 "Failed to reguest IRQ: %d\n", ret);
1235 return ret;
1236 }
1237 }
1238
07cf7cba
BL		 1239 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt286,
1240 rt286_dai, ARRAY_SIZE(rt286_dai));
1241
1242 return ret;
1243}
1244
1245static int rt286_i2c_remove(struct i2c_client *i2c)
1246{
1247 struct rt286_priv *rt286 = i2c_get_clientdata(i2c);
1248
1249 if (i2c->irq)
1250 free_irq(i2c->irq, rt286);
1251 snd_soc_unregister_codec(&i2c->dev);
1252
1253 return 0;
1254}
1255
1256
23c4fd5c 1257static struct i2c_driver rt286_i2c_driver = {
07cf7cba
BL		 1258 .driver = {
1259 .name = "rt286",
07cf7cba
BL		 1260 .acpi_match_table = ACPI_PTR(rt286_acpi_match),
1261 },
1262 .probe = rt286_i2c_probe,
1263 .remove = rt286_i2c_remove,
1264 .id_table = rt286_i2c_id,
1265};
1266
1267module_i2c_driver(rt286_i2c_driver);
1268
1269MODULE_DESCRIPTION("ASoC RT286 driver");
1270MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
1271MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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