Commit | Line | Data |
---|---|---|
9b34e6cc ZZ |
1 | /* |
2 | * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver | |
3 | * | |
4 | * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/pm.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/clk.h> | |
bd0593f5 | 19 | #include <linux/log2.h> |
e5d80e82 | 20 | #include <linux/regmap.h> |
9b34e6cc ZZ |
21 | #include <linux/regulator/driver.h> |
22 | #include <linux/regulator/machine.h> | |
23 | #include <linux/regulator/consumer.h> | |
58e49424 | 24 | #include <linux/of_device.h> |
9b34e6cc ZZ |
25 | #include <sound/core.h> |
26 | #include <sound/tlv.h> | |
27 | #include <sound/pcm.h> | |
28 | #include <sound/pcm_params.h> | |
29 | #include <sound/soc.h> | |
30 | #include <sound/soc-dapm.h> | |
31 | #include <sound/initval.h> | |
9b34e6cc ZZ |
32 | |
33 | #include "sgtl5000.h" | |
34 | ||
35 | #define SGTL5000_DAP_REG_OFFSET 0x0100 | |
36 | #define SGTL5000_MAX_REG_OFFSET 0x013A | |
37 | ||
151798f8 | 38 | /* default value of sgtl5000 registers */ |
e5d80e82 | 39 | static const struct reg_default sgtl5000_reg_defaults[] = { |
29aa37cd | 40 | { SGTL5000_CHIP_DIG_POWER, 0x0000 }, |
e5d80e82 | 41 | { SGTL5000_CHIP_I2S_CTRL, 0x0010 }, |
016fcab8 | 42 | { SGTL5000_CHIP_SSS_CTRL, 0x0010 }, |
29aa37cd | 43 | { SGTL5000_CHIP_ADCDAC_CTRL, 0x020c }, |
e5d80e82 FE |
44 | { SGTL5000_CHIP_DAC_VOL, 0x3c3c }, |
45 | { SGTL5000_CHIP_PAD_STRENGTH, 0x015f }, | |
29aa37cd | 46 | { SGTL5000_CHIP_ANA_ADC_CTRL, 0x0000 }, |
e5d80e82 FE |
47 | { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 }, |
48 | { SGTL5000_CHIP_ANA_CTRL, 0x0111 }, | |
29aa37cd FE |
49 | { SGTL5000_CHIP_REF_CTRL, 0x0000 }, |
50 | { SGTL5000_CHIP_MIC_CTRL, 0x0000 }, | |
51 | { SGTL5000_CHIP_LINE_OUT_CTRL, 0x0000 }, | |
e5d80e82 | 52 | { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 }, |
e5d80e82 | 53 | { SGTL5000_CHIP_PLL_CTRL, 0x5000 }, |
29aa37cd FE |
54 | { SGTL5000_CHIP_CLK_TOP_CTRL, 0x0000 }, |
55 | { SGTL5000_CHIP_ANA_STATUS, 0x0000 }, | |
56 | { SGTL5000_CHIP_SHORT_CTRL, 0x0000 }, | |
57 | { SGTL5000_CHIP_ANA_TEST2, 0x0000 }, | |
58 | { SGTL5000_DAP_CTRL, 0x0000 }, | |
59 | { SGTL5000_DAP_PEQ, 0x0000 }, | |
e5d80e82 FE |
60 | { SGTL5000_DAP_BASS_ENHANCE, 0x0040 }, |
61 | { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f }, | |
29aa37cd | 62 | { SGTL5000_DAP_AUDIO_EQ, 0x0000 }, |
e5d80e82 FE |
63 | { SGTL5000_DAP_SURROUND, 0x0040 }, |
64 | { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f }, | |
65 | { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f }, | |
66 | { SGTL5000_DAP_EQ_BASS_BAND2, 0x002f }, | |
67 | { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f }, | |
68 | { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f }, | |
69 | { SGTL5000_DAP_MAIN_CHAN, 0x8000 }, | |
29aa37cd | 70 | { SGTL5000_DAP_MIX_CHAN, 0x0000 }, |
e5d80e82 FE |
71 | { SGTL5000_DAP_AVC_CTRL, 0x0510 }, |
72 | { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 }, | |
73 | { SGTL5000_DAP_AVC_ATTACK, 0x0028 }, | |
74 | { SGTL5000_DAP_AVC_DECAY, 0x0050 }, | |
9b34e6cc ZZ |
75 | }; |
76 | ||
77 | /* regulator supplies for sgtl5000, VDDD is an optional external supply */ | |
78 | enum sgtl5000_regulator_supplies { | |
79 | VDDA, | |
80 | VDDIO, | |
81 | VDDD, | |
82 | SGTL5000_SUPPLY_NUM | |
83 | }; | |
84 | ||
85 | /* vddd is optional supply */ | |
86 | static const char *supply_names[SGTL5000_SUPPLY_NUM] = { | |
87 | "VDDA", | |
88 | "VDDIO", | |
89 | "VDDD" | |
90 | }; | |
91 | ||
9b34e6cc | 92 | #define LDO_VOLTAGE 1200000 |
3d632cc8 | 93 | #define LINREG_VDDD ((1600 - LDO_VOLTAGE / 1000) / 50) |
9b34e6cc | 94 | |
bd0593f5 JMH |
95 | enum sgtl5000_micbias_resistor { |
96 | SGTL5000_MICBIAS_OFF = 0, | |
97 | SGTL5000_MICBIAS_2K = 2, | |
98 | SGTL5000_MICBIAS_4K = 4, | |
99 | SGTL5000_MICBIAS_8K = 8, | |
100 | }; | |
101 | ||
9b34e6cc ZZ |
102 | /* sgtl5000 private structure in codec */ |
103 | struct sgtl5000_priv { | |
104 | int sysclk; /* sysclk rate */ | |
105 | int master; /* i2s master or not */ | |
106 | int fmt; /* i2s data format */ | |
107 | struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM]; | |
940adb28 | 108 | int num_supplies; |
e5d80e82 | 109 | struct regmap *regmap; |
9e13f345 | 110 | struct clk *mclk; |
252e91ff | 111 | int revision; |
bd0593f5 | 112 | u8 micbias_resistor; |
87357797 | 113 | u8 micbias_voltage; |
9b34e6cc ZZ |
114 | }; |
115 | ||
116 | /* | |
117 | * mic_bias power on/off share the same register bits with | |
118 | * output impedance of mic bias, when power on mic bias, we | |
119 | * need reclaim it to impedance value. | |
120 | * 0x0 = Powered off | |
121 | * 0x1 = 2Kohm | |
122 | * 0x2 = 4Kohm | |
123 | * 0x3 = 8Kohm | |
124 | */ | |
125 | static int mic_bias_event(struct snd_soc_dapm_widget *w, | |
126 | struct snd_kcontrol *kcontrol, int event) | |
127 | { | |
73bffd17 LPC |
128 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
129 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
bd0593f5 | 130 | |
9b34e6cc ZZ |
131 | switch (event) { |
132 | case SND_SOC_DAPM_POST_PMU: | |
bd0593f5 | 133 | /* change mic bias resistor */ |
73bffd17 | 134 | snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL, |
bd0593f5 JMH |
135 | SGTL5000_BIAS_R_MASK, |
136 | sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT); | |
9b34e6cc ZZ |
137 | break; |
138 | ||
139 | case SND_SOC_DAPM_PRE_PMD: | |
73bffd17 | 140 | snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL, |
dc56c5a8 | 141 | SGTL5000_BIAS_R_MASK, 0); |
9b34e6cc ZZ |
142 | break; |
143 | } | |
144 | return 0; | |
145 | } | |
146 | ||
147 | /* | |
f0cdcf3a ZZ |
148 | * As manual described, ADC/DAC only works when VAG powerup, |
149 | * So enabled VAG before ADC/DAC up. | |
150 | * In power down case, we need wait 400ms when vag fully ramped down. | |
9b34e6cc | 151 | */ |
f0cdcf3a | 152 | static int power_vag_event(struct snd_soc_dapm_widget *w, |
9b34e6cc ZZ |
153 | struct snd_kcontrol *kcontrol, int event) |
154 | { | |
73bffd17 | 155 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
f091f3f0 LW |
156 | const u32 mask = SGTL5000_DAC_POWERUP | SGTL5000_ADC_POWERUP; |
157 | ||
9b34e6cc | 158 | switch (event) { |
dd4d2d6d | 159 | case SND_SOC_DAPM_POST_PMU: |
73bffd17 | 160 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, |
9b34e6cc | 161 | SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP); |
c803cc2d | 162 | msleep(400); |
9b34e6cc ZZ |
163 | break; |
164 | ||
dd4d2d6d | 165 | case SND_SOC_DAPM_PRE_PMD: |
f091f3f0 LW |
166 | /* |
167 | * Don't clear VAG_POWERUP, when both DAC and ADC are | |
168 | * operational to prevent inadvertently starving the | |
169 | * other one of them. | |
170 | */ | |
73bffd17 | 171 | if ((snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER) & |
f091f3f0 | 172 | mask) != mask) { |
73bffd17 | 173 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, |
f091f3f0 LW |
174 | SGTL5000_VAG_POWERUP, 0); |
175 | msleep(400); | |
176 | } | |
9b34e6cc ZZ |
177 | break; |
178 | default: | |
179 | break; | |
180 | } | |
181 | ||
182 | return 0; | |
183 | } | |
184 | ||
185 | /* input sources for ADC */ | |
186 | static const char *adc_mux_text[] = { | |
187 | "MIC_IN", "LINE_IN" | |
188 | }; | |
189 | ||
c8ed6504 TI |
190 | static SOC_ENUM_SINGLE_DECL(adc_enum, |
191 | SGTL5000_CHIP_ANA_CTRL, 2, | |
192 | adc_mux_text); | |
9b34e6cc ZZ |
193 | |
194 | static const struct snd_kcontrol_new adc_mux = | |
195 | SOC_DAPM_ENUM("Capture Mux", adc_enum); | |
196 | ||
197 | /* input sources for DAC */ | |
198 | static const char *dac_mux_text[] = { | |
199 | "DAC", "LINE_IN" | |
200 | }; | |
201 | ||
c8ed6504 TI |
202 | static SOC_ENUM_SINGLE_DECL(dac_enum, |
203 | SGTL5000_CHIP_ANA_CTRL, 6, | |
204 | dac_mux_text); | |
9b34e6cc ZZ |
205 | |
206 | static const struct snd_kcontrol_new dac_mux = | |
207 | SOC_DAPM_ENUM("Headphone Mux", dac_enum); | |
208 | ||
209 | static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = { | |
210 | SND_SOC_DAPM_INPUT("LINE_IN"), | |
211 | SND_SOC_DAPM_INPUT("MIC_IN"), | |
212 | ||
213 | SND_SOC_DAPM_OUTPUT("HP_OUT"), | |
214 | SND_SOC_DAPM_OUTPUT("LINE_OUT"), | |
215 | ||
8fc8ec92 MB |
216 | SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0, |
217 | mic_bias_event, | |
218 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
9b34e6cc | 219 | |
f0cdcf3a ZZ |
220 | SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0), |
221 | SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0), | |
9b34e6cc ZZ |
222 | |
223 | SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux), | |
224 | SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux), | |
225 | ||
226 | /* aif for i2s input */ | |
227 | SND_SOC_DAPM_AIF_IN("AIFIN", "Playback", | |
228 | 0, SGTL5000_CHIP_DIG_POWER, | |
229 | 0, 0), | |
230 | ||
231 | /* aif for i2s output */ | |
232 | SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture", | |
233 | 0, SGTL5000_CHIP_DIG_POWER, | |
234 | 1, 0), | |
235 | ||
f0cdcf3a | 236 | SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0), |
9b34e6cc | 237 | SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0), |
dd4d2d6d MV |
238 | |
239 | SND_SOC_DAPM_PRE("VAG_POWER_PRE", power_vag_event), | |
240 | SND_SOC_DAPM_POST("VAG_POWER_POST", power_vag_event), | |
9b34e6cc ZZ |
241 | }; |
242 | ||
243 | /* routes for sgtl5000 */ | |
89989637 | 244 | static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = { |
9b34e6cc ZZ |
245 | {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */ |
246 | {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */ | |
247 | ||
248 | {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */ | |
249 | {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */ | |
250 | ||
251 | {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */ | |
252 | {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */ | |
253 | {"LO", NULL, "DAC"}, /* dac --> line_out */ | |
254 | ||
255 | {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */ | |
256 | {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */ | |
257 | ||
258 | {"LINE_OUT", NULL, "LO"}, | |
259 | {"HP_OUT", NULL, "HP"}, | |
260 | }; | |
261 | ||
262 | /* custom function to fetch info of PCM playback volume */ | |
263 | static int dac_info_volsw(struct snd_kcontrol *kcontrol, | |
264 | struct snd_ctl_elem_info *uinfo) | |
265 | { | |
266 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
267 | uinfo->count = 2; | |
268 | uinfo->value.integer.min = 0; | |
269 | uinfo->value.integer.max = 0xfc - 0x3c; | |
270 | return 0; | |
271 | } | |
272 | ||
273 | /* | |
274 | * custom function to get of PCM playback volume | |
275 | * | |
276 | * dac volume register | |
277 | * 15-------------8-7--------------0 | |
278 | * | R channel vol | L channel vol | | |
279 | * ------------------------------- | |
280 | * | |
281 | * PCM volume with 0.5017 dB steps from 0 to -90 dB | |
282 | * | |
283 | * register values map to dB | |
284 | * 0x3B and less = Reserved | |
285 | * 0x3C = 0 dB | |
286 | * 0x3D = -0.5 dB | |
287 | * 0xF0 = -90 dB | |
288 | * 0xFC and greater = Muted | |
289 | * | |
290 | * register value map to userspace value | |
291 | * | |
292 | * register value 0x3c(0dB) 0xf0(-90dB)0xfc | |
293 | * ------------------------------ | |
294 | * userspace value 0xc0 0 | |
295 | */ | |
296 | static int dac_get_volsw(struct snd_kcontrol *kcontrol, | |
297 | struct snd_ctl_elem_value *ucontrol) | |
298 | { | |
ea53bf77 | 299 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
9b34e6cc ZZ |
300 | int reg; |
301 | int l; | |
302 | int r; | |
303 | ||
304 | reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL); | |
305 | ||
306 | /* get left channel volume */ | |
307 | l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT; | |
308 | ||
309 | /* get right channel volume */ | |
310 | r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT; | |
311 | ||
312 | /* make sure value fall in (0x3c,0xfc) */ | |
313 | l = clamp(l, 0x3c, 0xfc); | |
314 | r = clamp(r, 0x3c, 0xfc); | |
315 | ||
316 | /* invert it and map to userspace value */ | |
317 | l = 0xfc - l; | |
318 | r = 0xfc - r; | |
319 | ||
320 | ucontrol->value.integer.value[0] = l; | |
321 | ucontrol->value.integer.value[1] = r; | |
322 | ||
323 | return 0; | |
324 | } | |
325 | ||
326 | /* | |
327 | * custom function to put of PCM playback volume | |
328 | * | |
329 | * dac volume register | |
330 | * 15-------------8-7--------------0 | |
331 | * | R channel vol | L channel vol | | |
332 | * ------------------------------- | |
333 | * | |
334 | * PCM volume with 0.5017 dB steps from 0 to -90 dB | |
335 | * | |
336 | * register values map to dB | |
337 | * 0x3B and less = Reserved | |
338 | * 0x3C = 0 dB | |
339 | * 0x3D = -0.5 dB | |
340 | * 0xF0 = -90 dB | |
341 | * 0xFC and greater = Muted | |
342 | * | |
343 | * userspace value map to register value | |
344 | * | |
345 | * userspace value 0xc0 0 | |
346 | * ------------------------------ | |
347 | * register value 0x3c(0dB) 0xf0(-90dB)0xfc | |
348 | */ | |
349 | static int dac_put_volsw(struct snd_kcontrol *kcontrol, | |
350 | struct snd_ctl_elem_value *ucontrol) | |
351 | { | |
ea53bf77 | 352 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
9b34e6cc ZZ |
353 | int reg; |
354 | int l; | |
355 | int r; | |
356 | ||
357 | l = ucontrol->value.integer.value[0]; | |
358 | r = ucontrol->value.integer.value[1]; | |
359 | ||
360 | /* make sure userspace volume fall in (0, 0xfc-0x3c) */ | |
361 | l = clamp(l, 0, 0xfc - 0x3c); | |
362 | r = clamp(r, 0, 0xfc - 0x3c); | |
363 | ||
364 | /* invert it, get the value can be set to register */ | |
365 | l = 0xfc - l; | |
366 | r = 0xfc - r; | |
367 | ||
368 | /* shift to get the register value */ | |
369 | reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT | | |
370 | r << SGTL5000_DAC_VOL_RIGHT_SHIFT; | |
371 | ||
372 | snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg); | |
373 | ||
374 | return 0; | |
375 | } | |
376 | ||
377 | static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0); | |
378 | ||
379 | /* tlv for mic gain, 0db 20db 30db 40db */ | |
53eb1ca3 | 380 | static const DECLARE_TLV_DB_RANGE(mic_gain_tlv, |
9b34e6cc | 381 | 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), |
53eb1ca3 LPC |
382 | 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0) |
383 | ); | |
9b34e6cc ZZ |
384 | |
385 | /* tlv for hp volume, -51.5db to 12.0db, step .5db */ | |
386 | static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0); | |
387 | ||
0593d461 KK |
388 | /* tlv for lineout volume, 31 steps of .5db each */ |
389 | static const DECLARE_TLV_DB_SCALE(lineout_volume, -1550, 50, 0); | |
390 | ||
9b34e6cc ZZ |
391 | static const struct snd_kcontrol_new sgtl5000_snd_controls[] = { |
392 | /* SOC_DOUBLE_S8_TLV with invert */ | |
393 | { | |
394 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
395 | .name = "PCM Playback Volume", | |
396 | .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | | |
397 | SNDRV_CTL_ELEM_ACCESS_READWRITE, | |
398 | .info = dac_info_volsw, | |
399 | .get = dac_get_volsw, | |
400 | .put = dac_put_volsw, | |
401 | }, | |
402 | ||
403 | SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0), | |
404 | SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)", | |
405 | SGTL5000_CHIP_ANA_ADC_CTRL, | |
65f2b226 | 406 | 8, 1, 0, capture_6db_attenuate), |
9b34e6cc ZZ |
407 | SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0), |
408 | ||
409 | SOC_DOUBLE_TLV("Headphone Playback Volume", | |
410 | SGTL5000_CHIP_ANA_HP_CTRL, | |
411 | 0, 8, | |
412 | 0x7f, 1, | |
413 | headphone_volume), | |
904a9873 RL |
414 | SOC_SINGLE("Headphone Playback Switch", SGTL5000_CHIP_ANA_CTRL, |
415 | 4, 1, 1), | |
9b34e6cc ZZ |
416 | SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL, |
417 | 5, 1, 0), | |
418 | ||
419 | SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL, | |
b50684da | 420 | 0, 3, 0, mic_gain_tlv), |
0593d461 KK |
421 | |
422 | SOC_DOUBLE_TLV("Lineout Playback Volume", | |
423 | SGTL5000_CHIP_LINE_OUT_VOL, | |
424 | SGTL5000_LINE_OUT_VOL_LEFT_SHIFT, | |
425 | SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT, | |
426 | 0x1f, 1, | |
427 | lineout_volume), | |
904a9873 | 428 | SOC_SINGLE("Lineout Playback Switch", SGTL5000_CHIP_ANA_CTRL, 8, 1, 1), |
9b34e6cc ZZ |
429 | }; |
430 | ||
431 | /* mute the codec used by alsa core */ | |
432 | static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute) | |
433 | { | |
434 | struct snd_soc_codec *codec = codec_dai->codec; | |
435 | u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT; | |
436 | ||
437 | snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL, | |
438 | adcdac_ctrl, mute ? adcdac_ctrl : 0); | |
439 | ||
440 | return 0; | |
441 | } | |
442 | ||
443 | /* set codec format */ | |
444 | static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) | |
445 | { | |
446 | struct snd_soc_codec *codec = codec_dai->codec; | |
447 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
448 | u16 i2sctl = 0; | |
449 | ||
450 | sgtl5000->master = 0; | |
451 | /* | |
452 | * i2s clock and frame master setting. | |
453 | * ONLY support: | |
454 | * - clock and frame slave, | |
455 | * - clock and frame master | |
456 | */ | |
457 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
458 | case SND_SOC_DAIFMT_CBS_CFS: | |
459 | break; | |
460 | case SND_SOC_DAIFMT_CBM_CFM: | |
461 | i2sctl |= SGTL5000_I2S_MASTER; | |
462 | sgtl5000->master = 1; | |
463 | break; | |
464 | default: | |
465 | return -EINVAL; | |
466 | } | |
467 | ||
468 | /* setting i2s data format */ | |
469 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
470 | case SND_SOC_DAIFMT_DSP_A: | |
9ee802ec | 471 | i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT; |
9b34e6cc ZZ |
472 | break; |
473 | case SND_SOC_DAIFMT_DSP_B: | |
9ee802ec | 474 | i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT; |
9b34e6cc ZZ |
475 | i2sctl |= SGTL5000_I2S_LRALIGN; |
476 | break; | |
477 | case SND_SOC_DAIFMT_I2S: | |
9ee802ec | 478 | i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT; |
9b34e6cc ZZ |
479 | break; |
480 | case SND_SOC_DAIFMT_RIGHT_J: | |
9ee802ec | 481 | i2sctl |= SGTL5000_I2S_MODE_RJ << SGTL5000_I2S_MODE_SHIFT; |
9b34e6cc ZZ |
482 | i2sctl |= SGTL5000_I2S_LRPOL; |
483 | break; | |
484 | case SND_SOC_DAIFMT_LEFT_J: | |
9ee802ec | 485 | i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT; |
9b34e6cc ZZ |
486 | i2sctl |= SGTL5000_I2S_LRALIGN; |
487 | break; | |
488 | default: | |
489 | return -EINVAL; | |
490 | } | |
491 | ||
492 | sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; | |
493 | ||
494 | /* Clock inversion */ | |
495 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
496 | case SND_SOC_DAIFMT_NB_NF: | |
497 | break; | |
498 | case SND_SOC_DAIFMT_IB_NF: | |
499 | i2sctl |= SGTL5000_I2S_SCLK_INV; | |
500 | break; | |
501 | default: | |
502 | return -EINVAL; | |
503 | } | |
504 | ||
505 | snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl); | |
506 | ||
507 | return 0; | |
508 | } | |
509 | ||
510 | /* set codec sysclk */ | |
511 | static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |
512 | int clk_id, unsigned int freq, int dir) | |
513 | { | |
514 | struct snd_soc_codec *codec = codec_dai->codec; | |
515 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
516 | ||
517 | switch (clk_id) { | |
518 | case SGTL5000_SYSCLK: | |
519 | sgtl5000->sysclk = freq; | |
520 | break; | |
521 | default: | |
522 | return -EINVAL; | |
523 | } | |
524 | ||
525 | return 0; | |
526 | } | |
527 | ||
528 | /* | |
529 | * set clock according to i2s frame clock, | |
7f6d75d7 FE |
530 | * sgtl5000 provides 2 clock sources: |
531 | * 1. sys_mclk: sample freq can only be configured to | |
9b34e6cc | 532 | * 1/256, 1/384, 1/512 of sys_mclk. |
7f6d75d7 | 533 | * 2. pll: can derive any audio clocks. |
9b34e6cc ZZ |
534 | * |
535 | * clock setting rules: | |
7f6d75d7 FE |
536 | * 1. in slave mode, only sys_mclk can be used |
537 | * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz | |
538 | * and above. | |
539 | * 3. usage of sys_mclk is preferred over pll to save power. | |
9b34e6cc ZZ |
540 | */ |
541 | static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate) | |
542 | { | |
543 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
544 | int clk_ctl = 0; | |
545 | int sys_fs; /* sample freq */ | |
546 | ||
547 | /* | |
548 | * sample freq should be divided by frame clock, | |
7f6d75d7 FE |
549 | * if frame clock is lower than 44.1 kHz, sample freq should be set to |
550 | * 32 kHz or 44.1 kHz. | |
9b34e6cc ZZ |
551 | */ |
552 | switch (frame_rate) { | |
553 | case 8000: | |
554 | case 16000: | |
555 | sys_fs = 32000; | |
556 | break; | |
557 | case 11025: | |
558 | case 22050: | |
559 | sys_fs = 44100; | |
560 | break; | |
561 | default: | |
562 | sys_fs = frame_rate; | |
563 | break; | |
564 | } | |
565 | ||
566 | /* set divided factor of frame clock */ | |
567 | switch (sys_fs / frame_rate) { | |
568 | case 4: | |
569 | clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT; | |
570 | break; | |
571 | case 2: | |
572 | clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT; | |
573 | break; | |
574 | case 1: | |
575 | clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT; | |
576 | break; | |
577 | default: | |
578 | return -EINVAL; | |
579 | } | |
580 | ||
581 | /* set the sys_fs according to frame rate */ | |
582 | switch (sys_fs) { | |
583 | case 32000: | |
584 | clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT; | |
585 | break; | |
586 | case 44100: | |
587 | clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT; | |
588 | break; | |
589 | case 48000: | |
590 | clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT; | |
591 | break; | |
592 | case 96000: | |
593 | clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT; | |
594 | break; | |
595 | default: | |
596 | dev_err(codec->dev, "frame rate %d not supported\n", | |
597 | frame_rate); | |
598 | return -EINVAL; | |
599 | } | |
600 | ||
601 | /* | |
602 | * calculate the divider of mclk/sample_freq, | |
7f6d75d7 FE |
603 | * factor of freq = 96 kHz can only be 256, since mclk is in the range |
604 | * of 8 MHz - 27 MHz | |
9b34e6cc | 605 | */ |
2a4cfd10 | 606 | switch (sgtl5000->sysclk / frame_rate) { |
9b34e6cc ZZ |
607 | case 256: |
608 | clk_ctl |= SGTL5000_MCLK_FREQ_256FS << | |
609 | SGTL5000_MCLK_FREQ_SHIFT; | |
610 | break; | |
611 | case 384: | |
612 | clk_ctl |= SGTL5000_MCLK_FREQ_384FS << | |
613 | SGTL5000_MCLK_FREQ_SHIFT; | |
614 | break; | |
615 | case 512: | |
616 | clk_ctl |= SGTL5000_MCLK_FREQ_512FS << | |
617 | SGTL5000_MCLK_FREQ_SHIFT; | |
618 | break; | |
619 | default: | |
7f6d75d7 | 620 | /* if mclk does not satisfy the divider, use pll */ |
9b34e6cc ZZ |
621 | if (sgtl5000->master) { |
622 | clk_ctl |= SGTL5000_MCLK_FREQ_PLL << | |
623 | SGTL5000_MCLK_FREQ_SHIFT; | |
624 | } else { | |
625 | dev_err(codec->dev, | |
626 | "PLL not supported in slave mode\n"); | |
fa558d01 FE |
627 | dev_err(codec->dev, "%d ratio is not supported. " |
628 | "SYS_MCLK needs to be 256, 384 or 512 * fs\n", | |
2a4cfd10 | 629 | sgtl5000->sysclk / frame_rate); |
9b34e6cc ZZ |
630 | return -EINVAL; |
631 | } | |
632 | } | |
633 | ||
634 | /* if using pll, please check manual 6.4.2 for detail */ | |
635 | if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) { | |
636 | u64 out, t; | |
637 | int div2; | |
638 | int pll_ctl; | |
639 | unsigned int in, int_div, frac_div; | |
640 | ||
641 | if (sgtl5000->sysclk > 17000000) { | |
642 | div2 = 1; | |
643 | in = sgtl5000->sysclk / 2; | |
644 | } else { | |
645 | div2 = 0; | |
646 | in = sgtl5000->sysclk; | |
647 | } | |
648 | if (sys_fs == 44100) | |
649 | out = 180633600; | |
650 | else | |
651 | out = 196608000; | |
652 | t = do_div(out, in); | |
653 | int_div = out; | |
654 | t *= 2048; | |
655 | do_div(t, in); | |
656 | frac_div = t; | |
657 | pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT | | |
658 | frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT; | |
659 | ||
660 | snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl); | |
661 | if (div2) | |
662 | snd_soc_update_bits(codec, | |
663 | SGTL5000_CHIP_CLK_TOP_CTRL, | |
664 | SGTL5000_INPUT_FREQ_DIV2, | |
665 | SGTL5000_INPUT_FREQ_DIV2); | |
666 | else | |
667 | snd_soc_update_bits(codec, | |
668 | SGTL5000_CHIP_CLK_TOP_CTRL, | |
669 | SGTL5000_INPUT_FREQ_DIV2, | |
670 | 0); | |
671 | ||
672 | /* power up pll */ | |
673 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, | |
674 | SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP, | |
675 | SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP); | |
e06e4c2d OS |
676 | |
677 | /* if using pll, clk_ctrl must be set after pll power up */ | |
678 | snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl); | |
9b34e6cc | 679 | } else { |
e06e4c2d OS |
680 | /* otherwise, clk_ctrl must be set before pll power down */ |
681 | snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl); | |
682 | ||
9b34e6cc ZZ |
683 | /* power down pll */ |
684 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, | |
685 | SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP, | |
686 | 0); | |
687 | } | |
688 | ||
9b34e6cc ZZ |
689 | return 0; |
690 | } | |
691 | ||
692 | /* | |
693 | * Set PCM DAI bit size and sample rate. | |
694 | * input: params_rate, params_fmt | |
695 | */ | |
696 | static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream, | |
697 | struct snd_pcm_hw_params *params, | |
698 | struct snd_soc_dai *dai) | |
699 | { | |
e6968a17 | 700 | struct snd_soc_codec *codec = dai->codec; |
9b34e6cc ZZ |
701 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); |
702 | int channels = params_channels(params); | |
703 | int i2s_ctl = 0; | |
704 | int stereo; | |
705 | int ret; | |
706 | ||
707 | /* sysclk should already set */ | |
708 | if (!sgtl5000->sysclk) { | |
709 | dev_err(codec->dev, "%s: set sysclk first!\n", __func__); | |
710 | return -EFAULT; | |
711 | } | |
712 | ||
713 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
714 | stereo = SGTL5000_DAC_STEREO; | |
715 | else | |
716 | stereo = SGTL5000_ADC_STEREO; | |
717 | ||
718 | /* set mono to save power */ | |
719 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo, | |
720 | channels == 1 ? 0 : stereo); | |
721 | ||
722 | /* set codec clock base on lrclk */ | |
723 | ret = sgtl5000_set_clock(codec, params_rate(params)); | |
724 | if (ret) | |
725 | return ret; | |
726 | ||
727 | /* set i2s data format */ | |
dacc2aef MB |
728 | switch (params_width(params)) { |
729 | case 16: | |
9b34e6cc ZZ |
730 | if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) |
731 | return -EINVAL; | |
732 | i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT; | |
733 | i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS << | |
734 | SGTL5000_I2S_SCLKFREQ_SHIFT; | |
735 | break; | |
dacc2aef | 736 | case 20: |
9b34e6cc ZZ |
737 | i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT; |
738 | i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << | |
739 | SGTL5000_I2S_SCLKFREQ_SHIFT; | |
740 | break; | |
dacc2aef | 741 | case 24: |
9b34e6cc ZZ |
742 | i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT; |
743 | i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << | |
744 | SGTL5000_I2S_SCLKFREQ_SHIFT; | |
745 | break; | |
dacc2aef | 746 | case 32: |
9b34e6cc ZZ |
747 | if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) |
748 | return -EINVAL; | |
749 | i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT; | |
750 | i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << | |
751 | SGTL5000_I2S_SCLKFREQ_SHIFT; | |
752 | break; | |
753 | default: | |
754 | return -EINVAL; | |
755 | } | |
756 | ||
33cb92cf AL |
757 | snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL, |
758 | SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK, | |
759 | i2s_ctl); | |
9b34e6cc ZZ |
760 | |
761 | return 0; | |
762 | } | |
763 | ||
9b34e6cc ZZ |
764 | /* |
765 | * set dac bias | |
766 | * common state changes: | |
767 | * startup: | |
768 | * off --> standby --> prepare --> on | |
769 | * standby --> prepare --> on | |
770 | * | |
771 | * stop: | |
772 | * on --> prepare --> standby | |
773 | */ | |
774 | static int sgtl5000_set_bias_level(struct snd_soc_codec *codec, | |
775 | enum snd_soc_bias_level level) | |
776 | { | |
9b34e6cc ZZ |
777 | switch (level) { |
778 | case SND_SOC_BIAS_ON: | |
779 | case SND_SOC_BIAS_PREPARE: | |
9b34e6cc | 780 | case SND_SOC_BIAS_STANDBY: |
8419caa7 EN |
781 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, |
782 | SGTL5000_REFTOP_POWERUP, | |
783 | SGTL5000_REFTOP_POWERUP); | |
9b34e6cc ZZ |
784 | break; |
785 | case SND_SOC_BIAS_OFF: | |
8419caa7 EN |
786 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, |
787 | SGTL5000_REFTOP_POWERUP, 0); | |
9b34e6cc ZZ |
788 | break; |
789 | } | |
790 | ||
9b34e6cc ZZ |
791 | return 0; |
792 | } | |
793 | ||
794 | #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ | |
795 | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
796 | SNDRV_PCM_FMTBIT_S24_LE |\ | |
797 | SNDRV_PCM_FMTBIT_S32_LE) | |
798 | ||
85e7652d | 799 | static const struct snd_soc_dai_ops sgtl5000_ops = { |
9b34e6cc ZZ |
800 | .hw_params = sgtl5000_pcm_hw_params, |
801 | .digital_mute = sgtl5000_digital_mute, | |
802 | .set_fmt = sgtl5000_set_dai_fmt, | |
803 | .set_sysclk = sgtl5000_set_dai_sysclk, | |
804 | }; | |
805 | ||
806 | static struct snd_soc_dai_driver sgtl5000_dai = { | |
807 | .name = "sgtl5000", | |
808 | .playback = { | |
809 | .stream_name = "Playback", | |
810 | .channels_min = 1, | |
811 | .channels_max = 2, | |
812 | /* | |
813 | * only support 8~48K + 96K, | |
814 | * TODO modify hw_param to support more | |
815 | */ | |
816 | .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000, | |
817 | .formats = SGTL5000_FORMATS, | |
818 | }, | |
819 | .capture = { | |
820 | .stream_name = "Capture", | |
821 | .channels_min = 1, | |
822 | .channels_max = 2, | |
823 | .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000, | |
824 | .formats = SGTL5000_FORMATS, | |
825 | }, | |
826 | .ops = &sgtl5000_ops, | |
827 | .symmetric_rates = 1, | |
828 | }; | |
829 | ||
e5d80e82 | 830 | static bool sgtl5000_volatile(struct device *dev, unsigned int reg) |
9b34e6cc ZZ |
831 | { |
832 | switch (reg) { | |
833 | case SGTL5000_CHIP_ID: | |
834 | case SGTL5000_CHIP_ADCDAC_CTRL: | |
835 | case SGTL5000_CHIP_ANA_STATUS: | |
e5d80e82 | 836 | return true; |
9b34e6cc ZZ |
837 | } |
838 | ||
e5d80e82 FE |
839 | return false; |
840 | } | |
841 | ||
842 | static bool sgtl5000_readable(struct device *dev, unsigned int reg) | |
843 | { | |
844 | switch (reg) { | |
845 | case SGTL5000_CHIP_ID: | |
846 | case SGTL5000_CHIP_DIG_POWER: | |
847 | case SGTL5000_CHIP_CLK_CTRL: | |
848 | case SGTL5000_CHIP_I2S_CTRL: | |
849 | case SGTL5000_CHIP_SSS_CTRL: | |
850 | case SGTL5000_CHIP_ADCDAC_CTRL: | |
851 | case SGTL5000_CHIP_DAC_VOL: | |
852 | case SGTL5000_CHIP_PAD_STRENGTH: | |
853 | case SGTL5000_CHIP_ANA_ADC_CTRL: | |
854 | case SGTL5000_CHIP_ANA_HP_CTRL: | |
855 | case SGTL5000_CHIP_ANA_CTRL: | |
856 | case SGTL5000_CHIP_LINREG_CTRL: | |
857 | case SGTL5000_CHIP_REF_CTRL: | |
858 | case SGTL5000_CHIP_MIC_CTRL: | |
859 | case SGTL5000_CHIP_LINE_OUT_CTRL: | |
860 | case SGTL5000_CHIP_LINE_OUT_VOL: | |
861 | case SGTL5000_CHIP_ANA_POWER: | |
862 | case SGTL5000_CHIP_PLL_CTRL: | |
863 | case SGTL5000_CHIP_CLK_TOP_CTRL: | |
864 | case SGTL5000_CHIP_ANA_STATUS: | |
865 | case SGTL5000_CHIP_SHORT_CTRL: | |
866 | case SGTL5000_CHIP_ANA_TEST2: | |
867 | case SGTL5000_DAP_CTRL: | |
868 | case SGTL5000_DAP_PEQ: | |
869 | case SGTL5000_DAP_BASS_ENHANCE: | |
870 | case SGTL5000_DAP_BASS_ENHANCE_CTRL: | |
871 | case SGTL5000_DAP_AUDIO_EQ: | |
872 | case SGTL5000_DAP_SURROUND: | |
873 | case SGTL5000_DAP_FLT_COEF_ACCESS: | |
874 | case SGTL5000_DAP_COEF_WR_B0_MSB: | |
875 | case SGTL5000_DAP_COEF_WR_B0_LSB: | |
876 | case SGTL5000_DAP_EQ_BASS_BAND0: | |
877 | case SGTL5000_DAP_EQ_BASS_BAND1: | |
878 | case SGTL5000_DAP_EQ_BASS_BAND2: | |
879 | case SGTL5000_DAP_EQ_BASS_BAND3: | |
880 | case SGTL5000_DAP_EQ_BASS_BAND4: | |
881 | case SGTL5000_DAP_MAIN_CHAN: | |
882 | case SGTL5000_DAP_MIX_CHAN: | |
883 | case SGTL5000_DAP_AVC_CTRL: | |
884 | case SGTL5000_DAP_AVC_THRESHOLD: | |
885 | case SGTL5000_DAP_AVC_ATTACK: | |
886 | case SGTL5000_DAP_AVC_DECAY: | |
887 | case SGTL5000_DAP_COEF_WR_B1_MSB: | |
888 | case SGTL5000_DAP_COEF_WR_B1_LSB: | |
889 | case SGTL5000_DAP_COEF_WR_B2_MSB: | |
890 | case SGTL5000_DAP_COEF_WR_B2_LSB: | |
891 | case SGTL5000_DAP_COEF_WR_A1_MSB: | |
892 | case SGTL5000_DAP_COEF_WR_A1_LSB: | |
893 | case SGTL5000_DAP_COEF_WR_A2_MSB: | |
894 | case SGTL5000_DAP_COEF_WR_A2_LSB: | |
895 | return true; | |
896 | ||
897 | default: | |
898 | return false; | |
899 | } | |
9b34e6cc ZZ |
900 | } |
901 | ||
1f39d939 AS |
902 | /* |
903 | * This precalculated table contains all (vag_val * 100 / lo_calcntrl) results | |
904 | * to select an appropriate lo_vol_* in SGTL5000_CHIP_LINE_OUT_VOL | |
905 | * The calculatation was done for all possible register values which | |
906 | * is the array index and the following formula: 10^((idx−15)/40) * 100 | |
907 | */ | |
908 | static const u8 vol_quot_table[] = { | |
909 | 42, 45, 47, 50, 53, 56, 60, 63, | |
910 | 67, 71, 75, 79, 84, 89, 94, 100, | |
911 | 106, 112, 119, 126, 133, 141, 150, 158, | |
912 | 168, 178, 188, 200, 211, 224, 237, 251 | |
913 | }; | |
914 | ||
9b34e6cc ZZ |
915 | /* |
916 | * sgtl5000 has 3 internal power supplies: | |
917 | * 1. VAG, normally set to vdda/2 | |
7f6d75d7 | 918 | * 2. charge pump, set to different value |
9b34e6cc ZZ |
919 | * according to voltage of vdda and vddio |
920 | * 3. line out VAG, normally set to vddio/2 | |
921 | * | |
922 | * and should be set according to: | |
923 | * 1. vddd provided by external or not | |
924 | * 2. vdda and vddio voltage value. > 3.1v or not | |
9b34e6cc ZZ |
925 | */ |
926 | static int sgtl5000_set_power_regs(struct snd_soc_codec *codec) | |
927 | { | |
928 | int vddd; | |
929 | int vdda; | |
930 | int vddio; | |
931 | u16 ana_pwr; | |
932 | u16 lreg_ctrl; | |
933 | int vag; | |
d2b7c2aa | 934 | int lo_vag; |
1f39d939 AS |
935 | int vol_quot; |
936 | int lo_vol; | |
937 | size_t i; | |
9b34e6cc ZZ |
938 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); |
939 | ||
940 | vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer); | |
941 | vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer); | |
940adb28 EN |
942 | vddd = (sgtl5000->num_supplies > VDDD) |
943 | ? regulator_get_voltage(sgtl5000->supplies[VDDD].consumer) | |
944 | : LDO_VOLTAGE; | |
9b34e6cc ZZ |
945 | |
946 | vdda = vdda / 1000; | |
947 | vddio = vddio / 1000; | |
948 | vddd = vddd / 1000; | |
949 | ||
950 | if (vdda <= 0 || vddio <= 0 || vddd < 0) { | |
951 | dev_err(codec->dev, "regulator voltage not set correctly\n"); | |
952 | ||
953 | return -EINVAL; | |
954 | } | |
955 | ||
956 | /* according to datasheet, maximum voltage of supplies */ | |
957 | if (vdda > 3600 || vddio > 3600 || vddd > 1980) { | |
958 | dev_err(codec->dev, | |
cf1ee98d | 959 | "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n", |
9b34e6cc ZZ |
960 | vdda, vddio, vddd); |
961 | ||
962 | return -EINVAL; | |
963 | } | |
964 | ||
965 | /* reset value */ | |
966 | ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER); | |
967 | ana_pwr |= SGTL5000_DAC_STEREO | | |
968 | SGTL5000_ADC_STEREO | | |
969 | SGTL5000_REFTOP_POWERUP; | |
970 | lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL); | |
971 | ||
972 | if (vddio < 3100 && vdda < 3100) { | |
973 | /* enable internal oscillator used for charge pump */ | |
974 | snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL, | |
975 | SGTL5000_INT_OSC_EN, | |
976 | SGTL5000_INT_OSC_EN); | |
977 | /* Enable VDDC charge pump */ | |
978 | ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP; | |
979 | } else if (vddio >= 3100 && vdda >= 3100) { | |
c7d910b8 | 980 | ana_pwr &= ~SGTL5000_VDDC_CHRGPMP_POWERUP; |
9b34e6cc ZZ |
981 | /* VDDC use VDDIO rail */ |
982 | lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD; | |
983 | lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO << | |
984 | SGTL5000_VDDC_MAN_ASSN_SHIFT; | |
985 | } | |
986 | ||
987 | snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl); | |
988 | ||
989 | snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr); | |
990 | ||
9b34e6cc ZZ |
991 | /* |
992 | * set ADC/DAC VAG to vdda / 2, | |
993 | * should stay in range (0.8v, 1.575v) | |
994 | */ | |
995 | vag = vdda / 2; | |
996 | if (vag <= SGTL5000_ANA_GND_BASE) | |
997 | vag = 0; | |
998 | else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP * | |
999 | (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT)) | |
1000 | vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT; | |
1001 | else | |
1002 | vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP; | |
1003 | ||
1004 | snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL, | |
33cb92cf | 1005 | SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT); |
9b34e6cc ZZ |
1006 | |
1007 | /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */ | |
d2b7c2aa AS |
1008 | lo_vag = vddio / 2; |
1009 | if (lo_vag <= SGTL5000_LINE_OUT_GND_BASE) | |
1010 | lo_vag = 0; | |
1011 | else if (lo_vag >= SGTL5000_LINE_OUT_GND_BASE + | |
9b34e6cc | 1012 | SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX) |
d2b7c2aa | 1013 | lo_vag = SGTL5000_LINE_OUT_GND_MAX; |
9b34e6cc | 1014 | else |
d2b7c2aa | 1015 | lo_vag = (lo_vag - SGTL5000_LINE_OUT_GND_BASE) / |
9b34e6cc ZZ |
1016 | SGTL5000_LINE_OUT_GND_STP; |
1017 | ||
1018 | snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL, | |
33cb92cf AL |
1019 | SGTL5000_LINE_OUT_CURRENT_MASK | |
1020 | SGTL5000_LINE_OUT_GND_MASK, | |
d2b7c2aa | 1021 | lo_vag << SGTL5000_LINE_OUT_GND_SHIFT | |
9b34e6cc ZZ |
1022 | SGTL5000_LINE_OUT_CURRENT_360u << |
1023 | SGTL5000_LINE_OUT_CURRENT_SHIFT); | |
1024 | ||
1f39d939 AS |
1025 | /* |
1026 | * Set lineout output level in range (0..31) | |
1027 | * the same value is used for right and left channel | |
1028 | * | |
1029 | * Searching for a suitable index solving this formula: | |
1030 | * idx = 40 * log10(vag_val / lo_cagcntrl) + 15 | |
1031 | */ | |
1032 | vol_quot = (vag * 100) / lo_vag; | |
1033 | lo_vol = 0; | |
1034 | for (i = 0; i < ARRAY_SIZE(vol_quot_table); i++) { | |
1035 | if (vol_quot >= vol_quot_table[i]) | |
1036 | lo_vol = i; | |
1037 | else | |
1038 | break; | |
1039 | } | |
1040 | ||
1041 | snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_VOL, | |
1042 | SGTL5000_LINE_OUT_VOL_RIGHT_MASK | | |
1043 | SGTL5000_LINE_OUT_VOL_LEFT_MASK, | |
1044 | lo_vol << SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT | | |
1045 | lo_vol << SGTL5000_LINE_OUT_VOL_LEFT_SHIFT); | |
1046 | ||
9b34e6cc ZZ |
1047 | return 0; |
1048 | } | |
1049 | ||
940adb28 | 1050 | static int sgtl5000_enable_regulators(struct i2c_client *client) |
9b34e6cc | 1051 | { |
9b34e6cc | 1052 | int ret; |
9b34e6cc ZZ |
1053 | int i; |
1054 | int external_vddd = 0; | |
11db0da8 | 1055 | struct regulator *vddd; |
940adb28 | 1056 | struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client); |
9b34e6cc ZZ |
1057 | |
1058 | for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++) | |
1059 | sgtl5000->supplies[i].supply = supply_names[i]; | |
1060 | ||
940adb28 EN |
1061 | vddd = regulator_get_optional(&client->dev, "VDDD"); |
1062 | if (IS_ERR(vddd)) { | |
1063 | /* See if it's just not registered yet */ | |
1064 | if (PTR_ERR(vddd) == -EPROBE_DEFER) | |
1065 | return -EPROBE_DEFER; | |
1066 | } else { | |
1067 | external_vddd = 1; | |
1068 | regulator_put(vddd); | |
9b34e6cc ZZ |
1069 | } |
1070 | ||
940adb28 EN |
1071 | sgtl5000->num_supplies = ARRAY_SIZE(sgtl5000->supplies) |
1072 | - 1 + external_vddd; | |
1073 | ret = regulator_bulk_get(&client->dev, sgtl5000->num_supplies, | |
11db0da8 SG |
1074 | sgtl5000->supplies); |
1075 | if (ret) | |
940adb28 | 1076 | return ret; |
9b34e6cc | 1077 | |
940adb28 EN |
1078 | ret = regulator_bulk_enable(sgtl5000->num_supplies, |
1079 | sgtl5000->supplies); | |
1080 | if (!ret) | |
1081 | usleep_range(10, 20); | |
1082 | else | |
1083 | regulator_bulk_free(sgtl5000->num_supplies, | |
1084 | sgtl5000->supplies); | |
9b34e6cc | 1085 | |
9b34e6cc | 1086 | return ret; |
9b34e6cc ZZ |
1087 | } |
1088 | ||
1089 | static int sgtl5000_probe(struct snd_soc_codec *codec) | |
1090 | { | |
1091 | int ret; | |
1092 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
1093 | ||
9b34e6cc ZZ |
1094 | /* power up sgtl5000 */ |
1095 | ret = sgtl5000_set_power_regs(codec); | |
1096 | if (ret) | |
1097 | goto err; | |
1098 | ||
1099 | /* enable small pop, introduce 400ms delay in turning off */ | |
1100 | snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL, | |
c251ea7b | 1101 | SGTL5000_SMALL_POP, 1); |
9b34e6cc ZZ |
1102 | |
1103 | /* disable short cut detector */ | |
1104 | snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0); | |
1105 | ||
1106 | /* | |
1107 | * set i2s as default input of sound switch | |
1108 | * TODO: add sound switch to control and dapm widge. | |
1109 | */ | |
1110 | snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL, | |
1111 | SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT); | |
1112 | snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER, | |
1113 | SGTL5000_ADC_EN | SGTL5000_DAC_EN); | |
1114 | ||
1115 | /* enable dac volume ramp by default */ | |
1116 | snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL, | |
1117 | SGTL5000_DAC_VOL_RAMP_EN | | |
1118 | SGTL5000_DAC_MUTE_RIGHT | | |
1119 | SGTL5000_DAC_MUTE_LEFT); | |
1120 | ||
1121 | snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f); | |
1122 | ||
1123 | snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL, | |
1124 | SGTL5000_HP_ZCD_EN | | |
1125 | SGTL5000_ADC_ZCD_EN); | |
1126 | ||
bd0593f5 JMH |
1127 | snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL, |
1128 | SGTL5000_BIAS_R_MASK, | |
1129 | sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT); | |
9b34e6cc | 1130 | |
87357797 | 1131 | snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL, |
e256da84 GR |
1132 | SGTL5000_BIAS_VOLT_MASK, |
1133 | sgtl5000->micbias_voltage << SGTL5000_BIAS_VOLT_SHIFT); | |
9b34e6cc ZZ |
1134 | /* |
1135 | * disable DAP | |
1136 | * TODO: | |
1137 | * Enable DAP in kcontrol and dapm. | |
1138 | */ | |
1139 | snd_soc_write(codec, SGTL5000_DAP_CTRL, 0); | |
1140 | ||
9b34e6cc ZZ |
1141 | return 0; |
1142 | ||
1143 | err: | |
9b34e6cc ZZ |
1144 | return ret; |
1145 | } | |
1146 | ||
1147 | static int sgtl5000_remove(struct snd_soc_codec *codec) | |
1148 | { | |
9b34e6cc ZZ |
1149 | return 0; |
1150 | } | |
1151 | ||
61a142b7 | 1152 | static struct snd_soc_codec_driver sgtl5000_driver = { |
9b34e6cc ZZ |
1153 | .probe = sgtl5000_probe, |
1154 | .remove = sgtl5000_remove, | |
9b34e6cc | 1155 | .set_bias_level = sgtl5000_set_bias_level, |
e649057a | 1156 | .suspend_bias_off = true, |
a324dbe5 KM |
1157 | .component_driver = { |
1158 | .controls = sgtl5000_snd_controls, | |
1159 | .num_controls = ARRAY_SIZE(sgtl5000_snd_controls), | |
1160 | .dapm_widgets = sgtl5000_dapm_widgets, | |
1161 | .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets), | |
1162 | .dapm_routes = sgtl5000_dapm_routes, | |
1163 | .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes), | |
1164 | }, | |
9b34e6cc ZZ |
1165 | }; |
1166 | ||
e5d80e82 FE |
1167 | static const struct regmap_config sgtl5000_regmap = { |
1168 | .reg_bits = 16, | |
1169 | .val_bits = 16, | |
cb23e852 | 1170 | .reg_stride = 2, |
e5d80e82 FE |
1171 | |
1172 | .max_register = SGTL5000_MAX_REG_OFFSET, | |
1173 | .volatile_reg = sgtl5000_volatile, | |
1174 | .readable_reg = sgtl5000_readable, | |
1175 | ||
1176 | .cache_type = REGCACHE_RBTREE, | |
1177 | .reg_defaults = sgtl5000_reg_defaults, | |
1178 | .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults), | |
1179 | }; | |
1180 | ||
af8ee112 FE |
1181 | /* |
1182 | * Write all the default values from sgtl5000_reg_defaults[] array into the | |
1183 | * sgtl5000 registers, to make sure we always start with the sane registers | |
1184 | * values as stated in the datasheet. | |
1185 | * | |
1186 | * Since sgtl5000 does not have a reset line, nor a reset command in software, | |
1187 | * we follow this approach to guarantee we always start from the default values | |
1188 | * and avoid problems like, not being able to probe after an audio playback | |
1189 | * followed by a system reset or a 'reboot' command in Linux | |
1190 | */ | |
f219b169 | 1191 | static void sgtl5000_fill_defaults(struct i2c_client *client) |
af8ee112 | 1192 | { |
f219b169 | 1193 | struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client); |
af8ee112 FE |
1194 | int i, ret, val, index; |
1195 | ||
1196 | for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) { | |
1197 | val = sgtl5000_reg_defaults[i].def; | |
1198 | index = sgtl5000_reg_defaults[i].reg; | |
1199 | ret = regmap_write(sgtl5000->regmap, index, val); | |
1200 | if (ret) | |
f219b169 EN |
1201 | dev_err(&client->dev, |
1202 | "%s: error %d setting reg 0x%02x to 0x%04x\n", | |
1203 | __func__, ret, index, val); | |
af8ee112 | 1204 | } |
af8ee112 FE |
1205 | } |
1206 | ||
7a79e94e BP |
1207 | static int sgtl5000_i2c_probe(struct i2c_client *client, |
1208 | const struct i2c_device_id *id) | |
9b34e6cc ZZ |
1209 | { |
1210 | struct sgtl5000_priv *sgtl5000; | |
b871f1ad | 1211 | int ret, reg, rev; |
bd0593f5 JMH |
1212 | struct device_node *np = client->dev.of_node; |
1213 | u32 value; | |
3d632cc8 | 1214 | u16 ana_pwr; |
9b34e6cc | 1215 | |
3f7256fe | 1216 | sgtl5000 = devm_kzalloc(&client->dev, sizeof(*sgtl5000), GFP_KERNEL); |
9b34e6cc ZZ |
1217 | if (!sgtl5000) |
1218 | return -ENOMEM; | |
1219 | ||
940adb28 EN |
1220 | i2c_set_clientdata(client, sgtl5000); |
1221 | ||
1222 | ret = sgtl5000_enable_regulators(client); | |
1223 | if (ret) | |
1224 | return ret; | |
1225 | ||
e5d80e82 FE |
1226 | sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap); |
1227 | if (IS_ERR(sgtl5000->regmap)) { | |
1228 | ret = PTR_ERR(sgtl5000->regmap); | |
1229 | dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret); | |
940adb28 | 1230 | goto disable_regs; |
e5d80e82 FE |
1231 | } |
1232 | ||
9e13f345 FE |
1233 | sgtl5000->mclk = devm_clk_get(&client->dev, NULL); |
1234 | if (IS_ERR(sgtl5000->mclk)) { | |
1235 | ret = PTR_ERR(sgtl5000->mclk); | |
1236 | dev_err(&client->dev, "Failed to get mclock: %d\n", ret); | |
46a5905e SG |
1237 | /* Defer the probe to see if the clk will be provided later */ |
1238 | if (ret == -ENOENT) | |
940adb28 EN |
1239 | ret = -EPROBE_DEFER; |
1240 | goto disable_regs; | |
9e13f345 FE |
1241 | } |
1242 | ||
1243 | ret = clk_prepare_enable(sgtl5000->mclk); | |
940adb28 EN |
1244 | if (ret) { |
1245 | dev_err(&client->dev, "Error enabling clock %d\n", ret); | |
1246 | goto disable_regs; | |
1247 | } | |
9e13f345 | 1248 | |
58cc9c9a EN |
1249 | /* Need 8 clocks before I2C accesses */ |
1250 | udelay(1); | |
1251 | ||
b871f1ad FE |
1252 | /* read chip information */ |
1253 | ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, ®); | |
940adb28 EN |
1254 | if (ret) { |
1255 | dev_err(&client->dev, "Error reading chip id %d\n", ret); | |
9e13f345 | 1256 | goto disable_clk; |
940adb28 | 1257 | } |
b871f1ad FE |
1258 | |
1259 | if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) != | |
1260 | SGTL5000_PARTID_PART_ID) { | |
1261 | dev_err(&client->dev, | |
1262 | "Device with ID register %x is not a sgtl5000\n", reg); | |
9e13f345 FE |
1263 | ret = -ENODEV; |
1264 | goto disable_clk; | |
b871f1ad FE |
1265 | } |
1266 | ||
1267 | rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT; | |
1268 | dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev); | |
252e91ff | 1269 | sgtl5000->revision = rev; |
b871f1ad | 1270 | |
08dea16e EN |
1271 | /* reconfigure the clocks in case we're using the PLL */ |
1272 | ret = regmap_write(sgtl5000->regmap, | |
1273 | SGTL5000_CHIP_CLK_CTRL, | |
1274 | SGTL5000_CHIP_CLK_CTRL_DEFAULT); | |
1275 | if (ret) | |
1276 | dev_err(&client->dev, | |
1277 | "Error %d initializing CHIP_CLK_CTRL\n", ret); | |
1278 | ||
940adb28 | 1279 | /* Follow section 2.2.1.1 of AN3663 */ |
3d632cc8 | 1280 | ana_pwr = SGTL5000_ANA_POWER_DEFAULT; |
940adb28 EN |
1281 | if (sgtl5000->num_supplies <= VDDD) { |
1282 | /* internal VDDD at 1.2V */ | |
3d632cc8 EN |
1283 | ret = regmap_update_bits(sgtl5000->regmap, |
1284 | SGTL5000_CHIP_LINREG_CTRL, | |
1285 | SGTL5000_LINREG_VDDD_MASK, | |
1286 | LINREG_VDDD); | |
1287 | if (ret) | |
1288 | dev_err(&client->dev, | |
1289 | "Error %d setting LINREG_VDDD\n", ret); | |
1290 | ||
1291 | ana_pwr |= SGTL5000_LINEREG_D_POWERUP; | |
1292 | dev_info(&client->dev, | |
1293 | "Using internal LDO instead of VDDD: check ER1\n"); | |
940adb28 EN |
1294 | } else { |
1295 | /* using external LDO for VDDD | |
1296 | * Clear startup powerup and simple powerup | |
1297 | * bits to save power | |
1298 | */ | |
3d632cc8 EN |
1299 | ana_pwr &= ~(SGTL5000_STARTUP_POWERUP |
1300 | | SGTL5000_LINREG_SIMPLE_POWERUP); | |
940adb28 EN |
1301 | dev_dbg(&client->dev, "Using external VDDD\n"); |
1302 | } | |
3d632cc8 EN |
1303 | ret = regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, ana_pwr); |
1304 | if (ret) | |
1305 | dev_err(&client->dev, | |
1306 | "Error %d setting CHIP_ANA_POWER to %04x\n", | |
1307 | ret, ana_pwr); | |
940adb28 | 1308 | |
bd0593f5 JMH |
1309 | if (np) { |
1310 | if (!of_property_read_u32(np, | |
1311 | "micbias-resistor-k-ohms", &value)) { | |
1312 | switch (value) { | |
1313 | case SGTL5000_MICBIAS_OFF: | |
1314 | sgtl5000->micbias_resistor = 0; | |
1315 | break; | |
1316 | case SGTL5000_MICBIAS_2K: | |
1317 | sgtl5000->micbias_resistor = 1; | |
1318 | break; | |
1319 | case SGTL5000_MICBIAS_4K: | |
1320 | sgtl5000->micbias_resistor = 2; | |
1321 | break; | |
1322 | case SGTL5000_MICBIAS_8K: | |
1323 | sgtl5000->micbias_resistor = 3; | |
1324 | break; | |
1325 | default: | |
1326 | sgtl5000->micbias_resistor = 2; | |
1327 | dev_err(&client->dev, | |
1328 | "Unsuitable MicBias resistor\n"); | |
1329 | } | |
1330 | } else { | |
1331 | /* default is 4Kohms */ | |
1332 | sgtl5000->micbias_resistor = 2; | |
1333 | } | |
87357797 JMH |
1334 | if (!of_property_read_u32(np, |
1335 | "micbias-voltage-m-volts", &value)) { | |
1336 | /* 1250mV => 0 */ | |
1337 | /* steps of 250mV */ | |
1338 | if ((value >= 1250) && (value <= 3000)) | |
1339 | sgtl5000->micbias_voltage = (value / 250) - 5; | |
1340 | else { | |
1341 | sgtl5000->micbias_voltage = 0; | |
bd0593f5 | 1342 | dev_err(&client->dev, |
fb97d75b | 1343 | "Unsuitable MicBias voltage\n"); |
bd0593f5 JMH |
1344 | } |
1345 | } else { | |
87357797 | 1346 | sgtl5000->micbias_voltage = 0; |
bd0593f5 JMH |
1347 | } |
1348 | } | |
1349 | ||
af8ee112 | 1350 | /* Ensure sgtl5000 will start with sane register values */ |
f219b169 | 1351 | sgtl5000_fill_defaults(client); |
af8ee112 | 1352 | |
9b34e6cc ZZ |
1353 | ret = snd_soc_register_codec(&client->dev, |
1354 | &sgtl5000_driver, &sgtl5000_dai, 1); | |
9e13f345 FE |
1355 | if (ret) |
1356 | goto disable_clk; | |
1357 | ||
1358 | return 0; | |
1359 | ||
1360 | disable_clk: | |
1361 | clk_disable_unprepare(sgtl5000->mclk); | |
940adb28 EN |
1362 | |
1363 | disable_regs: | |
1364 | regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies); | |
1365 | regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies); | |
1366 | ||
512fa7c4 | 1367 | return ret; |
9b34e6cc ZZ |
1368 | } |
1369 | ||
7a79e94e | 1370 | static int sgtl5000_i2c_remove(struct i2c_client *client) |
9b34e6cc | 1371 | { |
7c647af4 | 1372 | struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client); |
9b34e6cc | 1373 | |
9e13f345 FE |
1374 | snd_soc_unregister_codec(&client->dev); |
1375 | clk_disable_unprepare(sgtl5000->mclk); | |
940adb28 EN |
1376 | regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies); |
1377 | regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies); | |
1378 | ||
9b34e6cc ZZ |
1379 | return 0; |
1380 | } | |
1381 | ||
1382 | static const struct i2c_device_id sgtl5000_id[] = { | |
1383 | {"sgtl5000", 0}, | |
1384 | {}, | |
1385 | }; | |
1386 | ||
1387 | MODULE_DEVICE_TABLE(i2c, sgtl5000_id); | |
1388 | ||
58e49424 SG |
1389 | static const struct of_device_id sgtl5000_dt_ids[] = { |
1390 | { .compatible = "fsl,sgtl5000", }, | |
1391 | { /* sentinel */ } | |
1392 | }; | |
4c54c6de | 1393 | MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids); |
58e49424 | 1394 | |
9b34e6cc ZZ |
1395 | static struct i2c_driver sgtl5000_i2c_driver = { |
1396 | .driver = { | |
1397 | .name = "sgtl5000", | |
58e49424 | 1398 | .of_match_table = sgtl5000_dt_ids, |
9b34e6cc ZZ |
1399 | }, |
1400 | .probe = sgtl5000_i2c_probe, | |
7a79e94e | 1401 | .remove = sgtl5000_i2c_remove, |
9b34e6cc ZZ |
1402 | .id_table = sgtl5000_id, |
1403 | }; | |
1404 | ||
67d45090 | 1405 | module_i2c_driver(sgtl5000_i2c_driver); |
9b34e6cc ZZ |
1406 | |
1407 | MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver"); | |
f7cb8a4b | 1408 | MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>"); |
9b34e6cc | 1409 | MODULE_LICENSE("GPL"); |