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Merge remote-tracking branch 'regulator/for-next'
[deliverable/linux.git] / sound / soc / codecs / tlv320aic3x.c
CommitLineData
44d0a879
VB		 1/*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
d6b52039 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
44d0a879
VB		 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
6184f105 15 * codecs aic31, aic32, aic33, aic3007.
44d0a879
VB		 16 *
17 * It supports full aic33 codec functionality.
6184f105
RC		 18 * The compatibility with aic32, aic31 and aic3007 is as follows:
19 * aic32/aic3007 | aic31
44d0a879
VB		 20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
a5302181 32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
44d0a879
VB		 33 */
34
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/pm.h>
40#include <linux/i2c.h>
5193d62f 41#include <linux/gpio.h>
07779fdd 42#include <linux/regulator/consumer.h>
b3b70786 43#include <linux/of.h>
c24fdc88 44#include <linux/of_gpio.h>
5a0e3ad6 45#include <linux/slab.h>
44d0a879
VB		 46#include <sound/core.h>
47#include <sound/pcm.h>
48#include <sound/pcm_params.h>
49#include <sound/soc.h>
44d0a879 50#include <sound/initval.h>
7565fc38 51#include <sound/tlv.h>
5193d62f 52#include <sound/tlv320aic3x.h>
44d0a879
VB		 53
54#include "tlv320aic3x.h"
55
07779fdd
JN		 56#define AIC3X_NUM_SUPPLIES 4
57static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
58 "IOVDD", /* I/O Voltage */
59 "DVDD", /* Digital Core Voltage */
60 "AVDD", /* Analog DAC Voltage */
61 "DRVDD", /* ADC Analog and Output Driver Voltage */
62};
44d0a879 63
414c73ab
JN		 64static LIST_HEAD(reset_list);
65
5a895f8a
JN		 66struct aic3x_priv;
67
68struct aic3x_disable_nb {
69 struct notifier_block nb;
70 struct aic3x_priv *aic3x;
71};
72
44d0a879
VB		 73/* codec private data */
74struct aic3x_priv {
5a895f8a 75 struct snd_soc_codec *codec;
2a6fedec 76 struct regmap *regmap;
07779fdd 77 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
5a895f8a 78 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
f0fba2ad 79 struct aic3x_setup_data *setup;
44d0a879 80 unsigned int sysclk;
36849409
PU		 81 unsigned int dai_fmt;
82 unsigned int tdm_delay;
3e8f5263 83 unsigned int slot_width;
414c73ab 84 struct list_head list;
44d0a879 85 int master;
5193d62f 86 int gpio_reset;
6c1a7d40 87 int power;
6184f105
RC		 88#define AIC3X_MODEL_3X 0
89#define AIC3X_MODEL_33 1
90#define AIC3X_MODEL_3007 2
9503112d 91#define AIC3X_MODEL_3104 3
6184f105 92 u16 model;
e2e8bfdf
HG		 93
94 /* Selects the micbias voltage */
95 enum aic3x_micbias_voltage micbias_vg;
44d0a879
VB		 96};
97
2a6fedec
MB		 98static const struct reg_default aic3x_reg[] = {
99 { 0, 0x00 }, { 1, 0x00 }, { 2, 0x00 }, { 3, 0x10 },
100 { 4, 0x04 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 },
101 { 8, 0x00 }, { 9, 0x00 }, { 10, 0x00 }, { 11, 0x01 },
102 { 12, 0x00 }, { 13, 0x00 }, { 14, 0x00 }, { 15, 0x80 },
103 { 16, 0x80 }, { 17, 0xff }, { 18, 0xff }, { 19, 0x78 },
104 { 20, 0x78 }, { 21, 0x78 }, { 22, 0x78 }, { 23, 0x78 },
105 { 24, 0x78 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0xfe },
106 { 28, 0x00 }, { 29, 0x00 }, { 30, 0xfe }, { 31, 0x00 },
107 { 32, 0x18 }, { 33, 0x18 }, { 34, 0x00 }, { 35, 0x00 },
108 { 36, 0x00 }, { 37, 0x00 }, { 38, 0x00 }, { 39, 0x00 },
109 { 40, 0x00 }, { 41, 0x00 }, { 42, 0x00 }, { 43, 0x80 },
110 { 44, 0x80 }, { 45, 0x00 }, { 46, 0x00 }, { 47, 0x00 },
111 { 48, 0x00 }, { 49, 0x00 }, { 50, 0x00 }, { 51, 0x04 },
112 { 52, 0x00 }, { 53, 0x00 }, { 54, 0x00 }, { 55, 0x00 },
113 { 56, 0x00 }, { 57, 0x00 }, { 58, 0x04 }, { 59, 0x00 },
114 { 60, 0x00 }, { 61, 0x00 }, { 62, 0x00 }, { 63, 0x00 },
115 { 64, 0x00 }, { 65, 0x04 }, { 66, 0x00 }, { 67, 0x00 },
116 { 68, 0x00 }, { 69, 0x00 }, { 70, 0x00 }, { 71, 0x00 },
117 { 72, 0x04 }, { 73, 0x00 }, { 74, 0x00 }, { 75, 0x00 },
118 { 76, 0x00 }, { 77, 0x00 }, { 78, 0x00 }, { 79, 0x00 },
119 { 80, 0x00 }, { 81, 0x00 }, { 82, 0x00 }, { 83, 0x00 },
120 { 84, 0x00 }, { 85, 0x00 }, { 86, 0x00 }, { 87, 0x00 },
121 { 88, 0x00 }, { 89, 0x00 }, { 90, 0x00 }, { 91, 0x00 },
122 { 92, 0x00 }, { 93, 0x00 }, { 94, 0x00 }, { 95, 0x00 },
123 { 96, 0x00 }, { 97, 0x00 }, { 98, 0x00 }, { 99, 0x00 },
124 { 100, 0x00 }, { 101, 0x00 }, { 102, 0x02 }, { 103, 0x00 },
125 { 104, 0x00 }, { 105, 0x00 }, { 106, 0x00 }, { 107, 0x00 },
126 { 108, 0x00 }, { 109, 0x00 },
127};
128
129static const struct regmap_config aic3x_regmap = {
130 .reg_bits = 8,
131 .val_bits = 8,
132
133 .max_register = DAC_ICC_ADJ,
134 .reg_defaults = aic3x_reg,
135 .num_reg_defaults = ARRAY_SIZE(aic3x_reg),
136 .cache_type = REGCACHE_RBTREE,
44d0a879
VB		 137};
138
44d0a879 139#define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
1476f66f
LPC		 140 SOC_SINGLE_EXT(xname, reg, shift, mask, invert, \
141 snd_soc_dapm_get_volsw, snd_soc_dapm_put_volsw_aic3x)
44d0a879
VB		 142
143/*
144 * All input lines are connected when !0xf and disconnected with 0xf bit field,
145 * so we have to use specific dapm_put call for input mixer
146 */
147static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
148 struct snd_ctl_elem_value *ucontrol)
149{
eee5d7f9 150 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
650a18ac 151 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
4453dba5
EN		 152 struct soc_mixer_control *mc =
153 (struct soc_mixer_control *)kcontrol->private_value;
154 unsigned int reg = mc->reg;
155 unsigned int shift = mc->shift;
156 int max = mc->max;
157 unsigned int mask = (1 << fls(max)) - 1;
158 unsigned int invert = mc->invert;
5d99d778
LPC		 159 unsigned short val;
160 struct snd_soc_dapm_update update;
161 int connect, change;
44d0a879
VB		 162
163 val = (ucontrol->value.integer.value[0] & mask);
164
165 mask = 0xf;
166 if (val)
167 val = mask;
168
5d99d778
LPC		 169 connect = !!val;
170
44d0a879
VB		 171 if (invert)
172 val = mask - val;
44d0a879 173
5d99d778
LPC		 174 mask <<= shift;
175 val <<= shift;
2894770e 176
e6c111fa 177 change = snd_soc_test_bits(codec, reg, mask, val);
5d99d778
LPC		 178 if (change) {
179 update.kcontrol = kcontrol;
180 update.reg = reg;
181 update.mask = mask;
182 update.val = val;
183
650a18ac 184 snd_soc_dapm_mixer_update_power(dapm, kcontrol, connect,
5d99d778
LPC		 185 &update);
186 }
2894770e 187
5d99d778 188 return change;
44d0a879
VB		 189}
190
e2e8bfdf
HG		 191/*
192 * mic bias power on/off share the same register bits with
193 * output voltage of mic bias. when power on mic bias, we
194 * need reclaim it to voltage value.
195 * 0x0 = Powered off
196 * 0x1 = MICBIAS output is powered to 2.0V,
197 * 0x2 = MICBIAS output is powered to 2.5V
198 * 0x3 = MICBIAS output is connected to AVDD
199 */
200static int mic_bias_event(struct snd_soc_dapm_widget *w,
201 struct snd_kcontrol *kcontrol, int event)
202{
38d3df61 203 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
e2e8bfdf
HG		 204 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
205
206 switch (event) {
207 case SND_SOC_DAPM_POST_PMU:
208 /* change mic bias voltage to user defined */
209 snd_soc_update_bits(codec, MICBIAS_CTRL,
210 MICBIAS_LEVEL_MASK,
211 aic3x->micbias_vg << MICBIAS_LEVEL_SHIFT);
212 break;
213
214 case SND_SOC_DAPM_PRE_PMD:
215 snd_soc_update_bits(codec, MICBIAS_CTRL,
216 MICBIAS_LEVEL_MASK, 0);
217 break;
218 }
219 return 0;
220}
221
a60e654b
PU		 222static const char * const aic3x_left_dac_mux[] = {
223 "DAC_L1", "DAC_L3", "DAC_L2" };
224static SOC_ENUM_SINGLE_DECL(aic3x_left_dac_enum, DAC_LINE_MUX, 6,
225 aic3x_left_dac_mux);
226
227static const char * const aic3x_right_dac_mux[] = {
228 "DAC_R1", "DAC_R3", "DAC_R2" };
229static SOC_ENUM_SINGLE_DECL(aic3x_right_dac_enum, DAC_LINE_MUX, 4,
230 aic3x_right_dac_mux);
231
232static const char * const aic3x_left_hpcom_mux[] = {
233 "differential of HPLOUT", "constant VCM", "single-ended" };
234static SOC_ENUM_SINGLE_DECL(aic3x_left_hpcom_enum, HPLCOM_CFG, 4,
235 aic3x_left_hpcom_mux);
236
237static const char * const aic3x_right_hpcom_mux[] = {
238 "differential of HPROUT", "constant VCM", "single-ended",
239 "differential of HPLCOM", "external feedback" };
240static SOC_ENUM_SINGLE_DECL(aic3x_right_hpcom_enum, HPRCOM_CFG, 3,
241 aic3x_right_hpcom_mux);
242
243static const char * const aic3x_linein_mode_mux[] = {
244 "single-ended", "differential" };
245static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_l_enum, LINE1L_2_LADC_CTRL, 7,
246 aic3x_linein_mode_mux);
247static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_r_enum, LINE1L_2_RADC_CTRL, 7,
248 aic3x_linein_mode_mux);
249static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_l_enum, LINE1R_2_LADC_CTRL, 7,
250 aic3x_linein_mode_mux);
251static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_r_enum, LINE1R_2_RADC_CTRL, 7,
252 aic3x_linein_mode_mux);
253static SOC_ENUM_SINGLE_DECL(aic3x_line2l_2_ldac_enum, LINE2L_2_LADC_CTRL, 7,
254 aic3x_linein_mode_mux);
255static SOC_ENUM_SINGLE_DECL(aic3x_line2r_2_rdac_enum, LINE2R_2_RADC_CTRL, 7,
256 aic3x_linein_mode_mux);
257
258static const char * const aic3x_adc_hpf[] = {
259 "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
260static SOC_ENUM_DOUBLE_DECL(aic3x_adc_hpf_enum, AIC3X_CODEC_DFILT_CTRL, 6, 4,
261 aic3x_adc_hpf);
262
263static const char * const aic3x_agc_level[] = {
264 "-5.5dB", "-8dB", "-10dB", "-12dB",
265 "-14dB", "-17dB", "-20dB", "-24dB" };
266static SOC_ENUM_SINGLE_DECL(aic3x_lagc_level_enum, LAGC_CTRL_A, 4,
267 aic3x_agc_level);
268static SOC_ENUM_SINGLE_DECL(aic3x_ragc_level_enum, RAGC_CTRL_A, 4,
269 aic3x_agc_level);
270
271static const char * const aic3x_agc_attack[] = {
272 "8ms", "11ms", "16ms", "20ms" };
273static SOC_ENUM_SINGLE_DECL(aic3x_lagc_attack_enum, LAGC_CTRL_A, 2,
274 aic3x_agc_attack);
275static SOC_ENUM_SINGLE_DECL(aic3x_ragc_attack_enum, RAGC_CTRL_A, 2,
276 aic3x_agc_attack);
277
278static const char * const aic3x_agc_decay[] = {
279 "100ms", "200ms", "400ms", "500ms" };
280static SOC_ENUM_SINGLE_DECL(aic3x_lagc_decay_enum, LAGC_CTRL_A, 0,
281 aic3x_agc_decay);
282static SOC_ENUM_SINGLE_DECL(aic3x_ragc_decay_enum, RAGC_CTRL_A, 0,
283 aic3x_agc_decay);
bb1daa80 284
68d66269
MLC		 285static const char * const aic3x_poweron_time[] = {
286 "0us", "10us", "100us", "1ms", "10ms", "50ms",
287 "100ms", "200ms", "400ms", "800ms", "2s", "4s" };
288static SOC_ENUM_SINGLE_DECL(aic3x_poweron_time_enum, HPOUT_POP_REDUCTION, 4,
289 aic3x_poweron_time);
290
291static const char * const aic3x_rampup_step[] = { "0ms", "1ms", "2ms", "4ms" };
292static SOC_ENUM_SINGLE_DECL(aic3x_rampup_step_enum, HPOUT_POP_REDUCTION, 2,
293 aic3x_rampup_step);
294
7565fc38
JN		 295/*
296 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
297 */
298static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
299/* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
300static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
301/*
302 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
303 * Step size is approximately 0.5 dB over most of the scale but increasing
304 * near the very low levels.
305 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
306 * but having increasing dB difference below that (and where it doesn't count
307 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
308 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
309 */
310static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
311
44d0a879
VB		 312static const struct snd_kcontrol_new aic3x_snd_controls[] = {
313 /* Output */
7565fc38
JN		 314 SOC_DOUBLE_R_TLV("PCM Playback Volume",
315 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
44d0a879 316
098b1718
JN		 317 /*
318 * Output controls that map to output mixer switches. Note these are
319 * only for swapped L-to-R and R-to-L routes. See below stereo controls
320 * for direct L-to-L and R-to-R routes.
321 */
098b1718
JN		 322 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
323 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
324 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
325 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
326
098b1718
JN		 327 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
328 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
329 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
330 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
331
098b1718
JN		 332 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
333 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
334 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
335 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
336
098b1718
JN		 337 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
338 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
339 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
340 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
341
098b1718
JN		 342 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
343 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
344 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
345 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
346
098b1718
JN		 347 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
348 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
349 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
350 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
351
352 /* Stereo output controls for direct L-to-L and R-to-R routes */
098b1718
JN		 353 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
354 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
355 0, 118, 1, output_stage_tlv),
7565fc38
JN		 356 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
357 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
358 0, 118, 1, output_stage_tlv),
098b1718 359
098b1718
JN		 360 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
361 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
7565fc38 362 0, 118, 1, output_stage_tlv),
7565fc38
JN		 363 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
364 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
365 0, 118, 1, output_stage_tlv),
098b1718 366
098b1718
JN		 367 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
368 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
7565fc38 369 0, 118, 1, output_stage_tlv),
7565fc38
JN		 370 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
371 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
372 0, 118, 1, output_stage_tlv),
098b1718
JN		 373
374 /* Output pin mute controls */
375 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
376 0x01, 0),
098b1718
JN		 377 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
378 0x01, 0),
f9bc0297 379 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
44d0a879 380 0x01, 0),
44d0a879
VB		 381
382 /*
383 * Note: enable Automatic input Gain Controller with care. It can
384 * adjust PGA to max value when ADC is on and will never go back.
385 */
386 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
a60e654b
PU		 387 SOC_ENUM("Left AGC Target level", aic3x_lagc_level_enum),
388 SOC_ENUM("Right AGC Target level", aic3x_ragc_level_enum),
389 SOC_ENUM("Left AGC Attack time", aic3x_lagc_attack_enum),
390 SOC_ENUM("Right AGC Attack time", aic3x_ragc_attack_enum),
391 SOC_ENUM("Left AGC Decay time", aic3x_lagc_decay_enum),
392 SOC_ENUM("Right AGC Decay time", aic3x_ragc_decay_enum),
44d0a879 393
77444191
JP		 394 /* De-emphasis */
395 SOC_DOUBLE("De-emphasis Switch", AIC3X_CODEC_DFILT_CTRL, 2, 0, 0x01, 0),
44d0a879
VB		 396
397 /* Input */
7565fc38
JN		 398 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
399 0, 119, 0, adc_tlv),
44d0a879 400 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
4d20f70a 401
a60e654b 402 SOC_ENUM("ADC HPF Cut-off", aic3x_adc_hpf_enum),
68d66269
MLC		 403
404 /* Pop reduction */
405 SOC_ENUM("Output Driver Power-On time", aic3x_poweron_time_enum),
406 SOC_ENUM("Output Driver Ramp-up step", aic3x_rampup_step_enum),
44d0a879
VB		 407};
408
9503112d
JS		 409/* For other than tlv320aic3104 */
410static const struct snd_kcontrol_new aic3x_extra_snd_controls[] = {
411 /*
412 * Output controls that map to output mixer switches. Note these are
413 * only for swapped L-to-R and R-to-L routes. See below stereo controls
414 * for direct L-to-L and R-to-R routes.
415 */
416 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
417 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
418
419 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
420 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
421
422 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
423 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
424
425 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
426 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
427
428 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
429 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
430
431 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
432 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
433
434 /* Stereo output controls for direct L-to-L and R-to-R routes */
435 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
436 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
437 0, 118, 1, output_stage_tlv),
438
439 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
440 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
441 0, 118, 1, output_stage_tlv),
442
443 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
444 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
445 0, 118, 1, output_stage_tlv),
446};
447
58381da6
JW		 448static const struct snd_kcontrol_new aic3x_mono_controls[] = {
449 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
450 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
451 0, 118, 1, output_stage_tlv),
452 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
453 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
454 0, 118, 1, output_stage_tlv),
455 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
456 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
457 0, 118, 1, output_stage_tlv),
458
459 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
460};
461
6184f105
RC		 462/*
463 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
464 */
465static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
466
467static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
14a95fe8 468 SOC_DOUBLE_TLV("Class-D Playback Volume", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
6184f105 469
44d0a879
VB		 470/* Left DAC Mux */
471static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
a60e654b 472SOC_DAPM_ENUM("Route", aic3x_left_dac_enum);
44d0a879
VB		 473
474/* Right DAC Mux */
475static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
a60e654b 476SOC_DAPM_ENUM("Route", aic3x_right_dac_enum);
44d0a879
VB		 477
478/* Left HPCOM Mux */
479static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
a60e654b 480SOC_DAPM_ENUM("Route", aic3x_left_hpcom_enum);
44d0a879
VB		 481
482/* Right HPCOM Mux */
483static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
a60e654b 484SOC_DAPM_ENUM("Route", aic3x_right_hpcom_enum);
44d0a879 485
c3b79e05
JN		 486/* Left Line Mixer */
487static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
c3b79e05
JN		 488 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
489 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
c3b79e05
JN		 490 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
491 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
9503112d
JS		 492 /* Not on tlv320aic3104 */
493 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
494 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
44d0a879
VB		 495};
496
c3b79e05
JN		 497/* Right Line Mixer */
498static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
c3b79e05
JN		 499 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
500 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
c3b79e05
JN		 501 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
502 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
9503112d
JS		 503 /* Not on tlv320aic3104 */
504 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
505 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
c3b79e05
JN		 506};
507
508/* Mono Mixer */
509static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
510 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
511 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
512 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
513 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
514 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
515 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
516};
517
518/* Left HP Mixer */
519static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
c3b79e05
JN		 520 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
521 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
c3b79e05
JN		 522 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
523 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
9503112d
JS		 524 /* Not on tlv320aic3104 */
525 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
526 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
c3b79e05
JN		 527};
528
529/* Right HP Mixer */
530static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
c3b79e05
JN		 531 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
532 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
c3b79e05
JN		 533 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
534 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
9503112d
JS		 535 /* Not on tlv320aic3104 */
536 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
537 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
c3b79e05
JN		 538};
539
540/* Left HPCOM Mixer */
541static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
c3b79e05
JN		 542 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
543 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
c3b79e05
JN		 544 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
545 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
9503112d
JS		 546 /* Not on tlv320aic3104 */
547 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
548 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
c3b79e05
JN		 549};
550
551/* Right HPCOM Mixer */
552static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
c3b79e05
JN		 553 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
554 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
c3b79e05
JN		 555 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
556 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
9503112d
JS		 557 /* Not on tlv320aic3104 */
558 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
559 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
44d0a879
VB		 560};
561
562/* Left PGA Mixer */
563static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
564 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
54f01916 565 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
44d0a879
VB		 566 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
567 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
54f01916 568 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
44d0a879
VB		 569};
570
571/* Right PGA Mixer */
572static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
573 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
54f01916 574 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
44d0a879 575 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
54f01916 576 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
44d0a879
VB		 577 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
578};
579
9503112d
JS		 580/* Left PGA Mixer for tlv320aic3104 */
581static const struct snd_kcontrol_new aic3104_left_pga_mixer_controls[] = {
582 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
583 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
584 SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
585 SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
586};
587
588/* Right PGA Mixer for tlv320aic3104 */
589static const struct snd_kcontrol_new aic3104_right_pga_mixer_controls[] = {
590 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
591 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
592 SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
593 SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
594};
595
44d0a879 596/* Left Line1 Mux */
404b5665 597static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls =
a60e654b 598SOC_DAPM_ENUM("Route", aic3x_line1l_2_l_enum);
404b5665 599static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls =
a60e654b 600SOC_DAPM_ENUM("Route", aic3x_line1l_2_r_enum);
44d0a879
VB		 601
602/* Right Line1 Mux */
404b5665 603static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls =
a60e654b 604SOC_DAPM_ENUM("Route", aic3x_line1r_2_r_enum);
404b5665 605static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls =
a60e654b 606SOC_DAPM_ENUM("Route", aic3x_line1r_2_l_enum);
44d0a879
VB		 607
608/* Left Line2 Mux */
609static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
a60e654b 610SOC_DAPM_ENUM("Route", aic3x_line2l_2_ldac_enum);
44d0a879
VB		 611
612/* Right Line2 Mux */
613static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
a60e654b 614SOC_DAPM_ENUM("Route", aic3x_line2r_2_rdac_enum);
44d0a879 615
44d0a879
VB		 616static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
617 /* Left DAC to Left Outputs */
618 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
619 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
620 &aic3x_left_dac_mux_controls),
44d0a879
VB		 621 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
622 &aic3x_left_hpcom_mux_controls),
623 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
624 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
625 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
626
627 /* Right DAC to Right Outputs */
628 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
629 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
630 &aic3x_right_dac_mux_controls),
44d0a879
VB		 631 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
632 &aic3x_right_hpcom_mux_controls),
633 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
634 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
635 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
636
54f01916 637 /* Inputs to Left ADC */
44d0a879 638 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
44d0a879 639 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
404b5665 640 &aic3x_left_line1l_mux_controls),
54f01916 641 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
404b5665 642 &aic3x_left_line1r_mux_controls),
44d0a879 643
54f01916 644 /* Inputs to Right ADC */
44d0a879
VB		 645 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
646 LINE1R_2_RADC_CTRL, 2, 0),
54f01916 647 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
404b5665 648 &aic3x_right_line1l_mux_controls),
44d0a879 649 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
404b5665 650 &aic3x_right_line1r_mux_controls),
9503112d
JS		 651
652 /* Mic Bias */
653 SND_SOC_DAPM_SUPPLY("Mic Bias", MICBIAS_CTRL, 6, 0,
654 mic_bias_event,
655 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
656
657 SND_SOC_DAPM_OUTPUT("LLOUT"),
658 SND_SOC_DAPM_OUTPUT("RLOUT"),
659 SND_SOC_DAPM_OUTPUT("HPLOUT"),
660 SND_SOC_DAPM_OUTPUT("HPROUT"),
661 SND_SOC_DAPM_OUTPUT("HPLCOM"),
662 SND_SOC_DAPM_OUTPUT("HPRCOM"),
663
664 SND_SOC_DAPM_INPUT("LINE1L"),
665 SND_SOC_DAPM_INPUT("LINE1R"),
666
667 /*
668 * Virtual output pin to detection block inside codec. This can be
669 * used to keep codec bias on if gpio or detection features are needed.
670 * Force pin on or construct a path with an input jack and mic bias
671 * widgets.
672 */
673 SND_SOC_DAPM_OUTPUT("Detection"),
674};
675
676/* For other than tlv320aic3104 */
677static const struct snd_soc_dapm_widget aic3x_extra_dapm_widgets[] = {
678 /* Inputs to Left ADC */
679 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
680 &aic3x_left_pga_mixer_controls[0],
681 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
682 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
683 &aic3x_left_line2_mux_controls),
684
685 /* Inputs to Right ADC */
686 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
687 &aic3x_right_pga_mixer_controls[0],
688 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
44d0a879
VB		 689 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
690 &aic3x_right_line2_mux_controls),
691
ee15ffdb
JN		 692 /*
693 * Not a real mic bias widget but similar function. This is for dynamic
694 * control of GPIO1 digital mic modulator clock output function when
695 * using digital mic.
696 */
697 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
698 AIC3X_GPIO1_REG, 4, 0xf,
699 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
700 AIC3X_GPIO1_FUNC_DISABLED),
701
702 /*
703 * Also similar function like mic bias. Selects digital mic with
704 * configurable oversampling rate instead of ADC converter.
705 */
706 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
707 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
708 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
709 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
710 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
711 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
712
c3b79e05
JN		 713 /* Output mixers */
714 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
715 &aic3x_left_line_mixer_controls[0],
716 ARRAY_SIZE(aic3x_left_line_mixer_controls)),
717 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
718 &aic3x_right_line_mixer_controls[0],
719 ARRAY_SIZE(aic3x_right_line_mixer_controls)),
c3b79e05
JN		 720 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
721 &aic3x_left_hp_mixer_controls[0],
722 ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
723 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
724 &aic3x_right_hp_mixer_controls[0],
725 ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
726 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
727 &aic3x_left_hpcom_mixer_controls[0],
728 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
729 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
730 &aic3x_right_hpcom_mixer_controls[0],
731 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
44d0a879 732
44d0a879
VB		 733 SND_SOC_DAPM_INPUT("MIC3L"),
734 SND_SOC_DAPM_INPUT("MIC3R"),
44d0a879
VB		 735 SND_SOC_DAPM_INPUT("LINE2L"),
736 SND_SOC_DAPM_INPUT("LINE2R"),
9503112d 737};
19f7ac50 738
9503112d
JS		 739/* For tlv320aic3104 */
740static const struct snd_soc_dapm_widget aic3104_extra_dapm_widgets[] = {
741 /* Inputs to Left ADC */
742 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
743 &aic3104_left_pga_mixer_controls[0],
744 ARRAY_SIZE(aic3104_left_pga_mixer_controls)),
745
746 /* Inputs to Right ADC */
747 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
748 &aic3104_right_pga_mixer_controls[0],
749 ARRAY_SIZE(aic3104_right_pga_mixer_controls)),
750
751 /* Output mixers */
752 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
753 &aic3x_left_line_mixer_controls[0],
754 ARRAY_SIZE(aic3x_left_line_mixer_controls) - 2),
755 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
756 &aic3x_right_line_mixer_controls[0],
757 ARRAY_SIZE(aic3x_right_line_mixer_controls) - 2),
758 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
759 &aic3x_left_hp_mixer_controls[0],
760 ARRAY_SIZE(aic3x_left_hp_mixer_controls) - 2),
761 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
762 &aic3x_right_hp_mixer_controls[0],
763 ARRAY_SIZE(aic3x_right_hp_mixer_controls) - 2),
764 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
765 &aic3x_left_hpcom_mixer_controls[0],
766 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls) - 2),
767 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
768 &aic3x_right_hpcom_mixer_controls[0],
769 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls) - 2),
770
771 SND_SOC_DAPM_INPUT("MIC2L"),
772 SND_SOC_DAPM_INPUT("MIC2R"),
44d0a879
VB		 773};
774
58381da6
JW		 775static const struct snd_soc_dapm_widget aic3x_dapm_mono_widgets[] = {
776 /* Mono Output */
777 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
778
779 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
780 &aic3x_mono_mixer_controls[0],
781 ARRAY_SIZE(aic3x_mono_mixer_controls)),
782
783 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
784};
785
6184f105
RC		 786static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
787 /* Class-D outputs */
788 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
789 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
790
791 SND_SOC_DAPM_OUTPUT("SPOP"),
792 SND_SOC_DAPM_OUTPUT("SPOM"),
793};
794
d0cc0d3a 795static const struct snd_soc_dapm_route intercon[] = {
44d0a879
VB		 796 /* Left Input */
797 {"Left Line1L Mux", "single-ended", "LINE1L"},
798 {"Left Line1L Mux", "differential", "LINE1L"},
6b2afee1
PU		 799 {"Left Line1R Mux", "single-ended", "LINE1R"},
800 {"Left Line1R Mux", "differential", "LINE1R"},
44d0a879 801
44d0a879 802 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
54f01916 803 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
44d0a879
VB		 804
805 {"Left ADC", NULL, "Left PGA Mixer"},
806
807 /* Right Input */
808 {"Right Line1R Mux", "single-ended", "LINE1R"},
809 {"Right Line1R Mux", "differential", "LINE1R"},
6b2afee1
PU		 810 {"Right Line1L Mux", "single-ended", "LINE1L"},
811 {"Right Line1L Mux", "differential", "LINE1L"},
44d0a879 812
54f01916 813 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
44d0a879 814 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
44d0a879
VB		 815
816 {"Right ADC", NULL, "Right PGA Mixer"},
c3b79e05
JN		 817
818 /* Left DAC Output */
819 {"Left DAC Mux", "DAC_L1", "Left DAC"},
820 {"Left DAC Mux", "DAC_L2", "Left DAC"},
821 {"Left DAC Mux", "DAC_L3", "Left DAC"},
822
823 /* Right DAC Output */
824 {"Right DAC Mux", "DAC_R1", "Right DAC"},
825 {"Right DAC Mux", "DAC_R2", "Right DAC"},
826 {"Right DAC Mux", "DAC_R3", "Right DAC"},
827
828 /* Left Line Output */
c3b79e05
JN		 829 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
830 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
c3b79e05
JN		 831 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
832 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
833
834 {"Left Line Out", NULL, "Left Line Mixer"},
835 {"Left Line Out", NULL, "Left DAC Mux"},
836 {"LLOUT", NULL, "Left Line Out"},
837
838 /* Right Line Output */
c3b79e05
JN		 839 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
840 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
c3b79e05
JN		 841 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
842 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
843
844 {"Right Line Out", NULL, "Right Line Mixer"},
845 {"Right Line Out", NULL, "Right DAC Mux"},
846 {"RLOUT", NULL, "Right Line Out"},
847
c3b79e05 848 /* Left HP Output */
c3b79e05
JN		 849 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
850 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
c3b79e05
JN		 851 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
852 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
853
854 {"Left HP Out", NULL, "Left HP Mixer"},
855 {"Left HP Out", NULL, "Left DAC Mux"},
856 {"HPLOUT", NULL, "Left HP Out"},
857
858 /* Right HP Output */
c3b79e05
JN		 859 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
860 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
c3b79e05
JN		 861 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
862 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
863
864 {"Right HP Out", NULL, "Right HP Mixer"},
865 {"Right HP Out", NULL, "Right DAC Mux"},
866 {"HPROUT", NULL, "Right HP Out"},
867
868 /* Left HPCOM Output */
c3b79e05
JN		 869 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
870 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
c3b79e05
JN		 871 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
872 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
873
874 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
875 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
876 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
877 {"Left HP Com", NULL, "Left HPCOM Mux"},
878 {"HPLCOM", NULL, "Left HP Com"},
879
880 /* Right HPCOM Output */
c3b79e05
JN		 881 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
882 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
c3b79e05
JN		 883 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
884 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
885
886 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
887 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
888 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
889 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
890 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
891 {"Right HP Com", NULL, "Right HPCOM Mux"},
892 {"HPRCOM", NULL, "Right HP Com"},
44d0a879
VB		 893};
894
9503112d
JS		 895/* For other than tlv320aic3104 */
896static const struct snd_soc_dapm_route intercon_extra[] = {
897 /* Left Input */
898 {"Left Line2L Mux", "single-ended", "LINE2L"},
899 {"Left Line2L Mux", "differential", "LINE2L"},
900
901 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
902 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
903 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
904
905 {"Left ADC", NULL, "GPIO1 dmic modclk"},
906
907 /* Right Input */
908 {"Right Line2R Mux", "single-ended", "LINE2R"},
909 {"Right Line2R Mux", "differential", "LINE2R"},
910
911 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
912 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
913 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
914
915 {"Right ADC", NULL, "GPIO1 dmic modclk"},
916
917 /*
918 * Logical path between digital mic enable and GPIO1 modulator clock
919 * output function
920 */
921 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
922 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
923 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
924
925 /* Left Line Output */
926 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
927 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
928
929 /* Right Line Output */
930 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
931 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
932
933 /* Left HP Output */
934 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
935 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
936
937 /* Right HP Output */
938 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
939 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
940
941 /* Left HPCOM Output */
942 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
943 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
944
945 /* Right HPCOM Output */
946 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
947 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
948};
949
b8255930 950/* For tlv320aic3104 */
9503112d
JS		 951static const struct snd_soc_dapm_route intercon_extra_3104[] = {
952 /* Left Input */
953 {"Left PGA Mixer", "Mic2L Switch", "MIC2L"},
954 {"Left PGA Mixer", "Mic2R Switch", "MIC2R"},
955
956 /* Right Input */
957 {"Right PGA Mixer", "Mic2L Switch", "MIC2L"},
958 {"Right PGA Mixer", "Mic2R Switch", "MIC2R"},
959};
960
58381da6
JW		 961static const struct snd_soc_dapm_route intercon_mono[] = {
962 /* Mono Output */
963 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
964 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
965 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
966 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
967 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
968 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
969 {"Mono Out", NULL, "Mono Mixer"},
970 {"MONO_LOUT", NULL, "Mono Out"},
971};
972
6184f105
RC		 973static const struct snd_soc_dapm_route intercon_3007[] = {
974 /* Class-D outputs */
975 {"Left Class-D Out", NULL, "Left Line Out"},
976 {"Right Class-D Out", NULL, "Left Line Out"},
977 {"SPOP", NULL, "Left Class-D Out"},
978 {"SPOM", NULL, "Right Class-D Out"},
979};
980
44d0a879
VB		 981static int aic3x_add_widgets(struct snd_soc_codec *codec)
982{
6184f105 983 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
650a18ac 984 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
6184f105 985
58381da6
JW		 986 switch (aic3x->model) {
987 case AIC3X_MODEL_3X:
988 case AIC3X_MODEL_33:
9503112d
JS		 989 snd_soc_dapm_new_controls(dapm, aic3x_extra_dapm_widgets,
990 ARRAY_SIZE(aic3x_extra_dapm_widgets));
991 snd_soc_dapm_add_routes(dapm, intercon_extra,
992 ARRAY_SIZE(intercon_extra));
58381da6
JW		 993 snd_soc_dapm_new_controls(dapm, aic3x_dapm_mono_widgets,
994 ARRAY_SIZE(aic3x_dapm_mono_widgets));
995 snd_soc_dapm_add_routes(dapm, intercon_mono,
996 ARRAY_SIZE(intercon_mono));
997 break;
998 case AIC3X_MODEL_3007:
9503112d
JS		 999 snd_soc_dapm_new_controls(dapm, aic3x_extra_dapm_widgets,
1000 ARRAY_SIZE(aic3x_extra_dapm_widgets));
1001 snd_soc_dapm_add_routes(dapm, intercon_extra,
1002 ARRAY_SIZE(intercon_extra));
ce6120cc 1003 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
6184f105 1004 ARRAY_SIZE(aic3007_dapm_widgets));
ce6120cc
LG		 1005 snd_soc_dapm_add_routes(dapm, intercon_3007,
1006 ARRAY_SIZE(intercon_3007));
58381da6 1007 break;
9503112d
JS		 1008 case AIC3X_MODEL_3104:
1009 snd_soc_dapm_new_controls(dapm, aic3104_extra_dapm_widgets,
1010 ARRAY_SIZE(aic3104_extra_dapm_widgets));
1011 snd_soc_dapm_add_routes(dapm, intercon_extra_3104,
1012 ARRAY_SIZE(intercon_extra_3104));
1013 break;
6184f105
RC		 1014 }
1015
44d0a879
VB		 1016 return 0;
1017}
1018
44d0a879 1019static int aic3x_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1020 struct snd_pcm_hw_params *params,
1021 struct snd_soc_dai *dai)
44d0a879 1022{
e6968a17 1023 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1024 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
4f9c16cc 1025 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
255173b4
PM		 1026 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
1027 u16 d, pll_d = 1;
255173b4 1028 int clk;
3e8f5263
JS		 1029 int width = aic3x->slot_width;
1030
1031 if (!width)
1032 width = params_width(params);
44d0a879 1033
4f9c16cc 1034 /* select data word length */
e18eca43 1035 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
3e8f5263 1036 switch (width) {
3e3e2922 1037 case 16:
44d0a879 1038 break;
3e3e2922 1039 case 20:
4f9c16cc 1040 data |= (0x01 << 4);
44d0a879 1041 break;
3e3e2922 1042 case 24:
4f9c16cc 1043 data |= (0x02 << 4);
44d0a879 1044 break;
3e3e2922 1045 case 32:
4f9c16cc 1046 data |= (0x03 << 4);
44d0a879
VB		 1047 break;
1048 }
e18eca43 1049 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data);
4f9c16cc
DM		 1050
1051 /* Fsref can be 44100 or 48000 */
1052 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
1053
1054 /* Try to find a value for Q which allows us to bypass the PLL and
1055 * generate CODEC_CLK directly. */
1056 for (pll_q = 2; pll_q < 18; pll_q++)
1057 if (aic3x->sysclk / (128 * pll_q) == fsref) {
1058 bypass_pll = 1;
1059 break;
1060 }
1061
1062 if (bypass_pll) {
1063 pll_q &= 0xf;
e18eca43
JN		 1064 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
1065 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
06c71282 1066 /* disable PLL if it is bypassed */
9c173d15 1067 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0);
06c71282
C		 1068
1069 } else {
e18eca43 1070 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
06c71282 1071 /* enable PLL when it is used */
9c173d15
AL		 1072 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1073 PLL_ENABLE, PLL_ENABLE);
06c71282 1074 }
4f9c16cc
DM		 1075
1076 /* Route Left DAC to left channel input and
1077 * right DAC to right channel input */
1078 data = (LDAC2LCH | RDAC2RCH);
1079 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
1080 if (params_rate(params) >= 64000)
1081 data |= DUAL_RATE_MODE;
e18eca43 1082 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
44d0a879
VB		 1083
1084 /* codec sample rate select */
4f9c16cc
DM		 1085 data = (fsref * 20) / params_rate(params);
1086 if (params_rate(params) < 64000)
1087 data /= 2;
1088 data /= 5;
1089 data -= 2;
44d0a879 1090 data |= (data << 4);
e18eca43 1091 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
44d0a879 1092
4f9c16cc
DM		 1093 if (bypass_pll)
1094 return 0;
1095
25985edc 1096 /* Use PLL, compute appropriate setup for j, d, r and p, the closest
255173b4
PM		 1097 * one wins the game. Try with d==0 first, next with d!=0.
1098 * Constraints for j are according to the datasheet.
4f9c16cc 1099 * The sysclk is divided by 1000 to prevent integer overflows.
44d0a879 1100 */
255173b4 1101
4f9c16cc
DM		 1102 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
1103
1104 for (r = 1; r <= 16; r++)
1105 for (p = 1; p <= 8; p++) {
255173b4
PM		 1106 for (j = 4; j <= 55; j++) {
1107 /* This is actually 1000*((j+(d/10000))*r)/p
1108 * The term had to be converted to get
1109 * rid of the division by 10000; d = 0 here
1110 */
5baf8315 1111 int tmp_clk = (1000 * j * r) / p;
255173b4
PM		 1112
1113 /* Check whether this values get closer than
1114 * the best ones we had before
1115 */
5baf8315 1116 if (abs(codec_clk - tmp_clk) <
255173b4
PM		 1117 abs(codec_clk - last_clk)) {
1118 pll_j = j; pll_d = 0;
1119 pll_r = r; pll_p = p;
5baf8315 1120 last_clk = tmp_clk;
255173b4
PM		 1121 }
1122
1123 /* Early exit for exact matches */
5baf8315 1124 if (tmp_clk == codec_clk)
255173b4
PM		 1125 goto found;
1126 }
1127 }
4f9c16cc 1128
255173b4
PM		 1129 /* try with d != 0 */
1130 for (p = 1; p <= 8; p++) {
1131 j = codec_clk * p / 1000;
4f9c16cc 1132
255173b4
PM		 1133 if (j < 4 || j > 11)
1134 continue;
4f9c16cc 1135
255173b4
PM		 1136 /* do not use codec_clk here since we'd loose precision */
1137 d = ((2048 * p * fsref) - j * aic3x->sysclk)
1138 * 100 / (aic3x->sysclk/100);
4f9c16cc 1139
255173b4 1140 clk = (10000 * j + d) / (10 * p);
4f9c16cc 1141
255173b4
PM		 1142 /* check whether this values get closer than the best
1143 * ones we had before */
1144 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
1145 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
1146 last_clk = clk;
4f9c16cc
DM		 1147 }
1148
255173b4
PM		 1149 /* Early exit for exact matches */
1150 if (clk == codec_clk)
1151 goto found;
1152 }
1153
4f9c16cc
DM		 1154 if (last_clk == 0) {
1155 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
1156 return -EINVAL;
1157 }
44d0a879 1158
255173b4 1159found:
c9fe573a 1160 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLLP_MASK, pll_p);
e18eca43
JN		 1161 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG,
1162 pll_r << PLLR_SHIFT);
1163 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
1164 snd_soc_write(codec, AIC3X_PLL_PROGC_REG,
1165 (pll_d >> 6) << PLLD_MSB_SHIFT);
1166 snd_soc_write(codec, AIC3X_PLL_PROGD_REG,
1167 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
44d0a879 1168
44d0a879
VB		 1169 return 0;
1170}
1171
36849409
PU		 1172static int aic3x_prepare(struct snd_pcm_substream *substream,
1173 struct snd_soc_dai *dai)
1174{
1175 struct snd_soc_codec *codec = dai->codec;
1176 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1177 int delay = 0;
3e8f5263
JS		 1178 int width = aic3x->slot_width;
1179
1180 if (!width)
1181 width = substream->runtime->sample_bits;
36849409
PU		 1182
1183 /* TDM slot selection only valid in DSP_A/_B mode */
1184 if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_A)
3e8f5263 1185 delay += (aic3x->tdm_delay*width + 1);
36849409 1186 else if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_B)
3e8f5263 1187 delay += aic3x->tdm_delay*width;
36849409
PU		 1188
1189 /* Configure data delay */
0b65ba99 1190 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
36849409
PU		 1191
1192 return 0;
1193}
1194
e550e17f 1195static int aic3x_mute(struct snd_soc_dai *dai, int mute)
44d0a879
VB		 1196{
1197 struct snd_soc_codec *codec = dai->codec;
e18eca43
JN		 1198 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON;
1199 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON;
44d0a879
VB		 1200
1201 if (mute) {
e18eca43
JN		 1202 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
1203 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
44d0a879 1204 } else {
e18eca43
JN		 1205 snd_soc_write(codec, LDAC_VOL, ldac_reg);
1206 snd_soc_write(codec, RDAC_VOL, rdac_reg);
44d0a879
VB		 1207 }
1208
1209 return 0;
1210}
1211
e550e17f 1212static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
44d0a879
VB		 1213 int clk_id, unsigned int freq, int dir)
1214{
1215 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1216 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879 1217
a1f34af0
JP		 1218 /* set clock on MCLK or GPIO2 or BCLK */
1219 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK,
1220 clk_id << PLLCLK_IN_SHIFT);
1221 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK,
1222 clk_id << CLKDIV_IN_SHIFT);
1223
4f9c16cc
DM		 1224 aic3x->sysclk = freq;
1225 return 0;
44d0a879
VB		 1226}
1227
e550e17f 1228static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
44d0a879
VB		 1229 unsigned int fmt)
1230{
1231 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1232 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
81971a14
JN		 1233 u8 iface_areg, iface_breg;
1234
e18eca43
JN		 1235 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
1236 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
44d0a879
VB		 1237
1238 /* set master/slave audio interface */
1239 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1240 case SND_SOC_DAIFMT_CBM_CFM:
1241 aic3x->master = 1;
1242 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1243 break;
1244 case SND_SOC_DAIFMT_CBS_CFS:
1245 aic3x->master = 0;
68e47981 1246 iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER);
44d0a879
VB		 1247 break;
1248 default:
1249 return -EINVAL;
1250 }
1251
4b7d2831
JN		 1252 /*
1253 * match both interface format and signal polarities since they
1254 * are fixed
1255 */
1256 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1257 SND_SOC_DAIFMT_INV_MASK)) {
1258 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
44d0a879 1259 break;
a24f4f68 1260 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
4b7d2831 1261 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
44d0a879
VB		 1262 iface_breg |= (0x01 << 6);
1263 break;
4b7d2831 1264 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 1265 iface_breg |= (0x02 << 6);
1266 break;
4b7d2831 1267 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 1268 iface_breg |= (0x03 << 6);
1269 break;
1270 default:
1271 return -EINVAL;
1272 }
1273
36849409
PU		 1274 aic3x->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
1275
44d0a879 1276 /* set iface */
e18eca43
JN		 1277 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1278 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
36849409
PU		 1279
1280 return 0;
1281}
1282
1283static int aic3x_set_dai_tdm_slot(struct snd_soc_dai *codec_dai,
1284 unsigned int tx_mask, unsigned int rx_mask,
1285 int slots, int slot_width)
1286{
1287 struct snd_soc_codec *codec = codec_dai->codec;
1288 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1289 unsigned int lsb;
1290
1291 if (tx_mask != rx_mask) {
1292 dev_err(codec->dev, "tx and rx masks must be symmetric\n");
1293 return -EINVAL;
1294 }
1295
1296 if (unlikely(!tx_mask)) {
1297 dev_err(codec->dev, "tx and rx masks need to be non 0\n");
1298 return -EINVAL;
1299 }
1300
1301 /* TDM based on DSP mode requires slots to be adjacent */
1302 lsb = __ffs(tx_mask);
1303 if ((lsb + 1) != __fls(tx_mask)) {
1304 dev_err(codec->dev, "Invalid mask, slots must be adjacent\n");
1305 return -EINVAL;
1306 }
1307
3e8f5263
JS		 1308 switch (slot_width) {
1309 case 16:
1310 case 20:
1311 case 24:
1312 case 32:
1313 break;
1314 default:
1315 dev_err(codec->dev, "Unsupported slot width %d\n", slot_width);
1316 return -EINVAL;
1317 }
1318
1319
1320 aic3x->tdm_delay = lsb;
1321 aic3x->slot_width = slot_width;
36849409
PU		 1322
1323 /* DOUT in high-impedance on inactive bit clocks */
1324 snd_soc_update_bits(codec, AIC3X_ASD_INTF_CTRLA,
1325 DOUT_TRISTATE, DOUT_TRISTATE);
44d0a879
VB		 1326
1327 return 0;
1328}
1329
5a895f8a
JN		 1330static int aic3x_regulator_event(struct notifier_block *nb,
1331 unsigned long event, void *data)
1332{
1333 struct aic3x_disable_nb *disable_nb =
1334 container_of(nb, struct aic3x_disable_nb, nb);
1335 struct aic3x_priv *aic3x = disable_nb->aic3x;
1336
1337 if (event & REGULATOR_EVENT_DISABLE) {
1338 /*
1339 * Put codec to reset and require cache sync as at least one
1340 * of the supplies was disabled
1341 */
79ee820d 1342 if (gpio_is_valid(aic3x->gpio_reset))
5a895f8a 1343 gpio_set_value(aic3x->gpio_reset, 0);
2a6fedec 1344 regcache_mark_dirty(aic3x->regmap);
5a895f8a
JN		 1345 }
1346
1347 return 0;
1348}
1349
6c1a7d40
JN		 1350static int aic3x_set_power(struct snd_soc_codec *codec, int power)
1351{
1352 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
31d9f8fa 1353 unsigned int pll_c, pll_d;
2a6fedec 1354 int ret;
6c1a7d40
JN		 1355
1356 if (power) {
1357 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1358 aic3x->supplies);
1359 if (ret)
1360 goto out;
1361 aic3x->power = 1;
5a895f8a 1362
79ee820d 1363 if (gpio_is_valid(aic3x->gpio_reset)) {
6c1a7d40
JN		 1364 udelay(1);
1365 gpio_set_value(aic3x->gpio_reset, 1);
1366 }
1367
1368 /* Sync reg_cache with the hardware */
2a6fedec
MB		 1369 regcache_cache_only(aic3x->regmap, false);
1370 regcache_sync(aic3x->regmap);
31d9f8fa
DL		 1371
1372 /* Rewrite paired PLL D registers in case cached sync skipped
1373 * writing one of them and thus caused other one also not
1374 * being written
1375 */
1376 pll_c = snd_soc_read(codec, AIC3X_PLL_PROGC_REG);
1377 pll_d = snd_soc_read(codec, AIC3X_PLL_PROGD_REG);
1378 if (pll_c == aic3x_reg[AIC3X_PLL_PROGC_REG].def ||
1379 pll_d == aic3x_reg[AIC3X_PLL_PROGD_REG].def) {
1380 snd_soc_write(codec, AIC3X_PLL_PROGC_REG, pll_c);
1381 snd_soc_write(codec, AIC3X_PLL_PROGD_REG, pll_d);
1382 }
6c1a7d40 1383 } else {
9fb352b1
JN		 1384 /*
1385 * Do soft reset to this codec instance in order to clear
1386 * possible VDD leakage currents in case the supply regulators
1387 * remain on
1388 */
1389 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
2a6fedec 1390 regcache_mark_dirty(aic3x->regmap);
6c1a7d40 1391 aic3x->power = 0;
5a895f8a 1392 /* HW writes are needless when bias is off */
2a6fedec 1393 regcache_cache_only(aic3x->regmap, true);
6c1a7d40
JN		 1394 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
1395 aic3x->supplies);
1396 }
1397out:
1398 return ret;
1399}
1400
0be9898a
MB		 1401static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1402 enum snd_soc_bias_level level)
44d0a879 1403{
b2c812e2 1404 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879 1405
0be9898a
MB		 1406 switch (level) {
1407 case SND_SOC_BIAS_ON:
db13802e
JN		 1408 break;
1409 case SND_SOC_BIAS_PREPARE:
650a18ac 1410 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY &&
c23fd751 1411 aic3x->master) {
44d0a879 1412 /* enable pll */
9c173d15
AL		 1413 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1414 PLL_ENABLE, PLL_ENABLE);
44d0a879
VB		 1415 }
1416 break;
0be9898a 1417 case SND_SOC_BIAS_STANDBY:
6c1a7d40
JN		 1418 if (!aic3x->power)
1419 aic3x_set_power(codec, 1);
650a18ac 1420 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_PREPARE &&
c23fd751 1421 aic3x->master) {
44d0a879 1422 /* disable pll */
9c173d15
AL		 1423 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1424 PLL_ENABLE, 0);
44d0a879
VB		 1425 }
1426 break;
c23fd751 1427 case SND_SOC_BIAS_OFF:
6c1a7d40
JN		 1428 if (aic3x->power)
1429 aic3x_set_power(codec, 0);
c23fd751 1430 break;
44d0a879 1431 }
44d0a879
VB		 1432
1433 return 0;
1434}
1435
1436#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1437#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2a11a10a
PU		 1438 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE | \
1439 SNDRV_PCM_FMTBIT_S32_LE)
44d0a879 1440
85e7652d 1441static const struct snd_soc_dai_ops aic3x_dai_ops = {
6335d055 1442 .hw_params = aic3x_hw_params,
36849409 1443 .prepare = aic3x_prepare,
6335d055
EM		 1444 .digital_mute = aic3x_mute,
1445 .set_sysclk = aic3x_set_dai_sysclk,
1446 .set_fmt = aic3x_set_dai_fmt,
36849409 1447 .set_tdm_slot = aic3x_set_dai_tdm_slot,
6335d055
EM		 1448};
1449
f0fba2ad
LG		 1450static struct snd_soc_dai_driver aic3x_dai = {
1451 .name = "tlv320aic3x-hifi",
44d0a879
VB		 1452 .playback = {
1453 .stream_name = "Playback",
06378da4 1454 .channels_min = 2,
44d0a879
VB		 1455 .channels_max = 2,
1456 .rates = AIC3X_RATES,
1457 .formats = AIC3X_FORMATS,},
1458 .capture = {
1459 .stream_name = "Capture",
06378da4 1460 .channels_min = 2,
44d0a879
VB		 1461 .channels_max = 2,
1462 .rates = AIC3X_RATES,
1463 .formats = AIC3X_FORMATS,},
6335d055 1464 .ops = &aic3x_dai_ops,
14017615 1465 .symmetric_rates = 1,
44d0a879 1466};
44d0a879 1467
58381da6
JW		 1468static void aic3x_mono_init(struct snd_soc_codec *codec)
1469{
1470 /* DAC to Mono Line Out default volume and route to Output mixer */
1471 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1472 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1473
1474 /* unmute all outputs */
1475 snd_soc_update_bits(codec, MONOLOPM_CTRL, UNMUTE, UNMUTE);
1476
1477 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1478 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1479 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1480
1481 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1482 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1483 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1484}
1485
44d0a879
VB		 1486/*
1487 * initialise the AIC3X driver
1488 * register the mixer and dsp interfaces with the kernel
1489 */
cb3826f5 1490static int aic3x_init(struct snd_soc_codec *codec)
44d0a879 1491{
6184f105 1492 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
cb3826f5 1493
e18eca43
JN		 1494 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1495 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
44d0a879 1496
44d0a879 1497 /* DAC default volume and mute */
e18eca43
JN		 1498 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1499 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
44d0a879
VB		 1500
1501 /* DAC to HP default volume and route to Output mixer */
e18eca43
JN		 1502 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1503 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1504 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1505 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879 1506 /* DAC to Line Out default volume and route to Output mixer */
e18eca43
JN		 1507 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1508 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879
VB		 1509
1510 /* unmute all outputs */
9c173d15
AL		 1511 snd_soc_update_bits(codec, LLOPM_CTRL, UNMUTE, UNMUTE);
1512 snd_soc_update_bits(codec, RLOPM_CTRL, UNMUTE, UNMUTE);
9c173d15
AL		 1513 snd_soc_update_bits(codec, HPLOUT_CTRL, UNMUTE, UNMUTE);
1514 snd_soc_update_bits(codec, HPROUT_CTRL, UNMUTE, UNMUTE);
1515 snd_soc_update_bits(codec, HPLCOM_CTRL, UNMUTE, UNMUTE);
1516 snd_soc_update_bits(codec, HPRCOM_CTRL, UNMUTE, UNMUTE);
44d0a879
VB		 1517
1518 /* ADC default volume and unmute */
e18eca43
JN		 1519 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN);
1520 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN);
44d0a879 1521 /* By default route Line1 to ADC PGA mixer */
e18eca43
JN		 1522 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1523 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0);
44d0a879
VB		 1524
1525 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
e18eca43
JN		 1526 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1527 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1528 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1529 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
44d0a879 1530 /* PGA to Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1531 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1532 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
44d0a879 1533
2d1180e3
RM		 1534 /* On tlv320aic3104, these registers are reserved and must not be written */
1535 if (aic3x->model != AIC3X_MODEL_3104) {
1536 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1537 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1538 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1539 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1540 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1541 /* Line2 Line Out default volume, disconnect from Output Mixer */
1542 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1543 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1544 }
44d0a879 1545
58381da6
JW		 1546 switch (aic3x->model) {
1547 case AIC3X_MODEL_3X:
1548 case AIC3X_MODEL_33:
1549 aic3x_mono_init(codec);
1550 break;
1551 case AIC3X_MODEL_3007:
e18eca43 1552 snd_soc_write(codec, CLASSD_CTRL, 0);
58381da6 1553 break;
6184f105
RC		 1554 }
1555
cb3826f5
BD		 1556 return 0;
1557}
54e7e616 1558
414c73ab
JN		 1559static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x)
1560{
1561 struct aic3x_priv *a;
1562
1563 list_for_each_entry(a, &reset_list, list) {
1564 if (gpio_is_valid(aic3x->gpio_reset) &&
1565 aic3x->gpio_reset == a->gpio_reset)
1566 return true;
1567 }
1568
1569 return false;
1570}
1571
f0fba2ad 1572static int aic3x_probe(struct snd_soc_codec *codec)
cb3826f5 1573{
f0fba2ad 1574 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
2f24111a 1575 int ret, i;
f0fba2ad 1576
414c73ab 1577 INIT_LIST_HEAD(&aic3x->list);
5a895f8a 1578 aic3x->codec = codec;
cb3826f5 1579
5a895f8a
JN		 1580 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
1581 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
1582 aic3x->disable_nb[i].aic3x = aic3x;
1583 ret = regulator_register_notifier(aic3x->supplies[i].consumer,
1584 &aic3x->disable_nb[i].nb);
1585 if (ret) {
1586 dev_err(codec->dev,
1587 "Failed to request regulator notifier: %d\n",
1588 ret);
1589 goto err_notif;
1590 }
1591 }
2f24111a 1592
2a6fedec 1593 regcache_mark_dirty(aic3x->regmap);
37b47656
JN		 1594 aic3x_init(codec);
1595
f0fba2ad 1596 if (aic3x->setup) {
9503112d
JS		 1597 if (aic3x->model != AIC3X_MODEL_3104) {
1598 /* setup GPIO functions */
1599 snd_soc_write(codec, AIC3X_GPIO1_REG,
1600 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1601 snd_soc_write(codec, AIC3X_GPIO2_REG,
1602 (aic3x->setup->gpio_func[1] & 0xf) << 4);
1603 } else {
1604 dev_warn(codec->dev, "GPIO functionality is not supported on tlv320aic3104\n");
1605 }
44d0a879
VB		 1606 }
1607
58381da6
JW		 1608 switch (aic3x->model) {
1609 case AIC3X_MODEL_3X:
1610 case AIC3X_MODEL_33:
9503112d
JS		 1611 snd_soc_add_codec_controls(codec, aic3x_extra_snd_controls,
1612 ARRAY_SIZE(aic3x_extra_snd_controls));
58381da6
JW		 1613 snd_soc_add_codec_controls(codec, aic3x_mono_controls,
1614 ARRAY_SIZE(aic3x_mono_controls));
1615 break;
1616 case AIC3X_MODEL_3007:
9503112d
JS		 1617 snd_soc_add_codec_controls(codec, aic3x_extra_snd_controls,
1618 ARRAY_SIZE(aic3x_extra_snd_controls));
58381da6
JW		 1619 snd_soc_add_codec_controls(codec,
1620 &aic3x_classd_amp_gain_ctrl, 1);
1621 break;
9503112d
JS		 1622 case AIC3X_MODEL_3104:
1623 break;
58381da6 1624 }
cb3826f5 1625
e2e8bfdf
HG		 1626 /* set mic bias voltage */
1627 switch (aic3x->micbias_vg) {
1628 case AIC3X_MICBIAS_2_0V:
1629 case AIC3X_MICBIAS_2_5V:
1630 case AIC3X_MICBIAS_AVDDV:
1631 snd_soc_update_bits(codec, MICBIAS_CTRL,
1632 MICBIAS_LEVEL_MASK,
1633 (aic3x->micbias_vg) << MICBIAS_LEVEL_SHIFT);
1634 break;
1635 case AIC3X_MICBIAS_OFF:
1636 /*
1637 * noting to do. target won't enter here. This is just to avoid
1638 * compile time warning "warning: enumeration value
1639 * 'AIC3X_MICBIAS_OFF' not handled in switch"
1640 */
1641 break;
1642 }
1643
f0fba2ad 1644 aic3x_add_widgets(codec);
cb3826f5
BD		 1645
1646 return 0;
2f24111a 1647
5a895f8a
JN		 1648err_notif:
1649 while (i--)
1650 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1651 &aic3x->disable_nb[i].nb);
2f24111a 1652 return ret;
44d0a879
VB		 1653}
1654
f0fba2ad 1655static int aic3x_remove(struct snd_soc_codec *codec)
cb3826f5 1656{
2f24111a 1657 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
5a895f8a 1658 int i;
2f24111a 1659
414c73ab 1660 list_del(&aic3x->list);
5a895f8a
JN		 1661 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1662 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1663 &aic3x->disable_nb[i].nb);
2f24111a 1664
cb3826f5
BD		 1665 return 0;
1666}
44d0a879 1667
f0fba2ad 1668static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
f0fba2ad 1669 .set_bias_level = aic3x_set_bias_level,
eb3032f8 1670 .idle_bias_off = true,
f0fba2ad
LG		 1671 .probe = aic3x_probe,
1672 .remove = aic3x_remove,
786e3a48
KM		 1673 .component_driver = {
1674 .controls = aic3x_snd_controls,
1675 .num_controls = ARRAY_SIZE(aic3x_snd_controls),
1676 .dapm_widgets = aic3x_dapm_widgets,
1677 .num_dapm_widgets = ARRAY_SIZE(aic3x_dapm_widgets),
1678 .dapm_routes = intercon,
1679 .num_dapm_routes = ARRAY_SIZE(intercon),
1680 },
f0fba2ad
LG		 1681};
1682
44d0a879
VB		 1683/*
1684 * AIC3X 2 wire address can be up to 4 devices with device addresses
1685 * 0x18, 0x19, 0x1A, 0x1B
1686 */
44d0a879 1687
6184f105 1688static const struct i2c_device_id aic3x_i2c_id[] = {
177fdd89
AL		 1689 { "tlv320aic3x", AIC3X_MODEL_3X },
1690 { "tlv320aic33", AIC3X_MODEL_33 },
1691 { "tlv320aic3007", AIC3X_MODEL_3007 },
cbaa5689 1692 { "tlv320aic3106", AIC3X_MODEL_3X },
9503112d 1693 { "tlv320aic3104", AIC3X_MODEL_3104 },
6184f105
RC		 1694 { }
1695};
1696MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1697
8019ff6c 1698static const struct reg_sequence aic3007_class_d[] = {
2a6fedec
MB		 1699 /* Class-D speaker driver init; datasheet p. 46 */
1700 { AIC3X_PAGE_SELECT, 0x0D },
1701 { 0xD, 0x0D },
1702 { 0x8, 0x5C },
1703 { 0x8, 0x5D },
1704 { 0x8, 0x5C },
1705 { AIC3X_PAGE_SELECT, 0x00 },
1706};
1707
44d0a879
VB		 1708/*
1709 * If the i2c layer weren't so broken, we could pass this kind of data
1710 * around
1711 */
ba8ed121
JD		 1712static int aic3x_i2c_probe(struct i2c_client *i2c,
1713 const struct i2c_device_id *id)
44d0a879 1714{
5193d62f 1715 struct aic3x_pdata *pdata = i2c->dev.platform_data;
f0fba2ad 1716 struct aic3x_priv *aic3x;
c24fdc88
HG		 1717 struct aic3x_setup_data *ai3x_setup;
1718 struct device_node *np = i2c->dev.of_node;
6f818e04 1719 int ret, i;
e2e8bfdf 1720 u32 value;
44d0a879 1721
e2257db3 1722 aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL);
b1117f52 1723 if (!aic3x)
cb3826f5 1724 return -ENOMEM;
cb3826f5 1725
2a6fedec
MB		 1726 aic3x->regmap = devm_regmap_init_i2c(i2c, &aic3x_regmap);
1727 if (IS_ERR(aic3x->regmap)) {
1728 ret = PTR_ERR(aic3x->regmap);
1729 return ret;
1730 }
1731
1732 regcache_cache_only(aic3x->regmap, true);
a84a441b 1733
cb3826f5 1734 i2c_set_clientdata(i2c, aic3x);
c776357e
JN		 1735 if (pdata) {
1736 aic3x->gpio_reset = pdata->gpio_reset;
1737 aic3x->setup = pdata->setup;
e2e8bfdf 1738 aic3x->micbias_vg = pdata->micbias_vg;
c24fdc88
HG		 1739 } else if (np) {
1740 ai3x_setup = devm_kzalloc(&i2c->dev, sizeof(*ai3x_setup),
1741 GFP_KERNEL);
b1117f52 1742 if (!ai3x_setup)
c24fdc88 1743 return -ENOMEM;
c24fdc88
HG		 1744
1745 ret = of_get_named_gpio(np, "gpio-reset", 0);
1746 if (ret >= 0)
1747 aic3x->gpio_reset = ret;
1748 else
1749 aic3x->gpio_reset = -1;
1750
1751 if (of_property_read_u32_array(np, "ai3x-gpio-func",
1752 ai3x_setup->gpio_func, 2) >= 0) {
1753 aic3x->setup = ai3x_setup;
1754 }
1755
e2e8bfdf
HG		 1756 if (!of_property_read_u32(np, "ai3x-micbias-vg", &value)) {
1757 switch (value) {
1758 case 1 :
1759 aic3x->micbias_vg = AIC3X_MICBIAS_2_0V;
1760 break;
1761 case 2 :
1762 aic3x->micbias_vg = AIC3X_MICBIAS_2_5V;
1763 break;
1764 case 3 :
1765 aic3x->micbias_vg = AIC3X_MICBIAS_AVDDV;
1766 break;
1767 default :
1768 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1769 dev_err(&i2c->dev, "Unsuitable MicBias voltage "
1770 "found in DT\n");
1771 }
1772 } else {
1773 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1774 }
1775
c776357e
JN		 1776 } else {
1777 aic3x->gpio_reset = -1;
1778 }
cb3826f5 1779
177fdd89 1780 aic3x->model = id->driver_data;
6184f105 1781
6f818e04
MB		 1782 if (gpio_is_valid(aic3x->gpio_reset) &&
1783 !aic3x_is_shared_reset(aic3x)) {
1784 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
1785 if (ret != 0)
1786 goto err;
1787 gpio_direction_output(aic3x->gpio_reset, 0);
1788 }
1789
1790 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1791 aic3x->supplies[i].supply = aic3x_supply_names[i];
1792
1793 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(aic3x->supplies),
1794 aic3x->supplies);
1795 if (ret != 0) {
1796 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1797 goto err_gpio;
1798 }
1799
2a6fedec
MB		 1800 if (aic3x->model == AIC3X_MODEL_3007) {
1801 ret = regmap_register_patch(aic3x->regmap, aic3007_class_d,
1802 ARRAY_SIZE(aic3007_class_d));
1803 if (ret != 0)
1804 dev_err(&i2c->dev, "Failed to init class D: %d\n",
1805 ret);
1806 }
1807
f0fba2ad
LG		 1808 ret = snd_soc_register_codec(&i2c->dev,
1809 &soc_codec_dev_aic3x, &aic3x_dai, 1);
3b5b2431
SR		 1810
1811 if (ret != 0)
1812 goto err_gpio;
1813
1814 list_add(&aic3x->list, &reset_list);
1815
1816 return 0;
6f818e04
MB		 1817
1818err_gpio:
1819 if (gpio_is_valid(aic3x->gpio_reset) &&
1820 !aic3x_is_shared_reset(aic3x))
1821 gpio_free(aic3x->gpio_reset);
1822err:
1823 return ret;
44d0a879
VB		 1824}
1825
ba8ed121 1826static int aic3x_i2c_remove(struct i2c_client *client)
44d0a879 1827{
6f818e04
MB		 1828 struct aic3x_priv *aic3x = i2c_get_clientdata(client);
1829
f0fba2ad 1830 snd_soc_unregister_codec(&client->dev);
6f818e04
MB		 1831 if (gpio_is_valid(aic3x->gpio_reset) &&
1832 !aic3x_is_shared_reset(aic3x)) {
1833 gpio_set_value(aic3x->gpio_reset, 0);
1834 gpio_free(aic3x->gpio_reset);
1835 }
f0fba2ad 1836 return 0;
44d0a879
VB		 1837}
1838
c24fdc88
HG		 1839#if defined(CONFIG_OF)
1840static const struct of_device_id tlv320aic3x_of_match[] = {
1841 { .compatible = "ti,tlv320aic3x", },
f2c4fa65
MB		 1842 { .compatible = "ti,tlv320aic33" },
1843 { .compatible = "ti,tlv320aic3007" },
cbaa5689 1844 { .compatible = "ti,tlv320aic3106" },
9503112d 1845 { .compatible = "ti,tlv320aic3104" },
c24fdc88
HG		 1846 {},
1847};
1848MODULE_DEVICE_TABLE(of, tlv320aic3x_of_match);
1849#endif
1850
44d0a879
VB		 1851/* machine i2c codec control layer */
1852static struct i2c_driver aic3x_i2c_driver = {
1853 .driver = {
f0fba2ad 1854 .name = "tlv320aic3x-codec",
c24fdc88 1855 .of_match_table = of_match_ptr(tlv320aic3x_of_match),
44d0a879 1856 },
cb3826f5 1857 .probe = aic3x_i2c_probe,
ba8ed121
JD		 1858 .remove = aic3x_i2c_remove,
1859 .id_table = aic3x_i2c_id,
44d0a879 1860};
44d0a879 1861
fd39d14b 1862module_i2c_driver(aic3x_i2c_driver);
64089b84 1863
44d0a879
VB		 1864MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1865MODULE_AUTHOR("Vladimir Barinov");
1866MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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