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[deliverable/linux.git] / sound / soc / codecs / wm8961.c
CommitLineData
74dc55ed
MB		 1/*
2 * wm8961.c -- WM8961 ALSA SoC Audio driver
3 *
656baaeb
MB		 4 * Copyright 2009-10 Wolfson Microelectronics, plc
5 *
74dc55ed
MB		 6 * Author: Mark Brown
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Currently unimplemented features:
13 * - ALC
14 */
15
16#include <linux/module.h>
17#include <linux/moduleparam.h>
18#include <linux/init.h>
19#include <linux/delay.h>
20#include <linux/pm.h>
21#include <linux/i2c.h>
35ecf7cd 22#include <linux/regmap.h>
5a0e3ad6 23#include <linux/slab.h>
74dc55ed
MB		 24#include <sound/core.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/soc.h>
74dc55ed
MB		 28#include <sound/initval.h>
29#include <sound/tlv.h>
30
31#include "wm8961.h"
32
33#define WM8961_MAX_REGISTER 0xFC
34
35ecf7cd
MB		 35static const struct reg_default wm8961_reg_defaults[] = {
36 { 0, 0x009F }, /* R0 - Left Input volume */
37 { 1, 0x009F }, /* R1 - Right Input volume */
38 { 2, 0x0000 }, /* R2 - LOUT1 volume */
39 { 3, 0x0000 }, /* R3 - ROUT1 volume */
40 { 4, 0x0020 }, /* R4 - Clocking1 */
41 { 5, 0x0008 }, /* R5 - ADC & DAC Control 1 */
42 { 6, 0x0000 }, /* R6 - ADC & DAC Control 2 */
43 { 7, 0x000A }, /* R7 - Audio Interface 0 */
44 { 8, 0x01F4 }, /* R8 - Clocking2 */
45 { 9, 0x0000 }, /* R9 - Audio Interface 1 */
46 { 10, 0x00FF }, /* R10 - Left DAC volume */
47 { 11, 0x00FF }, /* R11 - Right DAC volume */
48
49 { 14, 0x0040 }, /* R14 - Audio Interface 2 */
50
51 { 17, 0x007B }, /* R17 - ALC1 */
52 { 18, 0x0000 }, /* R18 - ALC2 */
53 { 19, 0x0032 }, /* R19 - ALC3 */
54 { 20, 0x0000 }, /* R20 - Noise Gate */
55 { 21, 0x00C0 }, /* R21 - Left ADC volume */
56 { 22, 0x00C0 }, /* R22 - Right ADC volume */
57 { 23, 0x0120 }, /* R23 - Additional control(1) */
58 { 24, 0x0000 }, /* R24 - Additional control(2) */
59 { 25, 0x0000 }, /* R25 - Pwr Mgmt (1) */
60 { 26, 0x0000 }, /* R26 - Pwr Mgmt (2) */
61 { 27, 0x0000 }, /* R27 - Additional Control (3) */
62 { 28, 0x0000 }, /* R28 - Anti-pop */
63
64 { 30, 0x005F }, /* R30 - Clocking 3 */
65
66 { 32, 0x0000 }, /* R32 - ADCL signal path */
67 { 33, 0x0000 }, /* R33 - ADCR signal path */
68
69 { 40, 0x0000 }, /* R40 - LOUT2 volume */
70 { 41, 0x0000 }, /* R41 - ROUT2 volume */
71
72 { 47, 0x0000 }, /* R47 - Pwr Mgmt (3) */
73 { 48, 0x0023 }, /* R48 - Additional Control (4) */
74 { 49, 0x0000 }, /* R49 - Class D Control 1 */
75
76 { 51, 0x0003 }, /* R51 - Class D Control 2 */
77
78 { 56, 0x0106 }, /* R56 - Clocking 4 */
79 { 57, 0x0000 }, /* R57 - DSP Sidetone 0 */
80 { 58, 0x0000 }, /* R58 - DSP Sidetone 1 */
81
82 { 60, 0x0000 }, /* R60 - DC Servo 0 */
83 { 61, 0x0000 }, /* R61 - DC Servo 1 */
84
85 { 63, 0x015E }, /* R63 - DC Servo 3 */
86
87 { 65, 0x0010 }, /* R65 - DC Servo 5 */
88
89 { 68, 0x0003 }, /* R68 - Analogue PGA Bias */
90 { 69, 0x0000 }, /* R69 - Analogue HP 0 */
91
92 { 71, 0x01FB }, /* R71 - Analogue HP 2 */
93 { 72, 0x0000 }, /* R72 - Charge Pump 1 */
94
95 { 82, 0x0000 }, /* R82 - Charge Pump B */
96
97 { 87, 0x0000 }, /* R87 - Write Sequencer 1 */
98 { 88, 0x0000 }, /* R88 - Write Sequencer 2 */
99 { 89, 0x0000 }, /* R89 - Write Sequencer 3 */
100 { 90, 0x0000 }, /* R90 - Write Sequencer 4 */
101 { 91, 0x0000 }, /* R91 - Write Sequencer 5 */
102 { 92, 0x0000 }, /* R92 - Write Sequencer 6 */
103 { 93, 0x0000 }, /* R93 - Write Sequencer 7 */
104
105 { 252, 0x0001 }, /* R252 - General test 1 */
74dc55ed
MB		 106};
107
108struct wm8961_priv {
35ecf7cd 109 struct regmap *regmap;
74dc55ed 110 int sysclk;
74dc55ed
MB		 111};
112
35ecf7cd 113static bool wm8961_volatile(struct device *dev, unsigned int reg)
74dc55ed
MB		 114{
115 switch (reg) {
8d50e447 116 case WM8961_SOFTWARE_RESET:
74dc55ed
MB		 117 case WM8961_WRITE_SEQUENCER_7:
118 case WM8961_DC_SERVO_1:
35ecf7cd 119 return true;
74dc55ed
MB		 120
121 default:
35ecf7cd
MB		 122 return false;
123 }
124}
125
126static bool wm8961_readable(struct device *dev, unsigned int reg)
127{
128 switch (reg) {
129 case WM8961_LEFT_INPUT_VOLUME:
130 case WM8961_RIGHT_INPUT_VOLUME:
131 case WM8961_LOUT1_VOLUME:
132 case WM8961_ROUT1_VOLUME:
133 case WM8961_CLOCKING1:
134 case WM8961_ADC_DAC_CONTROL_1:
135 case WM8961_ADC_DAC_CONTROL_2:
136 case WM8961_AUDIO_INTERFACE_0:
137 case WM8961_CLOCKING2:
138 case WM8961_AUDIO_INTERFACE_1:
139 case WM8961_LEFT_DAC_VOLUME:
140 case WM8961_RIGHT_DAC_VOLUME:
141 case WM8961_AUDIO_INTERFACE_2:
142 case WM8961_SOFTWARE_RESET:
143 case WM8961_ALC1:
144 case WM8961_ALC2:
145 case WM8961_ALC3:
146 case WM8961_NOISE_GATE:
147 case WM8961_LEFT_ADC_VOLUME:
148 case WM8961_RIGHT_ADC_VOLUME:
149 case WM8961_ADDITIONAL_CONTROL_1:
150 case WM8961_ADDITIONAL_CONTROL_2:
151 case WM8961_PWR_MGMT_1:
152 case WM8961_PWR_MGMT_2:
153 case WM8961_ADDITIONAL_CONTROL_3:
154 case WM8961_ANTI_POP:
155 case WM8961_CLOCKING_3:
156 case WM8961_ADCL_SIGNAL_PATH:
157 case WM8961_ADCR_SIGNAL_PATH:
158 case WM8961_LOUT2_VOLUME:
159 case WM8961_ROUT2_VOLUME:
160 case WM8961_PWR_MGMT_3:
161 case WM8961_ADDITIONAL_CONTROL_4:
162 case WM8961_CLASS_D_CONTROL_1:
163 case WM8961_CLASS_D_CONTROL_2:
164 case WM8961_CLOCKING_4:
165 case WM8961_DSP_SIDETONE_0:
166 case WM8961_DSP_SIDETONE_1:
167 case WM8961_DC_SERVO_0:
168 case WM8961_DC_SERVO_1:
169 case WM8961_DC_SERVO_3:
170 case WM8961_DC_SERVO_5:
171 case WM8961_ANALOGUE_PGA_BIAS:
172 case WM8961_ANALOGUE_HP_0:
173 case WM8961_ANALOGUE_HP_2:
174 case WM8961_CHARGE_PUMP_1:
175 case WM8961_CHARGE_PUMP_B:
176 case WM8961_WRITE_SEQUENCER_1:
177 case WM8961_WRITE_SEQUENCER_2:
178 case WM8961_WRITE_SEQUENCER_3:
179 case WM8961_WRITE_SEQUENCER_4:
180 case WM8961_WRITE_SEQUENCER_5:
181 case WM8961_WRITE_SEQUENCER_6:
182 case WM8961_WRITE_SEQUENCER_7:
183 case WM8961_GENERAL_TEST_1:
184 return true;
185 default:
186 return false;
74dc55ed
MB		 187 }
188}
189
74dc55ed
MB		 190/*
191 * The headphone output supports special anti-pop sequences giving
192 * silent power up and power down.
193 */
194static int wm8961_hp_event(struct snd_soc_dapm_widget *w,
195 struct snd_kcontrol *kcontrol, int event)
196{
0e13064d 197 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
8d50e447
MB		 198 u16 hp_reg = snd_soc_read(codec, WM8961_ANALOGUE_HP_0);
199 u16 cp_reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_1);
200 u16 pwr_reg = snd_soc_read(codec, WM8961_PWR_MGMT_2);
201 u16 dcs_reg = snd_soc_read(codec, WM8961_DC_SERVO_1);
74dc55ed
MB		 202 int timeout = 500;
203
204 if (event & SND_SOC_DAPM_POST_PMU) {
205 /* Make sure the output is shorted */
206 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
8d50e447 207 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
74dc55ed
MB		 208
209 /* Enable the charge pump */
210 cp_reg |= WM8961_CP_ENA;
8d50e447 211 snd_soc_write(codec, WM8961_CHARGE_PUMP_1, cp_reg);
74dc55ed
MB		 212 mdelay(5);
213
214 /* Enable the PGA */
215 pwr_reg |= WM8961_LOUT1_PGA | WM8961_ROUT1_PGA;
8d50e447 216 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
74dc55ed
MB		 217
218 /* Enable the amplifier */
219 hp_reg |= WM8961_HPR_ENA | WM8961_HPL_ENA;
8d50e447 220 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
74dc55ed
MB		 221
222 /* Second stage enable */
223 hp_reg |= WM8961_HPR_ENA_DLY | WM8961_HPL_ENA_DLY;
8d50e447 224 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
74dc55ed
MB		 225
226 /* Enable the DC servo & trigger startup */
227 dcs_reg |=
228 WM8961_DCS_ENA_CHAN_HPR | WM8961_DCS_TRIG_STARTUP_HPR |
229 WM8961_DCS_ENA_CHAN_HPL | WM8961_DCS_TRIG_STARTUP_HPL;
230 dev_dbg(codec->dev, "Enabling DC servo\n");
231
8d50e447 232 snd_soc_write(codec, WM8961_DC_SERVO_1, dcs_reg);
74dc55ed
MB		 233 do {
234 msleep(1);
8d50e447 235 dcs_reg = snd_soc_read(codec, WM8961_DC_SERVO_1);
74dc55ed
MB		 236 } while (--timeout &&
237 dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
238 WM8961_DCS_TRIG_STARTUP_HPL));
239 if (dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
240 WM8961_DCS_TRIG_STARTUP_HPL))
241 dev_err(codec->dev, "DC servo timed out\n");
242 else
243 dev_dbg(codec->dev, "DC servo startup complete\n");
244
245 /* Enable the output stage */
246 hp_reg |= WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP;
8d50e447 247 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
74dc55ed
MB		 248
249 /* Remove the short on the output stage */
250 hp_reg |= WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT;
8d50e447 251 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
74dc55ed
MB		 252 }
253
254 if (event & SND_SOC_DAPM_PRE_PMD) {
255 /* Short the output */
256 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
8d50e447 257 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
74dc55ed
MB		 258
259 /* Disable the output stage */
260 hp_reg &= ~(WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP);
8d50e447 261 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
74dc55ed
MB		 262
263 /* Disable DC offset cancellation */
264 dcs_reg &= ~(WM8961_DCS_ENA_CHAN_HPR |
265 WM8961_DCS_ENA_CHAN_HPL);
8d50e447 266 snd_soc_write(codec, WM8961_DC_SERVO_1, dcs_reg);
74dc55ed
MB		 267
268 /* Finish up */
269 hp_reg &= ~(WM8961_HPR_ENA_DLY | WM8961_HPR_ENA |
270 WM8961_HPL_ENA_DLY | WM8961_HPL_ENA);
8d50e447 271 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
74dc55ed
MB		 272
273 /* Disable the PGA */
274 pwr_reg &= ~(WM8961_LOUT1_PGA | WM8961_ROUT1_PGA);
8d50e447 275 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
74dc55ed
MB		 276
277 /* Disable the charge pump */
278 dev_dbg(codec->dev, "Disabling charge pump\n");
8d50e447 279 snd_soc_write(codec, WM8961_CHARGE_PUMP_1,
74dc55ed
MB		 280 cp_reg & ~WM8961_CP_ENA);
281 }
282
283 return 0;
284}
285
286static int wm8961_spk_event(struct snd_soc_dapm_widget *w,
287 struct snd_kcontrol *kcontrol, int event)
288{
0e13064d 289 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
8d50e447
MB		 290 u16 pwr_reg = snd_soc_read(codec, WM8961_PWR_MGMT_2);
291 u16 spk_reg = snd_soc_read(codec, WM8961_CLASS_D_CONTROL_1);
74dc55ed
MB		 292
293 if (event & SND_SOC_DAPM_POST_PMU) {
294 /* Enable the PGA */
295 pwr_reg |= WM8961_SPKL_PGA | WM8961_SPKR_PGA;
8d50e447 296 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
74dc55ed
MB		 297
298 /* Enable the amplifier */
299 spk_reg |= WM8961_SPKL_ENA | WM8961_SPKR_ENA;
8d50e447 300 snd_soc_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg);
74dc55ed
MB		 301 }
302
303 if (event & SND_SOC_DAPM_PRE_PMD) {
7fcadfd1 304 /* Disable the amplifier */
74dc55ed 305 spk_reg &= ~(WM8961_SPKL_ENA | WM8961_SPKR_ENA);
8d50e447 306 snd_soc_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg);
74dc55ed 307
7fcadfd1 308 /* Disable the PGA */
74dc55ed 309 pwr_reg &= ~(WM8961_SPKL_PGA | WM8961_SPKR_PGA);
8d50e447 310 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
74dc55ed
MB		 311 }
312
313 return 0;
314}
315
316static const char *adc_hpf_text[] = {
317 "Hi-fi", "Voice 1", "Voice 2", "Voice 3",
318};
319
a6616cda
TI		 320static SOC_ENUM_SINGLE_DECL(adc_hpf,
321 WM8961_ADC_DAC_CONTROL_2, 7, adc_hpf_text);
74dc55ed
MB		 322
323static const char *dac_deemph_text[] = {
324 "None", "32kHz", "44.1kHz", "48kHz",
325};
326
a6616cda
TI		 327static SOC_ENUM_SINGLE_DECL(dac_deemph,
328 WM8961_ADC_DAC_CONTROL_1, 1, dac_deemph_text);
74dc55ed
MB		 329
330static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
331static const DECLARE_TLV_DB_SCALE(hp_sec_tlv, -700, 100, 0);
332static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
333static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
5d272d89 334static const DECLARE_TLV_DB_RANGE(boost_tlv,
74dc55ed
MB		 335 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
336 1, 1, TLV_DB_SCALE_ITEM(13, 0, 0),
337 2, 2, TLV_DB_SCALE_ITEM(20, 0, 0),
5d272d89
LPC		 338 3, 3, TLV_DB_SCALE_ITEM(29, 0, 0)
339);
74dc55ed
MB		 340static const DECLARE_TLV_DB_SCALE(pga_tlv, -2325, 75, 0);
341
342static const struct snd_kcontrol_new wm8961_snd_controls[] = {
343SOC_DOUBLE_R_TLV("Headphone Volume", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME,
344 0, 127, 0, out_tlv),
345SOC_DOUBLE_TLV("Headphone Secondary Volume", WM8961_ANALOGUE_HP_2,
346 6, 3, 7, 0, hp_sec_tlv),
347SOC_DOUBLE_R("Headphone ZC Switch", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME,
348 7, 1, 0),
349
350SOC_DOUBLE_R_TLV("Speaker Volume", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME,
351 0, 127, 0, out_tlv),
352SOC_DOUBLE_R("Speaker ZC Switch", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME,
353 7, 1, 0),
354SOC_SINGLE("Speaker AC Gain", WM8961_CLASS_D_CONTROL_2, 0, 7, 0),
355
356SOC_SINGLE("DAC x128 OSR Switch", WM8961_ADC_DAC_CONTROL_2, 0, 1, 0),
357SOC_ENUM("DAC Deemphasis", dac_deemph),
358SOC_SINGLE("DAC Soft Mute Switch", WM8961_ADC_DAC_CONTROL_2, 3, 1, 0),
359
360SOC_DOUBLE_R_TLV("Sidetone Volume", WM8961_DSP_SIDETONE_0,
361 WM8961_DSP_SIDETONE_1, 4, 12, 0, sidetone_tlv),
362
363SOC_SINGLE("ADC High Pass Filter Switch", WM8961_ADC_DAC_CONTROL_1, 0, 1, 0),
364SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
365
366SOC_DOUBLE_R_TLV("Capture Volume",
367 WM8961_LEFT_ADC_VOLUME, WM8961_RIGHT_ADC_VOLUME,
368 1, 119, 0, adc_tlv),
369SOC_DOUBLE_R_TLV("Capture Boost Volume",
370 WM8961_ADCL_SIGNAL_PATH, WM8961_ADCR_SIGNAL_PATH,
371 4, 3, 0, boost_tlv),
372SOC_DOUBLE_R_TLV("Capture PGA Volume",
373 WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
374 0, 62, 0, pga_tlv),
375SOC_DOUBLE_R("Capture PGA ZC Switch",
376 WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
377 6, 1, 1),
378SOC_DOUBLE_R("Capture PGA Switch",
379 WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
380 7, 1, 1),
381};
382
383static const char *sidetone_text[] = {
384 "None", "Left", "Right"
385};
386
a6616cda
TI		 387static SOC_ENUM_SINGLE_DECL(dacl_sidetone,
388 WM8961_DSP_SIDETONE_0, 2, sidetone_text);
74dc55ed 389
a6616cda
TI		 390static SOC_ENUM_SINGLE_DECL(dacr_sidetone,
391 WM8961_DSP_SIDETONE_1, 2, sidetone_text);
74dc55ed
MB		 392
393static const struct snd_kcontrol_new dacl_mux =
394 SOC_DAPM_ENUM("DACL Sidetone", dacl_sidetone);
395
396static const struct snd_kcontrol_new dacr_mux =
397 SOC_DAPM_ENUM("DACR Sidetone", dacr_sidetone);
398
399static const struct snd_soc_dapm_widget wm8961_dapm_widgets[] = {
400SND_SOC_DAPM_INPUT("LINPUT"),
401SND_SOC_DAPM_INPUT("RINPUT"),
402
403SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8961_CLOCKING2, 4, 0, NULL, 0),
404
405SND_SOC_DAPM_PGA("Left Input", WM8961_PWR_MGMT_1, 5, 0, NULL, 0),
406SND_SOC_DAPM_PGA("Right Input", WM8961_PWR_MGMT_1, 4, 0, NULL, 0),
407
408SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", WM8961_PWR_MGMT_1, 3, 0),
409SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", WM8961_PWR_MGMT_1, 2, 0),
410
20abf088 411SND_SOC_DAPM_SUPPLY("MICBIAS", WM8961_PWR_MGMT_1, 1, 0, NULL, 0),
74dc55ed
MB		 412
413SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &dacl_mux),
414SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &dacr_mux),
415
416SND_SOC_DAPM_DAC("DACL", "HiFi Playback", WM8961_PWR_MGMT_2, 8, 0),
417SND_SOC_DAPM_DAC("DACR", "HiFi Playback", WM8961_PWR_MGMT_2, 7, 0),
418
419/* Handle as a mono path for DCS */
420SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM,
421 4, 0, NULL, 0, wm8961_hp_event,
422 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
423SND_SOC_DAPM_PGA_E("Speaker Output", SND_SOC_NOPM,
424 4, 0, NULL, 0, wm8961_spk_event,
425 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
426
427SND_SOC_DAPM_OUTPUT("HP_L"),
428SND_SOC_DAPM_OUTPUT("HP_R"),
429SND_SOC_DAPM_OUTPUT("SPK_LN"),
430SND_SOC_DAPM_OUTPUT("SPK_LP"),
431SND_SOC_DAPM_OUTPUT("SPK_RN"),
432SND_SOC_DAPM_OUTPUT("SPK_RP"),
433};
434
435
436static const struct snd_soc_dapm_route audio_paths[] = {
437 { "DACL", NULL, "CLK_DSP" },
438 { "DACL", NULL, "DACL Sidetone" },
439 { "DACR", NULL, "CLK_DSP" },
440 { "DACR", NULL, "DACR Sidetone" },
441
442 { "DACL Sidetone", "Left", "ADCL" },
443 { "DACL Sidetone", "Right", "ADCR" },
444
445 { "DACR Sidetone", "Left", "ADCL" },
446 { "DACR Sidetone", "Right", "ADCR" },
447
448 { "HP_L", NULL, "Headphone Output" },
449 { "HP_R", NULL, "Headphone Output" },
450 { "Headphone Output", NULL, "DACL" },
451 { "Headphone Output", NULL, "DACR" },
452
453 { "SPK_LN", NULL, "Speaker Output" },
454 { "SPK_LP", NULL, "Speaker Output" },
455 { "SPK_RN", NULL, "Speaker Output" },
456 { "SPK_RP", NULL, "Speaker Output" },
457
458 { "Speaker Output", NULL, "DACL" },
459 { "Speaker Output", NULL, "DACR" },
460
461 { "ADCL", NULL, "Left Input" },
462 { "ADCL", NULL, "CLK_DSP" },
463 { "ADCR", NULL, "Right Input" },
464 { "ADCR", NULL, "CLK_DSP" },
465
466 { "Left Input", NULL, "LINPUT" },
467 { "Right Input", NULL, "RINPUT" },
468
469};
470
471/* Values for CLK_SYS_RATE */
472static struct {
473 int ratio;
474 u16 val;
475} wm8961_clk_sys_ratio[] = {
476 { 64, 0 },
477 { 128, 1 },
478 { 192, 2 },
479 { 256, 3 },
480 { 384, 4 },
481 { 512, 5 },
482 { 768, 6 },
483 { 1024, 7 },
484 { 1408, 8 },
485 { 1536, 9 },
486};
487
488/* Values for SAMPLE_RATE */
489static struct {
490 int rate;
491 u16 val;
492} wm8961_srate[] = {
493 { 48000, 0 },
494 { 44100, 0 },
495 { 32000, 1 },
496 { 22050, 2 },
497 { 24000, 2 },
498 { 16000, 3 },
499 { 11250, 4 },
500 { 12000, 4 },
501 { 8000, 5 },
502};
503
504static int wm8961_hw_params(struct snd_pcm_substream *substream,
505 struct snd_pcm_hw_params *params,
506 struct snd_soc_dai *dai)
507{
508 struct snd_soc_codec *codec = dai->codec;
b2c812e2 509 struct wm8961_priv *wm8961 = snd_soc_codec_get_drvdata(codec);
74dc55ed
MB		 510 int i, best, target, fs;
511 u16 reg;
512
513 fs = params_rate(params);
514
515 if (!wm8961->sysclk) {
516 dev_err(codec->dev, "MCLK has not been specified\n");
517 return -EINVAL;
518 }
519
520 /* Find the closest sample rate for the filters */
521 best = 0;
522 for (i = 0; i < ARRAY_SIZE(wm8961_srate); i++) {
523 if (abs(wm8961_srate[i].rate - fs) <
524 abs(wm8961_srate[best].rate - fs))
525 best = i;
526 }
8d50e447 527 reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_3);
74dc55ed
MB		 528 reg &= ~WM8961_SAMPLE_RATE_MASK;
529 reg |= wm8961_srate[best].val;
8d50e447 530 snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_3, reg);
74dc55ed
MB		 531 dev_dbg(codec->dev, "Selected SRATE %dHz for %dHz\n",
532 wm8961_srate[best].rate, fs);
533
534 /* Select a CLK_SYS/fs ratio equal to or higher than required */
535 target = wm8961->sysclk / fs;
536
537 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && target < 64) {
538 dev_err(codec->dev,
539 "SYSCLK must be at least 64*fs for DAC\n");
540 return -EINVAL;
541 }
542 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && target < 256) {
543 dev_err(codec->dev,
544 "SYSCLK must be at least 256*fs for ADC\n");
545 return -EINVAL;
546 }
547
548 for (i = 0; i < ARRAY_SIZE(wm8961_clk_sys_ratio); i++) {
549 if (wm8961_clk_sys_ratio[i].ratio >= target)
550 break;
551 }
552 if (i == ARRAY_SIZE(wm8961_clk_sys_ratio)) {
553 dev_err(codec->dev, "Unable to generate CLK_SYS_RATE\n");
554 return -EINVAL;
555 }
556 dev_dbg(codec->dev, "Selected CLK_SYS_RATE of %d for %d/%d=%d\n",
557 wm8961_clk_sys_ratio[i].ratio, wm8961->sysclk, fs,
558 wm8961->sysclk / fs);
559
8d50e447 560 reg = snd_soc_read(codec, WM8961_CLOCKING_4);
74dc55ed
MB		 561 reg &= ~WM8961_CLK_SYS_RATE_MASK;
562 reg |= wm8961_clk_sys_ratio[i].val << WM8961_CLK_SYS_RATE_SHIFT;
8d50e447 563 snd_soc_write(codec, WM8961_CLOCKING_4, reg);
74dc55ed 564
8d50e447 565 reg = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_0);
74dc55ed 566 reg &= ~WM8961_WL_MASK;
5d3aef91
MB		 567 switch (params_width(params)) {
568 case 16:
74dc55ed 569 break;
5d3aef91 570 case 20:
74dc55ed
MB		 571 reg |= 1 << WM8961_WL_SHIFT;
572 break;
5d3aef91 573 case 24:
74dc55ed
MB		 574 reg |= 2 << WM8961_WL_SHIFT;
575 break;
5d3aef91 576 case 32:
74dc55ed
MB		 577 reg |= 3 << WM8961_WL_SHIFT;
578 break;
579 default:
580 return -EINVAL;
581 }
8d50e447 582 snd_soc_write(codec, WM8961_AUDIO_INTERFACE_0, reg);
74dc55ed
MB		 583
584 /* Sloping stop-band filter is recommended for <= 24kHz */
8d50e447 585 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2);
74dc55ed
MB		 586 if (fs <= 24000)
587 reg |= WM8961_DACSLOPE;
588 else
08b1a384 589 reg &= ~WM8961_DACSLOPE;
8d50e447 590 snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg);
74dc55ed
MB		 591
592 return 0;
593}
594
595static int wm8961_set_sysclk(struct snd_soc_dai *dai, int clk_id,
596 unsigned int freq,
597 int dir)
598{
599 struct snd_soc_codec *codec = dai->codec;
b2c812e2 600 struct wm8961_priv *wm8961 = snd_soc_codec_get_drvdata(codec);
8d50e447 601 u16 reg = snd_soc_read(codec, WM8961_CLOCKING1);
74dc55ed
MB		 602
603 if (freq > 33000000) {
604 dev_err(codec->dev, "MCLK must be <33MHz\n");
605 return -EINVAL;
606 }
607
608 if (freq > 16500000) {
609 dev_dbg(codec->dev, "Using MCLK/2 for %dHz MCLK\n", freq);
610 reg |= WM8961_MCLKDIV;
611 freq /= 2;
612 } else {
613 dev_dbg(codec->dev, "Using MCLK/1 for %dHz MCLK\n", freq);
2f7dceed 614 reg &= ~WM8961_MCLKDIV;
74dc55ed
MB		 615 }
616
8d50e447 617 snd_soc_write(codec, WM8961_CLOCKING1, reg);
74dc55ed
MB		 618
619 wm8961->sysclk = freq;
620
621 return 0;
622}
623
624static int wm8961_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
625{
626 struct snd_soc_codec *codec = dai->codec;
8d50e447 627 u16 aif = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_0);
74dc55ed
MB		 628
629 aif &= ~(WM8961_BCLKINV | WM8961_LRP |
630 WM8961_MS | WM8961_FORMAT_MASK);
631
632 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
633 case SND_SOC_DAIFMT_CBM_CFM:
634 aif |= WM8961_MS;
635 break;
636 case SND_SOC_DAIFMT_CBS_CFS:
637 break;
638 default:
639 return -EINVAL;
640 }
641
642 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
643 case SND_SOC_DAIFMT_RIGHT_J:
644 break;
645
646 case SND_SOC_DAIFMT_LEFT_J:
647 aif |= 1;
648 break;
649
650 case SND_SOC_DAIFMT_I2S:
651 aif |= 2;
652 break;
653
654 case SND_SOC_DAIFMT_DSP_B:
655 aif |= WM8961_LRP;
656 case SND_SOC_DAIFMT_DSP_A:
657 aif |= 3;
658 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
659 case SND_SOC_DAIFMT_NB_NF:
660 case SND_SOC_DAIFMT_IB_NF:
661 break;
662 default:
663 return -EINVAL;
664 }
665 break;
666
667 default:
668 return -EINVAL;
669 }
670
671 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
672 case SND_SOC_DAIFMT_NB_NF:
673 break;
674 case SND_SOC_DAIFMT_NB_IF:
675 aif |= WM8961_LRP;
676 break;
677 case SND_SOC_DAIFMT_IB_NF:
678 aif |= WM8961_BCLKINV;
679 break;
680 case SND_SOC_DAIFMT_IB_IF:
681 aif |= WM8961_BCLKINV | WM8961_LRP;
682 break;
683 default:
684 return -EINVAL;
685 }
686
8d50e447 687 return snd_soc_write(codec, WM8961_AUDIO_INTERFACE_0, aif);
74dc55ed
MB		 688}
689
690static int wm8961_set_tristate(struct snd_soc_dai *dai, int tristate)
691{
692 struct snd_soc_codec *codec = dai->codec;
8d50e447 693 u16 reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_2);
74dc55ed
MB		 694
695 if (tristate)
696 reg |= WM8961_TRIS;
697 else
698 reg &= ~WM8961_TRIS;
699
8d50e447 700 return snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_2, reg);
74dc55ed
MB		 701}
702
703static int wm8961_digital_mute(struct snd_soc_dai *dai, int mute)
704{
705 struct snd_soc_codec *codec = dai->codec;
8d50e447 706 u16 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_1);
74dc55ed
MB		 707
708 if (mute)
709 reg |= WM8961_DACMU;
710 else
711 reg &= ~WM8961_DACMU;
712
713 msleep(17);
714
8d50e447 715 return snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_1, reg);
74dc55ed
MB		 716}
717
718static int wm8961_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
719{
720 struct snd_soc_codec *codec = dai->codec;
721 u16 reg;
722
723 switch (div_id) {
724 case WM8961_BCLK:
8d50e447 725 reg = snd_soc_read(codec, WM8961_CLOCKING2);
74dc55ed
MB		 726 reg &= ~WM8961_BCLKDIV_MASK;
727 reg |= div;
8d50e447 728 snd_soc_write(codec, WM8961_CLOCKING2, reg);
74dc55ed
MB		 729 break;
730
731 case WM8961_LRCLK:
8d50e447 732 reg = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_2);
74dc55ed
MB		 733 reg &= ~WM8961_LRCLK_RATE_MASK;
734 reg |= div;
8d50e447 735 snd_soc_write(codec, WM8961_AUDIO_INTERFACE_2, reg);
74dc55ed
MB		 736 break;
737
738 default:
739 return -EINVAL;
740 }
741
742 return 0;
743}
744
745static int wm8961_set_bias_level(struct snd_soc_codec *codec,
746 enum snd_soc_bias_level level)
747{
748 u16 reg;
749
750 /* This is all slightly unusual since we have no bypass paths
751 * and the output amplifier structure means we can just slam
752 * the biases straight up rather than having to ramp them
753 * slowly.
754 */
755 switch (level) {
756 case SND_SOC_BIAS_ON:
757 break;
758
759 case SND_SOC_BIAS_PREPARE:
049e17d7 760 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY) {
74dc55ed 761 /* Enable bias generation */
8d50e447 762 reg = snd_soc_read(codec, WM8961_ANTI_POP);
74dc55ed 763 reg |= WM8961_BUFIOEN | WM8961_BUFDCOPEN;
8d50e447 764 snd_soc_write(codec, WM8961_ANTI_POP, reg);
74dc55ed
MB		 765
766 /* VMID=2*50k, VREF */
8d50e447 767 reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
74dc55ed
MB		 768 reg &= ~WM8961_VMIDSEL_MASK;
769 reg |= (1 << WM8961_VMIDSEL_SHIFT) | WM8961_VREF;
8d50e447 770 snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
74dc55ed
MB		 771 }
772 break;
773
774 case SND_SOC_BIAS_STANDBY:
049e17d7 775 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_PREPARE) {
74dc55ed 776 /* VREF off */
8d50e447 777 reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
74dc55ed 778 reg &= ~WM8961_VREF;
8d50e447 779 snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
74dc55ed
MB		 780
781 /* Bias generation off */
8d50e447 782 reg = snd_soc_read(codec, WM8961_ANTI_POP);
74dc55ed 783 reg &= ~(WM8961_BUFIOEN | WM8961_BUFDCOPEN);
8d50e447 784 snd_soc_write(codec, WM8961_ANTI_POP, reg);
74dc55ed
MB		 785
786 /* VMID off */
8d50e447 787 reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
74dc55ed 788 reg &= ~WM8961_VMIDSEL_MASK;
8d50e447 789 snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
74dc55ed
MB		 790 }
791 break;
792
793 case SND_SOC_BIAS_OFF:
794 break;
795 }
796
74dc55ed
MB		 797 return 0;
798}
799
800
801#define WM8961_RATES SNDRV_PCM_RATE_8000_48000
802
803#define WM8961_FORMATS \
804 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
805 SNDRV_PCM_FMTBIT_S24_LE)
806
85e7652d 807static const struct snd_soc_dai_ops wm8961_dai_ops = {
74dc55ed
MB		 808 .hw_params = wm8961_hw_params,
809 .set_sysclk = wm8961_set_sysclk,
810 .set_fmt = wm8961_set_fmt,
811 .digital_mute = wm8961_digital_mute,
812 .set_tristate = wm8961_set_tristate,
813 .set_clkdiv = wm8961_set_clkdiv,
814};
815
f0fba2ad
LG		 816static struct snd_soc_dai_driver wm8961_dai = {
817 .name = "wm8961-hifi",
74dc55ed
MB		 818 .playback = {
819 .stream_name = "HiFi Playback",
820 .channels_min = 1,
821 .channels_max = 2,
822 .rates = WM8961_RATES,
823 .formats = WM8961_FORMATS,},
824 .capture = {
825 .stream_name = "HiFi Capture",
826 .channels_min = 1,
827 .channels_max = 2,
828 .rates = WM8961_RATES,
829 .formats = WM8961_FORMATS,},
830 .ops = &wm8961_dai_ops,
831};
74dc55ed 832
f0fba2ad 833static int wm8961_probe(struct snd_soc_codec *codec)
74dc55ed 834{
74dc55ed
MB		 835 u16 reg;
836
74dc55ed 837 /* Enable class W */
8d50e447 838 reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_B);
74dc55ed 839 reg |= WM8961_CP_DYN_PWR_MASK;
8d50e447 840 snd_soc_write(codec, WM8961_CHARGE_PUMP_B, reg);
74dc55ed
MB		 841
842 /* Latch volume update bits (right channel only, we always
843 * write both out) and default ZC on. */
8d50e447
MB		 844 reg = snd_soc_read(codec, WM8961_ROUT1_VOLUME);
845 snd_soc_write(codec, WM8961_ROUT1_VOLUME,
74dc55ed 846 reg | WM8961_LO1ZC | WM8961_OUT1VU);
8d50e447
MB		 847 snd_soc_write(codec, WM8961_LOUT1_VOLUME, reg | WM8961_LO1ZC);
848 reg = snd_soc_read(codec, WM8961_ROUT2_VOLUME);
849 snd_soc_write(codec, WM8961_ROUT2_VOLUME,
74dc55ed 850 reg | WM8961_SPKRZC | WM8961_SPKVU);
8d50e447 851 snd_soc_write(codec, WM8961_LOUT2_VOLUME, reg | WM8961_SPKLZC);
74dc55ed 852
8d50e447
MB		 853 reg = snd_soc_read(codec, WM8961_RIGHT_ADC_VOLUME);
854 snd_soc_write(codec, WM8961_RIGHT_ADC_VOLUME, reg | WM8961_ADCVU);
855 reg = snd_soc_read(codec, WM8961_RIGHT_INPUT_VOLUME);
856 snd_soc_write(codec, WM8961_RIGHT_INPUT_VOLUME, reg | WM8961_IPVU);
74dc55ed
MB		 857
858 /* Use soft mute by default */
8d50e447 859 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2);
74dc55ed 860 reg |= WM8961_DACSMM;
8d50e447 861 snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg);
74dc55ed
MB		 862
863 /* Use automatic clocking mode by default; for now this is all
864 * we support.
865 */
8d50e447 866 reg = snd_soc_read(codec, WM8961_CLOCKING_3);
74dc55ed 867 reg &= ~WM8961_MANUAL_MODE;
8d50e447 868 snd_soc_write(codec, WM8961_CLOCKING_3, reg);
74dc55ed 869
f0fba2ad
LG		 870 return 0;
871}
74dc55ed 872
f0fba2ad 873#ifdef CONFIG_PM
74dc55ed 874
f0fba2ad 875static int wm8961_resume(struct snd_soc_codec *codec)
74dc55ed 876{
202a51a8 877 snd_soc_cache_sync(codec);
f0fba2ad 878
f0fba2ad 879 return 0;
74dc55ed 880}
f0fba2ad 881#else
f0fba2ad
LG		 882#define wm8961_resume NULL
883#endif
74dc55ed 884
f802d6c0 885static const struct snd_soc_codec_driver soc_codec_dev_wm8961 = {
f0fba2ad 886 .probe = wm8961_probe,
f0fba2ad
LG		 887 .resume = wm8961_resume,
888 .set_bias_level = wm8961_set_bias_level,
7bea32c5 889 .suspend_bias_off = true,
c4f50dbc 890
5e731b7e
KM		 891 .component_driver = {
892 .controls = wm8961_snd_controls,
893 .num_controls = ARRAY_SIZE(wm8961_snd_controls),
894 .dapm_widgets = wm8961_dapm_widgets,
895 .num_dapm_widgets = ARRAY_SIZE(wm8961_dapm_widgets),
896 .dapm_routes = audio_paths,
897 .num_dapm_routes = ARRAY_SIZE(audio_paths),
898 },
35ecf7cd
MB		 899};
900
901static const struct regmap_config wm8961_regmap = {
902 .reg_bits = 8,
903 .val_bits = 16,
904 .max_register = WM8961_MAX_REGISTER,
905
906 .reg_defaults = wm8961_reg_defaults,
907 .num_reg_defaults = ARRAY_SIZE(wm8961_reg_defaults),
908 .cache_type = REGCACHE_RBTREE,
909
910 .volatile_reg = wm8961_volatile,
911 .readable_reg = wm8961_readable,
f0fba2ad
LG		 912};
913
7a79e94e
BP		 914static int wm8961_i2c_probe(struct i2c_client *i2c,
915 const struct i2c_device_id *id)
74dc55ed
MB		 916{
917 struct wm8961_priv *wm8961;
b306e84f 918 unsigned int val;
f0fba2ad 919 int ret;
74dc55ed 920
2ec2a906
MB		 921 wm8961 = devm_kzalloc(&i2c->dev, sizeof(struct wm8961_priv),
922 GFP_KERNEL);
74dc55ed
MB		 923 if (wm8961 == NULL)
924 return -ENOMEM;
925
35ecf7cd
MB		 926 wm8961->regmap = devm_regmap_init_i2c(i2c, &wm8961_regmap);
927 if (IS_ERR(wm8961->regmap))
928 return PTR_ERR(wm8961->regmap);
929
b306e84f
MB		 930 ret = regmap_read(wm8961->regmap, WM8961_SOFTWARE_RESET, &val);
931 if (ret != 0) {
932 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
933 return ret;
934 }
935
936 if (val != 0x1801) {
937 dev_err(&i2c->dev, "Device is not a WM8961: ID=0x%x\n", val);
938 return -EINVAL;
939 }
940
941 /* This isn't volatile - readback doesn't correspond to write */
942 regcache_cache_bypass(wm8961->regmap, true);
943 ret = regmap_read(wm8961->regmap, WM8961_RIGHT_INPUT_VOLUME, &val);
944 regcache_cache_bypass(wm8961->regmap, false);
945
946 if (ret != 0) {
947 dev_err(&i2c->dev, "Failed to read chip revision: %d\n", ret);
948 return ret;
949 }
950
951 dev_info(&i2c->dev, "WM8961 family %d revision %c\n",
952 (val & WM8961_DEVICE_ID_MASK) >> WM8961_DEVICE_ID_SHIFT,
953 ((val & WM8961_CHIP_REV_MASK) >> WM8961_CHIP_REV_SHIFT)
954 + 'A');
955
956 ret = regmap_write(wm8961->regmap, WM8961_SOFTWARE_RESET, 0x1801);
957 if (ret != 0) {
958 dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
959 return ret;
960 }
961
74dc55ed 962 i2c_set_clientdata(i2c, wm8961);
74dc55ed 963
f0fba2ad
LG		 964 ret = snd_soc_register_codec(&i2c->dev,
965 &soc_codec_dev_wm8961, &wm8961_dai, 1);
2ec2a906 966
f0fba2ad 967 return ret;
74dc55ed
MB		 968}
969
7a79e94e 970static int wm8961_i2c_remove(struct i2c_client *client)
74dc55ed 971{
f0fba2ad 972 snd_soc_unregister_codec(&client->dev);
2ec2a906 973
74dc55ed
MB		 974 return 0;
975}
976
977static const struct i2c_device_id wm8961_i2c_id[] = {
978 { "wm8961", 0 },
979 { }
980};
981MODULE_DEVICE_TABLE(i2c, wm8961_i2c_id);
982
983static struct i2c_driver wm8961_i2c_driver = {
984 .driver = {
091edccf 985 .name = "wm8961",
74dc55ed
MB		 986 },
987 .probe = wm8961_i2c_probe,
7a79e94e 988 .remove = wm8961_i2c_remove,
74dc55ed
MB		 989 .id_table = wm8961_i2c_id,
990};
991
8b08eb28 992module_i2c_driver(wm8961_i2c_driver);
74dc55ed 993
74dc55ed
MB		 994MODULE_DESCRIPTION("ASoC WM8961 driver");
995MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
996MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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