Merge remote-tracking branch 'ftrace/for-next'
[deliverable/linux.git] / sound / soc / intel / skylake / skl-tplg-interface.h
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1/*
2 * skl-tplg-interface.h - Intel DSP FW private data interface
3 *
4 * Copyright (C) 2015 Intel Corp
5 * Author: Jeeja KP <jeeja.kp@intel.com>
6 * Nilofer, Samreen <samreen.nilofer@intel.com>
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 */
18
19#ifndef __HDA_TPLG_INTERFACE_H__
20#define __HDA_TPLG_INTERFACE_H__
21
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22/*
23 * Default types range from 0~12. type can range from 0 to 0xff
24 * SST types start at higher to avoid any overlapping in future
25 */
140adfba 26#define SKL_CONTROL_TYPE_BYTE_TLV 0x100
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27
28#define HDA_SST_CFG_MAX 900 /* size of copier cfg*/
29#define MAX_IN_QUEUE 8
30#define MAX_OUT_QUEUE 8
31
65aecfa8 32#define SKL_UUID_STR_SZ 40
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33/* Event types goes here */
34/* Reserve event type 0 for no event handlers */
35enum skl_event_types {
36 SKL_EVENT_NONE = 0,
37 SKL_MIXER_EVENT,
38 SKL_MUX_EVENT,
39 SKL_VMIXER_EVENT,
40 SKL_PGA_EVENT
41};
42
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43/**
44 * enum skl_ch_cfg - channel configuration
45 *
46 * @SKL_CH_CFG_MONO: One channel only
47 * @SKL_CH_CFG_STEREO: L & R
48 * @SKL_CH_CFG_2_1: L, R & LFE
49 * @SKL_CH_CFG_3_0: L, C & R
50 * @SKL_CH_CFG_3_1: L, C, R & LFE
51 * @SKL_CH_CFG_QUATRO: L, R, Ls & Rs
52 * @SKL_CH_CFG_4_0: L, C, R & Cs
53 * @SKL_CH_CFG_5_0: L, C, R, Ls & Rs
54 * @SKL_CH_CFG_5_1: L, C, R, Ls, Rs & LFE
55 * @SKL_CH_CFG_DUAL_MONO: One channel replicated in two
56 * @SKL_CH_CFG_I2S_DUAL_STEREO_0: Stereo(L,R) in 4 slots, 1st stream:[ L, R, -, - ]
57 * @SKL_CH_CFG_I2S_DUAL_STEREO_1: Stereo(L,R) in 4 slots, 2nd stream:[ -, -, L, R ]
58 * @SKL_CH_CFG_INVALID: Invalid
59 */
60enum skl_ch_cfg {
61 SKL_CH_CFG_MONO = 0,
62 SKL_CH_CFG_STEREO = 1,
63 SKL_CH_CFG_2_1 = 2,
64 SKL_CH_CFG_3_0 = 3,
65 SKL_CH_CFG_3_1 = 4,
66 SKL_CH_CFG_QUATRO = 5,
67 SKL_CH_CFG_4_0 = 6,
68 SKL_CH_CFG_5_0 = 7,
69 SKL_CH_CFG_5_1 = 8,
70 SKL_CH_CFG_DUAL_MONO = 9,
71 SKL_CH_CFG_I2S_DUAL_STEREO_0 = 10,
72 SKL_CH_CFG_I2S_DUAL_STEREO_1 = 11,
04afbbbb 73 SKL_CH_CFG_4_CHANNEL = 12,
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74 SKL_CH_CFG_INVALID
75};
76
77enum skl_module_type {
78 SKL_MODULE_TYPE_MIXER = 0,
79 SKL_MODULE_TYPE_COPIER,
80 SKL_MODULE_TYPE_UPDWMIX,
399b210b 81 SKL_MODULE_TYPE_SRCINT,
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82 SKL_MODULE_TYPE_ALGO,
83 SKL_MODULE_TYPE_BASE_OUTFMT
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84};
85
86enum skl_core_affinity {
87 SKL_AFFINITY_CORE_0 = 0,
88 SKL_AFFINITY_CORE_1,
89 SKL_AFFINITY_CORE_MAX
90};
91
92enum skl_pipe_conn_type {
93 SKL_PIPE_CONN_TYPE_NONE = 0,
94 SKL_PIPE_CONN_TYPE_FE,
95 SKL_PIPE_CONN_TYPE_BE
96};
97
98enum skl_hw_conn_type {
99 SKL_CONN_NONE = 0,
100 SKL_CONN_SOURCE = 1,
101 SKL_CONN_SINK = 2
102};
103
104enum skl_dev_type {
105 SKL_DEVICE_BT = 0x0,
106 SKL_DEVICE_DMIC = 0x1,
107 SKL_DEVICE_I2S = 0x2,
108 SKL_DEVICE_SLIMBUS = 0x3,
109 SKL_DEVICE_HDALINK = 0x4,
bfa764ac 110 SKL_DEVICE_HDAHOST = 0x5,
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111 SKL_DEVICE_NONE
112};
3af36706 113
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114/**
115 * enum skl_interleaving - interleaving style
116 *
117 * @SKL_INTERLEAVING_PER_CHANNEL: [s1_ch1...s1_chN,...,sM_ch1...sM_chN]
118 * @SKL_INTERLEAVING_PER_SAMPLE: [s1_ch1...sM_ch1,...,s1_chN...sM_chN]
119 */
120enum skl_interleaving {
121 SKL_INTERLEAVING_PER_CHANNEL = 0,
122 SKL_INTERLEAVING_PER_SAMPLE = 1,
123};
124
125enum skl_sample_type {
126 SKL_SAMPLE_TYPE_INT_MSB = 0,
127 SKL_SAMPLE_TYPE_INT_LSB = 1,
128 SKL_SAMPLE_TYPE_INT_SIGNED = 2,
129 SKL_SAMPLE_TYPE_INT_UNSIGNED = 3,
130 SKL_SAMPLE_TYPE_FLOAT = 4
131};
132
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133enum module_pin_type {
134 /* All pins of the module takes same PCM inputs or outputs
135 * e.g. mixout
136 */
137 SKL_PIN_TYPE_HOMOGENEOUS,
138 /* All pins of the module takes different PCM inputs or outputs
139 * e.g mux
140 */
141 SKL_PIN_TYPE_HETEROGENEOUS,
142};
143
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144enum skl_module_param_type {
145 SKL_PARAM_DEFAULT = 0,
146 SKL_PARAM_INIT,
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147 SKL_PARAM_SET,
148 SKL_PARAM_BIND
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149};
150
3af36706 151struct skl_dfw_algo_data {
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152 u32 set_params:2;
153 u32 rsvd:30;
140adfba 154 u32 param_id;
4ced1827 155 u32 max;
04afbbbb 156 char params[0];
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157} __packed;
158
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159#define LIB_NAME_LENGTH 128
160#define HDA_MAX_LIB 16
161
162struct lib_info {
163 char name[LIB_NAME_LENGTH];
164} __packed;
165
166struct skl_dfw_manifest {
167 u32 lib_count;
168 struct lib_info lib[HDA_MAX_LIB];
169} __packed;
170
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171enum skl_tkn_dir {
172 SKL_DIR_IN,
173 SKL_DIR_OUT
174};
175
176enum skl_tuple_type {
177 SKL_TYPE_TUPLE,
178 SKL_TYPE_DATA
179};
180
23db472b 181#endif
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