[deliverable/linux.git] / sound / soc / qcom / lpass-platform.c

/*
 * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * lpass-platform.c -- ALSA SoC platform driver for QTi LPASS
 */

#include <linux/dma-mapping.h>
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <sound/pcm_params.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "lpass-lpaif-reg.h"
#include "lpass.h"

struct lpass_pcm_data {
	int rdma_ch;
	int wrdma_ch;
	int i2s_port;
};

#define LPASS_PLATFORM_BUFFER_SIZE	(16 * 1024)
#define LPASS_PLATFORM_PERIODS		2

static struct snd_pcm_hardware lpass_platform_pcm_hardware = {
	.info			=	SNDRV_PCM_INFO_MMAP |
					SNDRV_PCM_INFO_MMAP_VALID |
					SNDRV_PCM_INFO_INTERLEAVED |
					SNDRV_PCM_INFO_PAUSE |
					SNDRV_PCM_INFO_RESUME,
	.formats		=	SNDRV_PCM_FMTBIT_S16 |
					SNDRV_PCM_FMTBIT_S24 |
					SNDRV_PCM_FMTBIT_S32,
	.rates			=	SNDRV_PCM_RATE_8000_192000,
	.rate_min		=	8000,
	.rate_max		=	192000,
	.channels_min		=	1,
	.channels_max		=	8,
	.buffer_bytes_max	=	LPASS_PLATFORM_BUFFER_SIZE,
	.period_bytes_max	=	LPASS_PLATFORM_BUFFER_SIZE /
						LPASS_PLATFORM_PERIODS,
	.period_bytes_min	=	LPASS_PLATFORM_BUFFER_SIZE /
						LPASS_PLATFORM_PERIODS,
	.periods_min		=	LPASS_PLATFORM_PERIODS,
	.periods_max		=	LPASS_PLATFORM_PERIODS,
	.fifo_size		=	0,
};

static int lpass_platform_pcmops_open(struct snd_pcm_substream *substream)
{
	struct snd_pcm_runtime *runtime = substream->runtime;
	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	int ret;

	snd_soc_set_runtime_hwparams(substream, &lpass_platform_pcm_hardware);

	runtime->dma_bytes = lpass_platform_pcm_hardware.buffer_bytes_max;

	ret = snd_pcm_hw_constraint_integer(runtime,
			SNDRV_PCM_HW_PARAM_PERIODS);
	if (ret < 0) {
		dev_err(soc_runtime->dev, "%s() setting constraints failed: %d\n",
				__func__, ret);
		return -EINVAL;
	}

	snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);

	return 0;
}

static int lpass_platform_pcmops_hw_params(struct snd_pcm_substream *substream,
		struct snd_pcm_hw_params *params)
{
	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	struct lpass_data *drvdata =
		snd_soc_platform_get_drvdata(soc_runtime->platform);
	struct lpass_pcm_data *pcm_data = drvdata->private_data;
	struct lpass_variant *v = drvdata->variant;
	snd_pcm_format_t format = params_format(params);
	unsigned int channels = params_channels(params);
	unsigned int regval;
	int ch, dir = substream->stream;
	int bitwidth;
	int ret, dma_port = pcm_data->i2s_port + v->dmactl_audif_start;

	if (dir ==  SNDRV_PCM_STREAM_PLAYBACK)
		ch = pcm_data->rdma_ch;
	else
		ch = pcm_data->wrdma_ch;

	bitwidth = snd_pcm_format_width(format);
	if (bitwidth < 0) {
		dev_err(soc_runtime->dev, "%s() invalid bit width given: %d\n",
				__func__, bitwidth);
		return bitwidth;
	}

	regval = LPAIF_DMACTL_BURSTEN_INCR4 |
			LPAIF_DMACTL_AUDINTF(dma_port) |
			LPAIF_DMACTL_FIFOWM_8;

	switch (bitwidth) {
	case 16:
		switch (channels) {
		case 1:
		case 2:
			regval |= LPAIF_DMACTL_WPSCNT_ONE;
			break;
		case 4:
			regval |= LPAIF_DMACTL_WPSCNT_TWO;
			break;
		case 6:
			regval |= LPAIF_DMACTL_WPSCNT_THREE;
			break;
		case 8:
			regval |= LPAIF_DMACTL_WPSCNT_FOUR;
			break;
		default:
			dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n",
					__func__, bitwidth, channels);
			return -EINVAL;
		}
		break;
	case 24:
	case 32:
		switch (channels) {
		case 1:
			regval |= LPAIF_DMACTL_WPSCNT_ONE;
			break;
		case 2:
			regval |= LPAIF_DMACTL_WPSCNT_TWO;
			break;
		case 4:
			regval |= LPAIF_DMACTL_WPSCNT_FOUR;
			break;
		case 6:
			regval |= LPAIF_DMACTL_WPSCNT_SIX;
			break;
		case 8:
			regval |= LPAIF_DMACTL_WPSCNT_EIGHT;
			break;
		default:
			dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n",
					__func__, bitwidth, channels);
			return -EINVAL;
		}
		break;
	default:
		dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n",
				__func__, bitwidth, channels);
		return -EINVAL;
	}

	ret = regmap_write(drvdata->lpaif_map,
			LPAIF_DMACTL_REG(v, ch, dir), regval);
	if (ret) {
		dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
				__func__, ret);
		return ret;
	}

	return 0;
}

static int lpass_platform_pcmops_hw_free(struct snd_pcm_substream *substream)
{
	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	struct lpass_data *drvdata =
		snd_soc_platform_get_drvdata(soc_runtime->platform);
	struct lpass_pcm_data *pcm_data = drvdata->private_data;
	struct lpass_variant *v = drvdata->variant;
	unsigned int reg;
	int ret;

	if (substream->stream ==  SNDRV_PCM_STREAM_PLAYBACK)
		reg = LPAIF_RDMACTL_REG(v, pcm_data->rdma_ch);
	else
		reg = LPAIF_WRDMACTL_REG(v, pcm_data->wrdma_ch);

	ret = regmap_write(drvdata->lpaif_map, reg, 0);
	if (ret)
		dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
				__func__, ret);

	return ret;
}

static int lpass_platform_pcmops_prepare(struct snd_pcm_substream *substream)
{
	struct snd_pcm_runtime *runtime = substream->runtime;
	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	struct lpass_data *drvdata =
		snd_soc_platform_get_drvdata(soc_runtime->platform);
	struct lpass_pcm_data *pcm_data = drvdata->private_data;
	struct lpass_variant *v = drvdata->variant;
	int ret, ch, dir = substream->stream;

	if (dir ==  SNDRV_PCM_STREAM_PLAYBACK)
		ch = pcm_data->rdma_ch;
	else
		ch = pcm_data->wrdma_ch;

	ret = regmap_write(drvdata->lpaif_map,
			LPAIF_DMABASE_REG(v, ch, dir),
			runtime->dma_addr);
	if (ret) {
		dev_err(soc_runtime->dev, "%s() error writing to rdmabase reg: %d\n",
				__func__, ret);
		return ret;
	}

	ret = regmap_write(drvdata->lpaif_map,
			LPAIF_DMABUFF_REG(v, ch, dir),
			(snd_pcm_lib_buffer_bytes(substream) >> 2) - 1);
	if (ret) {
		dev_err(soc_runtime->dev, "%s() error writing to rdmabuff reg: %d\n",
				__func__, ret);
		return ret;
	}

	ret = regmap_write(drvdata->lpaif_map,
			LPAIF_DMAPER_REG(v, ch, dir),
			(snd_pcm_lib_period_bytes(substream) >> 2) - 1);
	if (ret) {
		dev_err(soc_runtime->dev, "%s() error writing to rdmaper reg: %d\n",
				__func__, ret);
		return ret;
	}

	ret = regmap_update_bits(drvdata->lpaif_map,
			LPAIF_DMACTL_REG(v, ch, dir),
			LPAIF_DMACTL_ENABLE_MASK, LPAIF_DMACTL_ENABLE_ON);
	if (ret) {
		dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
				__func__, ret);
		return ret;
	}

	return 0;
}

static int lpass_platform_pcmops_trigger(struct snd_pcm_substream *substream,
		int cmd)
{
	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	struct lpass_data *drvdata =
		snd_soc_platform_get_drvdata(soc_runtime->platform);
	struct lpass_pcm_data *pcm_data = drvdata->private_data;
	struct lpass_variant *v = drvdata->variant;
	int ret, ch, dir = substream->stream;

	if (dir == SNDRV_PCM_STREAM_PLAYBACK)
		ch = pcm_data->rdma_ch;
	else
		ch = pcm_data->wrdma_ch;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		/* clear status before enabling interrupts */
		ret = regmap_write(drvdata->lpaif_map,
				LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
				LPAIF_IRQ_ALL(ch));
		if (ret) {
			dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
					__func__, ret);
			return ret;
		}

		ret = regmap_update_bits(drvdata->lpaif_map,
				LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST),
				LPAIF_IRQ_ALL(ch),
				LPAIF_IRQ_ALL(ch));
		if (ret) {
			dev_err(soc_runtime->dev, "%s() error writing to irqen reg: %d\n",
					__func__, ret);
			return ret;
		}

		ret = regmap_update_bits(drvdata->lpaif_map,
				LPAIF_DMACTL_REG(v, ch, dir),
				LPAIF_DMACTL_ENABLE_MASK,
				LPAIF_DMACTL_ENABLE_ON);
		if (ret) {
			dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
					__func__, ret);
			return ret;
		}
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		ret = regmap_update_bits(drvdata->lpaif_map,
				LPAIF_DMACTL_REG(v, ch, dir),
				LPAIF_DMACTL_ENABLE_MASK,
				LPAIF_DMACTL_ENABLE_OFF);
		if (ret) {
			dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
					__func__, ret);
			return ret;
		}

		ret = regmap_update_bits(drvdata->lpaif_map,
				LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST),
				LPAIF_IRQ_ALL(ch), 0);
		if (ret) {
			dev_err(soc_runtime->dev, "%s() error writing to irqen reg: %d\n",
					__func__, ret);
			return ret;
		}
		break;
	}

	return 0;
}

static snd_pcm_uframes_t lpass_platform_pcmops_pointer(
		struct snd_pcm_substream *substream)
{
	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	struct lpass_data *drvdata =
			snd_soc_platform_get_drvdata(soc_runtime->platform);
	struct lpass_pcm_data *pcm_data = drvdata->private_data;
	struct lpass_variant *v = drvdata->variant;
	unsigned int base_addr, curr_addr;
	int ret, ch, dir = substream->stream;

	if (dir == SNDRV_PCM_STREAM_PLAYBACK)
		ch = pcm_data->rdma_ch;
	else
		ch = pcm_data->wrdma_ch;

	ret = regmap_read(drvdata->lpaif_map,
			LPAIF_DMABASE_REG(v, ch, dir), &base_addr);
	if (ret) {
		dev_err(soc_runtime->dev, "%s() error reading from rdmabase reg: %d\n",
				__func__, ret);
		return ret;
	}

	ret = regmap_read(drvdata->lpaif_map,
			LPAIF_DMACURR_REG(v, ch, dir), &curr_addr);
	if (ret) {
		dev_err(soc_runtime->dev, "%s() error reading from rdmacurr reg: %d\n",
				__func__, ret);
		return ret;
	}

	return bytes_to_frames(substream->runtime, curr_addr - base_addr);
}

static int lpass_platform_pcmops_mmap(struct snd_pcm_substream *substream,
		struct vm_area_struct *vma)
{
	struct snd_pcm_runtime *runtime = substream->runtime;

	return dma_mmap_coherent(substream->pcm->card->dev, vma,
			runtime->dma_area, runtime->dma_addr,
			runtime->dma_bytes);
}

static const struct snd_pcm_ops lpass_platform_pcm_ops = {
	.open		= lpass_platform_pcmops_open,
	.ioctl		= snd_pcm_lib_ioctl,
	.hw_params	= lpass_platform_pcmops_hw_params,
	.hw_free	= lpass_platform_pcmops_hw_free,
	.prepare	= lpass_platform_pcmops_prepare,
	.trigger	= lpass_platform_pcmops_trigger,
	.pointer	= lpass_platform_pcmops_pointer,
	.mmap		= lpass_platform_pcmops_mmap,
};

static irqreturn_t lpass_dma_interrupt_handler(
			struct snd_pcm_substream *substream,
			struct lpass_data *drvdata,
			int chan, u32 interrupts)
{
	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	struct lpass_variant *v = drvdata->variant;
	irqreturn_t ret = IRQ_NONE;
	int rv;

	if (interrupts & LPAIF_IRQ_PER(chan)) {
		rv = regmap_write(drvdata->lpaif_map,
				LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
				LPAIF_IRQ_PER(chan));
		if (rv) {
			dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
					__func__, rv);
			return IRQ_NONE;
		}
		snd_pcm_period_elapsed(substream);
		ret = IRQ_HANDLED;
	}

	if (interrupts & LPAIF_IRQ_XRUN(chan)) {
		rv = regmap_write(drvdata->lpaif_map,
				LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
				LPAIF_IRQ_XRUN(chan));
		if (rv) {
			dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
					__func__, rv);
			return IRQ_NONE;
		}
		dev_warn(soc_runtime->dev, "%s() xrun warning\n", __func__);
		snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
		ret = IRQ_HANDLED;
	}

	if (interrupts & LPAIF_IRQ_ERR(chan)) {
		rv = regmap_write(drvdata->lpaif_map,
				LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
				LPAIF_IRQ_ERR(chan));
		if (rv) {
			dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
					__func__, rv);
			return IRQ_NONE;
		}
		dev_err(soc_runtime->dev, "%s() bus access error\n", __func__);
		snd_pcm_stop(substream, SNDRV_PCM_STATE_DISCONNECTED);
		ret = IRQ_HANDLED;
	}

	return ret;
}

static irqreturn_t lpass_platform_lpaif_irq(int irq, void *data)
{
	struct lpass_data *drvdata = data;
	struct lpass_variant *v = drvdata->variant;
	unsigned int irqs;
	int rv, chan;

	rv = regmap_read(drvdata->lpaif_map,
			LPAIF_IRQSTAT_REG(v, LPAIF_IRQ_PORT_HOST), &irqs);
	if (rv) {
		pr_err("%s() error reading from irqstat reg: %d\n",
				__func__, rv);
		return IRQ_NONE;
	}

	/* Handle per channel interrupts */
	for (chan = 0; chan < LPASS_MAX_DMA_CHANNELS; chan++) {
		if (irqs & LPAIF_IRQ_ALL(chan) && drvdata->substream[chan]) {
			rv = lpass_dma_interrupt_handler(
						drvdata->substream[chan],
						drvdata, chan, irqs);
			if (rv != IRQ_HANDLED)
				return rv;
		}
	}

	return IRQ_HANDLED;
}

static int lpass_platform_pcm_new(struct snd_soc_pcm_runtime *soc_runtime)
{
	struct snd_pcm *pcm = soc_runtime->pcm;
	struct snd_pcm_substream *psubstream, *csubstream;
	struct snd_soc_dai *cpu_dai = soc_runtime->cpu_dai;
	struct lpass_data *drvdata =
		snd_soc_platform_get_drvdata(soc_runtime->platform);
	struct lpass_variant *v = drvdata->variant;
	int ret = -EINVAL;
	struct lpass_pcm_data *data;
	size_t size = lpass_platform_pcm_hardware.buffer_bytes_max;

	data = devm_kzalloc(soc_runtime->dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->i2s_port = cpu_dai->driver->id;
	drvdata->private_data = data;

	psubstream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
	if (psubstream) {
		if (v->alloc_dma_channel)
			data->rdma_ch = v->alloc_dma_channel(drvdata,
						SNDRV_PCM_STREAM_PLAYBACK);

		if (data->rdma_ch < 0)
			return data->rdma_ch;

		drvdata->substream[data->rdma_ch] = psubstream;

		ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
					soc_runtime->platform->dev,
					size, &psubstream->dma_buffer);
		if (ret)
			goto playback_alloc_err;

		ret = regmap_write(drvdata->lpaif_map,
			LPAIF_RDMACTL_REG(v, data->rdma_ch), 0);
		if (ret) {
			dev_err(soc_runtime->dev,
				"%s() error writing to rdmactl reg: %d\n",
				__func__, ret);
			goto capture_alloc_err;
		}
	}

	csubstream = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream;
	if (csubstream) {
		if (v->alloc_dma_channel)
			data->wrdma_ch = v->alloc_dma_channel(drvdata,
						SNDRV_PCM_STREAM_CAPTURE);

		if (data->wrdma_ch < 0) {
			ret = data->wrdma_ch;
			goto capture_alloc_err;
		}

		drvdata->substream[data->wrdma_ch] = csubstream;

		ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
					soc_runtime->platform->dev,
					size, &csubstream->dma_buffer);
		if (ret)
			goto capture_alloc_err;

		ret = regmap_write(drvdata->lpaif_map,
			LPAIF_WRDMACTL_REG(v, data->wrdma_ch), 0);
		if (ret) {
			dev_err(soc_runtime->dev,
				"%s() error writing to wrdmactl reg: %d\n",
				__func__, ret);
			goto capture_reg_err;
		}
	}

	return 0;

capture_reg_err:
	if (csubstream)
		snd_dma_free_pages(&csubstream->dma_buffer);

capture_alloc_err:
	if (psubstream)
		snd_dma_free_pages(&psubstream->dma_buffer);

 playback_alloc_err:
	dev_err(soc_runtime->dev, "Cannot allocate buffer(s)\n");

	return ret;
}

static void lpass_platform_pcm_free(struct snd_pcm *pcm)
{
	struct snd_soc_pcm_runtime *rt;
	struct lpass_data *drvdata;
	struct lpass_pcm_data *data;
	struct lpass_variant *v;
	struct snd_pcm_substream *substream;
	int ch, i;

	for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) {
		substream = pcm->streams[i].substream;
		if (substream) {
			rt = substream->private_data;
			drvdata = snd_soc_platform_get_drvdata(rt->platform);
			data = drvdata->private_data;

			ch = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
				? data->rdma_ch
				: data->wrdma_ch;
			v = drvdata->variant;
			drvdata->substream[ch] = NULL;
			if (v->free_dma_channel)
				v->free_dma_channel(drvdata, ch);

			snd_dma_free_pages(&substream->dma_buffer);
			substream->dma_buffer.area = NULL;
			substream->dma_buffer.addr = 0;
		}
	}
}

static struct snd_soc_platform_driver lpass_platform_driver = {
	.pcm_new	= lpass_platform_pcm_new,
	.pcm_free	= lpass_platform_pcm_free,
	.ops		= &lpass_platform_pcm_ops,
};

int asoc_qcom_lpass_platform_register(struct platform_device *pdev)
{
	struct lpass_data *drvdata = platform_get_drvdata(pdev);
	struct lpass_variant *v = drvdata->variant;
	int ret;

	drvdata->lpaif_irq = platform_get_irq_byname(pdev, "lpass-irq-lpaif");
	if (drvdata->lpaif_irq < 0) {
		dev_err(&pdev->dev, "%s() error getting irq handle: %d\n",
				__func__, drvdata->lpaif_irq);
		return -ENODEV;
	}

	/* ensure audio hardware is disabled */
	ret = regmap_write(drvdata->lpaif_map,
			LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST), 0);
	if (ret) {
		dev_err(&pdev->dev, "%s() error writing to irqen reg: %d\n",
				__func__, ret);
		return ret;
	}

	ret = devm_request_irq(&pdev->dev, drvdata->lpaif_irq,
			lpass_platform_lpaif_irq, IRQF_TRIGGER_RISING,
			"lpass-irq-lpaif", drvdata);
	if (ret) {
		dev_err(&pdev->dev, "%s() irq request failed: %d\n",
				__func__, ret);
		return ret;
	}


	return devm_snd_soc_register_platform(&pdev->dev,
			&lpass_platform_driver);
}
EXPORT_SYMBOL_GPL(asoc_qcom_lpass_platform_register);

MODULE_DESCRIPTION("QTi LPASS Platform Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
c5c8635a KW	1	/*
	2	* Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 and
	6	* only version 2 as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* lpass-platform.c -- ALSA SoC platform driver for QTi LPASS
	14	*/
	15
c5c8635a	16	#include <linux/dma-mapping.h>
c5c8635a KW	17	#include <linux/export.h>
	18	#include <linux/kernel.h>
	19	#include <linux/module.h>
c5c8635a	20	#include <linux/platform_device.h>
c5c8635a KW	21	#include <sound/pcm_params.h>
	22	#include <linux/regmap.h>
	23	#include <sound/soc.h>
9bae4880	24	#include "lpass-lpaif-reg.h"
c5c8635a KW	25	#include "lpass.h"
c5c8635a KW	26
6db1c6ba SK	27	struct lpass_pcm_data {
6db1c6ba SK	28	int rdma_ch;
fb5d1152	29	int wrdma_ch;
6db1c6ba SK	30	int i2s_port;
	31	};
	32
c5c8635a KW	33	#define LPASS_PLATFORM_BUFFER_SIZE (16 * 1024)
	34	#define LPASS_PLATFORM_PERIODS 2
	35
	36	static struct snd_pcm_hardware lpass_platform_pcm_hardware = {
	37	.info = SNDRV_PCM_INFO_MMAP \|
	38	SNDRV_PCM_INFO_MMAP_VALID \|
	39	SNDRV_PCM_INFO_INTERLEAVED \|
	40	SNDRV_PCM_INFO_PAUSE \|
	41	SNDRV_PCM_INFO_RESUME,
	42	.formats = SNDRV_PCM_FMTBIT_S16 \|
	43	SNDRV_PCM_FMTBIT_S24 \|
	44	SNDRV_PCM_FMTBIT_S32,
	45	.rates = SNDRV_PCM_RATE_8000_192000,
	46	.rate_min = 8000,
	47	.rate_max = 192000,
	48	.channels_min = 1,
	49	.channels_max = 8,
	50	.buffer_bytes_max = LPASS_PLATFORM_BUFFER_SIZE,
	51	.period_bytes_max = LPASS_PLATFORM_BUFFER_SIZE /
	52	LPASS_PLATFORM_PERIODS,
	53	.period_bytes_min = LPASS_PLATFORM_BUFFER_SIZE /
	54	LPASS_PLATFORM_PERIODS,
	55	.periods_min = LPASS_PLATFORM_PERIODS,
	56	.periods_max = LPASS_PLATFORM_PERIODS,
	57	.fifo_size = 0,
	58	};
	59
	60	static int lpass_platform_pcmops_open(struct snd_pcm_substream *substream)
	61	{
	62	struct snd_pcm_runtime *runtime = substream->runtime;
	63	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	64	int ret;
	65
	66	snd_soc_set_runtime_hwparams(substream, &lpass_platform_pcm_hardware);
	67
	68	runtime->dma_bytes = lpass_platform_pcm_hardware.buffer_bytes_max;
	69
	70	ret = snd_pcm_hw_constraint_integer(runtime,
	71	SNDRV_PCM_HW_PARAM_PERIODS);
	72	if (ret < 0) {
	73	dev_err(soc_runtime->dev, "%s() setting constraints failed: %d\n",
	74	__func__, ret);
	75	return -EINVAL;
	76	}
	77
	78	snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
	79
	80	return 0;
	81	}
	82
	83	static int lpass_platform_pcmops_hw_params(struct snd_pcm_substream *substream,
	84	struct snd_pcm_hw_params *params)
	85	{
	86	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	87	struct lpass_data *drvdata =
	88	snd_soc_platform_get_drvdata(soc_runtime->platform);
6adcbdcd	89	struct lpass_pcm_data *pcm_data = drvdata->private_data;
9bae4880	90	struct lpass_variant *v = drvdata->variant;
c5c8635a KW	91	snd_pcm_format_t format = params_format(params);
	92	unsigned int channels = params_channels(params);
	93	unsigned int regval;
fb5d1152	94	int ch, dir = substream->stream;
c5c8635a	95	int bitwidth;
ec5b8287	96	int ret, dma_port = pcm_data->i2s_port + v->dmactl_audif_start;
c5c8635a	97
fb5d1152 SK	98	if (dir == SNDRV_PCM_STREAM_PLAYBACK)
	99	ch = pcm_data->rdma_ch;
	100	else
	101	ch = pcm_data->wrdma_ch;
	102
c5c8635a KW	103	bitwidth = snd_pcm_format_width(format);
	104	if (bitwidth < 0) {
	105	dev_err(soc_runtime->dev, "%s() invalid bit width given: %d\n",
	106	__func__, bitwidth);
	107	return bitwidth;
	108	}
	109
ec9e0ec8 SK	110	regval = LPAIF_DMACTL_BURSTEN_INCR4 \|
	111	LPAIF_DMACTL_AUDINTF(dma_port) \|
	112	LPAIF_DMACTL_FIFOWM_8;
c5c8635a KW	113
	114	switch (bitwidth) {
	115	case 16:
	116	switch (channels) {
	117	case 1:
	118	case 2:
ec9e0ec8	119	regval \|= LPAIF_DMACTL_WPSCNT_ONE;
c5c8635a KW	120	break;
c5c8635a KW	121	case 4:
ec9e0ec8	122	regval \|= LPAIF_DMACTL_WPSCNT_TWO;
c5c8635a KW	123	break;
c5c8635a KW	124	case 6:
ec9e0ec8	125	regval \|= LPAIF_DMACTL_WPSCNT_THREE;
c5c8635a KW	126	break;
c5c8635a KW	127	case 8:
ec9e0ec8	128	regval \|= LPAIF_DMACTL_WPSCNT_FOUR;
c5c8635a KW	129	break;
	130	default:
	131	dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n",
	132	__func__, bitwidth, channels);
	133	return -EINVAL;
	134	}
	135	break;
	136	case 24:
	137	case 32:
	138	switch (channels) {
	139	case 1:
ec9e0ec8	140	regval \|= LPAIF_DMACTL_WPSCNT_ONE;
c5c8635a KW	141	break;
c5c8635a KW	142	case 2:
ec9e0ec8	143	regval \|= LPAIF_DMACTL_WPSCNT_TWO;
c5c8635a KW	144	break;
c5c8635a KW	145	case 4:
ec9e0ec8	146	regval \|= LPAIF_DMACTL_WPSCNT_FOUR;
c5c8635a KW	147	break;
c5c8635a KW	148	case 6:
ec9e0ec8	149	regval \|= LPAIF_DMACTL_WPSCNT_SIX;
c5c8635a KW	150	break;
c5c8635a KW	151	case 8:
ec9e0ec8	152	regval \|= LPAIF_DMACTL_WPSCNT_EIGHT;
c5c8635a KW	153	break;
	154	default:
	155	dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n",
	156	__func__, bitwidth, channels);
	157	return -EINVAL;
	158	}
	159	break;
	160	default:
	161	dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n",
	162	__func__, bitwidth, channels);
	163	return -EINVAL;
	164	}
	165
	166	ret = regmap_write(drvdata->lpaif_map,
fb5d1152	167	LPAIF_DMACTL_REG(v, ch, dir), regval);
c5c8635a KW	168	if (ret) {
	169	dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
	170	__func__, ret);
	171	return ret;
	172	}
	173
	174	return 0;
	175	}
	176
	177	static int lpass_platform_pcmops_hw_free(struct snd_pcm_substream *substream)
	178	{
	179	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	180	struct lpass_data *drvdata =
	181	snd_soc_platform_get_drvdata(soc_runtime->platform);
6adcbdcd	182	struct lpass_pcm_data *pcm_data = drvdata->private_data;
9bae4880	183	struct lpass_variant *v = drvdata->variant;
fb5d1152	184	unsigned int reg;
c5c8635a KW	185	int ret;
c5c8635a KW	186
fb5d1152 SK	187	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	188	reg = LPAIF_RDMACTL_REG(v, pcm_data->rdma_ch);
	189	else
	190	reg = LPAIF_WRDMACTL_REG(v, pcm_data->wrdma_ch);
	191
	192	ret = regmap_write(drvdata->lpaif_map, reg, 0);
c5c8635a KW	193	if (ret)
	194	dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
	195	__func__, ret);
	196
	197	return ret;
	198	}
	199
	200	static int lpass_platform_pcmops_prepare(struct snd_pcm_substream *substream)
	201	{
	202	struct snd_pcm_runtime *runtime = substream->runtime;
	203	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	204	struct lpass_data *drvdata =
	205	snd_soc_platform_get_drvdata(soc_runtime->platform);
6adcbdcd	206	struct lpass_pcm_data *pcm_data = drvdata->private_data;
9bae4880	207	struct lpass_variant *v = drvdata->variant;
fb5d1152 SK	208	int ret, ch, dir = substream->stream;
	209
	210	if (dir == SNDRV_PCM_STREAM_PLAYBACK)
	211	ch = pcm_data->rdma_ch;
	212	else
	213	ch = pcm_data->wrdma_ch;
c5c8635a KW	214
c5c8635a KW	215	ret = regmap_write(drvdata->lpaif_map,
fb5d1152	216	LPAIF_DMABASE_REG(v, ch, dir),
c5c8635a KW	217	runtime->dma_addr);
	218	if (ret) {
	219	dev_err(soc_runtime->dev, "%s() error writing to rdmabase reg: %d\n",
	220	__func__, ret);
	221	return ret;
	222	}
	223
	224	ret = regmap_write(drvdata->lpaif_map,
ec9e0ec8	225	LPAIF_DMABUFF_REG(v, ch, dir),
c5c8635a KW	226	(snd_pcm_lib_buffer_bytes(substream) >> 2) - 1);
	227	if (ret) {
	228	dev_err(soc_runtime->dev, "%s() error writing to rdmabuff reg: %d\n",
	229	__func__, ret);
	230	return ret;
	231	}
	232
	233	ret = regmap_write(drvdata->lpaif_map,
ec9e0ec8	234	LPAIF_DMAPER_REG(v, ch, dir),
c5c8635a KW	235	(snd_pcm_lib_period_bytes(substream) >> 2) - 1);
	236	if (ret) {
	237	dev_err(soc_runtime->dev, "%s() error writing to rdmaper reg: %d\n",
	238	__func__, ret);
	239	return ret;
	240	}
	241
	242	ret = regmap_update_bits(drvdata->lpaif_map,
ec9e0ec8 SK	243	LPAIF_DMACTL_REG(v, ch, dir),
ec9e0ec8 SK	244	LPAIF_DMACTL_ENABLE_MASK, LPAIF_DMACTL_ENABLE_ON);
c5c8635a KW	245	if (ret) {
	246	dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
	247	__func__, ret);
	248	return ret;
	249	}
	250
	251	return 0;
	252	}
	253
	254	static int lpass_platform_pcmops_trigger(struct snd_pcm_substream *substream,
	255	int cmd)
	256	{
	257	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	258	struct lpass_data *drvdata =
	259	snd_soc_platform_get_drvdata(soc_runtime->platform);
6adcbdcd	260	struct lpass_pcm_data *pcm_data = drvdata->private_data;
9bae4880	261	struct lpass_variant *v = drvdata->variant;
fb5d1152 SK	262	int ret, ch, dir = substream->stream;
	263
	264	if (dir == SNDRV_PCM_STREAM_PLAYBACK)
	265	ch = pcm_data->rdma_ch;
	266	else
	267	ch = pcm_data->wrdma_ch;
c5c8635a KW	268
	269	switch (cmd) {
	270	case SNDRV_PCM_TRIGGER_START:
	271	case SNDRV_PCM_TRIGGER_RESUME:
	272	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	273	/* clear status before enabling interrupts */
	274	ret = regmap_write(drvdata->lpaif_map,
9bae4880	275	LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
6db1c6ba	276	LPAIF_IRQ_ALL(ch));
c5c8635a KW	277	if (ret) {
	278	dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
	279	__func__, ret);
	280	return ret;
	281	}
	282
	283	ret = regmap_update_bits(drvdata->lpaif_map,
9bae4880	284	LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST),
6db1c6ba SK	285	LPAIF_IRQ_ALL(ch),
6db1c6ba SK	286	LPAIF_IRQ_ALL(ch));
c5c8635a KW	287	if (ret) {
	288	dev_err(soc_runtime->dev, "%s() error writing to irqen reg: %d\n",
	289	__func__, ret);
	290	return ret;
	291	}
	292
	293	ret = regmap_update_bits(drvdata->lpaif_map,
ec9e0ec8 SK	294	LPAIF_DMACTL_REG(v, ch, dir),
	295	LPAIF_DMACTL_ENABLE_MASK,
	296	LPAIF_DMACTL_ENABLE_ON);
c5c8635a KW	297	if (ret) {
	298	dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
	299	__func__, ret);
	300	return ret;
	301	}
	302	break;
	303	case SNDRV_PCM_TRIGGER_STOP:
	304	case SNDRV_PCM_TRIGGER_SUSPEND:
	305	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	306	ret = regmap_update_bits(drvdata->lpaif_map,
ec9e0ec8 SK	307	LPAIF_DMACTL_REG(v, ch, dir),
	308	LPAIF_DMACTL_ENABLE_MASK,
	309	LPAIF_DMACTL_ENABLE_OFF);
c5c8635a KW	310	if (ret) {
	311	dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
	312	__func__, ret);
	313	return ret;
	314	}
	315
	316	ret = regmap_update_bits(drvdata->lpaif_map,
9bae4880	317	LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST),
6db1c6ba	318	LPAIF_IRQ_ALL(ch), 0);
c5c8635a KW	319	if (ret) {
	320	dev_err(soc_runtime->dev, "%s() error writing to irqen reg: %d\n",
	321	__func__, ret);
	322	return ret;
	323	}
	324	break;
	325	}
	326
	327	return 0;
	328	}
	329
	330	static snd_pcm_uframes_t lpass_platform_pcmops_pointer(
	331	struct snd_pcm_substream *substream)
	332	{
	333	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	334	struct lpass_data *drvdata =
	335	snd_soc_platform_get_drvdata(soc_runtime->platform);
6adcbdcd	336	struct lpass_pcm_data *pcm_data = drvdata->private_data;
9bae4880	337	struct lpass_variant *v = drvdata->variant;
c5c8635a	338	unsigned int base_addr, curr_addr;
fb5d1152 SK	339	int ret, ch, dir = substream->stream;
	340
	341	if (dir == SNDRV_PCM_STREAM_PLAYBACK)
	342	ch = pcm_data->rdma_ch;
	343	else
	344	ch = pcm_data->wrdma_ch;
c5c8635a KW	345
c5c8635a KW	346	ret = regmap_read(drvdata->lpaif_map,
ec9e0ec8	347	LPAIF_DMABASE_REG(v, ch, dir), &base_addr);
c5c8635a KW	348	if (ret) {
	349	dev_err(soc_runtime->dev, "%s() error reading from rdmabase reg: %d\n",
	350	__func__, ret);
	351	return ret;
	352	}
	353
	354	ret = regmap_read(drvdata->lpaif_map,
ec9e0ec8	355	LPAIF_DMACURR_REG(v, ch, dir), &curr_addr);
c5c8635a KW	356	if (ret) {
	357	dev_err(soc_runtime->dev, "%s() error reading from rdmacurr reg: %d\n",
	358	__func__, ret);
	359	return ret;
	360	}
	361
	362	return bytes_to_frames(substream->runtime, curr_addr - base_addr);
	363	}
	364
	365	static int lpass_platform_pcmops_mmap(struct snd_pcm_substream *substream,
	366	struct vm_area_struct *vma)
	367	{
	368	struct snd_pcm_runtime *runtime = substream->runtime;
	369
	370	return dma_mmap_coherent(substream->pcm->card->dev, vma,
	371	runtime->dma_area, runtime->dma_addr,
	372	runtime->dma_bytes);
	373	}
	374
115c7254	375	static const struct snd_pcm_ops lpass_platform_pcm_ops = {
c5c8635a KW	376	.open = lpass_platform_pcmops_open,
	377	.ioctl = snd_pcm_lib_ioctl,
	378	.hw_params = lpass_platform_pcmops_hw_params,
	379	.hw_free = lpass_platform_pcmops_hw_free,
	380	.prepare = lpass_platform_pcmops_prepare,
	381	.trigger = lpass_platform_pcmops_trigger,
	382	.pointer = lpass_platform_pcmops_pointer,
	383	.mmap = lpass_platform_pcmops_mmap,
	384	};
	385
4f629e4b SK	386	static irqreturn_t lpass_dma_interrupt_handler(
	387	struct snd_pcm_substream *substream,
	388	struct lpass_data *drvdata,
	389	int chan, u32 interrupts)
c5c8635a	390	{
c5c8635a	391	struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
9bae4880	392	struct lpass_variant *v = drvdata->variant;
c5c8635a	393	irqreturn_t ret = IRQ_NONE;
4f629e4b	394	int rv;
6db1c6ba SK	395
6db1c6ba SK	396	if (interrupts & LPAIF_IRQ_PER(chan)) {
c5c8635a	397	rv = regmap_write(drvdata->lpaif_map,
9bae4880	398	LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
6db1c6ba	399	LPAIF_IRQ_PER(chan));
c5c8635a KW	400	if (rv) {
	401	dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
	402	__func__, rv);
	403	return IRQ_NONE;
	404	}
	405	snd_pcm_period_elapsed(substream);
	406	ret = IRQ_HANDLED;
	407	}
	408
6db1c6ba	409	if (interrupts & LPAIF_IRQ_XRUN(chan)) {
c5c8635a	410	rv = regmap_write(drvdata->lpaif_map,
9bae4880	411	LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
6db1c6ba	412	LPAIF_IRQ_XRUN(chan));
c5c8635a KW	413	if (rv) {
	414	dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
	415	__func__, rv);
	416	return IRQ_NONE;
	417	}
	418	dev_warn(soc_runtime->dev, "%s() xrun warning\n", __func__);
	419	snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
	420	ret = IRQ_HANDLED;
	421	}
	422
6db1c6ba	423	if (interrupts & LPAIF_IRQ_ERR(chan)) {
c5c8635a	424	rv = regmap_write(drvdata->lpaif_map,
9bae4880	425	LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
6db1c6ba	426	LPAIF_IRQ_ERR(chan));
c5c8635a KW	427	if (rv) {
	428	dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
	429	__func__, rv);
	430	return IRQ_NONE;
	431	}
	432	dev_err(soc_runtime->dev, "%s() bus access error\n", __func__);
	433	snd_pcm_stop(substream, SNDRV_PCM_STATE_DISCONNECTED);
	434	ret = IRQ_HANDLED;
	435	}
	436
	437	return ret;
	438	}
	439
4f629e4b SK	440	static irqreturn_t lpass_platform_lpaif_irq(int irq, void *data)
	441	{
	442	struct lpass_data *drvdata = data;
	443	struct lpass_variant *v = drvdata->variant;
	444	unsigned int irqs;
	445	int rv, chan;
	446
	447	rv = regmap_read(drvdata->lpaif_map,
	448	LPAIF_IRQSTAT_REG(v, LPAIF_IRQ_PORT_HOST), &irqs);
	449	if (rv) {
	450	pr_err("%s() error reading from irqstat reg: %d\n",
	451	__func__, rv);
	452	return IRQ_NONE;
	453	}
	454
	455	/* Handle per channel interrupts */
	456	for (chan = 0; chan < LPASS_MAX_DMA_CHANNELS; chan++) {
	457	if (irqs & LPAIF_IRQ_ALL(chan) && drvdata->substream[chan]) {
	458	rv = lpass_dma_interrupt_handler(
	459	drvdata->substream[chan],
	460	drvdata, chan, irqs);
	461	if (rv != IRQ_HANDLED)
	462	return rv;
	463	}
	464	}
	465
	466	return IRQ_HANDLED;
	467	}
	468
c5c8635a KW	469	static int lpass_platform_pcm_new(struct snd_soc_pcm_runtime *soc_runtime)
	470	{
	471	struct snd_pcm *pcm = soc_runtime->pcm;
fb5d1152	472	struct snd_pcm_substream psubstream, csubstream;
6db1c6ba	473	struct snd_soc_dai *cpu_dai = soc_runtime->cpu_dai;
c5c8635a KW	474	struct lpass_data *drvdata =
c5c8635a KW	475	snd_soc_platform_get_drvdata(soc_runtime->platform);
9bae4880	476	struct lpass_variant *v = drvdata->variant;
ea4d25d5	477	int ret = -EINVAL;
6db1c6ba	478	struct lpass_pcm_data *data;
144a9883	479	size_t size = lpass_platform_pcm_hardware.buffer_bytes_max;
6db1c6ba SK	480
	481	data = devm_kzalloc(soc_runtime->dev, sizeof(*data), GFP_KERNEL);
	482	if (!data)
	483	return -ENOMEM;
	484
fb5d1152	485	data->i2s_port = cpu_dai->driver->id;
6adcbdcd	486	drvdata->private_data = data;
6db1c6ba	487
fb5d1152 SK	488	psubstream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
	489	if (psubstream) {
	490	if (v->alloc_dma_channel)
	491	data->rdma_ch = v->alloc_dma_channel(drvdata,
	492	SNDRV_PCM_STREAM_PLAYBACK);
6db1c6ba	493
cef794f7	494	if (data->rdma_ch < 0)
fb5d1152	495	return data->rdma_ch;
6db1c6ba	496
fb5d1152	497	drvdata->substream[data->rdma_ch] = psubstream;
c5c8635a	498
fb5d1152 SK	499	ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
	500	soc_runtime->platform->dev,
	501	size, &psubstream->dma_buffer);
	502	if (ret)
	503	goto playback_alloc_err;
c5c8635a	504
fb5d1152	505	ret = regmap_write(drvdata->lpaif_map,
6db1c6ba	506	LPAIF_RDMACTL_REG(v, data->rdma_ch), 0);
fb5d1152 SK	507	if (ret) {
	508	dev_err(soc_runtime->dev,
	509	"%s() error writing to rdmactl reg: %d\n",
c5c8635a	510	__func__, ret);
fb5d1152 SK	511	goto capture_alloc_err;
	512	}
	513	}
	514
	515	csubstream = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream;
	516	if (csubstream) {
	517	if (v->alloc_dma_channel)
	518	data->wrdma_ch = v->alloc_dma_channel(drvdata,
	519	SNDRV_PCM_STREAM_CAPTURE);
	520
cef794f7 SK	521	if (data->wrdma_ch < 0) {
cef794f7 SK	522	ret = data->wrdma_ch;
fb5d1152	523	goto capture_alloc_err;
cef794f7	524	}
fb5d1152 SK	525
	526	drvdata->substream[data->wrdma_ch] = csubstream;
	527
	528	ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
	529	soc_runtime->platform->dev,
	530	size, &csubstream->dma_buffer);
	531	if (ret)
	532	goto capture_alloc_err;
	533
	534	ret = regmap_write(drvdata->lpaif_map,
	535	LPAIF_WRDMACTL_REG(v, data->wrdma_ch), 0);
	536	if (ret) {
	537	dev_err(soc_runtime->dev,
	538	"%s() error writing to wrdmactl reg: %d\n",
	539	__func__, ret);
	540	goto capture_reg_err;
	541	}
c5c8635a KW	542	}
	543
	544	return 0;
	545
fb5d1152 SK	546	capture_reg_err:
	547	if (csubstream)
	548	snd_dma_free_pages(&csubstream->dma_buffer);
	549
	550	capture_alloc_err:
	551	if (psubstream)
	552	snd_dma_free_pages(&psubstream->dma_buffer);
	553
	554	playback_alloc_err:
	555	dev_err(soc_runtime->dev, "Cannot allocate buffer(s)\n");
	556
c5c8635a KW	557	return ret;
	558	}
	559
	560	static void lpass_platform_pcm_free(struct snd_pcm *pcm)
	561	{
fb5d1152 SK	562	struct snd_soc_pcm_runtime *rt;
	563	struct lpass_data *drvdata;
	564	struct lpass_pcm_data *data;
	565	struct lpass_variant *v;
	566	struct snd_pcm_substream *substream;
	567	int ch, i;
	568
	569	for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) {
	570	substream = pcm->streams[i].substream;
	571	if (substream) {
	572	rt = substream->private_data;
fb5d1152	573	drvdata = snd_soc_platform_get_drvdata(rt->platform);
6adcbdcd	574	data = drvdata->private_data;
fb5d1152 SK	575
	576	ch = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	577	? data->rdma_ch
	578	: data->wrdma_ch;
	579	v = drvdata->variant;
	580	drvdata->substream[ch] = NULL;
	581	if (v->free_dma_channel)
	582	v->free_dma_channel(drvdata, ch);
	583
	584	snd_dma_free_pages(&substream->dma_buffer);
	585	substream->dma_buffer.area = NULL;
	586	substream->dma_buffer.addr = 0;
	587	}
	588	}
c5c8635a KW	589	}
	590
	591	static struct snd_soc_platform_driver lpass_platform_driver = {
	592	.pcm_new = lpass_platform_pcm_new,
	593	.pcm_free = lpass_platform_pcm_free,
	594	.ops = &lpass_platform_pcm_ops,
	595	};
	596
	597	int asoc_qcom_lpass_platform_register(struct platform_device *pdev)
	598	{
	599	struct lpass_data *drvdata = platform_get_drvdata(pdev);
4f629e4b SK	600	struct lpass_variant *v = drvdata->variant;
4f629e4b SK	601	int ret;
c5c8635a KW	602
	603	drvdata->lpaif_irq = platform_get_irq_byname(pdev, "lpass-irq-lpaif");
	604	if (drvdata->lpaif_irq < 0) {
	605	dev_err(&pdev->dev, "%s() error getting irq handle: %d\n",
	606	__func__, drvdata->lpaif_irq);
	607	return -ENODEV;
	608	}
	609
4f629e4b SK	610	/* ensure audio hardware is disabled */
	611	ret = regmap_write(drvdata->lpaif_map,
	612	LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST), 0);
	613	if (ret) {
	614	dev_err(&pdev->dev, "%s() error writing to irqen reg: %d\n",
	615	__func__, ret);
	616	return ret;
	617	}
	618
	619	ret = devm_request_irq(&pdev->dev, drvdata->lpaif_irq,
	620	lpass_platform_lpaif_irq, IRQF_TRIGGER_RISING,
	621	"lpass-irq-lpaif", drvdata);
	622	if (ret) {
	623	dev_err(&pdev->dev, "%s() irq request failed: %d\n",
	624	__func__, ret);
	625	return ret;
	626	}
	627
	628
c5c8635a KW	629	return devm_snd_soc_register_platform(&pdev->dev,
	630	&lpass_platform_driver);
	631	}
	632	EXPORT_SYMBOL_GPL(asoc_qcom_lpass_platform_register);
	633
	634	MODULE_DESCRIPTION("QTi LPASS Platform Driver");
	635	MODULE_LICENSE("GPL v2");