[deliverable/linux.git] / sound / soc / samsung / s3c-i2s-v2.c

/* ALSA Soc Audio Layer - I2S core for newer Samsung SoCs.
 *
 * Copyright (c) 2006 Wolfson Microelectronics PLC.
 *	Graeme Gregory graeme.gregory@wolfsonmicro.com
 *	linux@wolfsonmicro.com
 *
 * Copyright (c) 2008, 2007, 2004-2005 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <sound/soc.h>
#include <sound/pcm_params.h>

#include "regs-i2s-v2.h"
#include "s3c-i2s-v2.h"

#undef S3C_IIS_V2_SUPPORTED

#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) \
	|| defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_CPU_S5PV210)
#define S3C_IIS_V2_SUPPORTED
#endif

#ifndef S3C_IIS_V2_SUPPORTED
#error Unsupported CPU model
#endif

#define S3C2412_I2S_DEBUG_CON 0

static inline struct s3c_i2sv2_info *to_info(struct snd_soc_dai *cpu_dai)
{
	return snd_soc_dai_get_drvdata(cpu_dai);
}

#define bit_set(v, b) (((v) & (b)) ? 1 : 0)

#if S3C2412_I2S_DEBUG_CON
static void dbg_showcon(const char *fn, u32 con)
{
	printk(KERN_DEBUG "%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d, RXFFULL=%d\n", fn,
	       bit_set(con, S3C2412_IISCON_LRINDEX),
	       bit_set(con, S3C2412_IISCON_TXFIFO_EMPTY),
	       bit_set(con, S3C2412_IISCON_RXFIFO_EMPTY),
	       bit_set(con, S3C2412_IISCON_TXFIFO_FULL),
	       bit_set(con, S3C2412_IISCON_RXFIFO_FULL));

	printk(KERN_DEBUG "%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n",
	       fn,
	       bit_set(con, S3C2412_IISCON_TXDMA_PAUSE),
	       bit_set(con, S3C2412_IISCON_RXDMA_PAUSE),
	       bit_set(con, S3C2412_IISCON_TXCH_PAUSE),
	       bit_set(con, S3C2412_IISCON_RXCH_PAUSE));
	printk(KERN_DEBUG "%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn,
	       bit_set(con, S3C2412_IISCON_TXDMA_ACTIVE),
	       bit_set(con, S3C2412_IISCON_RXDMA_ACTIVE),
	       bit_set(con, S3C2412_IISCON_IIS_ACTIVE));
}
#else
static inline void dbg_showcon(const char *fn, u32 con)
{
}
#endif


/* Turn on or off the transmission path. */
static void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on)
{
	void __iomem *regs = i2s->regs;
	u32 fic, con, mod;

	pr_debug("%s(%d)\n", __func__, on);

	fic = readl(regs + S3C2412_IISFIC);
	con = readl(regs + S3C2412_IISCON);
	mod = readl(regs + S3C2412_IISMOD);

	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);

	if (on) {
		con |= S3C2412_IISCON_TXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
		con &= ~S3C2412_IISCON_TXDMA_PAUSE;
		con &= ~S3C2412_IISCON_TXCH_PAUSE;

		switch (mod & S3C2412_IISMOD_MODE_MASK) {
		case S3C2412_IISMOD_MODE_TXONLY:
		case S3C2412_IISMOD_MODE_TXRX:
			/* do nothing, we are in the right mode */
			break;

		case S3C2412_IISMOD_MODE_RXONLY:
			mod &= ~S3C2412_IISMOD_MODE_MASK;
			mod |= S3C2412_IISMOD_MODE_TXRX;
			break;

		default:
			dev_err(i2s->dev, "TXEN: Invalid MODE %x in IISMOD\n",
				mod & S3C2412_IISMOD_MODE_MASK);
			break;
		}

		writel(con, regs + S3C2412_IISCON);
		writel(mod, regs + S3C2412_IISMOD);
	} else {
		/* Note, we do not have any indication that the FIFO problems
		 * tha the S3C2410/2440 had apply here, so we should be able
		 * to disable the DMA and TX without resetting the FIFOS.
		 */

		con |=  S3C2412_IISCON_TXDMA_PAUSE;
		con |=  S3C2412_IISCON_TXCH_PAUSE;
		con &= ~S3C2412_IISCON_TXDMA_ACTIVE;

		switch (mod & S3C2412_IISMOD_MODE_MASK) {
		case S3C2412_IISMOD_MODE_TXRX:
			mod &= ~S3C2412_IISMOD_MODE_MASK;
			mod |= S3C2412_IISMOD_MODE_RXONLY;
			break;

		case S3C2412_IISMOD_MODE_TXONLY:
			mod &= ~S3C2412_IISMOD_MODE_MASK;
			con &= ~S3C2412_IISCON_IIS_ACTIVE;
			break;

		default:
			dev_err(i2s->dev, "TXDIS: Invalid MODE %x in IISMOD\n",
				mod & S3C2412_IISMOD_MODE_MASK);
			break;
		}

		writel(mod, regs + S3C2412_IISMOD);
		writel(con, regs + S3C2412_IISCON);
	}

	fic = readl(regs + S3C2412_IISFIC);
	dbg_showcon(__func__, con);
	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
}

static void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on)
{
	void __iomem *regs = i2s->regs;
	u32 fic, con, mod;

	pr_debug("%s(%d)\n", __func__, on);

	fic = readl(regs + S3C2412_IISFIC);
	con = readl(regs + S3C2412_IISCON);
	mod = readl(regs + S3C2412_IISMOD);

	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);

	if (on) {
		con |= S3C2412_IISCON_RXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
		con &= ~S3C2412_IISCON_RXDMA_PAUSE;
		con &= ~S3C2412_IISCON_RXCH_PAUSE;

		switch (mod & S3C2412_IISMOD_MODE_MASK) {
		case S3C2412_IISMOD_MODE_TXRX:
		case S3C2412_IISMOD_MODE_RXONLY:
			/* do nothing, we are in the right mode */
			break;

		case S3C2412_IISMOD_MODE_TXONLY:
			mod &= ~S3C2412_IISMOD_MODE_MASK;
			mod |= S3C2412_IISMOD_MODE_TXRX;
			break;

		default:
			dev_err(i2s->dev, "RXEN: Invalid MODE %x in IISMOD\n",
				mod & S3C2412_IISMOD_MODE_MASK);
		}

		writel(mod, regs + S3C2412_IISMOD);
		writel(con, regs + S3C2412_IISCON);
	} else {
		/* See txctrl notes on FIFOs. */

		con &= ~S3C2412_IISCON_RXDMA_ACTIVE;
		con |=  S3C2412_IISCON_RXDMA_PAUSE;
		con |=  S3C2412_IISCON_RXCH_PAUSE;

		switch (mod & S3C2412_IISMOD_MODE_MASK) {
		case S3C2412_IISMOD_MODE_RXONLY:
			con &= ~S3C2412_IISCON_IIS_ACTIVE;
			mod &= ~S3C2412_IISMOD_MODE_MASK;
			break;

		case S3C2412_IISMOD_MODE_TXRX:
			mod &= ~S3C2412_IISMOD_MODE_MASK;
			mod |= S3C2412_IISMOD_MODE_TXONLY;
			break;

		default:
			dev_err(i2s->dev, "RXDIS: Invalid MODE %x in IISMOD\n",
				mod & S3C2412_IISMOD_MODE_MASK);
		}

		writel(con, regs + S3C2412_IISCON);
		writel(mod, regs + S3C2412_IISMOD);
	}

	fic = readl(regs + S3C2412_IISFIC);
	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
}

#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)

/*
 * Wait for the LR signal to allow synchronisation to the L/R clock
 * from the codec. May only be needed for slave mode.
 */
static int s3c2412_snd_lrsync(struct s3c_i2sv2_info *i2s)
{
	u32 iiscon;
	unsigned long loops = msecs_to_loops(5);

	pr_debug("Entered %s\n", __func__);

	while (--loops) {
		iiscon = readl(i2s->regs + S3C2412_IISCON);
		if (iiscon & S3C2412_IISCON_LRINDEX)
			break;

		cpu_relax();
	}

	if (!loops) {
		printk(KERN_ERR "%s: timeout\n", __func__);
		return -ETIMEDOUT;
	}

	return 0;
}

/*
 * Set S3C2412 I2S DAI format
 */
static int s3c2412_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
			       unsigned int fmt)
{
	struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
	u32 iismod;

	pr_debug("Entered %s\n", __func__);

	iismod = readl(i2s->regs + S3C2412_IISMOD);
	pr_debug("hw_params r: IISMOD: %x \n", iismod);

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBM_CFM:
		i2s->master = 0;
		iismod |= S3C2412_IISMOD_SLAVE;
		break;
	case SND_SOC_DAIFMT_CBS_CFS:
		i2s->master = 1;
		iismod &= ~S3C2412_IISMOD_SLAVE;
		break;
	default:
		pr_err("unknown master/slave format\n");
		return -EINVAL;
	}

	iismod &= ~S3C2412_IISMOD_SDF_MASK;

	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_RIGHT_J:
		iismod |= S3C2412_IISMOD_LR_RLOW;
		iismod |= S3C2412_IISMOD_SDF_MSB;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		iismod |= S3C2412_IISMOD_LR_RLOW;
		iismod |= S3C2412_IISMOD_SDF_LSB;
		break;
	case SND_SOC_DAIFMT_I2S:
		iismod &= ~S3C2412_IISMOD_LR_RLOW;
		iismod |= S3C2412_IISMOD_SDF_IIS;
		break;
	default:
		pr_err("Unknown data format\n");
		return -EINVAL;
	}

	writel(iismod, i2s->regs + S3C2412_IISMOD);
	pr_debug("hw_params w: IISMOD: %x \n", iismod);
	return 0;
}

static int s3c_i2sv2_hw_params(struct snd_pcm_substream *substream,
				 struct snd_pcm_hw_params *params,
				 struct snd_soc_dai *dai)
{
	struct s3c_i2sv2_info *i2s = to_info(dai);
	struct snd_dmaengine_dai_dma_data *dma_data;
	u32 iismod;

	pr_debug("Entered %s\n", __func__);

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		dma_data = i2s->dma_playback;
	else
		dma_data = i2s->dma_capture;

	snd_soc_dai_set_dma_data(dai, substream, dma_data);

	/* Working copies of register */
	iismod = readl(i2s->regs + S3C2412_IISMOD);
	pr_debug("%s: r: IISMOD: %x\n", __func__, iismod);

	iismod &= ~S3C64XX_IISMOD_BLC_MASK;
	/* Sample size */
	switch (params_width(params)) {
	case 8:
		iismod |= S3C64XX_IISMOD_BLC_8BIT;
		break;
	case 16:
		break;
	case 24:
		iismod |= S3C64XX_IISMOD_BLC_24BIT;
		break;
	}

	writel(iismod, i2s->regs + S3C2412_IISMOD);
	pr_debug("%s: w: IISMOD: %x\n", __func__, iismod);

	return 0;
}

static int s3c_i2sv2_set_sysclk(struct snd_soc_dai *cpu_dai,
				  int clk_id, unsigned int freq, int dir)
{
	struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
	u32 iismod = readl(i2s->regs + S3C2412_IISMOD);

	pr_debug("Entered %s\n", __func__);
	pr_debug("%s r: IISMOD: %x\n", __func__, iismod);

	switch (clk_id) {
	case S3C_I2SV2_CLKSRC_PCLK:
		iismod &= ~S3C2412_IISMOD_IMS_SYSMUX;
		break;

	case S3C_I2SV2_CLKSRC_AUDIOBUS:
		iismod |= S3C2412_IISMOD_IMS_SYSMUX;
		break;

	case S3C_I2SV2_CLKSRC_CDCLK:
		/* Error if controller doesn't have the CDCLKCON bit */
		if (!(i2s->feature & S3C_FEATURE_CDCLKCON))
			return -EINVAL;

		switch (dir) {
		case SND_SOC_CLOCK_IN:
			iismod |= S3C64XX_IISMOD_CDCLKCON;
			break;
		case SND_SOC_CLOCK_OUT:
			iismod &= ~S3C64XX_IISMOD_CDCLKCON;
			break;
		default:
			return -EINVAL;
		}
		break;

	default:
		return -EINVAL;
	}

	writel(iismod, i2s->regs + S3C2412_IISMOD);
	pr_debug("%s w: IISMOD: %x\n", __func__, iismod);

	return 0;
}

static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
			       struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct s3c_i2sv2_info *i2s = to_info(rtd->cpu_dai);
	int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
	unsigned long irqs;
	int ret = 0;

	pr_debug("Entered %s\n", __func__);

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
		/* On start, ensure that the FIFOs are cleared and reset. */

		writel(capture ? S3C2412_IISFIC_RXFLUSH : S3C2412_IISFIC_TXFLUSH,
		       i2s->regs + S3C2412_IISFIC);

		/* clear again, just in case */
		writel(0x0, i2s->regs + S3C2412_IISFIC);

	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		if (!i2s->master) {
			ret = s3c2412_snd_lrsync(i2s);
			if (ret)
				goto exit_err;
		}

		local_irq_save(irqs);

		if (capture)
			s3c2412_snd_rxctrl(i2s, 1);
		else
			s3c2412_snd_txctrl(i2s, 1);

		local_irq_restore(irqs);

		break;

	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		local_irq_save(irqs);

		if (capture)
			s3c2412_snd_rxctrl(i2s, 0);
		else
			s3c2412_snd_txctrl(i2s, 0);

		local_irq_restore(irqs);
		break;
	default:
		ret = -EINVAL;
		break;
	}

exit_err:
	return ret;
}

/*
 * Set S3C2412 Clock dividers
 */
static int s3c2412_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
				  int div_id, int div)
{
	struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
	u32 reg;

	pr_debug("%s(%p, %d, %d)\n", __func__, cpu_dai, div_id, div);

	switch (div_id) {
	case S3C_I2SV2_DIV_BCLK:
		switch (div) {
		case 16:
			div = S3C2412_IISMOD_BCLK_16FS;
			break;

		case 32:
			div = S3C2412_IISMOD_BCLK_32FS;
			break;

		case 24:
			div = S3C2412_IISMOD_BCLK_24FS;
			break;

		case 48:
			div = S3C2412_IISMOD_BCLK_48FS;
			break;

		default:
			return -EINVAL;
		}

		reg = readl(i2s->regs + S3C2412_IISMOD);
		reg &= ~S3C2412_IISMOD_BCLK_MASK;
		writel(reg | div, i2s->regs + S3C2412_IISMOD);

		pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
		break;

	case S3C_I2SV2_DIV_RCLK:
		switch (div) {
		case 256:
			div = S3C2412_IISMOD_RCLK_256FS;
			break;

		case 384:
			div = S3C2412_IISMOD_RCLK_384FS;
			break;

		case 512:
			div = S3C2412_IISMOD_RCLK_512FS;
			break;

		case 768:
			div = S3C2412_IISMOD_RCLK_768FS;
			break;

		default:
			return -EINVAL;
		}

		reg = readl(i2s->regs + S3C2412_IISMOD);
		reg &= ~S3C2412_IISMOD_RCLK_MASK;
		writel(reg | div, i2s->regs + S3C2412_IISMOD);
		pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
		break;

	case S3C_I2SV2_DIV_PRESCALER:
		if (div >= 0) {
			writel((div << 8) | S3C2412_IISPSR_PSREN,
			       i2s->regs + S3C2412_IISPSR);
		} else {
			writel(0x0, i2s->regs + S3C2412_IISPSR);
		}
		pr_debug("%s: PSR=%08x\n", __func__, readl(i2s->regs + S3C2412_IISPSR));
		break;

	default:
		return -EINVAL;
	}

	return 0;
}

static snd_pcm_sframes_t s3c2412_i2s_delay(struct snd_pcm_substream *substream,
					   struct snd_soc_dai *dai)
{
	struct s3c_i2sv2_info *i2s = to_info(dai);
	u32 reg = readl(i2s->regs + S3C2412_IISFIC);
	snd_pcm_sframes_t delay;

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		delay = S3C2412_IISFIC_TXCOUNT(reg);
	else
		delay = S3C2412_IISFIC_RXCOUNT(reg);

	return delay;
}

struct clk *s3c_i2sv2_get_clock(struct snd_soc_dai *cpu_dai)
{
	struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
	u32 iismod = readl(i2s->regs + S3C2412_IISMOD);

	if (iismod & S3C2412_IISMOD_IMS_SYSMUX)
		return i2s->iis_cclk;
	else
		return i2s->iis_pclk;
}
EXPORT_SYMBOL_GPL(s3c_i2sv2_get_clock);

/* default table of all avaialable root fs divisors */
static unsigned int iis_fs_tab[] = { 256, 512, 384, 768 };

int s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc *info,
			    unsigned int *fstab,
			    unsigned int rate, struct clk *clk)
{
	unsigned long clkrate = clk_get_rate(clk);
	unsigned int div;
	unsigned int fsclk;
	unsigned int actual;
	unsigned int fs;
	unsigned int fsdiv;
	signed int deviation = 0;
	unsigned int best_fs = 0;
	unsigned int best_div = 0;
	unsigned int best_rate = 0;
	unsigned int best_deviation = INT_MAX;

	pr_debug("Input clock rate %ldHz\n", clkrate);

	if (fstab == NULL)
		fstab = iis_fs_tab;

	for (fs = 0; fs < ARRAY_SIZE(iis_fs_tab); fs++) {
		fsdiv = iis_fs_tab[fs];

		fsclk = clkrate / fsdiv;
		div = fsclk / rate;

		if ((fsclk % rate) > (rate / 2))
			div++;

		if (div <= 1)
			continue;

		actual = clkrate / (fsdiv * div);
		deviation = actual - rate;

		printk(KERN_DEBUG "%ufs: div %u => result %u, deviation %d\n",
		       fsdiv, div, actual, deviation);

		deviation = abs(deviation);

		if (deviation < best_deviation) {
			best_fs = fsdiv;
			best_div = div;
			best_rate = actual;
			best_deviation = deviation;
		}

		if (deviation == 0)
			break;
	}

	printk(KERN_DEBUG "best: fs=%u, div=%u, rate=%u\n",
	       best_fs, best_div, best_rate);

	info->fs_div = best_fs;
	info->clk_div = best_div;

	return 0;
}
EXPORT_SYMBOL_GPL(s3c_i2sv2_iis_calc_rate);

int s3c_i2sv2_probe(struct snd_soc_dai *dai,
		    struct s3c_i2sv2_info *i2s,
		    unsigned long base)
{
	struct device *dev = dai->dev;
	unsigned int iismod;

	i2s->dev = dev;

	/* record our i2s structure for later use in the callbacks */
	snd_soc_dai_set_drvdata(dai, i2s);

	i2s->iis_pclk = clk_get(dev, "iis");
	if (IS_ERR(i2s->iis_pclk)) {
		dev_err(dev, "failed to get iis_clock\n");
		iounmap(i2s->regs);
		return -ENOENT;
	}

	clk_enable(i2s->iis_pclk);

	/* Mark ourselves as in TXRX mode so we can run through our cleanup
	 * process without warnings. */
	iismod = readl(i2s->regs + S3C2412_IISMOD);
	iismod |= S3C2412_IISMOD_MODE_TXRX;
	writel(iismod, i2s->regs + S3C2412_IISMOD);
	s3c2412_snd_txctrl(i2s, 0);
	s3c2412_snd_rxctrl(i2s, 0);

	return 0;
}
EXPORT_SYMBOL_GPL(s3c_i2sv2_probe);

#ifdef CONFIG_PM
static int s3c2412_i2s_suspend(struct snd_soc_dai *dai)
{
	struct s3c_i2sv2_info *i2s = to_info(dai);
	u32 iismod;

	if (dai->active) {
		i2s->suspend_iismod = readl(i2s->regs + S3C2412_IISMOD);
		i2s->suspend_iiscon = readl(i2s->regs + S3C2412_IISCON);
		i2s->suspend_iispsr = readl(i2s->regs + S3C2412_IISPSR);

		/* some basic suspend checks */

		iismod = readl(i2s->regs + S3C2412_IISMOD);

		if (iismod & S3C2412_IISCON_RXDMA_ACTIVE)
			pr_warning("%s: RXDMA active?\n", __func__);

		if (iismod & S3C2412_IISCON_TXDMA_ACTIVE)
			pr_warning("%s: TXDMA active?\n", __func__);

		if (iismod & S3C2412_IISCON_IIS_ACTIVE)
			pr_warning("%s: IIS active\n", __func__);
	}

	return 0;
}

static int s3c2412_i2s_resume(struct snd_soc_dai *dai)
{
	struct s3c_i2sv2_info *i2s = to_info(dai);

	pr_info("dai_active %d, IISMOD %08x, IISCON %08x\n",
		dai->active, i2s->suspend_iismod, i2s->suspend_iiscon);

	if (dai->active) {
		writel(i2s->suspend_iiscon, i2s->regs + S3C2412_IISCON);
		writel(i2s->suspend_iismod, i2s->regs + S3C2412_IISMOD);
		writel(i2s->suspend_iispsr, i2s->regs + S3C2412_IISPSR);

		writel(S3C2412_IISFIC_RXFLUSH | S3C2412_IISFIC_TXFLUSH,
		       i2s->regs + S3C2412_IISFIC);

		ndelay(250);
		writel(0x0, i2s->regs + S3C2412_IISFIC);
	}

	return 0;
}
#else
#define s3c2412_i2s_suspend NULL
#define s3c2412_i2s_resume  NULL
#endif

int s3c_i2sv2_register_component(struct device *dev, int id,
			   const struct snd_soc_component_driver *cmp_drv,
			   struct snd_soc_dai_driver *dai_drv)
{
	struct snd_soc_dai_ops *ops = (struct snd_soc_dai_ops *)dai_drv->ops;

	ops->trigger = s3c2412_i2s_trigger;
	if (!ops->hw_params)
		ops->hw_params = s3c_i2sv2_hw_params;
	ops->set_fmt = s3c2412_i2s_set_fmt;
	ops->set_clkdiv = s3c2412_i2s_set_clkdiv;
	ops->set_sysclk = s3c_i2sv2_set_sysclk;

	/* Allow overriding by (for example) IISv4 */
	if (!ops->delay)
		ops->delay = s3c2412_i2s_delay;

	dai_drv->suspend = s3c2412_i2s_suspend;
	dai_drv->resume = s3c2412_i2s_resume;

	return devm_snd_soc_register_component(dev, cmp_drv, dai_drv, 1);
}
EXPORT_SYMBOL_GPL(s3c_i2sv2_register_component);

MODULE_LICENSE("GPL");
Commit	Line	Data
b3ff0466	1	/* ALSA Soc Audio Layer - I2S core for newer Samsung SoCs.
dc85447b BD	2	*
	3	* Copyright (c) 2006 Wolfson Microelectronics PLC.
	4	* Graeme Gregory graeme.gregory@wolfsonmicro.com
	5	* linux@wolfsonmicro.com
	6	*
	7	* Copyright (c) 2008, 2007, 2004-2005 Simtec Electronics
	8	* http://armlinux.simtec.co.uk/
	9	* Ben Dooks <ben@simtec.co.uk>
	10	*
	11	* This program is free software; you can redistribute it and/or modify it
	12	* under the terms of the GNU General Public License as published by the
	13	* Free Software Foundation; either version 2 of the License, or (at your
	14	* option) any later version.
	15	*/
	16
f3a54a28	17	#include <linux/module.h>
dc85447b BD	18	#include <linux/delay.h>
dc85447b BD	19	#include <linux/clk.h>
dc85447b BD	20	#include <linux/io.h>
dc85447b BD	21
dc85447b	22	#include <sound/soc.h>
0378b6ac	23	#include <sound/pcm_params.h>
dc85447b	24
d07e7ce9	25	#include "regs-i2s-v2.h"
dc85447b BD	26	#include "s3c-i2s-v2.h"
dc85447b BD	27
8a0f62b8 MB	28	#undef S3C_IIS_V2_SUPPORTED
8a0f62b8 MB	29
5c519767	30	#if defined(CONFIG_CPU_S3C2412) \|\| defined(CONFIG_CPU_S3C2413) \
7472a2f2	31	\|\| defined(CONFIG_ARCH_S3C64XX) \|\| defined(CONFIG_CPU_S5PV210)
8a0f62b8 MB	32	#define S3C_IIS_V2_SUPPORTED
	33	#endif
	34
	35	#ifndef S3C_IIS_V2_SUPPORTED
	36	#error Unsupported CPU model
	37	#endif
	38
dc85447b	39	#define S3C2412_I2S_DEBUG_CON 0
dc85447b BD	40
	41	static inline struct s3c_i2sv2_info to_info(struct snd_soc_dai cpu_dai)
	42	{
f0fba2ad	43	return snd_soc_dai_get_drvdata(cpu_dai);
dc85447b BD	44	}
	45
	46	#define bit_set(v, b) (((v) & (b)) ? 1 : 0)
	47
	48	#if S3C2412_I2S_DEBUG_CON
	49	static void dbg_showcon(const char *fn, u32 con)
	50	{
	51	printk(KERN_DEBUG "%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d, RXFFULL=%d\n", fn,
	52	bit_set(con, S3C2412_IISCON_LRINDEX),
	53	bit_set(con, S3C2412_IISCON_TXFIFO_EMPTY),
	54	bit_set(con, S3C2412_IISCON_RXFIFO_EMPTY),
	55	bit_set(con, S3C2412_IISCON_TXFIFO_FULL),
	56	bit_set(con, S3C2412_IISCON_RXFIFO_FULL));
	57
	58	printk(KERN_DEBUG "%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n",
	59	fn,
	60	bit_set(con, S3C2412_IISCON_TXDMA_PAUSE),
	61	bit_set(con, S3C2412_IISCON_RXDMA_PAUSE),
	62	bit_set(con, S3C2412_IISCON_TXCH_PAUSE),
	63	bit_set(con, S3C2412_IISCON_RXCH_PAUSE));
	64	printk(KERN_DEBUG "%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn,
	65	bit_set(con, S3C2412_IISCON_TXDMA_ACTIVE),
	66	bit_set(con, S3C2412_IISCON_RXDMA_ACTIVE),
	67	bit_set(con, S3C2412_IISCON_IIS_ACTIVE));
	68	}
	69	#else
	70	static inline void dbg_showcon(const char *fn, u32 con)
	71	{
	72	}
	73	#endif
	74
	75
	76	/* Turn on or off the transmission path. */
abbc8246	77	static void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on)
dc85447b BD	78	{
	79	void __iomem *regs = i2s->regs;
	80	u32 fic, con, mod;
	81
ee7d4767	82	pr_debug("%s(%d)\n", __func__, on);
dc85447b BD	83
	84	fic = readl(regs + S3C2412_IISFIC);
	85	con = readl(regs + S3C2412_IISCON);
	86	mod = readl(regs + S3C2412_IISMOD);
	87
ee7d4767	88	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b BD	89
	90	if (on) {
	91	con \|= S3C2412_IISCON_TXDMA_ACTIVE \| S3C2412_IISCON_IIS_ACTIVE;
	92	con &= ~S3C2412_IISCON_TXDMA_PAUSE;
	93	con &= ~S3C2412_IISCON_TXCH_PAUSE;
	94
	95	switch (mod & S3C2412_IISMOD_MODE_MASK) {
	96	case S3C2412_IISMOD_MODE_TXONLY:
	97	case S3C2412_IISMOD_MODE_TXRX:
	98	/* do nothing, we are in the right mode */
	99	break;
	100
	101	case S3C2412_IISMOD_MODE_RXONLY:
	102	mod &= ~S3C2412_IISMOD_MODE_MASK;
	103	mod \|= S3C2412_IISMOD_MODE_TXRX;
	104	break;
	105
	106	default:
abbc8246 MB	107	dev_err(i2s->dev, "TXEN: Invalid MODE %x in IISMOD\n",
	108	mod & S3C2412_IISMOD_MODE_MASK);
	109	break;
dc85447b BD	110	}
	111
	112	writel(con, regs + S3C2412_IISCON);
	113	writel(mod, regs + S3C2412_IISMOD);
	114	} else {
	115	/* Note, we do not have any indication that the FIFO problems
	116	* tha the S3C2410/2440 had apply here, so we should be able
	117	* to disable the DMA and TX without resetting the FIFOS.
	118	*/
	119
	120	con \|= S3C2412_IISCON_TXDMA_PAUSE;
	121	con \|= S3C2412_IISCON_TXCH_PAUSE;
	122	con &= ~S3C2412_IISCON_TXDMA_ACTIVE;
	123
	124	switch (mod & S3C2412_IISMOD_MODE_MASK) {
	125	case S3C2412_IISMOD_MODE_TXRX:
	126	mod &= ~S3C2412_IISMOD_MODE_MASK;
	127	mod \|= S3C2412_IISMOD_MODE_RXONLY;
	128	break;
	129
	130	case S3C2412_IISMOD_MODE_TXONLY:
	131	mod &= ~S3C2412_IISMOD_MODE_MASK;
	132	con &= ~S3C2412_IISCON_IIS_ACTIVE;
	133	break;
	134
	135	default:
abbc8246 MB	136	dev_err(i2s->dev, "TXDIS: Invalid MODE %x in IISMOD\n",
	137	mod & S3C2412_IISMOD_MODE_MASK);
	138	break;
dc85447b BD	139	}
	140
	141	writel(mod, regs + S3C2412_IISMOD);
	142	writel(con, regs + S3C2412_IISCON);
	143	}
	144
	145	fic = readl(regs + S3C2412_IISFIC);
	146	dbg_showcon(__func__, con);
ee7d4767	147	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b	148	}
dc85447b	149
abbc8246	150	static void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on)
dc85447b BD	151	{
	152	void __iomem *regs = i2s->regs;
	153	u32 fic, con, mod;
	154
ee7d4767	155	pr_debug("%s(%d)\n", __func__, on);
dc85447b BD	156
	157	fic = readl(regs + S3C2412_IISFIC);
	158	con = readl(regs + S3C2412_IISCON);
	159	mod = readl(regs + S3C2412_IISMOD);
	160
ee7d4767	161	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b BD	162
	163	if (on) {
	164	con \|= S3C2412_IISCON_RXDMA_ACTIVE \| S3C2412_IISCON_IIS_ACTIVE;
	165	con &= ~S3C2412_IISCON_RXDMA_PAUSE;
	166	con &= ~S3C2412_IISCON_RXCH_PAUSE;
	167
	168	switch (mod & S3C2412_IISMOD_MODE_MASK) {
	169	case S3C2412_IISMOD_MODE_TXRX:
	170	case S3C2412_IISMOD_MODE_RXONLY:
	171	/* do nothing, we are in the right mode */
	172	break;
	173
	174	case S3C2412_IISMOD_MODE_TXONLY:
	175	mod &= ~S3C2412_IISMOD_MODE_MASK;
	176	mod \|= S3C2412_IISMOD_MODE_TXRX;
	177	break;
	178
	179	default:
abbc8246 MB	180	dev_err(i2s->dev, "RXEN: Invalid MODE %x in IISMOD\n",
abbc8246 MB	181	mod & S3C2412_IISMOD_MODE_MASK);
dc85447b BD	182	}
	183
	184	writel(mod, regs + S3C2412_IISMOD);
	185	writel(con, regs + S3C2412_IISCON);
	186	} else {
	187	/* See txctrl notes on FIFOs. */
	188
	189	con &= ~S3C2412_IISCON_RXDMA_ACTIVE;
	190	con \|= S3C2412_IISCON_RXDMA_PAUSE;
	191	con \|= S3C2412_IISCON_RXCH_PAUSE;
	192
	193	switch (mod & S3C2412_IISMOD_MODE_MASK) {
	194	case S3C2412_IISMOD_MODE_RXONLY:
	195	con &= ~S3C2412_IISCON_IIS_ACTIVE;
	196	mod &= ~S3C2412_IISMOD_MODE_MASK;
	197	break;
	198
	199	case S3C2412_IISMOD_MODE_TXRX:
	200	mod &= ~S3C2412_IISMOD_MODE_MASK;
	201	mod \|= S3C2412_IISMOD_MODE_TXONLY;
	202	break;
	203
	204	default:
abbc8246 MB	205	dev_err(i2s->dev, "RXDIS: Invalid MODE %x in IISMOD\n",
abbc8246 MB	206	mod & S3C2412_IISMOD_MODE_MASK);
dc85447b BD	207	}
	208
	209	writel(con, regs + S3C2412_IISCON);
	210	writel(mod, regs + S3C2412_IISMOD);
	211	}
	212
	213	fic = readl(regs + S3C2412_IISFIC);
ee7d4767	214	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b	215	}
dc85447b	216
fa68e002 J	217	#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
fa68e002 J	218
dc85447b BD	219	/*
	220	* Wait for the LR signal to allow synchronisation to the L/R clock
	221	* from the codec. May only be needed for slave mode.
	222	*/
	223	static int s3c2412_snd_lrsync(struct s3c_i2sv2_info *i2s)
	224	{
	225	u32 iiscon;
fa68e002	226	unsigned long loops = msecs_to_loops(5);
dc85447b	227
ee7d4767	228	pr_debug("Entered %s\n", __func__);
dc85447b	229
fa68e002	230	while (--loops) {
dc85447b BD	231	iiscon = readl(i2s->regs + S3C2412_IISCON);
	232	if (iiscon & S3C2412_IISCON_LRINDEX)
	233	break;
	234
fa68e002 J	235	cpu_relax();
	236	}
	237
	238	if (!loops) {
	239	printk(KERN_ERR "%s: timeout\n", __func__);
	240	return -ETIMEDOUT;
dc85447b BD	241	}
	242
	243	return 0;
	244	}
	245
	246	/*
	247	* Set S3C2412 I2S DAI format
	248	*/
	249	static int s3c2412_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
	250	unsigned int fmt)
	251	{
	252	struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
	253	u32 iismod;
	254
ee7d4767	255	pr_debug("Entered %s\n", __func__);
dc85447b BD	256
dc85447b BD	257	iismod = readl(i2s->regs + S3C2412_IISMOD);
ee7d4767	258	pr_debug("hw_params r: IISMOD: %x \n", iismod);
dc85447b	259
dc85447b BD	260	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	261	case SND_SOC_DAIFMT_CBM_CFM:
	262	i2s->master = 0;
ce76f9fd	263	iismod \|= S3C2412_IISMOD_SLAVE;
dc85447b BD	264	break;
	265	case SND_SOC_DAIFMT_CBS_CFS:
	266	i2s->master = 1;
ce76f9fd	267	iismod &= ~S3C2412_IISMOD_SLAVE;
dc85447b BD	268	break;
dc85447b BD	269	default:
48b418d7	270	pr_err("unknown master/slave format\n");
dc85447b BD	271	return -EINVAL;
	272	}
	273
	274	iismod &= ~S3C2412_IISMOD_SDF_MASK;
	275
	276	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	277	case SND_SOC_DAIFMT_RIGHT_J:
fd5ad654	278	iismod \|= S3C2412_IISMOD_LR_RLOW;
dc85447b BD	279	iismod \|= S3C2412_IISMOD_SDF_MSB;
	280	break;
	281	case SND_SOC_DAIFMT_LEFT_J:
fd5ad654	282	iismod \|= S3C2412_IISMOD_LR_RLOW;
dc85447b BD	283	iismod \|= S3C2412_IISMOD_SDF_LSB;
	284	break;
	285	case SND_SOC_DAIFMT_I2S:
fd5ad654	286	iismod &= ~S3C2412_IISMOD_LR_RLOW;
dc85447b BD	287	iismod \|= S3C2412_IISMOD_SDF_IIS;
	288	break;
	289	default:
38e43c81	290	pr_err("Unknown data format\n");
dc85447b BD	291	return -EINVAL;
	292	}
	293
	294	writel(iismod, i2s->regs + S3C2412_IISMOD);
ee7d4767	295	pr_debug("hw_params w: IISMOD: %x \n", iismod);
dc85447b BD	296	return 0;
	297	}
	298
9c9b1257	299	static int s3c_i2sv2_hw_params(struct snd_pcm_substream *substream,
dc85447b	300	struct snd_pcm_hw_params *params,
f0fba2ad	301	struct snd_soc_dai *dai)
dc85447b	302	{
f0fba2ad	303	struct s3c_i2sv2_info *i2s = to_info(dai);
ea37bd4d	304	struct snd_dmaengine_dai_dma_data *dma_data;
dc85447b BD	305	u32 iismod;
dc85447b BD	306
ee7d4767	307	pr_debug("Entered %s\n", __func__);
dc85447b BD	308
dc85447b BD	309	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
fd23b7de	310	dma_data = i2s->dma_playback;
dc85447b	311	else
fd23b7de DM	312	dma_data = i2s->dma_capture;
fd23b7de DM	313
f0fba2ad	314	snd_soc_dai_set_dma_data(dai, substream, dma_data);
dc85447b BD	315
	316	/* Working copies of register */
	317	iismod = readl(i2s->regs + S3C2412_IISMOD);
ee7d4767	318	pr_debug("%s: r: IISMOD: %x\n", __func__, iismod);
dc85447b	319
bf328826	320	iismod &= ~S3C64XX_IISMOD_BLC_MASK;
553b1dd5	321	/* Sample size */
88ce1465 TB	322	switch (params_width(params)) {
88ce1465 TB	323	case 8:
bf328826	324	iismod \|= S3C64XX_IISMOD_BLC_8BIT;
553b1dd5	325	break;
88ce1465	326	case 16:
553b1dd5	327	break;
88ce1465	328	case 24:
bf328826	329	iismod \|= S3C64XX_IISMOD_BLC_24BIT;
553b1dd5 MB	330	break;
553b1dd5 MB	331	}
dc85447b BD	332
dc85447b BD	333	writel(iismod, i2s->regs + S3C2412_IISMOD);
ee7d4767	334	pr_debug("%s: w: IISMOD: %x\n", __func__, iismod);
8a7c2518 JB	335
	336	return 0;
	337	}
	338
	339	static int s3c_i2sv2_set_sysclk(struct snd_soc_dai *cpu_dai,
	340	int clk_id, unsigned int freq, int dir)
	341	{
	342	struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
	343	u32 iismod = readl(i2s->regs + S3C2412_IISMOD);
	344
	345	pr_debug("Entered %s\n", __func__);
	346	pr_debug("%s r: IISMOD: %x\n", __func__, iismod);
	347
	348	switch (clk_id) {
	349	case S3C_I2SV2_CLKSRC_PCLK:
	350	iismod &= ~S3C2412_IISMOD_IMS_SYSMUX;
	351	break;
	352
	353	case S3C_I2SV2_CLKSRC_AUDIOBUS:
	354	iismod \|= S3C2412_IISMOD_IMS_SYSMUX;
	355	break;
	356
	357	case S3C_I2SV2_CLKSRC_CDCLK:
	358	/* Error if controller doesn't have the CDCLKCON bit */
	359	if (!(i2s->feature & S3C_FEATURE_CDCLKCON))
	360	return -EINVAL;
	361
	362	switch (dir) {
	363	case SND_SOC_CLOCK_IN:
	364	iismod \|= S3C64XX_IISMOD_CDCLKCON;
	365	break;
	366	case SND_SOC_CLOCK_OUT:
	367	iismod &= ~S3C64XX_IISMOD_CDCLKCON;
	368	break;
	369	default:
	370	return -EINVAL;
	371	}
	372	break;
	373
	374	default:
	375	return -EINVAL;
	376	}
	377
	378	writel(iismod, i2s->regs + S3C2412_IISMOD);
	379	pr_debug("%s w: IISMOD: %x\n", __func__, iismod);
	380
dc85447b BD	381	return 0;
	382	}
	383
	384	static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
	385	struct snd_soc_dai *dai)
	386	{
	387	struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad	388	struct s3c_i2sv2_info *i2s = to_info(rtd->cpu_dai);
dc85447b BD	389	int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
	390	unsigned long irqs;
	391	int ret = 0;
	392
ee7d4767	393	pr_debug("Entered %s\n", __func__);
dc85447b BD	394
	395	switch (cmd) {
	396	case SNDRV_PCM_TRIGGER_START:
	397	/* On start, ensure that the FIFOs are cleared and reset. */
	398
	399	writel(capture ? S3C2412_IISFIC_RXFLUSH : S3C2412_IISFIC_TXFLUSH,
	400	i2s->regs + S3C2412_IISFIC);
	401
	402	/* clear again, just in case */
	403	writel(0x0, i2s->regs + S3C2412_IISFIC);
	404
	405	case SNDRV_PCM_TRIGGER_RESUME:
	406	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	407	if (!i2s->master) {
	408	ret = s3c2412_snd_lrsync(i2s);
	409	if (ret)
	410	goto exit_err;
	411	}
	412
	413	local_irq_save(irqs);
	414
	415	if (capture)
	416	s3c2412_snd_rxctrl(i2s, 1);
	417	else
	418	s3c2412_snd_txctrl(i2s, 1);
	419
	420	local_irq_restore(irqs);
faf907c7	421
dc85447b BD	422	break;
	423
	424	case SNDRV_PCM_TRIGGER_STOP:
	425	case SNDRV_PCM_TRIGGER_SUSPEND:
	426	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	427	local_irq_save(irqs);
	428
	429	if (capture)
	430	s3c2412_snd_rxctrl(i2s, 0);
	431	else
	432	s3c2412_snd_txctrl(i2s, 0);
	433
	434	local_irq_restore(irqs);
	435	break;
	436	default:
	437	ret = -EINVAL;
	438	break;
	439	}
	440
	441	exit_err:
	442	return ret;
	443	}
	444
	445	/*
	446	* Set S3C2412 Clock dividers
	447	*/
	448	static int s3c2412_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
	449	int div_id, int div)
	450	{
	451	struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
	452	u32 reg;
	453
ee7d4767	454	pr_debug("%s(%p, %d, %d)\n", __func__, cpu_dai, div_id, div);
dc85447b BD	455
	456	switch (div_id) {
	457	case S3C_I2SV2_DIV_BCLK:
51c6ab13 JB	458	switch (div) {
	459	case 16:
	460	div = S3C2412_IISMOD_BCLK_16FS;
	461	break;
fd5ad654	462
51c6ab13 JB	463	case 32:
	464	div = S3C2412_IISMOD_BCLK_32FS;
	465	break;
fd5ad654	466
51c6ab13 JB	467	case 24:
	468	div = S3C2412_IISMOD_BCLK_24FS;
	469	break;
fd5ad654	470
51c6ab13 JB	471	case 48:
	472	div = S3C2412_IISMOD_BCLK_48FS;
	473	break;
fd5ad654	474
51c6ab13 JB	475	default:
51c6ab13 JB	476	return -EINVAL;
fd5ad654 J	477	}
fd5ad654 J	478
dc85447b BD	479	reg = readl(i2s->regs + S3C2412_IISMOD);
	480	reg &= ~S3C2412_IISMOD_BCLK_MASK;
	481	writel(reg \| div, i2s->regs + S3C2412_IISMOD);
	482
ee7d4767	483	pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
dc85447b BD	484	break;
	485
	486	case S3C_I2SV2_DIV_RCLK:
51c6ab13 JB	487	switch (div) {
	488	case 256:
	489	div = S3C2412_IISMOD_RCLK_256FS;
	490	break;
dc85447b	491
51c6ab13 JB	492	case 384:
	493	div = S3C2412_IISMOD_RCLK_384FS;
	494	break;
dc85447b	495
51c6ab13 JB	496	case 512:
	497	div = S3C2412_IISMOD_RCLK_512FS;
	498	break;
dc85447b	499
51c6ab13 JB	500	case 768:
	501	div = S3C2412_IISMOD_RCLK_768FS;
	502	break;
dc85447b	503
51c6ab13 JB	504	default:
51c6ab13 JB	505	return -EINVAL;
dc85447b BD	506	}
	507
	508	reg = readl(i2s->regs + S3C2412_IISMOD);
	509	reg &= ~S3C2412_IISMOD_RCLK_MASK;
	510	writel(reg \| div, i2s->regs + S3C2412_IISMOD);
ee7d4767	511	pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
dc85447b BD	512	break;
	513
	514	case S3C_I2SV2_DIV_PRESCALER:
	515	if (div >= 0) {
	516	writel((div << 8) \| S3C2412_IISPSR_PSREN,
	517	i2s->regs + S3C2412_IISPSR);
	518	} else {
	519	writel(0x0, i2s->regs + S3C2412_IISPSR);
	520	}
ee7d4767	521	pr_debug("%s: PSR=%08x\n", __func__, readl(i2s->regs + S3C2412_IISPSR));
dc85447b BD	522	break;
	523
	524	default:
	525	return -EINVAL;
	526	}
	527
	528	return 0;
	529	}
	530
1ca75780 MB	531	static snd_pcm_sframes_t s3c2412_i2s_delay(struct snd_pcm_substream *substream,
	532	struct snd_soc_dai *dai)
	533	{
	534	struct s3c_i2sv2_info *i2s = to_info(dai);
	535	u32 reg = readl(i2s->regs + S3C2412_IISFIC);
	536	snd_pcm_sframes_t delay;
	537
	538	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	539	delay = S3C2412_IISFIC_TXCOUNT(reg);
	540	else
	541	delay = S3C2412_IISFIC_RXCOUNT(reg);
	542
	543	return delay;
	544	}
	545
57282427 JB	546	struct clk s3c_i2sv2_get_clock(struct snd_soc_dai cpu_dai)
	547	{
	548	struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
	549	u32 iismod = readl(i2s->regs + S3C2412_IISMOD);
	550
	551	if (iismod & S3C2412_IISMOD_IMS_SYSMUX)
	552	return i2s->iis_cclk;
	553	else
	554	return i2s->iis_pclk;
	555	}
	556	EXPORT_SYMBOL_GPL(s3c_i2sv2_get_clock);
	557
dc85447b BD	558	/* default table of all avaialable root fs divisors */
	559	static unsigned int iis_fs_tab[] = { 256, 512, 384, 768 };
	560
1d2b7ae9 BD	561	int s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc *info,
	562	unsigned int *fstab,
	563	unsigned int rate, struct clk *clk)
dc85447b BD	564	{
	565	unsigned long clkrate = clk_get_rate(clk);
	566	unsigned int div;
	567	unsigned int fsclk;
	568	unsigned int actual;
	569	unsigned int fs;
	570	unsigned int fsdiv;
	571	signed int deviation = 0;
	572	unsigned int best_fs = 0;
	573	unsigned int best_div = 0;
	574	unsigned int best_rate = 0;
	575	unsigned int best_deviation = INT_MAX;
	576
af3ea7bd MB	577	pr_debug("Input clock rate %ldHz\n", clkrate);
af3ea7bd MB	578
dc85447b BD	579	if (fstab == NULL)
	580	fstab = iis_fs_tab;
	581
	582	for (fs = 0; fs < ARRAY_SIZE(iis_fs_tab); fs++) {
	583	fsdiv = iis_fs_tab[fs];
	584
	585	fsclk = clkrate / fsdiv;
	586	div = fsclk / rate;
	587
	588	if ((fsclk % rate) > (rate / 2))
	589	div++;
	590
	591	if (div <= 1)
	592	continue;
	593
	594	actual = clkrate / (fsdiv * div);
	595	deviation = actual - rate;
	596
449bd54d	597	printk(KERN_DEBUG "%ufs: div %u => result %u, deviation %d\n",
dc85447b BD	598	fsdiv, div, actual, deviation);
	599
	600	deviation = abs(deviation);
	601
	602	if (deviation < best_deviation) {
	603	best_fs = fsdiv;
	604	best_div = div;
	605	best_rate = actual;
	606	best_deviation = deviation;
	607	}
	608
	609	if (deviation == 0)
	610	break;
	611	}
	612
449bd54d	613	printk(KERN_DEBUG "best: fs=%u, div=%u, rate=%u\n",
dc85447b BD	614	best_fs, best_div, best_rate);
	615
	616	info->fs_div = best_fs;
	617	info->clk_div = best_div;
	618
	619	return 0;
	620	}
1d2b7ae9	621	EXPORT_SYMBOL_GPL(s3c_i2sv2_iis_calc_rate);
dc85447b	622
f0fba2ad	623	int s3c_i2sv2_probe(struct snd_soc_dai *dai,
dc85447b BD	624	struct s3c_i2sv2_info *i2s,
	625	unsigned long base)
	626	{
f0fba2ad	627	struct device *dev = dai->dev;
07736d48	628	unsigned int iismod;
dc85447b BD	629
	630	i2s->dev = dev;
	631
	632	/* record our i2s structure for later use in the callbacks */
f0fba2ad	633	snd_soc_dai_set_drvdata(dai, i2s);
c86bde54	634
dc85447b	635	i2s->iis_pclk = clk_get(dev, "iis");
fd5ad654	636	if (IS_ERR(i2s->iis_pclk)) {
b52a5195	637	dev_err(dev, "failed to get iis_clock\n");
dc85447b BD	638	iounmap(i2s->regs);
	639	return -ENOENT;
	640	}
	641
	642	clk_enable(i2s->iis_pclk);
	643
07736d48 MB	644	/* Mark ourselves as in TXRX mode so we can run through our cleanup
	645	* process without warnings. */
	646	iismod = readl(i2s->regs + S3C2412_IISMOD);
	647	iismod \|= S3C2412_IISMOD_MODE_TXRX;
	648	writel(iismod, i2s->regs + S3C2412_IISMOD);
dc85447b BD	649	s3c2412_snd_txctrl(i2s, 0);
	650	s3c2412_snd_rxctrl(i2s, 0);
	651
	652	return 0;
	653	}
dc85447b BD	654	EXPORT_SYMBOL_GPL(s3c_i2sv2_probe);
	655
	656	#ifdef CONFIG_PM
	657	static int s3c2412_i2s_suspend(struct snd_soc_dai *dai)
	658	{
	659	struct s3c_i2sv2_info *i2s = to_info(dai);
	660	u32 iismod;
	661
	662	if (dai->active) {
	663	i2s->suspend_iismod = readl(i2s->regs + S3C2412_IISMOD);
	664	i2s->suspend_iiscon = readl(i2s->regs + S3C2412_IISCON);
	665	i2s->suspend_iispsr = readl(i2s->regs + S3C2412_IISPSR);
	666
	667	/* some basic suspend checks */
	668
	669	iismod = readl(i2s->regs + S3C2412_IISMOD);
	670
	671	if (iismod & S3C2412_IISCON_RXDMA_ACTIVE)
	672	pr_warning("%s: RXDMA active?\n", __func__);
	673
	674	if (iismod & S3C2412_IISCON_TXDMA_ACTIVE)
	675	pr_warning("%s: TXDMA active?\n", __func__);
	676
	677	if (iismod & S3C2412_IISCON_IIS_ACTIVE)
	678	pr_warning("%s: IIS active\n", __func__);
	679	}
	680
	681	return 0;
	682	}
	683
	684	static int s3c2412_i2s_resume(struct snd_soc_dai *dai)
	685	{
	686	struct s3c_i2sv2_info *i2s = to_info(dai);
	687
	688	pr_info("dai_active %d, IISMOD %08x, IISCON %08x\n",
	689	dai->active, i2s->suspend_iismod, i2s->suspend_iiscon);
	690
	691	if (dai->active) {
	692	writel(i2s->suspend_iiscon, i2s->regs + S3C2412_IISCON);
	693	writel(i2s->suspend_iismod, i2s->regs + S3C2412_IISMOD);
	694	writel(i2s->suspend_iispsr, i2s->regs + S3C2412_IISPSR);
	695
	696	writel(S3C2412_IISFIC_RXFLUSH \| S3C2412_IISFIC_TXFLUSH,
	697	i2s->regs + S3C2412_IISFIC);
	698
	699	ndelay(250);
	700	writel(0x0, i2s->regs + S3C2412_IISFIC);
	701	}
	702
	703	return 0;
	704	}
	705	#else
	706	#define s3c2412_i2s_suspend NULL
	707	#define s3c2412_i2s_resume NULL
	708	#endif
	709
eca3b01d	710	int s3c_i2sv2_register_component(struct device *dev, int id,
ba4bc32e	711	const struct snd_soc_component_driver *cmp_drv,
eca3b01d	712	struct snd_soc_dai_driver *dai_drv)
dc85447b	713	{
87b132bc	714	struct snd_soc_dai_ops ops = (struct snd_soc_dai_ops )dai_drv->ops;
3715c6aa BD	715
3715c6aa BD	716	ops->trigger = s3c2412_i2s_trigger;
9c9b1257 JB	717	if (!ops->hw_params)
9c9b1257 JB	718	ops->hw_params = s3c_i2sv2_hw_params;
3715c6aa BD	719	ops->set_fmt = s3c2412_i2s_set_fmt;
3715c6aa BD	720	ops->set_clkdiv = s3c2412_i2s_set_clkdiv;
8a7c2518	721	ops->set_sysclk = s3c_i2sv2_set_sysclk;
dc85447b	722
1ca75780 MB	723	/* Allow overriding by (for example) IISv4 */
1ca75780 MB	724	if (!ops->delay)
08226614	725	ops->delay = s3c2412_i2s_delay;
1ca75780	726
9eeb9572 SK	727	dai_drv->suspend = s3c2412_i2s_suspend;
9eeb9572 SK	728	dai_drv->resume = s3c2412_i2s_resume;
dc85447b	729
7253e354	730	return devm_snd_soc_register_component(dev, cmp_drv, dai_drv, 1);
dc85447b	731	}
eca3b01d	732	EXPORT_SYMBOL_GPL(s3c_i2sv2_register_component);
a396e32e MB	733
a396e32e MB	734	MODULE_LICENSE("GPL");