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libnvdimm, nfit: move flush hint mapping to region-device driver-data
[deliverable/linux.git] / tools / testing / nvdimm / test / nfit.c
CommitLineData
6bc75619
DW		 1/*
2 * Copyright(c) 2013-2015 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of version 2 of the GNU General Public License as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14#include <linux/platform_device.h>
15#include <linux/dma-mapping.h>
16#include <linux/libnvdimm.h>
17#include <linux/vmalloc.h>
18#include <linux/device.h>
19#include <linux/module.h>
20985164 20#include <linux/mutex.h>
6bc75619
DW		 21#include <linux/ndctl.h>
22#include <linux/sizes.h>
20985164 23#include <linux/list.h>
6bc75619
DW		 24#include <linux/slab.h>
25#include <nfit.h>
26#include <nd.h>
27#include "nfit_test.h"
28
29/*
30 * Generate an NFIT table to describe the following topology:
31 *
32 * BUS0: Interleaved PMEM regions, and aliasing with BLK regions
33 *
34 * (a) (b) DIMM BLK-REGION
35 * +----------+--------------+----------+---------+
36 * +------+ | blk2.0 | pm0.0 | blk2.1 | pm1.0 | 0 region2
37 * | imc0 +--+- - - - - region0 - - - -+----------+ +
38 * +--+---+ | blk3.0 | pm0.0 | blk3.1 | pm1.0 | 1 region3
39 * | +----------+--------------v----------v v
40 * +--+---+ | |
41 * | cpu0 | region1
42 * +--+---+ | |
43 * | +-------------------------^----------^ ^
44 * +--+---+ | blk4.0 | pm1.0 | 2 region4
45 * | imc1 +--+-------------------------+----------+ +
46 * +------+ | blk5.0 | pm1.0 | 3 region5
47 * +-------------------------+----------+-+-------+
48 *
20985164
VV		 49 * +--+---+
50 * | cpu1 |
51 * +--+---+ (Hotplug DIMM)
52 * | +----------------------------------------------+
53 * +--+---+ | blk6.0/pm7.0 | 4 region6/7
54 * | imc0 +--+----------------------------------------------+
55 * +------+
56 *
57 *
6bc75619
DW		 58 * *) In this layout we have four dimms and two memory controllers in one
59 * socket. Each unique interface (BLK or PMEM) to DPA space
60 * is identified by a region device with a dynamically assigned id.
61 *
62 * *) The first portion of dimm0 and dimm1 are interleaved as REGION0.
63 * A single PMEM namespace "pm0.0" is created using half of the
64 * REGION0 SPA-range. REGION0 spans dimm0 and dimm1. PMEM namespace
65 * allocate from from the bottom of a region. The unallocated
66 * portion of REGION0 aliases with REGION2 and REGION3. That
67 * unallacted capacity is reclaimed as BLK namespaces ("blk2.0" and
68 * "blk3.0") starting at the base of each DIMM to offset (a) in those
69 * DIMMs. "pm0.0", "blk2.0" and "blk3.0" are free-form readable
70 * names that can be assigned to a namespace.
71 *
72 * *) In the last portion of dimm0 and dimm1 we have an interleaved
73 * SPA range, REGION1, that spans those two dimms as well as dimm2
74 * and dimm3. Some of REGION1 allocated to a PMEM namespace named
75 * "pm1.0" the rest is reclaimed in 4 BLK namespaces (for each
76 * dimm in the interleave set), "blk2.1", "blk3.1", "blk4.0", and
77 * "blk5.0".
78 *
79 * *) The portion of dimm2 and dimm3 that do not participate in the
80 * REGION1 interleaved SPA range (i.e. the DPA address below offset
81 * (b) are also included in the "blk4.0" and "blk5.0" namespaces.
82 * Note, that BLK namespaces need not be contiguous in DPA-space, and
83 * can consume aliased capacity from multiple interleave sets.
84 *
85 * BUS1: Legacy NVDIMM (single contiguous range)
86 *
87 * region2
88 * +---------------------+
89 * |---------------------|
90 * || pm2.0 ||
91 * |---------------------|
92 * +---------------------+
93 *
94 * *) A NFIT-table may describe a simple system-physical-address range
95 * with no BLK aliasing. This type of region may optionally
96 * reference an NVDIMM.
97 */
98enum {
20985164
VV		 99 NUM_PM = 3,
100 NUM_DCR = 5,
6bc75619
DW		 101 NUM_BDW = NUM_DCR,
102 NUM_SPA = NUM_PM + NUM_DCR + NUM_BDW,
103 NUM_MEM = NUM_DCR + NUM_BDW + 2 /* spa0 iset */ + 4 /* spa1 iset */,
104 DIMM_SIZE = SZ_32M,
105 LABEL_SIZE = SZ_128K,
106 SPA0_SIZE = DIMM_SIZE,
107 SPA1_SIZE = DIMM_SIZE*2,
108 SPA2_SIZE = DIMM_SIZE,
109 BDW_SIZE = 64 << 8,
110 DCR_SIZE = 12,
111 NUM_NFITS = 2, /* permit testing multiple NFITs per system */
112};
113
114struct nfit_test_dcr {
115 __le64 bdw_addr;
116 __le32 bdw_status;
117 __u8 aperature[BDW_SIZE];
118};
119
120#define NFIT_DIMM_HANDLE(node, socket, imc, chan, dimm) \
121 (((node & 0xfff) << 16) | ((socket & 0xf) << 12) \
122 | ((imc & 0xf) << 8) | ((chan & 0xf) << 4) | (dimm & 0xf))
123
124static u32 handle[NUM_DCR] = {
125 [0] = NFIT_DIMM_HANDLE(0, 0, 0, 0, 0),
126 [1] = NFIT_DIMM_HANDLE(0, 0, 0, 0, 1),
127 [2] = NFIT_DIMM_HANDLE(0, 0, 1, 0, 0),
128 [3] = NFIT_DIMM_HANDLE(0, 0, 1, 0, 1),
20985164 129 [4] = NFIT_DIMM_HANDLE(0, 1, 0, 0, 0),
6bc75619
DW		 130};
131
132struct nfit_test {
133 struct acpi_nfit_desc acpi_desc;
134 struct platform_device pdev;
135 struct list_head resources;
136 void *nfit_buf;
137 dma_addr_t nfit_dma;
138 size_t nfit_size;
139 int num_dcr;
140 int num_pm;
141 void **dimm;
142 dma_addr_t *dimm_dma;
9d27a87e
DW		 143 void **flush;
144 dma_addr_t *flush_dma;
6bc75619
DW		 145 void **label;
146 dma_addr_t *label_dma;
147 void **spa_set;
148 dma_addr_t *spa_set_dma;
149 struct nfit_test_dcr **dcr;
150 dma_addr_t *dcr_dma;
151 int (*alloc)(struct nfit_test *t);
152 void (*setup)(struct nfit_test *t);
20985164 153 int setup_hotplug;
f471f1a7
DW		 154 struct ars_state {
155 struct nd_cmd_ars_status *ars_status;
156 unsigned long deadline;
157 spinlock_t lock;
158 } ars_state;
6bc75619
DW		 159};
160
161static struct nfit_test *to_nfit_test(struct device *dev)
162{
163 struct platform_device *pdev = to_platform_device(dev);
164
165 return container_of(pdev, struct nfit_test, pdev);
166}
167
39c686b8
VV		 168static int nfit_test_cmd_get_config_size(struct nd_cmd_get_config_size *nd_cmd,
169 unsigned int buf_len)
170{
171 if (buf_len < sizeof(*nd_cmd))
172 return -EINVAL;
173
174 nd_cmd->status = 0;
175 nd_cmd->config_size = LABEL_SIZE;
176 nd_cmd->max_xfer = SZ_4K;
177
178 return 0;
179}
180
181static int nfit_test_cmd_get_config_data(struct nd_cmd_get_config_data_hdr
182 *nd_cmd, unsigned int buf_len, void *label)
183{
184 unsigned int len, offset = nd_cmd->in_offset;
185 int rc;
186
187 if (buf_len < sizeof(*nd_cmd))
188 return -EINVAL;
189 if (offset >= LABEL_SIZE)
190 return -EINVAL;
191 if (nd_cmd->in_length + sizeof(*nd_cmd) > buf_len)
192 return -EINVAL;
193
194 nd_cmd->status = 0;
195 len = min(nd_cmd->in_length, LABEL_SIZE - offset);
196 memcpy(nd_cmd->out_buf, label + offset, len);
197 rc = buf_len - sizeof(*nd_cmd) - len;
198
199 return rc;
200}
201
202static int nfit_test_cmd_set_config_data(struct nd_cmd_set_config_hdr *nd_cmd,
203 unsigned int buf_len, void *label)
204{
205 unsigned int len, offset = nd_cmd->in_offset;
206 u32 *status;
207 int rc;
208
209 if (buf_len < sizeof(*nd_cmd))
210 return -EINVAL;
211 if (offset >= LABEL_SIZE)
212 return -EINVAL;
213 if (nd_cmd->in_length + sizeof(*nd_cmd) + 4 > buf_len)
214 return -EINVAL;
215
216 status = (void *)nd_cmd + nd_cmd->in_length + sizeof(*nd_cmd);
217 *status = 0;
218 len = min(nd_cmd->in_length, LABEL_SIZE - offset);
219 memcpy(label + offset, nd_cmd->in_buf, len);
220 rc = buf_len - sizeof(*nd_cmd) - (len + 4);
221
222 return rc;
223}
224
747ffe11 225#define NFIT_TEST_ARS_RECORDS 4
d4f32367 226#define NFIT_TEST_CLEAR_ERR_UNIT 256
747ffe11 227
39c686b8
VV		 228static int nfit_test_cmd_ars_cap(struct nd_cmd_ars_cap *nd_cmd,
229 unsigned int buf_len)
230{
231 if (buf_len < sizeof(*nd_cmd))
232 return -EINVAL;
233
747ffe11
DW		 234 nd_cmd->max_ars_out = sizeof(struct nd_cmd_ars_status)
235 + NFIT_TEST_ARS_RECORDS * sizeof(struct nd_ars_record);
39c686b8 236 nd_cmd->status = (ND_ARS_PERSISTENT | ND_ARS_VOLATILE) << 16;
d4f32367 237 nd_cmd->clear_err_unit = NFIT_TEST_CLEAR_ERR_UNIT;
39c686b8
VV		 238
239 return 0;
240}
241
f471f1a7
DW		 242/*
243 * Initialize the ars_state to return an ars_result 1 second in the future with
244 * a 4K error range in the middle of the requested address range.
245 */
246static void post_ars_status(struct ars_state *ars_state, u64 addr, u64 len)
39c686b8 247{
f471f1a7
DW		 248 struct nd_cmd_ars_status *ars_status;
249 struct nd_ars_record *ars_record;
250
251 ars_state->deadline = jiffies + 1*HZ;
252 ars_status = ars_state->ars_status;
253 ars_status->status = 0;
254 ars_status->out_length = sizeof(struct nd_cmd_ars_status)
255 + sizeof(struct nd_ars_record);
256 ars_status->address = addr;
257 ars_status->length = len;
258 ars_status->type = ND_ARS_PERSISTENT;
259 ars_status->num_records = 1;
260 ars_record = &ars_status->records[0];
261 ars_record->handle = 0;
262 ars_record->err_address = addr + len / 2;
263 ars_record->length = SZ_4K;
264}
265
266static int nfit_test_cmd_ars_start(struct ars_state *ars_state,
267 struct nd_cmd_ars_start *ars_start, unsigned int buf_len,
268 int *cmd_rc)
269{
270 if (buf_len < sizeof(*ars_start))
39c686b8
VV		 271 return -EINVAL;
272
f471f1a7
DW		 273 spin_lock(&ars_state->lock);
274 if (time_before(jiffies, ars_state->deadline)) {
275 ars_start->status = NFIT_ARS_START_BUSY;
276 *cmd_rc = -EBUSY;
277 } else {
278 ars_start->status = 0;
279 ars_start->scrub_time = 1;
280 post_ars_status(ars_state, ars_start->address,
281 ars_start->length);
282 *cmd_rc = 0;
283 }
284 spin_unlock(&ars_state->lock);
39c686b8
VV		 285
286 return 0;
287}
288
f471f1a7
DW		 289static int nfit_test_cmd_ars_status(struct ars_state *ars_state,
290 struct nd_cmd_ars_status *ars_status, unsigned int buf_len,
291 int *cmd_rc)
39c686b8 292{
f471f1a7 293 if (buf_len < ars_state->ars_status->out_length)
39c686b8
VV		 294 return -EINVAL;
295
f471f1a7
DW		 296 spin_lock(&ars_state->lock);
297 if (time_before(jiffies, ars_state->deadline)) {
298 memset(ars_status, 0, buf_len);
299 ars_status->status = NFIT_ARS_STATUS_BUSY;
300 ars_status->out_length = sizeof(*ars_status);
301 *cmd_rc = -EBUSY;
302 } else {
303 memcpy(ars_status, ars_state->ars_status,
304 ars_state->ars_status->out_length);
305 *cmd_rc = 0;
306 }
307 spin_unlock(&ars_state->lock);
39c686b8
VV		 308 return 0;
309}
310
d4f32367
DW		 311static int nfit_test_cmd_clear_error(struct nd_cmd_clear_error *clear_err,
312 unsigned int buf_len, int *cmd_rc)
313{
314 const u64 mask = NFIT_TEST_CLEAR_ERR_UNIT - 1;
315 if (buf_len < sizeof(*clear_err))
316 return -EINVAL;
317
318 if ((clear_err->address & mask) || (clear_err->length & mask))
319 return -EINVAL;
320
321 /*
322 * Report 'all clear' success for all commands even though a new
323 * scrub will find errors again. This is enough to have the
324 * error removed from the 'badblocks' tracking in the pmem
325 * driver.
326 */
327 clear_err->status = 0;
328 clear_err->cleared = clear_err->length;
329 *cmd_rc = 0;
330 return 0;
331}
332
baa51277
DW		 333static int nfit_test_cmd_smart(struct nd_cmd_smart *smart, unsigned int buf_len)
334{
335 static const struct nd_smart_payload smart_data = {
336 .flags = ND_SMART_HEALTH_VALID | ND_SMART_TEMP_VALID
337 | ND_SMART_SPARES_VALID | ND_SMART_ALARM_VALID
338 | ND_SMART_USED_VALID | ND_SMART_SHUTDOWN_VALID,
339 .health = ND_SMART_NON_CRITICAL_HEALTH,
340 .temperature = 23 * 16,
341 .spares = 75,
342 .alarm_flags = ND_SMART_SPARE_TRIP | ND_SMART_TEMP_TRIP,
343 .life_used = 5,
344 .shutdown_state = 0,
345 .vendor_size = 0,
346 };
347
348 if (buf_len < sizeof(*smart))
349 return -EINVAL;
350 memcpy(smart->data, &smart_data, sizeof(smart_data));
351 return 0;
352}
353
354static int nfit_test_cmd_smart_threshold(struct nd_cmd_smart_threshold *smart_t,
355 unsigned int buf_len)
356{
357 static const struct nd_smart_threshold_payload smart_t_data = {
358 .alarm_control = ND_SMART_SPARE_TRIP | ND_SMART_TEMP_TRIP,
359 .temperature = 40 * 16,
360 .spares = 5,
361 };
362
363 if (buf_len < sizeof(*smart_t))
364 return -EINVAL;
365 memcpy(smart_t->data, &smart_t_data, sizeof(smart_t_data));
366 return 0;
367}
368
6bc75619
DW		 369static int nfit_test_ctl(struct nvdimm_bus_descriptor *nd_desc,
370 struct nvdimm *nvdimm, unsigned int cmd, void *buf,
aef25338 371 unsigned int buf_len, int *cmd_rc)
6bc75619
DW		 372{
373 struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);
374 struct nfit_test *t = container_of(acpi_desc, typeof(*t), acpi_desc);
6634fb06 375 unsigned int func = cmd;
f471f1a7
DW		 376 int i, rc = 0, __cmd_rc;
377
378 if (!cmd_rc)
379 cmd_rc = &__cmd_rc;
380 *cmd_rc = 0;
6bc75619 381
39c686b8
VV		 382 if (nvdimm) {
383 struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
e3654eca 384 unsigned long cmd_mask = nvdimm_cmd_mask(nvdimm);
6bc75619 385
6634fb06
DW		 386 if (!nfit_mem)
387 return -ENOTTY;
388
389 if (cmd == ND_CMD_CALL) {
390 struct nd_cmd_pkg *call_pkg = buf;
391
392 buf_len = call_pkg->nd_size_in + call_pkg->nd_size_out;
393 buf = (void *) call_pkg->nd_payload;
394 func = call_pkg->nd_command;
395 if (call_pkg->nd_family != nfit_mem->family)
396 return -ENOTTY;
397 }
398
399 if (!test_bit(cmd, &cmd_mask)
400 || !test_bit(func, &nfit_mem->dsm_mask))
39c686b8
VV		 401 return -ENOTTY;
402
403 /* lookup label space for the given dimm */
404 for (i = 0; i < ARRAY_SIZE(handle); i++)
405 if (__to_nfit_memdev(nfit_mem)->device_handle ==
406 handle[i])
407 break;
408 if (i >= ARRAY_SIZE(handle))
409 return -ENXIO;
410
6634fb06 411 switch (func) {
39c686b8
VV		 412 case ND_CMD_GET_CONFIG_SIZE:
413 rc = nfit_test_cmd_get_config_size(buf, buf_len);
6bc75619 414 break;
39c686b8
VV		 415 case ND_CMD_GET_CONFIG_DATA:
416 rc = nfit_test_cmd_get_config_data(buf, buf_len,
417 t->label[i]);
418 break;
419 case ND_CMD_SET_CONFIG_DATA:
420 rc = nfit_test_cmd_set_config_data(buf, buf_len,
421 t->label[i]);
422 break;
baa51277
DW		 423 case ND_CMD_SMART:
424 rc = nfit_test_cmd_smart(buf, buf_len);
425 break;
426 case ND_CMD_SMART_THRESHOLD:
427 rc = nfit_test_cmd_smart_threshold(buf, buf_len);
428 break;
39c686b8
VV		 429 default:
430 return -ENOTTY;
431 }
432 } else {
f471f1a7
DW		 433 struct ars_state *ars_state = &t->ars_state;
434
e3654eca 435 if (!nd_desc || !test_bit(cmd, &nd_desc->cmd_mask))
39c686b8
VV		 436 return -ENOTTY;
437
6634fb06 438 switch (func) {
39c686b8
VV		 439 case ND_CMD_ARS_CAP:
440 rc = nfit_test_cmd_ars_cap(buf, buf_len);
441 break;
442 case ND_CMD_ARS_START:
f471f1a7
DW		 443 rc = nfit_test_cmd_ars_start(ars_state, buf, buf_len,
444 cmd_rc);
39c686b8
VV		 445 break;
446 case ND_CMD_ARS_STATUS:
f471f1a7
DW		 447 rc = nfit_test_cmd_ars_status(ars_state, buf, buf_len,
448 cmd_rc);
39c686b8 449 break;
d4f32367
DW		 450 case ND_CMD_CLEAR_ERROR:
451 rc = nfit_test_cmd_clear_error(buf, buf_len, cmd_rc);
452 break;
39c686b8
VV		 453 default:
454 return -ENOTTY;
455 }
6bc75619
DW		 456 }
457
458 return rc;
459}
460
461static DEFINE_SPINLOCK(nfit_test_lock);
462static struct nfit_test *instances[NUM_NFITS];
463
464static void release_nfit_res(void *data)
465{
466 struct nfit_test_resource *nfit_res = data;
467 struct resource *res = nfit_res->res;
468
469 spin_lock(&nfit_test_lock);
470 list_del(&nfit_res->list);
471 spin_unlock(&nfit_test_lock);
472
ee8520fe 473 vfree(nfit_res->buf);
6bc75619
DW		 474 kfree(res);
475 kfree(nfit_res);
476}
477
478static void *__test_alloc(struct nfit_test *t, size_t size, dma_addr_t *dma,
479 void *buf)
480{
481 struct device *dev = &t->pdev.dev;
482 struct resource *res = kzalloc(sizeof(*res) * 2, GFP_KERNEL);
483 struct nfit_test_resource *nfit_res = kzalloc(sizeof(*nfit_res),
484 GFP_KERNEL);
485 int rc;
486
487 if (!res || !buf || !nfit_res)
488 goto err;
489 rc = devm_add_action(dev, release_nfit_res, nfit_res);
490 if (rc)
491 goto err;
492 INIT_LIST_HEAD(&nfit_res->list);
493 memset(buf, 0, size);
494 nfit_res->dev = dev;
495 nfit_res->buf = buf;
496 nfit_res->res = res;
497 res->start = *dma;
498 res->end = *dma + size - 1;
499 res->name = "NFIT";
500 spin_lock(&nfit_test_lock);
501 list_add(&nfit_res->list, &t->resources);
502 spin_unlock(&nfit_test_lock);
503
504 return nfit_res->buf;
505 err:
ee8520fe 506 if (buf)
6bc75619
DW		 507 vfree(buf);
508 kfree(res);
509 kfree(nfit_res);
510 return NULL;
511}
512
513static void *test_alloc(struct nfit_test *t, size_t size, dma_addr_t *dma)
514{
515 void *buf = vmalloc(size);
516
517 *dma = (unsigned long) buf;
518 return __test_alloc(t, size, dma, buf);
519}
520
6bc75619
DW		 521static struct nfit_test_resource *nfit_test_lookup(resource_size_t addr)
522{
523 int i;
524
525 for (i = 0; i < ARRAY_SIZE(instances); i++) {
526 struct nfit_test_resource *n, *nfit_res = NULL;
527 struct nfit_test *t = instances[i];
528
529 if (!t)
530 continue;
531 spin_lock(&nfit_test_lock);
532 list_for_each_entry(n, &t->resources, list) {
533 if (addr >= n->res->start && (addr < n->res->start
534 + resource_size(n->res))) {
535 nfit_res = n;
536 break;
537 } else if (addr >= (unsigned long) n->buf
538 && (addr < (unsigned long) n->buf
539 + resource_size(n->res))) {
540 nfit_res = n;
541 break;
542 }
543 }
544 spin_unlock(&nfit_test_lock);
545 if (nfit_res)
546 return nfit_res;
547 }
548
549 return NULL;
550}
551
f471f1a7
DW		 552static int ars_state_init(struct device *dev, struct ars_state *ars_state)
553{
554 ars_state->ars_status = devm_kzalloc(dev,
555 sizeof(struct nd_cmd_ars_status)
556 + sizeof(struct nd_ars_record) * NFIT_TEST_ARS_RECORDS,
557 GFP_KERNEL);
558 if (!ars_state->ars_status)
559 return -ENOMEM;
560 spin_lock_init(&ars_state->lock);
561 return 0;
562}
563
6bc75619
DW		 564static int nfit_test0_alloc(struct nfit_test *t)
565{
6b577c9d 566 size_t nfit_size = sizeof(struct acpi_nfit_system_address) * NUM_SPA
6bc75619
DW		 567 + sizeof(struct acpi_nfit_memory_map) * NUM_MEM
568 + sizeof(struct acpi_nfit_control_region) * NUM_DCR
3b87356f
DW		 569 + offsetof(struct acpi_nfit_control_region,
570 window_size) * NUM_DCR
9d27a87e
DW		 571 + sizeof(struct acpi_nfit_data_region) * NUM_BDW
572 + sizeof(struct acpi_nfit_flush_address) * NUM_DCR;
6bc75619
DW		 573 int i;
574
575 t->nfit_buf = test_alloc(t, nfit_size, &t->nfit_dma);
576 if (!t->nfit_buf)
577 return -ENOMEM;
578 t->nfit_size = nfit_size;
579
ee8520fe 580 t->spa_set[0] = test_alloc(t, SPA0_SIZE, &t->spa_set_dma[0]);
6bc75619
DW		 581 if (!t->spa_set[0])
582 return -ENOMEM;
583
ee8520fe 584 t->spa_set[1] = test_alloc(t, SPA1_SIZE, &t->spa_set_dma[1]);
6bc75619
DW		 585 if (!t->spa_set[1])
586 return -ENOMEM;
587
ee8520fe 588 t->spa_set[2] = test_alloc(t, SPA0_SIZE, &t->spa_set_dma[2]);
20985164
VV		 589 if (!t->spa_set[2])
590 return -ENOMEM;
591
6bc75619
DW		 592 for (i = 0; i < NUM_DCR; i++) {
593 t->dimm[i] = test_alloc(t, DIMM_SIZE, &t->dimm_dma[i]);
594 if (!t->dimm[i])
595 return -ENOMEM;
596
597 t->label[i] = test_alloc(t, LABEL_SIZE, &t->label_dma[i]);
598 if (!t->label[i])
599 return -ENOMEM;
600 sprintf(t->label[i], "label%d", i);
9d27a87e
DW		 601
602 t->flush[i] = test_alloc(t, 8, &t->flush_dma[i]);
603 if (!t->flush[i])
604 return -ENOMEM;
6bc75619
DW		 605 }
606
607 for (i = 0; i < NUM_DCR; i++) {
608 t->dcr[i] = test_alloc(t, LABEL_SIZE, &t->dcr_dma[i]);
609 if (!t->dcr[i])
610 return -ENOMEM;
611 }
612
f471f1a7 613 return ars_state_init(&t->pdev.dev, &t->ars_state);
6bc75619
DW		 614}
615
616static int nfit_test1_alloc(struct nfit_test *t)
617{
6b577c9d 618 size_t nfit_size = sizeof(struct acpi_nfit_system_address)
6bc75619 619 + sizeof(struct acpi_nfit_memory_map)
3b87356f 620 + offsetof(struct acpi_nfit_control_region, window_size);
6bc75619
DW		 621
622 t->nfit_buf = test_alloc(t, nfit_size, &t->nfit_dma);
623 if (!t->nfit_buf)
624 return -ENOMEM;
625 t->nfit_size = nfit_size;
626
ee8520fe 627 t->spa_set[0] = test_alloc(t, SPA2_SIZE, &t->spa_set_dma[0]);
6bc75619
DW		 628 if (!t->spa_set[0])
629 return -ENOMEM;
630
f471f1a7 631 return ars_state_init(&t->pdev.dev, &t->ars_state);
6bc75619
DW		 632}
633
6bc75619
DW		 634static void nfit_test0_setup(struct nfit_test *t)
635{
6bc75619
DW		 636 struct acpi_nfit_desc *acpi_desc;
637 struct acpi_nfit_memory_map *memdev;
638 void *nfit_buf = t->nfit_buf;
6bc75619
DW		 639 struct acpi_nfit_system_address *spa;
640 struct acpi_nfit_control_region *dcr;
641 struct acpi_nfit_data_region *bdw;
9d27a87e 642 struct acpi_nfit_flush_address *flush;
6bc75619
DW		 643 unsigned int offset;
644
6bc75619
DW		 645 /*
646 * spa0 (interleave first half of dimm0 and dimm1, note storage
647 * does not actually alias the related block-data-window
648 * regions)
649 */
6b577c9d 650 spa = nfit_buf;
6bc75619
DW		 651 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
652 spa->header.length = sizeof(*spa);
653 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
654 spa->range_index = 0+1;
655 spa->address = t->spa_set_dma[0];
656 spa->length = SPA0_SIZE;
657
658 /*
659 * spa1 (interleave last half of the 4 DIMMS, note storage
660 * does not actually alias the related block-data-window
661 * regions)
662 */
6b577c9d 663 spa = nfit_buf + sizeof(*spa);
6bc75619
DW		 664 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
665 spa->header.length = sizeof(*spa);
666 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
667 spa->range_index = 1+1;
668 spa->address = t->spa_set_dma[1];
669 spa->length = SPA1_SIZE;
670
671 /* spa2 (dcr0) dimm0 */
6b577c9d 672 spa = nfit_buf + sizeof(*spa) * 2;
6bc75619
DW		 673 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
674 spa->header.length = sizeof(*spa);
675 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
676 spa->range_index = 2+1;
677 spa->address = t->dcr_dma[0];
678 spa->length = DCR_SIZE;
679
680 /* spa3 (dcr1) dimm1 */
6b577c9d 681 spa = nfit_buf + sizeof(*spa) * 3;
6bc75619
DW		 682 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
683 spa->header.length = sizeof(*spa);
684 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
685 spa->range_index = 3+1;
686 spa->address = t->dcr_dma[1];
687 spa->length = DCR_SIZE;
688
689 /* spa4 (dcr2) dimm2 */
6b577c9d 690 spa = nfit_buf + sizeof(*spa) * 4;
6bc75619
DW		 691 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
692 spa->header.length = sizeof(*spa);
693 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
694 spa->range_index = 4+1;
695 spa->address = t->dcr_dma[2];
696 spa->length = DCR_SIZE;
697
698 /* spa5 (dcr3) dimm3 */
6b577c9d 699 spa = nfit_buf + sizeof(*spa) * 5;
6bc75619
DW		 700 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
701 spa->header.length = sizeof(*spa);
702 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
703 spa->range_index = 5+1;
704 spa->address = t->dcr_dma[3];
705 spa->length = DCR_SIZE;
706
707 /* spa6 (bdw for dcr0) dimm0 */
6b577c9d 708 spa = nfit_buf + sizeof(*spa) * 6;
6bc75619
DW		 709 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
710 spa->header.length = sizeof(*spa);
711 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
712 spa->range_index = 6+1;
713 spa->address = t->dimm_dma[0];
714 spa->length = DIMM_SIZE;
715
716 /* spa7 (bdw for dcr1) dimm1 */
6b577c9d 717 spa = nfit_buf + sizeof(*spa) * 7;
6bc75619
DW		 718 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
719 spa->header.length = sizeof(*spa);
720 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
721 spa->range_index = 7+1;
722 spa->address = t->dimm_dma[1];
723 spa->length = DIMM_SIZE;
724
725 /* spa8 (bdw for dcr2) dimm2 */
6b577c9d 726 spa = nfit_buf + sizeof(*spa) * 8;
6bc75619
DW		 727 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
728 spa->header.length = sizeof(*spa);
729 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
730 spa->range_index = 8+1;
731 spa->address = t->dimm_dma[2];
732 spa->length = DIMM_SIZE;
733
734 /* spa9 (bdw for dcr3) dimm3 */
6b577c9d 735 spa = nfit_buf + sizeof(*spa) * 9;
6bc75619
DW		 736 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
737 spa->header.length = sizeof(*spa);
738 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
739 spa->range_index = 9+1;
740 spa->address = t->dimm_dma[3];
741 spa->length = DIMM_SIZE;
742
6b577c9d 743 offset = sizeof(*spa) * 10;
6bc75619
DW		 744 /* mem-region0 (spa0, dimm0) */
745 memdev = nfit_buf + offset;
746 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
747 memdev->header.length = sizeof(*memdev);
748 memdev->device_handle = handle[0];
749 memdev->physical_id = 0;
750 memdev->region_id = 0;
751 memdev->range_index = 0+1;
3b87356f 752 memdev->region_index = 4+1;
6bc75619
DW		 753 memdev->region_size = SPA0_SIZE/2;
754 memdev->region_offset = t->spa_set_dma[0];
755 memdev->address = 0;
756 memdev->interleave_index = 0;
757 memdev->interleave_ways = 2;
758
759 /* mem-region1 (spa0, dimm1) */
760 memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map);
761 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
762 memdev->header.length = sizeof(*memdev);
763 memdev->device_handle = handle[1];
764 memdev->physical_id = 1;
765 memdev->region_id = 0;
766 memdev->range_index = 0+1;
3b87356f 767 memdev->region_index = 5+1;
6bc75619
DW		 768 memdev->region_size = SPA0_SIZE/2;
769 memdev->region_offset = t->spa_set_dma[0] + SPA0_SIZE/2;
770 memdev->address = 0;
771 memdev->interleave_index = 0;
772 memdev->interleave_ways = 2;
773
774 /* mem-region2 (spa1, dimm0) */
775 memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 2;
776 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
777 memdev->header.length = sizeof(*memdev);
778 memdev->device_handle = handle[0];
779 memdev->physical_id = 0;
780 memdev->region_id = 1;
781 memdev->range_index = 1+1;
3b87356f 782 memdev->region_index = 4+1;
6bc75619
DW		 783 memdev->region_size = SPA1_SIZE/4;
784 memdev->region_offset = t->spa_set_dma[1];
785 memdev->address = SPA0_SIZE/2;
786 memdev->interleave_index = 0;
787 memdev->interleave_ways = 4;
788
789 /* mem-region3 (spa1, dimm1) */
790 memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 3;
791 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
792 memdev->header.length = sizeof(*memdev);
793 memdev->device_handle = handle[1];
794 memdev->physical_id = 1;
795 memdev->region_id = 1;
796 memdev->range_index = 1+1;
3b87356f 797 memdev->region_index = 5+1;
6bc75619
DW		 798 memdev->region_size = SPA1_SIZE/4;
799 memdev->region_offset = t->spa_set_dma[1] + SPA1_SIZE/4;
800 memdev->address = SPA0_SIZE/2;
801 memdev->interleave_index = 0;
802 memdev->interleave_ways = 4;
803
804 /* mem-region4 (spa1, dimm2) */
805 memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 4;
806 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
807 memdev->header.length = sizeof(*memdev);
808 memdev->device_handle = handle[2];
809 memdev->physical_id = 2;
810 memdev->region_id = 0;
811 memdev->range_index = 1+1;
3b87356f 812 memdev->region_index = 6+1;
6bc75619
DW		 813 memdev->region_size = SPA1_SIZE/4;
814 memdev->region_offset = t->spa_set_dma[1] + 2*SPA1_SIZE/4;
815 memdev->address = SPA0_SIZE/2;
816 memdev->interleave_index = 0;
817 memdev->interleave_ways = 4;
818
819 /* mem-region5 (spa1, dimm3) */
820 memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 5;
821 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
822 memdev->header.length = sizeof(*memdev);
823 memdev->device_handle = handle[3];
824 memdev->physical_id = 3;
825 memdev->region_id = 0;
826 memdev->range_index = 1+1;
3b87356f 827 memdev->region_index = 7+1;
6bc75619
DW		 828 memdev->region_size = SPA1_SIZE/4;
829 memdev->region_offset = t->spa_set_dma[1] + 3*SPA1_SIZE/4;
830 memdev->address = SPA0_SIZE/2;
831 memdev->interleave_index = 0;
832 memdev->interleave_ways = 4;
833
834 /* mem-region6 (spa/dcr0, dimm0) */
835 memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 6;
836 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
837 memdev->header.length = sizeof(*memdev);
838 memdev->device_handle = handle[0];
839 memdev->physical_id = 0;
840 memdev->region_id = 0;
841 memdev->range_index = 2+1;
842 memdev->region_index = 0+1;
843 memdev->region_size = 0;
844 memdev->region_offset = 0;
845 memdev->address = 0;
846 memdev->interleave_index = 0;
847 memdev->interleave_ways = 1;
848
849 /* mem-region7 (spa/dcr1, dimm1) */
850 memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 7;
851 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
852 memdev->header.length = sizeof(*memdev);
853 memdev->device_handle = handle[1];
854 memdev->physical_id = 1;
855 memdev->region_id = 0;
856 memdev->range_index = 3+1;
857 memdev->region_index = 1+1;
858 memdev->region_size = 0;
859 memdev->region_offset = 0;
860 memdev->address = 0;
861 memdev->interleave_index = 0;
862 memdev->interleave_ways = 1;
863
864 /* mem-region8 (spa/dcr2, dimm2) */
865 memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 8;
866 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
867 memdev->header.length = sizeof(*memdev);
868 memdev->device_handle = handle[2];
869 memdev->physical_id = 2;
870 memdev->region_id = 0;
871 memdev->range_index = 4+1;
872 memdev->region_index = 2+1;
873 memdev->region_size = 0;
874 memdev->region_offset = 0;
875 memdev->address = 0;
876 memdev->interleave_index = 0;
877 memdev->interleave_ways = 1;
878
879 /* mem-region9 (spa/dcr3, dimm3) */
880 memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 9;
881 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
882 memdev->header.length = sizeof(*memdev);
883 memdev->device_handle = handle[3];
884 memdev->physical_id = 3;
885 memdev->region_id = 0;
886 memdev->range_index = 5+1;
887 memdev->region_index = 3+1;
888 memdev->region_size = 0;
889 memdev->region_offset = 0;
890 memdev->address = 0;
891 memdev->interleave_index = 0;
892 memdev->interleave_ways = 1;
893
894 /* mem-region10 (spa/bdw0, dimm0) */
895 memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 10;
896 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
897 memdev->header.length = sizeof(*memdev);
898 memdev->device_handle = handle[0];
899 memdev->physical_id = 0;
900 memdev->region_id = 0;
901 memdev->range_index = 6+1;
902 memdev->region_index = 0+1;
903 memdev->region_size = 0;
904 memdev->region_offset = 0;
905 memdev->address = 0;
906 memdev->interleave_index = 0;
907 memdev->interleave_ways = 1;
908
909 /* mem-region11 (spa/bdw1, dimm1) */
910 memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 11;
911 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
912 memdev->header.length = sizeof(*memdev);
913 memdev->device_handle = handle[1];
914 memdev->physical_id = 1;
915 memdev->region_id = 0;
916 memdev->range_index = 7+1;
917 memdev->region_index = 1+1;
918 memdev->region_size = 0;
919 memdev->region_offset = 0;
920 memdev->address = 0;
921 memdev->interleave_index = 0;
922 memdev->interleave_ways = 1;
923
924 /* mem-region12 (spa/bdw2, dimm2) */
925 memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 12;
926 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
927 memdev->header.length = sizeof(*memdev);
928 memdev->device_handle = handle[2];
929 memdev->physical_id = 2;
930 memdev->region_id = 0;
931 memdev->range_index = 8+1;
932 memdev->region_index = 2+1;
933 memdev->region_size = 0;
934 memdev->region_offset = 0;
935 memdev->address = 0;
936 memdev->interleave_index = 0;
937 memdev->interleave_ways = 1;
938
939 /* mem-region13 (spa/dcr3, dimm3) */
940 memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 13;
941 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
942 memdev->header.length = sizeof(*memdev);
943 memdev->device_handle = handle[3];
944 memdev->physical_id = 3;
945 memdev->region_id = 0;
946 memdev->range_index = 9+1;
947 memdev->region_index = 3+1;
948 memdev->region_size = 0;
949 memdev->region_offset = 0;
950 memdev->address = 0;
951 memdev->interleave_index = 0;
952 memdev->interleave_ways = 1;
953
954 offset = offset + sizeof(struct acpi_nfit_memory_map) * 14;
3b87356f 955 /* dcr-descriptor0: blk */
6bc75619
DW		 956 dcr = nfit_buf + offset;
957 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
958 dcr->header.length = sizeof(struct acpi_nfit_control_region);
959 dcr->region_index = 0+1;
960 dcr->vendor_id = 0xabcd;
961 dcr->device_id = 0;
962 dcr->revision_id = 1;
963 dcr->serial_number = ~handle[0];
be26f9ae 964 dcr->code = NFIT_FIC_BLK;
6bc75619
DW		 965 dcr->windows = 1;
966 dcr->window_size = DCR_SIZE;
967 dcr->command_offset = 0;
968 dcr->command_size = 8;
969 dcr->status_offset = 8;
970 dcr->status_size = 4;
971
3b87356f 972 /* dcr-descriptor1: blk */
6bc75619
DW		 973 dcr = nfit_buf + offset + sizeof(struct acpi_nfit_control_region);
974 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
975 dcr->header.length = sizeof(struct acpi_nfit_control_region);
976 dcr->region_index = 1+1;
977 dcr->vendor_id = 0xabcd;
978 dcr->device_id = 0;
979 dcr->revision_id = 1;
980 dcr->serial_number = ~handle[1];
be26f9ae 981 dcr->code = NFIT_FIC_BLK;
6bc75619
DW		 982 dcr->windows = 1;
983 dcr->window_size = DCR_SIZE;
984 dcr->command_offset = 0;
985 dcr->command_size = 8;
986 dcr->status_offset = 8;
987 dcr->status_size = 4;
988
3b87356f 989 /* dcr-descriptor2: blk */
6bc75619
DW		 990 dcr = nfit_buf + offset + sizeof(struct acpi_nfit_control_region) * 2;
991 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
992 dcr->header.length = sizeof(struct acpi_nfit_control_region);
993 dcr->region_index = 2+1;
994 dcr->vendor_id = 0xabcd;
995 dcr->device_id = 0;
996 dcr->revision_id = 1;
997 dcr->serial_number = ~handle[2];
be26f9ae 998 dcr->code = NFIT_FIC_BLK;
6bc75619
DW		 999 dcr->windows = 1;
1000 dcr->window_size = DCR_SIZE;
1001 dcr->command_offset = 0;
1002 dcr->command_size = 8;
1003 dcr->status_offset = 8;
1004 dcr->status_size = 4;
1005
3b87356f 1006 /* dcr-descriptor3: blk */
6bc75619
DW		 1007 dcr = nfit_buf + offset + sizeof(struct acpi_nfit_control_region) * 3;
1008 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1009 dcr->header.length = sizeof(struct acpi_nfit_control_region);
1010 dcr->region_index = 3+1;
1011 dcr->vendor_id = 0xabcd;
1012 dcr->device_id = 0;
1013 dcr->revision_id = 1;
1014 dcr->serial_number = ~handle[3];
be26f9ae 1015 dcr->code = NFIT_FIC_BLK;
6bc75619
DW		 1016 dcr->windows = 1;
1017 dcr->window_size = DCR_SIZE;
1018 dcr->command_offset = 0;
1019 dcr->command_size = 8;
1020 dcr->status_offset = 8;
1021 dcr->status_size = 4;
1022
1023 offset = offset + sizeof(struct acpi_nfit_control_region) * 4;
3b87356f
DW		 1024 /* dcr-descriptor0: pmem */
1025 dcr = nfit_buf + offset;
1026 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1027 dcr->header.length = offsetof(struct acpi_nfit_control_region,
1028 window_size);
1029 dcr->region_index = 4+1;
1030 dcr->vendor_id = 0xabcd;
1031 dcr->device_id = 0;
1032 dcr->revision_id = 1;
1033 dcr->serial_number = ~handle[0];
1034 dcr->code = NFIT_FIC_BYTEN;
1035 dcr->windows = 0;
1036
1037 /* dcr-descriptor1: pmem */
1038 dcr = nfit_buf + offset + offsetof(struct acpi_nfit_control_region,
1039 window_size);
1040 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1041 dcr->header.length = offsetof(struct acpi_nfit_control_region,
1042 window_size);
1043 dcr->region_index = 5+1;
1044 dcr->vendor_id = 0xabcd;
1045 dcr->device_id = 0;
1046 dcr->revision_id = 1;
1047 dcr->serial_number = ~handle[1];
1048 dcr->code = NFIT_FIC_BYTEN;
1049 dcr->windows = 0;
1050
1051 /* dcr-descriptor2: pmem */
1052 dcr = nfit_buf + offset + offsetof(struct acpi_nfit_control_region,
1053 window_size) * 2;
1054 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1055 dcr->header.length = offsetof(struct acpi_nfit_control_region,
1056 window_size);
1057 dcr->region_index = 6+1;
1058 dcr->vendor_id = 0xabcd;
1059 dcr->device_id = 0;
1060 dcr->revision_id = 1;
1061 dcr->serial_number = ~handle[2];
1062 dcr->code = NFIT_FIC_BYTEN;
1063 dcr->windows = 0;
1064
1065 /* dcr-descriptor3: pmem */
1066 dcr = nfit_buf + offset + offsetof(struct acpi_nfit_control_region,
1067 window_size) * 3;
1068 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1069 dcr->header.length = offsetof(struct acpi_nfit_control_region,
1070 window_size);
1071 dcr->region_index = 7+1;
1072 dcr->vendor_id = 0xabcd;
1073 dcr->device_id = 0;
1074 dcr->revision_id = 1;
1075 dcr->serial_number = ~handle[3];
1076 dcr->code = NFIT_FIC_BYTEN;
1077 dcr->windows = 0;
1078
1079 offset = offset + offsetof(struct acpi_nfit_control_region,
1080 window_size) * 4;
6bc75619
DW		 1081 /* bdw0 (spa/dcr0, dimm0) */
1082 bdw = nfit_buf + offset;
1083 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
1084 bdw->header.length = sizeof(struct acpi_nfit_data_region);
1085 bdw->region_index = 0+1;
1086 bdw->windows = 1;
1087 bdw->offset = 0;
1088 bdw->size = BDW_SIZE;
1089 bdw->capacity = DIMM_SIZE;
1090 bdw->start_address = 0;
1091
1092 /* bdw1 (spa/dcr1, dimm1) */
1093 bdw = nfit_buf + offset + sizeof(struct acpi_nfit_data_region);
1094 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
1095 bdw->header.length = sizeof(struct acpi_nfit_data_region);
1096 bdw->region_index = 1+1;
1097 bdw->windows = 1;
1098 bdw->offset = 0;
1099 bdw->size = BDW_SIZE;
1100 bdw->capacity = DIMM_SIZE;
1101 bdw->start_address = 0;
1102
1103 /* bdw2 (spa/dcr2, dimm2) */
1104 bdw = nfit_buf + offset + sizeof(struct acpi_nfit_data_region) * 2;
1105 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
1106 bdw->header.length = sizeof(struct acpi_nfit_data_region);
1107 bdw->region_index = 2+1;
1108 bdw->windows = 1;
1109 bdw->offset = 0;
1110 bdw->size = BDW_SIZE;
1111 bdw->capacity = DIMM_SIZE;
1112 bdw->start_address = 0;
1113
1114 /* bdw3 (spa/dcr3, dimm3) */
1115 bdw = nfit_buf + offset + sizeof(struct acpi_nfit_data_region) * 3;
1116 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
1117 bdw->header.length = sizeof(struct acpi_nfit_data_region);
1118 bdw->region_index = 3+1;
1119 bdw->windows = 1;
1120 bdw->offset = 0;
1121 bdw->size = BDW_SIZE;
1122 bdw->capacity = DIMM_SIZE;
1123 bdw->start_address = 0;
1124
9d27a87e
DW		 1125 offset = offset + sizeof(struct acpi_nfit_data_region) * 4;
1126 /* flush0 (dimm0) */
1127 flush = nfit_buf + offset;
1128 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
1129 flush->header.length = sizeof(struct acpi_nfit_flush_address);
1130 flush->device_handle = handle[0];
1131 flush->hint_count = 1;
1132 flush->hint_address[0] = t->flush_dma[0];
1133
1134 /* flush1 (dimm1) */
1135 flush = nfit_buf + offset + sizeof(struct acpi_nfit_flush_address) * 1;
1136 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
1137 flush->header.length = sizeof(struct acpi_nfit_flush_address);
1138 flush->device_handle = handle[1];
1139 flush->hint_count = 1;
1140 flush->hint_address[0] = t->flush_dma[1];
1141
1142 /* flush2 (dimm2) */
1143 flush = nfit_buf + offset + sizeof(struct acpi_nfit_flush_address) * 2;
1144 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
1145 flush->header.length = sizeof(struct acpi_nfit_flush_address);
1146 flush->device_handle = handle[2];
1147 flush->hint_count = 1;
1148 flush->hint_address[0] = t->flush_dma[2];
1149
1150 /* flush3 (dimm3) */
1151 flush = nfit_buf + offset + sizeof(struct acpi_nfit_flush_address) * 3;
1152 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
1153 flush->header.length = sizeof(struct acpi_nfit_flush_address);
1154 flush->device_handle = handle[3];
1155 flush->hint_count = 1;
1156 flush->hint_address[0] = t->flush_dma[3];
1157
20985164
VV		 1158 if (t->setup_hotplug) {
1159 offset = offset + sizeof(struct acpi_nfit_flush_address) * 4;
3b87356f 1160 /* dcr-descriptor4: blk */
20985164
VV		 1161 dcr = nfit_buf + offset;
1162 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1163 dcr->header.length = sizeof(struct acpi_nfit_control_region);
3b87356f 1164 dcr->region_index = 8+1;
20985164
VV		 1165 dcr->vendor_id = 0xabcd;
1166 dcr->device_id = 0;
1167 dcr->revision_id = 1;
1168 dcr->serial_number = ~handle[4];
be26f9ae 1169 dcr->code = NFIT_FIC_BLK;
20985164
VV		 1170 dcr->windows = 1;
1171 dcr->window_size = DCR_SIZE;
1172 dcr->command_offset = 0;
1173 dcr->command_size = 8;
1174 dcr->status_offset = 8;
1175 dcr->status_size = 4;
1176
1177 offset = offset + sizeof(struct acpi_nfit_control_region);
3b87356f
DW		 1178 /* dcr-descriptor4: pmem */
1179 dcr = nfit_buf + offset;
1180 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1181 dcr->header.length = offsetof(struct acpi_nfit_control_region,
1182 window_size);
1183 dcr->region_index = 9+1;
1184 dcr->vendor_id = 0xabcd;
1185 dcr->device_id = 0;
1186 dcr->revision_id = 1;
1187 dcr->serial_number = ~handle[4];
1188 dcr->code = NFIT_FIC_BYTEN;
1189 dcr->windows = 0;
1190
1191 offset = offset + offsetof(struct acpi_nfit_control_region,
1192 window_size);
20985164
VV		 1193 /* bdw4 (spa/dcr4, dimm4) */
1194 bdw = nfit_buf + offset;
1195 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
1196 bdw->header.length = sizeof(struct acpi_nfit_data_region);
3b87356f 1197 bdw->region_index = 8+1;
20985164
VV		 1198 bdw->windows = 1;
1199 bdw->offset = 0;
1200 bdw->size = BDW_SIZE;
1201 bdw->capacity = DIMM_SIZE;
1202 bdw->start_address = 0;
1203
1204 offset = offset + sizeof(struct acpi_nfit_data_region);
1205 /* spa10 (dcr4) dimm4 */
1206 spa = nfit_buf + offset;
1207 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1208 spa->header.length = sizeof(*spa);
1209 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
1210 spa->range_index = 10+1;
1211 spa->address = t->dcr_dma[4];
1212 spa->length = DCR_SIZE;
1213
1214 /*
1215 * spa11 (single-dimm interleave for hotplug, note storage
1216 * does not actually alias the related block-data-window
1217 * regions)
1218 */
1219 spa = nfit_buf + offset + sizeof(*spa);
1220 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1221 spa->header.length = sizeof(*spa);
1222 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
1223 spa->range_index = 11+1;
1224 spa->address = t->spa_set_dma[2];
1225 spa->length = SPA0_SIZE;
1226
1227 /* spa12 (bdw for dcr4) dimm4 */
1228 spa = nfit_buf + offset + sizeof(*spa) * 2;
1229 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1230 spa->header.length = sizeof(*spa);
1231 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
1232 spa->range_index = 12+1;
1233 spa->address = t->dimm_dma[4];
1234 spa->length = DIMM_SIZE;
1235
1236 offset = offset + sizeof(*spa) * 3;
1237 /* mem-region14 (spa/dcr4, dimm4) */
1238 memdev = nfit_buf + offset;
1239 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1240 memdev->header.length = sizeof(*memdev);
1241 memdev->device_handle = handle[4];
1242 memdev->physical_id = 4;
1243 memdev->region_id = 0;
1244 memdev->range_index = 10+1;
3b87356f 1245 memdev->region_index = 8+1;
20985164
VV		 1246 memdev->region_size = 0;
1247 memdev->region_offset = 0;
1248 memdev->address = 0;
1249 memdev->interleave_index = 0;
1250 memdev->interleave_ways = 1;
1251
1252 /* mem-region15 (spa0, dimm4) */
1253 memdev = nfit_buf + offset +
1254 sizeof(struct acpi_nfit_memory_map);
1255 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1256 memdev->header.length = sizeof(*memdev);
1257 memdev->device_handle = handle[4];
1258 memdev->physical_id = 4;
1259 memdev->region_id = 0;
1260 memdev->range_index = 11+1;
3b87356f 1261 memdev->region_index = 9+1;
20985164
VV		 1262 memdev->region_size = SPA0_SIZE;
1263 memdev->region_offset = t->spa_set_dma[2];
1264 memdev->address = 0;
1265 memdev->interleave_index = 0;
1266 memdev->interleave_ways = 1;
1267
3b87356f 1268 /* mem-region16 (spa/bdw4, dimm4) */
20985164
VV		 1269 memdev = nfit_buf + offset +
1270 sizeof(struct acpi_nfit_memory_map) * 2;
1271 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1272 memdev->header.length = sizeof(*memdev);
1273 memdev->device_handle = handle[4];
1274 memdev->physical_id = 4;
1275 memdev->region_id = 0;
1276 memdev->range_index = 12+1;
3b87356f 1277 memdev->region_index = 8+1;
20985164
VV		 1278 memdev->region_size = 0;
1279 memdev->region_offset = 0;
1280 memdev->address = 0;
1281 memdev->interleave_index = 0;
1282 memdev->interleave_ways = 1;
1283
1284 offset = offset + sizeof(struct acpi_nfit_memory_map) * 3;
1285 /* flush3 (dimm4) */
1286 flush = nfit_buf + offset;
1287 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
1288 flush->header.length = sizeof(struct acpi_nfit_flush_address);
1289 flush->device_handle = handle[4];
1290 flush->hint_count = 1;
1291 flush->hint_address[0] = t->flush_dma[4];
1292 }
1293
f471f1a7
DW		 1294 post_ars_status(&t->ars_state, t->spa_set_dma[0], SPA0_SIZE);
1295
6bc75619 1296 acpi_desc = &t->acpi_desc;
e3654eca
DW		 1297 set_bit(ND_CMD_GET_CONFIG_SIZE, &acpi_desc->dimm_cmd_force_en);
1298 set_bit(ND_CMD_GET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en);
1299 set_bit(ND_CMD_SET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en);
1f716d05 1300 set_bit(ND_CMD_SMART, &acpi_desc->dimm_cmd_force_en);
e3654eca
DW		 1301 set_bit(ND_CMD_ARS_CAP, &acpi_desc->bus_cmd_force_en);
1302 set_bit(ND_CMD_ARS_START, &acpi_desc->bus_cmd_force_en);
1303 set_bit(ND_CMD_ARS_STATUS, &acpi_desc->bus_cmd_force_en);
1304 set_bit(ND_CMD_CLEAR_ERROR, &acpi_desc->bus_cmd_force_en);
1f716d05 1305 set_bit(ND_CMD_SMART_THRESHOLD, &acpi_desc->dimm_cmd_force_en);
6bc75619
DW		 1306}
1307
1308static void nfit_test1_setup(struct nfit_test *t)
1309{
6b577c9d 1310 size_t offset;
6bc75619
DW		 1311 void *nfit_buf = t->nfit_buf;
1312 struct acpi_nfit_memory_map *memdev;
1313 struct acpi_nfit_control_region *dcr;
1314 struct acpi_nfit_system_address *spa;
d26f73f0 1315 struct acpi_nfit_desc *acpi_desc;
6bc75619 1316
6b577c9d 1317 offset = 0;
6bc75619
DW		 1318 /* spa0 (flat range with no bdw aliasing) */
1319 spa = nfit_buf + offset;
1320 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1321 spa->header.length = sizeof(*spa);
1322 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
1323 spa->range_index = 0+1;
1324 spa->address = t->spa_set_dma[0];
1325 spa->length = SPA2_SIZE;
1326
1327 offset += sizeof(*spa);
1328 /* mem-region0 (spa0, dimm0) */
1329 memdev = nfit_buf + offset;
1330 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1331 memdev->header.length = sizeof(*memdev);
1332 memdev->device_handle = 0;
1333 memdev->physical_id = 0;
1334 memdev->region_id = 0;
1335 memdev->range_index = 0+1;
1336 memdev->region_index = 0+1;
1337 memdev->region_size = SPA2_SIZE;
1338 memdev->region_offset = 0;
1339 memdev->address = 0;
1340 memdev->interleave_index = 0;
1341 memdev->interleave_ways = 1;
58138820
DW		 1342 memdev->flags = ACPI_NFIT_MEM_SAVE_FAILED | ACPI_NFIT_MEM_RESTORE_FAILED
1343 | ACPI_NFIT_MEM_FLUSH_FAILED | ACPI_NFIT_MEM_HEALTH_OBSERVED
f4295796 1344 | ACPI_NFIT_MEM_NOT_ARMED;
6bc75619
DW		 1345
1346 offset += sizeof(*memdev);
1347 /* dcr-descriptor0 */
1348 dcr = nfit_buf + offset;
1349 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
3b87356f
DW		 1350 dcr->header.length = offsetof(struct acpi_nfit_control_region,
1351 window_size);
6bc75619
DW		 1352 dcr->region_index = 0+1;
1353 dcr->vendor_id = 0xabcd;
1354 dcr->device_id = 0;
1355 dcr->revision_id = 1;
1356 dcr->serial_number = ~0;
be26f9ae 1357 dcr->code = NFIT_FIC_BYTE;
6bc75619 1358 dcr->windows = 0;
d26f73f0 1359
f471f1a7
DW		 1360 post_ars_status(&t->ars_state, t->spa_set_dma[0], SPA2_SIZE);
1361
d26f73f0 1362 acpi_desc = &t->acpi_desc;
e3654eca
DW		 1363 set_bit(ND_CMD_ARS_CAP, &acpi_desc->bus_cmd_force_en);
1364 set_bit(ND_CMD_ARS_START, &acpi_desc->bus_cmd_force_en);
1365 set_bit(ND_CMD_ARS_STATUS, &acpi_desc->bus_cmd_force_en);
1366 set_bit(ND_CMD_CLEAR_ERROR, &acpi_desc->bus_cmd_force_en);
6bc75619
DW		 1367}
1368
1369static int nfit_test_blk_do_io(struct nd_blk_region *ndbr, resource_size_t dpa,
1370 void *iobuf, u64 len, int rw)
1371{
1372 struct nfit_blk *nfit_blk = ndbr->blk_provider_data;
1373 struct nfit_blk_mmio *mmio = &nfit_blk->mmio[BDW];
1374 struct nd_region *nd_region = &ndbr->nd_region;
1375 unsigned int lane;
1376
1377 lane = nd_region_acquire_lane(nd_region);
1378 if (rw)
67a3e8fe
RZ		 1379 memcpy(mmio->addr.base + dpa, iobuf, len);
1380 else {
1381 memcpy(iobuf, mmio->addr.base + dpa, len);
1382
1383 /* give us some some coverage of the mmio_flush_range() API */
1384 mmio_flush_range(mmio->addr.base + dpa, len);
1385 }
6bc75619
DW		 1386 nd_region_release_lane(nd_region, lane);
1387
1388 return 0;
1389}
1390
1391static int nfit_test_probe(struct platform_device *pdev)
1392{
1393 struct nvdimm_bus_descriptor *nd_desc;
1394 struct acpi_nfit_desc *acpi_desc;
1395 struct device *dev = &pdev->dev;
1396 struct nfit_test *nfit_test;
1397 int rc;
1398
1399 nfit_test = to_nfit_test(&pdev->dev);
1400
1401 /* common alloc */
1402 if (nfit_test->num_dcr) {
1403 int num = nfit_test->num_dcr;
1404
1405 nfit_test->dimm = devm_kcalloc(dev, num, sizeof(void *),
1406 GFP_KERNEL);
1407 nfit_test->dimm_dma = devm_kcalloc(dev, num, sizeof(dma_addr_t),
1408 GFP_KERNEL);
9d27a87e
DW		 1409 nfit_test->flush = devm_kcalloc(dev, num, sizeof(void *),
1410 GFP_KERNEL);
1411 nfit_test->flush_dma = devm_kcalloc(dev, num, sizeof(dma_addr_t),
1412 GFP_KERNEL);
6bc75619
DW		 1413 nfit_test->label = devm_kcalloc(dev, num, sizeof(void *),
1414 GFP_KERNEL);
1415 nfit_test->label_dma = devm_kcalloc(dev, num,
1416 sizeof(dma_addr_t), GFP_KERNEL);
1417 nfit_test->dcr = devm_kcalloc(dev, num,
1418 sizeof(struct nfit_test_dcr *), GFP_KERNEL);
1419 nfit_test->dcr_dma = devm_kcalloc(dev, num,
1420 sizeof(dma_addr_t), GFP_KERNEL);
1421 if (nfit_test->dimm && nfit_test->dimm_dma && nfit_test->label
1422 && nfit_test->label_dma && nfit_test->dcr
9d27a87e
DW		 1423 && nfit_test->dcr_dma && nfit_test->flush
1424 && nfit_test->flush_dma)
6bc75619
DW		 1425 /* pass */;
1426 else
1427 return -ENOMEM;
1428 }
1429
1430 if (nfit_test->num_pm) {
1431 int num = nfit_test->num_pm;
1432
1433 nfit_test->spa_set = devm_kcalloc(dev, num, sizeof(void *),
1434 GFP_KERNEL);
1435 nfit_test->spa_set_dma = devm_kcalloc(dev, num,
1436 sizeof(dma_addr_t), GFP_KERNEL);
1437 if (nfit_test->spa_set && nfit_test->spa_set_dma)
1438 /* pass */;
1439 else
1440 return -ENOMEM;
1441 }
1442
1443 /* per-nfit specific alloc */
1444 if (nfit_test->alloc(nfit_test))
1445 return -ENOMEM;
1446
1447 nfit_test->setup(nfit_test);
1448 acpi_desc = &nfit_test->acpi_desc;
a61fe6f7 1449 acpi_nfit_desc_init(acpi_desc, &pdev->dev);
6bc75619
DW		 1450 acpi_desc->nfit = nfit_test->nfit_buf;
1451 acpi_desc->blk_do_io = nfit_test_blk_do_io;
1452 nd_desc = &acpi_desc->nd_desc;
a61fe6f7
DW		 1453 nd_desc->provider_name = NULL;
1454 nd_desc->ndctl = nfit_test_ctl;
6bc75619
DW		 1455 acpi_desc->nvdimm_bus = nvdimm_bus_register(&pdev->dev, nd_desc);
1456 if (!acpi_desc->nvdimm_bus)
1457 return -ENXIO;
1458
20985164
VV		 1459 rc = acpi_nfit_init(acpi_desc, nfit_test->nfit_size);
1460 if (rc) {
1461 nvdimm_bus_unregister(acpi_desc->nvdimm_bus);
1462 return rc;
1463 }
1464
1465 if (nfit_test->setup != nfit_test0_setup)
1466 return 0;
1467
1468 nfit_test->setup_hotplug = 1;
1469 nfit_test->setup(nfit_test);
1470
6bc75619
DW		 1471 rc = acpi_nfit_init(acpi_desc, nfit_test->nfit_size);
1472 if (rc) {
1473 nvdimm_bus_unregister(acpi_desc->nvdimm_bus);
1474 return rc;
1475 }
1476
1477 return 0;
1478}
1479
1480static int nfit_test_remove(struct platform_device *pdev)
1481{
1482 struct nfit_test *nfit_test = to_nfit_test(&pdev->dev);
1483 struct acpi_nfit_desc *acpi_desc = &nfit_test->acpi_desc;
1484
1485 nvdimm_bus_unregister(acpi_desc->nvdimm_bus);
1486
1487 return 0;
1488}
1489
1490static void nfit_test_release(struct device *dev)
1491{
1492 struct nfit_test *nfit_test = to_nfit_test(dev);
1493
1494 kfree(nfit_test);
1495}
1496
1497static const struct platform_device_id nfit_test_id[] = {
1498 { KBUILD_MODNAME },
1499 { },
1500};
1501
1502static struct platform_driver nfit_test_driver = {
1503 .probe = nfit_test_probe,
1504 .remove = nfit_test_remove,
1505 .driver = {
1506 .name = KBUILD_MODNAME,
1507 },
1508 .id_table = nfit_test_id,
1509};
1510
6bc75619
DW		 1511static __init int nfit_test_init(void)
1512{
1513 int rc, i;
1514
1515 nfit_test_setup(nfit_test_lookup);
1516
1517 for (i = 0; i < NUM_NFITS; i++) {
1518 struct nfit_test *nfit_test;
1519 struct platform_device *pdev;
6bc75619
DW		 1520
1521 nfit_test = kzalloc(sizeof(*nfit_test), GFP_KERNEL);
1522 if (!nfit_test) {
1523 rc = -ENOMEM;
1524 goto err_register;
1525 }
1526 INIT_LIST_HEAD(&nfit_test->resources);
1527 switch (i) {
1528 case 0:
1529 nfit_test->num_pm = NUM_PM;
1530 nfit_test->num_dcr = NUM_DCR;
1531 nfit_test->alloc = nfit_test0_alloc;
1532 nfit_test->setup = nfit_test0_setup;
1533 break;
1534 case 1:
1535 nfit_test->num_pm = 1;
1536 nfit_test->alloc = nfit_test1_alloc;
1537 nfit_test->setup = nfit_test1_setup;
1538 break;
1539 default:
1540 rc = -EINVAL;
1541 goto err_register;
1542 }
1543 pdev = &nfit_test->pdev;
1544 pdev->name = KBUILD_MODNAME;
1545 pdev->id = i;
1546 pdev->dev.release = nfit_test_release;
1547 rc = platform_device_register(pdev);
1548 if (rc) {
1549 put_device(&pdev->dev);
1550 goto err_register;
1551 }
1552
1553 rc = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1554 if (rc)
1555 goto err_register;
1556
1557 instances[i] = nfit_test;
6bc75619
DW		 1558 }
1559
1560 rc = platform_driver_register(&nfit_test_driver);
1561 if (rc)
1562 goto err_register;
1563 return 0;
1564
1565 err_register:
1566 for (i = 0; i < NUM_NFITS; i++)
1567 if (instances[i])
1568 platform_device_unregister(&instances[i]->pdev);
1569 nfit_test_teardown();
1570 return rc;
1571}
1572
1573static __exit void nfit_test_exit(void)
1574{
1575 int i;
1576
1577 platform_driver_unregister(&nfit_test_driver);
1578 for (i = 0; i < NUM_NFITS; i++)
1579 platform_device_unregister(&instances[i]->pdev);
1580 nfit_test_teardown();
1581}
1582
1583module_init(nfit_test_init);
1584module_exit(nfit_test_exit);
1585MODULE_LICENSE("GPL v2");
1586MODULE_AUTHOR("Intel Corporation");
Linux kernel - Deliverables
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