x86/topology: Fix logical package mapping
[deliverable/linux.git] / arch / x86 / kernel / smpboot.c
... / ...
CommitLineData
1 /*
2 * x86 SMP booting functions
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
7 *
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
10 *
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
14 *
15 * This code is released under the GNU General Public License version 2 or
16 * later.
17 *
18 * Fixes
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
29 * from Jose Renau
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
40 */
41
42#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
43
44#include <linux/init.h>
45#include <linux/smp.h>
46#include <linux/module.h>
47#include <linux/sched.h>
48#include <linux/percpu.h>
49#include <linux/bootmem.h>
50#include <linux/err.h>
51#include <linux/nmi.h>
52#include <linux/tboot.h>
53#include <linux/stackprotector.h>
54#include <linux/gfp.h>
55#include <linux/cpuidle.h>
56
57#include <asm/acpi.h>
58#include <asm/desc.h>
59#include <asm/nmi.h>
60#include <asm/irq.h>
61#include <asm/idle.h>
62#include <asm/realmode.h>
63#include <asm/cpu.h>
64#include <asm/numa.h>
65#include <asm/pgtable.h>
66#include <asm/tlbflush.h>
67#include <asm/mtrr.h>
68#include <asm/mwait.h>
69#include <asm/apic.h>
70#include <asm/io_apic.h>
71#include <asm/fpu/internal.h>
72#include <asm/setup.h>
73#include <asm/uv/uv.h>
74#include <linux/mc146818rtc.h>
75#include <asm/i8259.h>
76#include <asm/realmode.h>
77#include <asm/misc.h>
78
79/* Number of siblings per CPU package */
80int smp_num_siblings = 1;
81EXPORT_SYMBOL(smp_num_siblings);
82
83/* Last level cache ID of each logical CPU */
84DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
85
86/* representing HT siblings of each logical CPU */
87DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
88EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
89
90/* representing HT and core siblings of each logical CPU */
91DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
92EXPORT_PER_CPU_SYMBOL(cpu_core_map);
93
94DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
95
96/* Per CPU bogomips and other parameters */
97DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
98EXPORT_PER_CPU_SYMBOL(cpu_info);
99
100/* Logical package management. We might want to allocate that dynamically */
101static int *physical_to_logical_pkg __read_mostly;
102static unsigned long *physical_package_map __read_mostly;;
103static unsigned long *logical_package_map __read_mostly;
104static unsigned int max_physical_pkg_id __read_mostly;
105unsigned int __max_logical_packages __read_mostly;
106EXPORT_SYMBOL(__max_logical_packages);
107
108static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
109{
110 unsigned long flags;
111
112 spin_lock_irqsave(&rtc_lock, flags);
113 CMOS_WRITE(0xa, 0xf);
114 spin_unlock_irqrestore(&rtc_lock, flags);
115 local_flush_tlb();
116 pr_debug("1.\n");
117 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
118 start_eip >> 4;
119 pr_debug("2.\n");
120 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
121 start_eip & 0xf;
122 pr_debug("3.\n");
123}
124
125static inline void smpboot_restore_warm_reset_vector(void)
126{
127 unsigned long flags;
128
129 /*
130 * Install writable page 0 entry to set BIOS data area.
131 */
132 local_flush_tlb();
133
134 /*
135 * Paranoid: Set warm reset code and vector here back
136 * to default values.
137 */
138 spin_lock_irqsave(&rtc_lock, flags);
139 CMOS_WRITE(0, 0xf);
140 spin_unlock_irqrestore(&rtc_lock, flags);
141
142 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
143}
144
145/*
146 * Report back to the Boot Processor during boot time or to the caller processor
147 * during CPU online.
148 */
149static void smp_callin(void)
150{
151 int cpuid, phys_id;
152
153 /*
154 * If waken up by an INIT in an 82489DX configuration
155 * cpu_callout_mask guarantees we don't get here before
156 * an INIT_deassert IPI reaches our local APIC, so it is
157 * now safe to touch our local APIC.
158 */
159 cpuid = smp_processor_id();
160
161 /*
162 * (This works even if the APIC is not enabled.)
163 */
164 phys_id = read_apic_id();
165
166 /*
167 * the boot CPU has finished the init stage and is spinning
168 * on callin_map until we finish. We are free to set up this
169 * CPU, first the APIC. (this is probably redundant on most
170 * boards)
171 */
172 apic_ap_setup();
173
174 /*
175 * Save our processor parameters. Note: this information
176 * is needed for clock calibration.
177 */
178 smp_store_cpu_info(cpuid);
179
180 /*
181 * Get our bogomips.
182 * Update loops_per_jiffy in cpu_data. Previous call to
183 * smp_store_cpu_info() stored a value that is close but not as
184 * accurate as the value just calculated.
185 */
186 calibrate_delay();
187 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
188 pr_debug("Stack at about %p\n", &cpuid);
189
190 /*
191 * This must be done before setting cpu_online_mask
192 * or calling notify_cpu_starting.
193 */
194 set_cpu_sibling_map(raw_smp_processor_id());
195 wmb();
196
197 notify_cpu_starting(cpuid);
198
199 /*
200 * Allow the master to continue.
201 */
202 cpumask_set_cpu(cpuid, cpu_callin_mask);
203}
204
205static int cpu0_logical_apicid;
206static int enable_start_cpu0;
207/*
208 * Activate a secondary processor.
209 */
210static void notrace start_secondary(void *unused)
211{
212 /*
213 * Don't put *anything* before cpu_init(), SMP booting is too
214 * fragile that we want to limit the things done here to the
215 * most necessary things.
216 */
217 cpu_init();
218 x86_cpuinit.early_percpu_clock_init();
219 preempt_disable();
220 smp_callin();
221
222 enable_start_cpu0 = 0;
223
224#ifdef CONFIG_X86_32
225 /* switch away from the initial page table */
226 load_cr3(swapper_pg_dir);
227 __flush_tlb_all();
228#endif
229
230 /* otherwise gcc will move up smp_processor_id before the cpu_init */
231 barrier();
232 /*
233 * Check TSC synchronization with the BP:
234 */
235 check_tsc_sync_target();
236
237 /*
238 * Lock vector_lock and initialize the vectors on this cpu
239 * before setting the cpu online. We must set it online with
240 * vector_lock held to prevent a concurrent setup/teardown
241 * from seeing a half valid vector space.
242 */
243 lock_vector_lock();
244 setup_vector_irq(smp_processor_id());
245 set_cpu_online(smp_processor_id(), true);
246 unlock_vector_lock();
247 cpu_set_state_online(smp_processor_id());
248 x86_platform.nmi_init();
249
250 /* enable local interrupts */
251 local_irq_enable();
252
253 /* to prevent fake stack check failure in clock setup */
254 boot_init_stack_canary();
255
256 x86_cpuinit.setup_percpu_clockev();
257
258 wmb();
259 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
260}
261
262int topology_update_package_map(unsigned int apicid, unsigned int cpu)
263{
264 unsigned int new, pkg = apicid >> boot_cpu_data.x86_coreid_bits;
265
266 /* Called from early boot ? */
267 if (!physical_package_map)
268 return 0;
269
270 if (pkg >= max_physical_pkg_id)
271 return -EINVAL;
272
273 /* Set the logical package id */
274 if (test_and_set_bit(pkg, physical_package_map))
275 goto found;
276
277 new = find_first_zero_bit(logical_package_map, __max_logical_packages);
278 if (new >= __max_logical_packages) {
279 physical_to_logical_pkg[pkg] = -1;
280 pr_warn("APIC(%x) Package %u exceeds logical package map\n",
281 apicid, pkg);
282 return -ENOSPC;
283 }
284 set_bit(new, logical_package_map);
285 pr_info("APIC(%x) Converting physical %u to logical package %u\n",
286 apicid, pkg, new);
287 physical_to_logical_pkg[pkg] = new;
288
289found:
290 cpu_data(cpu).logical_proc_id = physical_to_logical_pkg[pkg];
291 return 0;
292}
293
294/**
295 * topology_phys_to_logical_pkg - Map a physical package id to a logical
296 *
297 * Returns logical package id or -1 if not found
298 */
299int topology_phys_to_logical_pkg(unsigned int phys_pkg)
300{
301 if (phys_pkg >= max_physical_pkg_id)
302 return -1;
303 return physical_to_logical_pkg[phys_pkg];
304}
305EXPORT_SYMBOL(topology_phys_to_logical_pkg);
306
307static void __init smp_init_package_map(void)
308{
309 unsigned int ncpus, cpu;
310 size_t size;
311
312 /*
313 * Today neither Intel nor AMD support heterogenous systems. That
314 * might change in the future....
315 */
316 ncpus = boot_cpu_data.x86_max_cores * smp_num_siblings;
317 __max_logical_packages = DIV_ROUND_UP(nr_cpu_ids, ncpus);
318
319 /*
320 * Possibly larger than what we need as the number of apic ids per
321 * package can be smaller than the actual used apic ids.
322 */
323 max_physical_pkg_id = DIV_ROUND_UP(MAX_LOCAL_APIC, ncpus);
324 size = max_physical_pkg_id * sizeof(unsigned int);
325 physical_to_logical_pkg = kmalloc(size, GFP_KERNEL);
326 memset(physical_to_logical_pkg, 0xff, size);
327 size = BITS_TO_LONGS(max_physical_pkg_id) * sizeof(unsigned long);
328 physical_package_map = kzalloc(size, GFP_KERNEL);
329 size = BITS_TO_LONGS(__max_logical_packages) * sizeof(unsigned long);
330 logical_package_map = kzalloc(size, GFP_KERNEL);
331
332 pr_info("Max logical packages: %u\n", __max_logical_packages);
333
334 for_each_present_cpu(cpu) {
335 unsigned int apicid = apic->cpu_present_to_apicid(cpu);
336
337 if (apicid == BAD_APICID || !apic->apic_id_valid(apicid))
338 continue;
339 if (!topology_update_package_map(apicid, cpu))
340 continue;
341 pr_warn("CPU %u APICId %x disabled\n", cpu, apicid);
342 per_cpu(x86_bios_cpu_apicid, cpu) = BAD_APICID;
343 set_cpu_possible(cpu, false);
344 set_cpu_present(cpu, false);
345 }
346}
347
348void __init smp_store_boot_cpu_info(void)
349{
350 int id = 0; /* CPU 0 */
351 struct cpuinfo_x86 *c = &cpu_data(id);
352
353 *c = boot_cpu_data;
354 c->cpu_index = id;
355 smp_init_package_map();
356}
357
358/*
359 * The bootstrap kernel entry code has set these up. Save them for
360 * a given CPU
361 */
362void smp_store_cpu_info(int id)
363{
364 struct cpuinfo_x86 *c = &cpu_data(id);
365
366 *c = boot_cpu_data;
367 c->cpu_index = id;
368 /*
369 * During boot time, CPU0 has this setup already. Save the info when
370 * bringing up AP or offlined CPU0.
371 */
372 identify_secondary_cpu(c);
373}
374
375static bool
376topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
377{
378 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
379
380 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
381}
382
383static bool
384topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
385{
386 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
387
388 return !WARN_ONCE(!topology_same_node(c, o),
389 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
390 "[node: %d != %d]. Ignoring dependency.\n",
391 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
392}
393
394#define link_mask(mfunc, c1, c2) \
395do { \
396 cpumask_set_cpu((c1), mfunc(c2)); \
397 cpumask_set_cpu((c2), mfunc(c1)); \
398} while (0)
399
400static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
401{
402 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
403 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
404
405 if (c->phys_proc_id == o->phys_proc_id &&
406 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) &&
407 c->compute_unit_id == o->compute_unit_id)
408 return topology_sane(c, o, "smt");
409
410 } else if (c->phys_proc_id == o->phys_proc_id &&
411 c->cpu_core_id == o->cpu_core_id) {
412 return topology_sane(c, o, "smt");
413 }
414
415 return false;
416}
417
418static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
419{
420 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
421
422 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
423 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
424 return topology_sane(c, o, "llc");
425
426 return false;
427}
428
429/*
430 * Unlike the other levels, we do not enforce keeping a
431 * multicore group inside a NUMA node. If this happens, we will
432 * discard the MC level of the topology later.
433 */
434static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
435{
436 if (c->phys_proc_id == o->phys_proc_id)
437 return true;
438 return false;
439}
440
441static struct sched_domain_topology_level numa_inside_package_topology[] = {
442#ifdef CONFIG_SCHED_SMT
443 { cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) },
444#endif
445#ifdef CONFIG_SCHED_MC
446 { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) },
447#endif
448 { NULL, },
449};
450/*
451 * set_sched_topology() sets the topology internal to a CPU. The
452 * NUMA topologies are layered on top of it to build the full
453 * system topology.
454 *
455 * If NUMA nodes are observed to occur within a CPU package, this
456 * function should be called. It forces the sched domain code to
457 * only use the SMT level for the CPU portion of the topology.
458 * This essentially falls back to relying on NUMA information
459 * from the SRAT table to describe the entire system topology
460 * (except for hyperthreads).
461 */
462static void primarily_use_numa_for_topology(void)
463{
464 set_sched_topology(numa_inside_package_topology);
465}
466
467void set_cpu_sibling_map(int cpu)
468{
469 bool has_smt = smp_num_siblings > 1;
470 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
471 struct cpuinfo_x86 *c = &cpu_data(cpu);
472 struct cpuinfo_x86 *o;
473 int i;
474
475 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
476
477 if (!has_mp) {
478 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
479 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
480 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
481 c->booted_cores = 1;
482 return;
483 }
484
485 for_each_cpu(i, cpu_sibling_setup_mask) {
486 o = &cpu_data(i);
487
488 if ((i == cpu) || (has_smt && match_smt(c, o)))
489 link_mask(topology_sibling_cpumask, cpu, i);
490
491 if ((i == cpu) || (has_mp && match_llc(c, o)))
492 link_mask(cpu_llc_shared_mask, cpu, i);
493
494 }
495
496 /*
497 * This needs a separate iteration over the cpus because we rely on all
498 * topology_sibling_cpumask links to be set-up.
499 */
500 for_each_cpu(i, cpu_sibling_setup_mask) {
501 o = &cpu_data(i);
502
503 if ((i == cpu) || (has_mp && match_die(c, o))) {
504 link_mask(topology_core_cpumask, cpu, i);
505
506 /*
507 * Does this new cpu bringup a new core?
508 */
509 if (cpumask_weight(
510 topology_sibling_cpumask(cpu)) == 1) {
511 /*
512 * for each core in package, increment
513 * the booted_cores for this new cpu
514 */
515 if (cpumask_first(
516 topology_sibling_cpumask(i)) == i)
517 c->booted_cores++;
518 /*
519 * increment the core count for all
520 * the other cpus in this package
521 */
522 if (i != cpu)
523 cpu_data(i).booted_cores++;
524 } else if (i != cpu && !c->booted_cores)
525 c->booted_cores = cpu_data(i).booted_cores;
526 }
527 if (match_die(c, o) && !topology_same_node(c, o))
528 primarily_use_numa_for_topology();
529 }
530}
531
532/* maps the cpu to the sched domain representing multi-core */
533const struct cpumask *cpu_coregroup_mask(int cpu)
534{
535 return cpu_llc_shared_mask(cpu);
536}
537
538static void impress_friends(void)
539{
540 int cpu;
541 unsigned long bogosum = 0;
542 /*
543 * Allow the user to impress friends.
544 */
545 pr_debug("Before bogomips\n");
546 for_each_possible_cpu(cpu)
547 if (cpumask_test_cpu(cpu, cpu_callout_mask))
548 bogosum += cpu_data(cpu).loops_per_jiffy;
549 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
550 num_online_cpus(),
551 bogosum/(500000/HZ),
552 (bogosum/(5000/HZ))%100);
553
554 pr_debug("Before bogocount - setting activated=1\n");
555}
556
557void __inquire_remote_apic(int apicid)
558{
559 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
560 const char * const names[] = { "ID", "VERSION", "SPIV" };
561 int timeout;
562 u32 status;
563
564 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
565
566 for (i = 0; i < ARRAY_SIZE(regs); i++) {
567 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
568
569 /*
570 * Wait for idle.
571 */
572 status = safe_apic_wait_icr_idle();
573 if (status)
574 pr_cont("a previous APIC delivery may have failed\n");
575
576 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
577
578 timeout = 0;
579 do {
580 udelay(100);
581 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
582 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
583
584 switch (status) {
585 case APIC_ICR_RR_VALID:
586 status = apic_read(APIC_RRR);
587 pr_cont("%08x\n", status);
588 break;
589 default:
590 pr_cont("failed\n");
591 }
592 }
593}
594
595/*
596 * The Multiprocessor Specification 1.4 (1997) example code suggests
597 * that there should be a 10ms delay between the BSP asserting INIT
598 * and de-asserting INIT, when starting a remote processor.
599 * But that slows boot and resume on modern processors, which include
600 * many cores and don't require that delay.
601 *
602 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
603 * Modern processor families are quirked to remove the delay entirely.
604 */
605#define UDELAY_10MS_DEFAULT 10000
606
607static unsigned int init_udelay = UINT_MAX;
608
609static int __init cpu_init_udelay(char *str)
610{
611 get_option(&str, &init_udelay);
612
613 return 0;
614}
615early_param("cpu_init_udelay", cpu_init_udelay);
616
617static void __init smp_quirk_init_udelay(void)
618{
619 /* if cmdline changed it from default, leave it alone */
620 if (init_udelay != UINT_MAX)
621 return;
622
623 /* if modern processor, use no delay */
624 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
625 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
626 init_udelay = 0;
627 return;
628 }
629 /* else, use legacy delay */
630 init_udelay = UDELAY_10MS_DEFAULT;
631}
632
633/*
634 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
635 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
636 * won't ... remember to clear down the APIC, etc later.
637 */
638int
639wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
640{
641 unsigned long send_status, accept_status = 0;
642 int maxlvt;
643
644 /* Target chip */
645 /* Boot on the stack */
646 /* Kick the second */
647 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
648
649 pr_debug("Waiting for send to finish...\n");
650 send_status = safe_apic_wait_icr_idle();
651
652 /*
653 * Give the other CPU some time to accept the IPI.
654 */
655 udelay(200);
656 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
657 maxlvt = lapic_get_maxlvt();
658 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
659 apic_write(APIC_ESR, 0);
660 accept_status = (apic_read(APIC_ESR) & 0xEF);
661 }
662 pr_debug("NMI sent\n");
663
664 if (send_status)
665 pr_err("APIC never delivered???\n");
666 if (accept_status)
667 pr_err("APIC delivery error (%lx)\n", accept_status);
668
669 return (send_status | accept_status);
670}
671
672static int
673wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
674{
675 unsigned long send_status = 0, accept_status = 0;
676 int maxlvt, num_starts, j;
677
678 maxlvt = lapic_get_maxlvt();
679
680 /*
681 * Be paranoid about clearing APIC errors.
682 */
683 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
684 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
685 apic_write(APIC_ESR, 0);
686 apic_read(APIC_ESR);
687 }
688
689 pr_debug("Asserting INIT\n");
690
691 /*
692 * Turn INIT on target chip
693 */
694 /*
695 * Send IPI
696 */
697 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
698 phys_apicid);
699
700 pr_debug("Waiting for send to finish...\n");
701 send_status = safe_apic_wait_icr_idle();
702
703 udelay(init_udelay);
704
705 pr_debug("Deasserting INIT\n");
706
707 /* Target chip */
708 /* Send IPI */
709 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
710
711 pr_debug("Waiting for send to finish...\n");
712 send_status = safe_apic_wait_icr_idle();
713
714 mb();
715
716 /*
717 * Should we send STARTUP IPIs ?
718 *
719 * Determine this based on the APIC version.
720 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
721 */
722 if (APIC_INTEGRATED(apic_version[phys_apicid]))
723 num_starts = 2;
724 else
725 num_starts = 0;
726
727 /*
728 * Run STARTUP IPI loop.
729 */
730 pr_debug("#startup loops: %d\n", num_starts);
731
732 for (j = 1; j <= num_starts; j++) {
733 pr_debug("Sending STARTUP #%d\n", j);
734 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
735 apic_write(APIC_ESR, 0);
736 apic_read(APIC_ESR);
737 pr_debug("After apic_write\n");
738
739 /*
740 * STARTUP IPI
741 */
742
743 /* Target chip */
744 /* Boot on the stack */
745 /* Kick the second */
746 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
747 phys_apicid);
748
749 /*
750 * Give the other CPU some time to accept the IPI.
751 */
752 if (init_udelay == 0)
753 udelay(10);
754 else
755 udelay(300);
756
757 pr_debug("Startup point 1\n");
758
759 pr_debug("Waiting for send to finish...\n");
760 send_status = safe_apic_wait_icr_idle();
761
762 /*
763 * Give the other CPU some time to accept the IPI.
764 */
765 if (init_udelay == 0)
766 udelay(10);
767 else
768 udelay(200);
769
770 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
771 apic_write(APIC_ESR, 0);
772 accept_status = (apic_read(APIC_ESR) & 0xEF);
773 if (send_status || accept_status)
774 break;
775 }
776 pr_debug("After Startup\n");
777
778 if (send_status)
779 pr_err("APIC never delivered???\n");
780 if (accept_status)
781 pr_err("APIC delivery error (%lx)\n", accept_status);
782
783 return (send_status | accept_status);
784}
785
786void smp_announce(void)
787{
788 int num_nodes = num_online_nodes();
789
790 printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n",
791 num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus());
792}
793
794/* reduce the number of lines printed when booting a large cpu count system */
795static void announce_cpu(int cpu, int apicid)
796{
797 static int current_node = -1;
798 int node = early_cpu_to_node(cpu);
799 static int width, node_width;
800
801 if (!width)
802 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
803
804 if (!node_width)
805 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
806
807 if (cpu == 1)
808 printk(KERN_INFO "x86: Booting SMP configuration:\n");
809
810 if (system_state == SYSTEM_BOOTING) {
811 if (node != current_node) {
812 if (current_node > (-1))
813 pr_cont("\n");
814 current_node = node;
815
816 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
817 node_width - num_digits(node), " ", node);
818 }
819
820 /* Add padding for the BSP */
821 if (cpu == 1)
822 pr_cont("%*s", width + 1, " ");
823
824 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
825
826 } else
827 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
828 node, cpu, apicid);
829}
830
831static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
832{
833 int cpu;
834
835 cpu = smp_processor_id();
836 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
837 return NMI_HANDLED;
838
839 return NMI_DONE;
840}
841
842/*
843 * Wake up AP by INIT, INIT, STARTUP sequence.
844 *
845 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
846 * boot-strap code which is not a desired behavior for waking up BSP. To
847 * void the boot-strap code, wake up CPU0 by NMI instead.
848 *
849 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
850 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
851 * We'll change this code in the future to wake up hard offlined CPU0 if
852 * real platform and request are available.
853 */
854static int
855wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
856 int *cpu0_nmi_registered)
857{
858 int id;
859 int boot_error;
860
861 preempt_disable();
862
863 /*
864 * Wake up AP by INIT, INIT, STARTUP sequence.
865 */
866 if (cpu) {
867 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
868 goto out;
869 }
870
871 /*
872 * Wake up BSP by nmi.
873 *
874 * Register a NMI handler to help wake up CPU0.
875 */
876 boot_error = register_nmi_handler(NMI_LOCAL,
877 wakeup_cpu0_nmi, 0, "wake_cpu0");
878
879 if (!boot_error) {
880 enable_start_cpu0 = 1;
881 *cpu0_nmi_registered = 1;
882 if (apic->dest_logical == APIC_DEST_LOGICAL)
883 id = cpu0_logical_apicid;
884 else
885 id = apicid;
886 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
887 }
888
889out:
890 preempt_enable();
891
892 return boot_error;
893}
894
895void common_cpu_up(unsigned int cpu, struct task_struct *idle)
896{
897 /* Just in case we booted with a single CPU. */
898 alternatives_enable_smp();
899
900 per_cpu(current_task, cpu) = idle;
901
902#ifdef CONFIG_X86_32
903 /* Stack for startup_32 can be just as for start_secondary onwards */
904 irq_ctx_init(cpu);
905 per_cpu(cpu_current_top_of_stack, cpu) =
906 (unsigned long)task_stack_page(idle) + THREAD_SIZE;
907#else
908 clear_tsk_thread_flag(idle, TIF_FORK);
909 initial_gs = per_cpu_offset(cpu);
910#endif
911}
912
913/*
914 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
915 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
916 * Returns zero if CPU booted OK, else error code from
917 * ->wakeup_secondary_cpu.
918 */
919static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
920{
921 volatile u32 *trampoline_status =
922 (volatile u32 *) __va(real_mode_header->trampoline_status);
923 /* start_ip had better be page-aligned! */
924 unsigned long start_ip = real_mode_header->trampoline_start;
925
926 unsigned long boot_error = 0;
927 int cpu0_nmi_registered = 0;
928 unsigned long timeout;
929
930 idle->thread.sp = (unsigned long) (((struct pt_regs *)
931 (THREAD_SIZE + task_stack_page(idle))) - 1);
932
933 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
934 initial_code = (unsigned long)start_secondary;
935 stack_start = idle->thread.sp;
936
937 /*
938 * Enable the espfix hack for this CPU
939 */
940#ifdef CONFIG_X86_ESPFIX64
941 init_espfix_ap(cpu);
942#endif
943
944 /* So we see what's up */
945 announce_cpu(cpu, apicid);
946
947 /*
948 * This grunge runs the startup process for
949 * the targeted processor.
950 */
951
952 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
953
954 pr_debug("Setting warm reset code and vector.\n");
955
956 smpboot_setup_warm_reset_vector(start_ip);
957 /*
958 * Be paranoid about clearing APIC errors.
959 */
960 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
961 apic_write(APIC_ESR, 0);
962 apic_read(APIC_ESR);
963 }
964 }
965
966 /*
967 * AP might wait on cpu_callout_mask in cpu_init() with
968 * cpu_initialized_mask set if previous attempt to online
969 * it timed-out. Clear cpu_initialized_mask so that after
970 * INIT/SIPI it could start with a clean state.
971 */
972 cpumask_clear_cpu(cpu, cpu_initialized_mask);
973 smp_mb();
974
975 /*
976 * Wake up a CPU in difference cases:
977 * - Use the method in the APIC driver if it's defined
978 * Otherwise,
979 * - Use an INIT boot APIC message for APs or NMI for BSP.
980 */
981 if (apic->wakeup_secondary_cpu)
982 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
983 else
984 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
985 &cpu0_nmi_registered);
986
987 if (!boot_error) {
988 /*
989 * Wait 10s total for first sign of life from AP
990 */
991 boot_error = -1;
992 timeout = jiffies + 10*HZ;
993 while (time_before(jiffies, timeout)) {
994 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
995 /*
996 * Tell AP to proceed with initialization
997 */
998 cpumask_set_cpu(cpu, cpu_callout_mask);
999 boot_error = 0;
1000 break;
1001 }
1002 schedule();
1003 }
1004 }
1005
1006 if (!boot_error) {
1007 /*
1008 * Wait till AP completes initial initialization
1009 */
1010 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1011 /*
1012 * Allow other tasks to run while we wait for the
1013 * AP to come online. This also gives a chance
1014 * for the MTRR work(triggered by the AP coming online)
1015 * to be completed in the stop machine context.
1016 */
1017 schedule();
1018 }
1019 }
1020
1021 /* mark "stuck" area as not stuck */
1022 *trampoline_status = 0;
1023
1024 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
1025 /*
1026 * Cleanup possible dangling ends...
1027 */
1028 smpboot_restore_warm_reset_vector();
1029 }
1030 /*
1031 * Clean up the nmi handler. Do this after the callin and callout sync
1032 * to avoid impact of possible long unregister time.
1033 */
1034 if (cpu0_nmi_registered)
1035 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1036
1037 return boot_error;
1038}
1039
1040int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1041{
1042 int apicid = apic->cpu_present_to_apicid(cpu);
1043 unsigned long flags;
1044 int err;
1045
1046 WARN_ON(irqs_disabled());
1047
1048 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1049
1050 if (apicid == BAD_APICID ||
1051 !physid_isset(apicid, phys_cpu_present_map) ||
1052 !apic->apic_id_valid(apicid)) {
1053 pr_err("%s: bad cpu %d\n", __func__, cpu);
1054 return -EINVAL;
1055 }
1056
1057 /*
1058 * Already booted CPU?
1059 */
1060 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1061 pr_debug("do_boot_cpu %d Already started\n", cpu);
1062 return -ENOSYS;
1063 }
1064
1065 /*
1066 * Save current MTRR state in case it was changed since early boot
1067 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1068 */
1069 mtrr_save_state();
1070
1071 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1072 err = cpu_check_up_prepare(cpu);
1073 if (err && err != -EBUSY)
1074 return err;
1075
1076 /* the FPU context is blank, nobody can own it */
1077 __cpu_disable_lazy_restore(cpu);
1078
1079 common_cpu_up(cpu, tidle);
1080
1081 /*
1082 * We have to walk the irq descriptors to setup the vector
1083 * space for the cpu which comes online. Prevent irq
1084 * alloc/free across the bringup.
1085 */
1086 irq_lock_sparse();
1087
1088 err = do_boot_cpu(apicid, cpu, tidle);
1089
1090 if (err) {
1091 irq_unlock_sparse();
1092 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1093 return -EIO;
1094 }
1095
1096 /*
1097 * Check TSC synchronization with the AP (keep irqs disabled
1098 * while doing so):
1099 */
1100 local_irq_save(flags);
1101 check_tsc_sync_source(cpu);
1102 local_irq_restore(flags);
1103
1104 while (!cpu_online(cpu)) {
1105 cpu_relax();
1106 touch_nmi_watchdog();
1107 }
1108
1109 irq_unlock_sparse();
1110
1111 return 0;
1112}
1113
1114/**
1115 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1116 */
1117void arch_disable_smp_support(void)
1118{
1119 disable_ioapic_support();
1120}
1121
1122/*
1123 * Fall back to non SMP mode after errors.
1124 *
1125 * RED-PEN audit/test this more. I bet there is more state messed up here.
1126 */
1127static __init void disable_smp(void)
1128{
1129 pr_info("SMP disabled\n");
1130
1131 disable_ioapic_support();
1132
1133 init_cpu_present(cpumask_of(0));
1134 init_cpu_possible(cpumask_of(0));
1135
1136 if (smp_found_config)
1137 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1138 else
1139 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1140 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1141 cpumask_set_cpu(0, topology_core_cpumask(0));
1142}
1143
1144enum {
1145 SMP_OK,
1146 SMP_NO_CONFIG,
1147 SMP_NO_APIC,
1148 SMP_FORCE_UP,
1149};
1150
1151/*
1152 * Various sanity checks.
1153 */
1154static int __init smp_sanity_check(unsigned max_cpus)
1155{
1156 preempt_disable();
1157
1158#if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1159 if (def_to_bigsmp && nr_cpu_ids > 8) {
1160 unsigned int cpu;
1161 unsigned nr;
1162
1163 pr_warn("More than 8 CPUs detected - skipping them\n"
1164 "Use CONFIG_X86_BIGSMP\n");
1165
1166 nr = 0;
1167 for_each_present_cpu(cpu) {
1168 if (nr >= 8)
1169 set_cpu_present(cpu, false);
1170 nr++;
1171 }
1172
1173 nr = 0;
1174 for_each_possible_cpu(cpu) {
1175 if (nr >= 8)
1176 set_cpu_possible(cpu, false);
1177 nr++;
1178 }
1179
1180 nr_cpu_ids = 8;
1181 }
1182#endif
1183
1184 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1185 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1186 hard_smp_processor_id());
1187
1188 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1189 }
1190
1191 /*
1192 * If we couldn't find an SMP configuration at boot time,
1193 * get out of here now!
1194 */
1195 if (!smp_found_config && !acpi_lapic) {
1196 preempt_enable();
1197 pr_notice("SMP motherboard not detected\n");
1198 return SMP_NO_CONFIG;
1199 }
1200
1201 /*
1202 * Should not be necessary because the MP table should list the boot
1203 * CPU too, but we do it for the sake of robustness anyway.
1204 */
1205 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1206 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1207 boot_cpu_physical_apicid);
1208 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1209 }
1210 preempt_enable();
1211
1212 /*
1213 * If we couldn't find a local APIC, then get out of here now!
1214 */
1215 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1216 !cpu_has_apic) {
1217 if (!disable_apic) {
1218 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1219 boot_cpu_physical_apicid);
1220 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1221 }
1222 return SMP_NO_APIC;
1223 }
1224
1225 /*
1226 * If SMP should be disabled, then really disable it!
1227 */
1228 if (!max_cpus) {
1229 pr_info("SMP mode deactivated\n");
1230 return SMP_FORCE_UP;
1231 }
1232
1233 return SMP_OK;
1234}
1235
1236static void __init smp_cpu_index_default(void)
1237{
1238 int i;
1239 struct cpuinfo_x86 *c;
1240
1241 for_each_possible_cpu(i) {
1242 c = &cpu_data(i);
1243 /* mark all to hotplug */
1244 c->cpu_index = nr_cpu_ids;
1245 }
1246}
1247
1248/*
1249 * Prepare for SMP bootup. The MP table or ACPI has been read
1250 * earlier. Just do some sanity checking here and enable APIC mode.
1251 */
1252void __init native_smp_prepare_cpus(unsigned int max_cpus)
1253{
1254 unsigned int i;
1255
1256 smp_cpu_index_default();
1257
1258 /*
1259 * Setup boot CPU information
1260 */
1261 smp_store_boot_cpu_info(); /* Final full version of the data */
1262 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1263 mb();
1264
1265 current_thread_info()->cpu = 0; /* needed? */
1266 for_each_possible_cpu(i) {
1267 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1268 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1269 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1270 }
1271 set_cpu_sibling_map(0);
1272
1273 switch (smp_sanity_check(max_cpus)) {
1274 case SMP_NO_CONFIG:
1275 disable_smp();
1276 if (APIC_init_uniprocessor())
1277 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1278 return;
1279 case SMP_NO_APIC:
1280 disable_smp();
1281 return;
1282 case SMP_FORCE_UP:
1283 disable_smp();
1284 apic_bsp_setup(false);
1285 return;
1286 case SMP_OK:
1287 break;
1288 }
1289
1290 default_setup_apic_routing();
1291
1292 if (read_apic_id() != boot_cpu_physical_apicid) {
1293 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1294 read_apic_id(), boot_cpu_physical_apicid);
1295 /* Or can we switch back to PIC here? */
1296 }
1297
1298 cpu0_logical_apicid = apic_bsp_setup(false);
1299
1300 pr_info("CPU%d: ", 0);
1301 print_cpu_info(&cpu_data(0));
1302
1303 if (is_uv_system())
1304 uv_system_init();
1305
1306 set_mtrr_aps_delayed_init();
1307
1308 smp_quirk_init_udelay();
1309}
1310
1311void arch_enable_nonboot_cpus_begin(void)
1312{
1313 set_mtrr_aps_delayed_init();
1314}
1315
1316void arch_enable_nonboot_cpus_end(void)
1317{
1318 mtrr_aps_init();
1319}
1320
1321/*
1322 * Early setup to make printk work.
1323 */
1324void __init native_smp_prepare_boot_cpu(void)
1325{
1326 int me = smp_processor_id();
1327 switch_to_new_gdt(me);
1328 /* already set me in cpu_online_mask in boot_cpu_init() */
1329 cpumask_set_cpu(me, cpu_callout_mask);
1330 cpu_set_state_online(me);
1331}
1332
1333void __init native_smp_cpus_done(unsigned int max_cpus)
1334{
1335 pr_debug("Boot done\n");
1336
1337 nmi_selftest();
1338 impress_friends();
1339 setup_ioapic_dest();
1340 mtrr_aps_init();
1341}
1342
1343static int __initdata setup_possible_cpus = -1;
1344static int __init _setup_possible_cpus(char *str)
1345{
1346 get_option(&str, &setup_possible_cpus);
1347 return 0;
1348}
1349early_param("possible_cpus", _setup_possible_cpus);
1350
1351
1352/*
1353 * cpu_possible_mask should be static, it cannot change as cpu's
1354 * are onlined, or offlined. The reason is per-cpu data-structures
1355 * are allocated by some modules at init time, and dont expect to
1356 * do this dynamically on cpu arrival/departure.
1357 * cpu_present_mask on the other hand can change dynamically.
1358 * In case when cpu_hotplug is not compiled, then we resort to current
1359 * behaviour, which is cpu_possible == cpu_present.
1360 * - Ashok Raj
1361 *
1362 * Three ways to find out the number of additional hotplug CPUs:
1363 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1364 * - The user can overwrite it with possible_cpus=NUM
1365 * - Otherwise don't reserve additional CPUs.
1366 * We do this because additional CPUs waste a lot of memory.
1367 * -AK
1368 */
1369__init void prefill_possible_map(void)
1370{
1371 int i, possible;
1372
1373 /* no processor from mptable or madt */
1374 if (!num_processors)
1375 num_processors = 1;
1376
1377 i = setup_max_cpus ?: 1;
1378 if (setup_possible_cpus == -1) {
1379 possible = num_processors;
1380#ifdef CONFIG_HOTPLUG_CPU
1381 if (setup_max_cpus)
1382 possible += disabled_cpus;
1383#else
1384 if (possible > i)
1385 possible = i;
1386#endif
1387 } else
1388 possible = setup_possible_cpus;
1389
1390 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1391
1392 /* nr_cpu_ids could be reduced via nr_cpus= */
1393 if (possible > nr_cpu_ids) {
1394 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1395 possible, nr_cpu_ids);
1396 possible = nr_cpu_ids;
1397 }
1398
1399#ifdef CONFIG_HOTPLUG_CPU
1400 if (!setup_max_cpus)
1401#endif
1402 if (possible > i) {
1403 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1404 possible, setup_max_cpus);
1405 possible = i;
1406 }
1407
1408 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1409 possible, max_t(int, possible - num_processors, 0));
1410
1411 for (i = 0; i < possible; i++)
1412 set_cpu_possible(i, true);
1413 for (; i < NR_CPUS; i++)
1414 set_cpu_possible(i, false);
1415
1416 nr_cpu_ids = possible;
1417}
1418
1419#ifdef CONFIG_HOTPLUG_CPU
1420
1421static void remove_siblinginfo(int cpu)
1422{
1423 int sibling;
1424 struct cpuinfo_x86 *c = &cpu_data(cpu);
1425
1426 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1427 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1428 /*/
1429 * last thread sibling in this cpu core going down
1430 */
1431 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1432 cpu_data(sibling).booted_cores--;
1433 }
1434
1435 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1436 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1437 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1438 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1439 cpumask_clear(cpu_llc_shared_mask(cpu));
1440 cpumask_clear(topology_sibling_cpumask(cpu));
1441 cpumask_clear(topology_core_cpumask(cpu));
1442 c->phys_proc_id = 0;
1443 c->cpu_core_id = 0;
1444 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1445}
1446
1447static void remove_cpu_from_maps(int cpu)
1448{
1449 set_cpu_online(cpu, false);
1450 cpumask_clear_cpu(cpu, cpu_callout_mask);
1451 cpumask_clear_cpu(cpu, cpu_callin_mask);
1452 /* was set by cpu_init() */
1453 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1454 numa_remove_cpu(cpu);
1455}
1456
1457void cpu_disable_common(void)
1458{
1459 int cpu = smp_processor_id();
1460
1461 remove_siblinginfo(cpu);
1462
1463 /* It's now safe to remove this processor from the online map */
1464 lock_vector_lock();
1465 remove_cpu_from_maps(cpu);
1466 unlock_vector_lock();
1467 fixup_irqs();
1468}
1469
1470int native_cpu_disable(void)
1471{
1472 int ret;
1473
1474 ret = check_irq_vectors_for_cpu_disable();
1475 if (ret)
1476 return ret;
1477
1478 clear_local_APIC();
1479 cpu_disable_common();
1480
1481 return 0;
1482}
1483
1484int common_cpu_die(unsigned int cpu)
1485{
1486 int ret = 0;
1487
1488 /* We don't do anything here: idle task is faking death itself. */
1489
1490 /* They ack this in play_dead() by setting CPU_DEAD */
1491 if (cpu_wait_death(cpu, 5)) {
1492 if (system_state == SYSTEM_RUNNING)
1493 pr_info("CPU %u is now offline\n", cpu);
1494 } else {
1495 pr_err("CPU %u didn't die...\n", cpu);
1496 ret = -1;
1497 }
1498
1499 return ret;
1500}
1501
1502void native_cpu_die(unsigned int cpu)
1503{
1504 common_cpu_die(cpu);
1505}
1506
1507void play_dead_common(void)
1508{
1509 idle_task_exit();
1510 reset_lazy_tlbstate();
1511 amd_e400_remove_cpu(raw_smp_processor_id());
1512
1513 /* Ack it */
1514 (void)cpu_report_death();
1515
1516 /*
1517 * With physical CPU hotplug, we should halt the cpu
1518 */
1519 local_irq_disable();
1520}
1521
1522static bool wakeup_cpu0(void)
1523{
1524 if (smp_processor_id() == 0 && enable_start_cpu0)
1525 return true;
1526
1527 return false;
1528}
1529
1530/*
1531 * We need to flush the caches before going to sleep, lest we have
1532 * dirty data in our caches when we come back up.
1533 */
1534static inline void mwait_play_dead(void)
1535{
1536 unsigned int eax, ebx, ecx, edx;
1537 unsigned int highest_cstate = 0;
1538 unsigned int highest_subcstate = 0;
1539 void *mwait_ptr;
1540 int i;
1541
1542 if (!this_cpu_has(X86_FEATURE_MWAIT))
1543 return;
1544 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1545 return;
1546 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1547 return;
1548
1549 eax = CPUID_MWAIT_LEAF;
1550 ecx = 0;
1551 native_cpuid(&eax, &ebx, &ecx, &edx);
1552
1553 /*
1554 * eax will be 0 if EDX enumeration is not valid.
1555 * Initialized below to cstate, sub_cstate value when EDX is valid.
1556 */
1557 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1558 eax = 0;
1559 } else {
1560 edx >>= MWAIT_SUBSTATE_SIZE;
1561 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1562 if (edx & MWAIT_SUBSTATE_MASK) {
1563 highest_cstate = i;
1564 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1565 }
1566 }
1567 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1568 (highest_subcstate - 1);
1569 }
1570
1571 /*
1572 * This should be a memory location in a cache line which is
1573 * unlikely to be touched by other processors. The actual
1574 * content is immaterial as it is not actually modified in any way.
1575 */
1576 mwait_ptr = &current_thread_info()->flags;
1577
1578 wbinvd();
1579
1580 while (1) {
1581 /*
1582 * The CLFLUSH is a workaround for erratum AAI65 for
1583 * the Xeon 7400 series. It's not clear it is actually
1584 * needed, but it should be harmless in either case.
1585 * The WBINVD is insufficient due to the spurious-wakeup
1586 * case where we return around the loop.
1587 */
1588 mb();
1589 clflush(mwait_ptr);
1590 mb();
1591 __monitor(mwait_ptr, 0, 0);
1592 mb();
1593 __mwait(eax, 0);
1594 /*
1595 * If NMI wants to wake up CPU0, start CPU0.
1596 */
1597 if (wakeup_cpu0())
1598 start_cpu0();
1599 }
1600}
1601
1602static inline void hlt_play_dead(void)
1603{
1604 if (__this_cpu_read(cpu_info.x86) >= 4)
1605 wbinvd();
1606
1607 while (1) {
1608 native_halt();
1609 /*
1610 * If NMI wants to wake up CPU0, start CPU0.
1611 */
1612 if (wakeup_cpu0())
1613 start_cpu0();
1614 }
1615}
1616
1617void native_play_dead(void)
1618{
1619 play_dead_common();
1620 tboot_shutdown(TB_SHUTDOWN_WFS);
1621
1622 mwait_play_dead(); /* Only returns on failure */
1623 if (cpuidle_play_dead())
1624 hlt_play_dead();
1625}
1626
1627#else /* ... !CONFIG_HOTPLUG_CPU */
1628int native_cpu_disable(void)
1629{
1630 return -ENOSYS;
1631}
1632
1633void native_cpu_die(unsigned int cpu)
1634{
1635 /* We said "no" in __cpu_disable */
1636 BUG();
1637}
1638
1639void native_play_dead(void)
1640{
1641 BUG();
1642}
1643
1644#endif
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