| 1 | /* |
| 2 | * Copyright (c) 2015, Mellanox Technologies. All rights reserved. |
| 3 | * |
| 4 | * This software is available to you under a choice of one of two |
| 5 | * licenses. You may choose to be licensed under the terms of the GNU |
| 6 | * General Public License (GPL) Version 2, available from the file |
| 7 | * COPYING in the main directory of this source tree, or the |
| 8 | * OpenIB.org BSD license below: |
| 9 | * |
| 10 | * Redistribution and use in source and binary forms, with or |
| 11 | * without modification, are permitted provided that the following |
| 12 | * conditions are met: |
| 13 | * |
| 14 | * - Redistributions of source code must retain the above |
| 15 | * copyright notice, this list of conditions and the following |
| 16 | * disclaimer. |
| 17 | * |
| 18 | * - Redistributions in binary form must reproduce the above |
| 19 | * copyright notice, this list of conditions and the following |
| 20 | * disclaimer in the documentation and/or other materials |
| 21 | * provided with the distribution. |
| 22 | * |
| 23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
| 27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
| 28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| 29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 30 | * SOFTWARE. |
| 31 | */ |
| 32 | |
| 33 | #include <linux/if_vlan.h> |
| 34 | #include <linux/etherdevice.h> |
| 35 | #include <linux/timecounter.h> |
| 36 | #include <linux/net_tstamp.h> |
| 37 | #include <linux/mlx5/driver.h> |
| 38 | #include <linux/mlx5/qp.h> |
| 39 | #include <linux/mlx5/cq.h> |
| 40 | #include <linux/mlx5/vport.h> |
| 41 | #include "wq.h" |
| 42 | #include "transobj.h" |
| 43 | #include "mlx5_core.h" |
| 44 | |
| 45 | #define MLX5E_MAX_NUM_TC 8 |
| 46 | |
| 47 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
| 48 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa |
| 49 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd |
| 50 | |
| 51 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1 |
| 52 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
| 53 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd |
| 54 | |
| 55 | #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024) |
| 56 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 |
| 57 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 |
| 58 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 |
| 59 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 |
| 60 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 |
| 61 | |
| 62 | #define MLX5E_LOG_INDIR_RQT_SIZE 0x7 |
| 63 | #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE) |
| 64 | #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1) |
| 65 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
| 66 | #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */ |
| 67 | #define MLX5E_SQ_BF_BUDGET 16 |
| 68 | |
| 69 | #define MLX5E_NUM_MAIN_GROUPS 9 |
| 70 | |
| 71 | static const char vport_strings[][ETH_GSTRING_LEN] = { |
| 72 | /* vport statistics */ |
| 73 | "rx_packets", |
| 74 | "rx_bytes", |
| 75 | "tx_packets", |
| 76 | "tx_bytes", |
| 77 | "rx_error_packets", |
| 78 | "rx_error_bytes", |
| 79 | "tx_error_packets", |
| 80 | "tx_error_bytes", |
| 81 | "rx_unicast_packets", |
| 82 | "rx_unicast_bytes", |
| 83 | "tx_unicast_packets", |
| 84 | "tx_unicast_bytes", |
| 85 | "rx_multicast_packets", |
| 86 | "rx_multicast_bytes", |
| 87 | "tx_multicast_packets", |
| 88 | "tx_multicast_bytes", |
| 89 | "rx_broadcast_packets", |
| 90 | "rx_broadcast_bytes", |
| 91 | "tx_broadcast_packets", |
| 92 | "tx_broadcast_bytes", |
| 93 | |
| 94 | /* SW counters */ |
| 95 | "tso_packets", |
| 96 | "tso_bytes", |
| 97 | "lro_packets", |
| 98 | "lro_bytes", |
| 99 | "rx_csum_good", |
| 100 | "rx_csum_none", |
| 101 | "rx_csum_sw", |
| 102 | "tx_csum_offload", |
| 103 | "tx_queue_stopped", |
| 104 | "tx_queue_wake", |
| 105 | "tx_queue_dropped", |
| 106 | "rx_wqe_err", |
| 107 | }; |
| 108 | |
| 109 | struct mlx5e_vport_stats { |
| 110 | /* HW counters */ |
| 111 | u64 rx_packets; |
| 112 | u64 rx_bytes; |
| 113 | u64 tx_packets; |
| 114 | u64 tx_bytes; |
| 115 | u64 rx_error_packets; |
| 116 | u64 rx_error_bytes; |
| 117 | u64 tx_error_packets; |
| 118 | u64 tx_error_bytes; |
| 119 | u64 rx_unicast_packets; |
| 120 | u64 rx_unicast_bytes; |
| 121 | u64 tx_unicast_packets; |
| 122 | u64 tx_unicast_bytes; |
| 123 | u64 rx_multicast_packets; |
| 124 | u64 rx_multicast_bytes; |
| 125 | u64 tx_multicast_packets; |
| 126 | u64 tx_multicast_bytes; |
| 127 | u64 rx_broadcast_packets; |
| 128 | u64 rx_broadcast_bytes; |
| 129 | u64 tx_broadcast_packets; |
| 130 | u64 tx_broadcast_bytes; |
| 131 | |
| 132 | /* SW counters */ |
| 133 | u64 tso_packets; |
| 134 | u64 tso_bytes; |
| 135 | u64 lro_packets; |
| 136 | u64 lro_bytes; |
| 137 | u64 rx_csum_good; |
| 138 | u64 rx_csum_none; |
| 139 | u64 rx_csum_sw; |
| 140 | u64 tx_csum_offload; |
| 141 | u64 tx_queue_stopped; |
| 142 | u64 tx_queue_wake; |
| 143 | u64 tx_queue_dropped; |
| 144 | u64 rx_wqe_err; |
| 145 | |
| 146 | #define NUM_VPORT_COUNTERS 32 |
| 147 | }; |
| 148 | |
| 149 | static const char pport_strings[][ETH_GSTRING_LEN] = { |
| 150 | /* IEEE802.3 counters */ |
| 151 | "frames_tx", |
| 152 | "frames_rx", |
| 153 | "check_seq_err", |
| 154 | "alignment_err", |
| 155 | "octets_tx", |
| 156 | "octets_received", |
| 157 | "multicast_xmitted", |
| 158 | "broadcast_xmitted", |
| 159 | "multicast_rx", |
| 160 | "broadcast_rx", |
| 161 | "in_range_len_errors", |
| 162 | "out_of_range_len", |
| 163 | "too_long_errors", |
| 164 | "symbol_err", |
| 165 | "mac_control_tx", |
| 166 | "mac_control_rx", |
| 167 | "unsupported_op_rx", |
| 168 | "pause_ctrl_rx", |
| 169 | "pause_ctrl_tx", |
| 170 | |
| 171 | /* RFC2863 counters */ |
| 172 | "in_octets", |
| 173 | "in_ucast_pkts", |
| 174 | "in_discards", |
| 175 | "in_errors", |
| 176 | "in_unknown_protos", |
| 177 | "out_octets", |
| 178 | "out_ucast_pkts", |
| 179 | "out_discards", |
| 180 | "out_errors", |
| 181 | "in_multicast_pkts", |
| 182 | "in_broadcast_pkts", |
| 183 | "out_multicast_pkts", |
| 184 | "out_broadcast_pkts", |
| 185 | |
| 186 | /* RFC2819 counters */ |
| 187 | "drop_events", |
| 188 | "octets", |
| 189 | "pkts", |
| 190 | "broadcast_pkts", |
| 191 | "multicast_pkts", |
| 192 | "crc_align_errors", |
| 193 | "undersize_pkts", |
| 194 | "oversize_pkts", |
| 195 | "fragments", |
| 196 | "jabbers", |
| 197 | "collisions", |
| 198 | "p64octets", |
| 199 | "p65to127octets", |
| 200 | "p128to255octets", |
| 201 | "p256to511octets", |
| 202 | "p512to1023octets", |
| 203 | "p1024to1518octets", |
| 204 | "p1519to2047octets", |
| 205 | "p2048to4095octets", |
| 206 | "p4096to8191octets", |
| 207 | "p8192to10239octets", |
| 208 | }; |
| 209 | |
| 210 | #define NUM_IEEE_802_3_COUNTERS 19 |
| 211 | #define NUM_RFC_2863_COUNTERS 13 |
| 212 | #define NUM_RFC_2819_COUNTERS 21 |
| 213 | #define NUM_PPORT_COUNTERS (NUM_IEEE_802_3_COUNTERS + \ |
| 214 | NUM_RFC_2863_COUNTERS + \ |
| 215 | NUM_RFC_2819_COUNTERS) |
| 216 | |
| 217 | struct mlx5e_pport_stats { |
| 218 | __be64 IEEE_802_3_counters[NUM_IEEE_802_3_COUNTERS]; |
| 219 | __be64 RFC_2863_counters[NUM_RFC_2863_COUNTERS]; |
| 220 | __be64 RFC_2819_counters[NUM_RFC_2819_COUNTERS]; |
| 221 | }; |
| 222 | |
| 223 | static const char rq_stats_strings[][ETH_GSTRING_LEN] = { |
| 224 | "packets", |
| 225 | "csum_none", |
| 226 | "csum_sw", |
| 227 | "lro_packets", |
| 228 | "lro_bytes", |
| 229 | "wqe_err" |
| 230 | }; |
| 231 | |
| 232 | struct mlx5e_rq_stats { |
| 233 | u64 packets; |
| 234 | u64 csum_none; |
| 235 | u64 csum_sw; |
| 236 | u64 lro_packets; |
| 237 | u64 lro_bytes; |
| 238 | u64 wqe_err; |
| 239 | #define NUM_RQ_STATS 6 |
| 240 | }; |
| 241 | |
| 242 | static const char sq_stats_strings[][ETH_GSTRING_LEN] = { |
| 243 | "packets", |
| 244 | "tso_packets", |
| 245 | "tso_bytes", |
| 246 | "csum_offload_none", |
| 247 | "stopped", |
| 248 | "wake", |
| 249 | "dropped", |
| 250 | "nop" |
| 251 | }; |
| 252 | |
| 253 | struct mlx5e_sq_stats { |
| 254 | u64 packets; |
| 255 | u64 tso_packets; |
| 256 | u64 tso_bytes; |
| 257 | u64 csum_offload_none; |
| 258 | u64 stopped; |
| 259 | u64 wake; |
| 260 | u64 dropped; |
| 261 | u64 nop; |
| 262 | #define NUM_SQ_STATS 8 |
| 263 | }; |
| 264 | |
| 265 | struct mlx5e_stats { |
| 266 | struct mlx5e_vport_stats vport; |
| 267 | struct mlx5e_pport_stats pport; |
| 268 | }; |
| 269 | |
| 270 | struct mlx5e_params { |
| 271 | u8 log_sq_size; |
| 272 | u8 log_rq_size; |
| 273 | u16 num_channels; |
| 274 | u8 default_vlan_prio; |
| 275 | u8 num_tc; |
| 276 | u16 rx_cq_moderation_usec; |
| 277 | u16 rx_cq_moderation_pkts; |
| 278 | u16 tx_cq_moderation_usec; |
| 279 | u16 tx_cq_moderation_pkts; |
| 280 | u16 min_rx_wqes; |
| 281 | bool lro_en; |
| 282 | u32 lro_wqe_sz; |
| 283 | u16 tx_max_inline; |
| 284 | u8 rss_hfunc; |
| 285 | u8 toeplitz_hash_key[40]; |
| 286 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; |
| 287 | }; |
| 288 | |
| 289 | struct mlx5e_tstamp { |
| 290 | rwlock_t lock; |
| 291 | struct cyclecounter cycles; |
| 292 | struct timecounter clock; |
| 293 | struct hwtstamp_config hwtstamp_config; |
| 294 | u32 nominal_c_mult; |
| 295 | unsigned long overflow_period; |
| 296 | struct delayed_work overflow_work; |
| 297 | struct mlx5_core_dev *mdev; |
| 298 | }; |
| 299 | |
| 300 | enum { |
| 301 | MLX5E_RQ_STATE_POST_WQES_ENABLE, |
| 302 | }; |
| 303 | |
| 304 | enum cq_flags { |
| 305 | MLX5E_CQ_HAS_CQES = 1, |
| 306 | }; |
| 307 | |
| 308 | struct mlx5e_cq { |
| 309 | /* data path - accessed per cqe */ |
| 310 | struct mlx5_cqwq wq; |
| 311 | unsigned long flags; |
| 312 | |
| 313 | /* data path - accessed per napi poll */ |
| 314 | struct napi_struct *napi; |
| 315 | struct mlx5_core_cq mcq; |
| 316 | struct mlx5e_channel *channel; |
| 317 | struct mlx5e_priv *priv; |
| 318 | |
| 319 | /* control */ |
| 320 | struct mlx5_wq_ctrl wq_ctrl; |
| 321 | } ____cacheline_aligned_in_smp; |
| 322 | |
| 323 | struct mlx5e_rq { |
| 324 | /* data path */ |
| 325 | struct mlx5_wq_ll wq; |
| 326 | u32 wqe_sz; |
| 327 | struct sk_buff **skb; |
| 328 | |
| 329 | struct device *pdev; |
| 330 | struct net_device *netdev; |
| 331 | struct mlx5e_tstamp *tstamp; |
| 332 | struct mlx5e_rq_stats stats; |
| 333 | struct mlx5e_cq cq; |
| 334 | |
| 335 | unsigned long state; |
| 336 | int ix; |
| 337 | |
| 338 | /* control */ |
| 339 | struct mlx5_wq_ctrl wq_ctrl; |
| 340 | u32 rqn; |
| 341 | struct mlx5e_channel *channel; |
| 342 | struct mlx5e_priv *priv; |
| 343 | } ____cacheline_aligned_in_smp; |
| 344 | |
| 345 | struct mlx5e_tx_wqe_info { |
| 346 | u32 num_bytes; |
| 347 | u8 num_wqebbs; |
| 348 | u8 num_dma; |
| 349 | }; |
| 350 | |
| 351 | enum mlx5e_dma_map_type { |
| 352 | MLX5E_DMA_MAP_SINGLE, |
| 353 | MLX5E_DMA_MAP_PAGE |
| 354 | }; |
| 355 | |
| 356 | struct mlx5e_sq_dma { |
| 357 | dma_addr_t addr; |
| 358 | u32 size; |
| 359 | enum mlx5e_dma_map_type type; |
| 360 | }; |
| 361 | |
| 362 | enum { |
| 363 | MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, |
| 364 | }; |
| 365 | |
| 366 | struct mlx5e_sq { |
| 367 | /* data path */ |
| 368 | |
| 369 | /* dirtied @completion */ |
| 370 | u16 cc; |
| 371 | u32 dma_fifo_cc; |
| 372 | |
| 373 | /* dirtied @xmit */ |
| 374 | u16 pc ____cacheline_aligned_in_smp; |
| 375 | u32 dma_fifo_pc; |
| 376 | u16 bf_offset; |
| 377 | u16 prev_cc; |
| 378 | u8 bf_budget; |
| 379 | struct mlx5e_sq_stats stats; |
| 380 | |
| 381 | struct mlx5e_cq cq; |
| 382 | |
| 383 | /* pointers to per packet info: write@xmit, read@completion */ |
| 384 | struct sk_buff **skb; |
| 385 | struct mlx5e_sq_dma *dma_fifo; |
| 386 | struct mlx5e_tx_wqe_info *wqe_info; |
| 387 | |
| 388 | /* read only */ |
| 389 | struct mlx5_wq_cyc wq; |
| 390 | u32 dma_fifo_mask; |
| 391 | void __iomem *uar_map; |
| 392 | void __iomem *uar_bf_map; |
| 393 | struct netdev_queue *txq; |
| 394 | u32 sqn; |
| 395 | u16 bf_buf_size; |
| 396 | u16 max_inline; |
| 397 | u16 edge; |
| 398 | struct device *pdev; |
| 399 | struct mlx5e_tstamp *tstamp; |
| 400 | __be32 mkey_be; |
| 401 | unsigned long state; |
| 402 | |
| 403 | /* control path */ |
| 404 | struct mlx5_wq_ctrl wq_ctrl; |
| 405 | struct mlx5_uar uar; |
| 406 | struct mlx5e_channel *channel; |
| 407 | int tc; |
| 408 | } ____cacheline_aligned_in_smp; |
| 409 | |
| 410 | static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) |
| 411 | { |
| 412 | return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) || |
| 413 | (sq->cc == sq->pc)); |
| 414 | } |
| 415 | |
| 416 | enum channel_flags { |
| 417 | MLX5E_CHANNEL_NAPI_SCHED = 1, |
| 418 | }; |
| 419 | |
| 420 | struct mlx5e_channel { |
| 421 | /* data path */ |
| 422 | struct mlx5e_rq rq; |
| 423 | struct mlx5e_sq sq[MLX5E_MAX_NUM_TC]; |
| 424 | struct napi_struct napi; |
| 425 | struct device *pdev; |
| 426 | struct net_device *netdev; |
| 427 | __be32 mkey_be; |
| 428 | u8 num_tc; |
| 429 | unsigned long flags; |
| 430 | |
| 431 | /* control */ |
| 432 | struct mlx5e_priv *priv; |
| 433 | int ix; |
| 434 | int cpu; |
| 435 | }; |
| 436 | |
| 437 | enum mlx5e_traffic_types { |
| 438 | MLX5E_TT_IPV4_TCP, |
| 439 | MLX5E_TT_IPV6_TCP, |
| 440 | MLX5E_TT_IPV4_UDP, |
| 441 | MLX5E_TT_IPV6_UDP, |
| 442 | MLX5E_TT_IPV4_IPSEC_AH, |
| 443 | MLX5E_TT_IPV6_IPSEC_AH, |
| 444 | MLX5E_TT_IPV4_IPSEC_ESP, |
| 445 | MLX5E_TT_IPV6_IPSEC_ESP, |
| 446 | MLX5E_TT_IPV4, |
| 447 | MLX5E_TT_IPV6, |
| 448 | MLX5E_TT_ANY, |
| 449 | MLX5E_NUM_TT, |
| 450 | }; |
| 451 | |
| 452 | enum mlx5e_rqt_ix { |
| 453 | MLX5E_INDIRECTION_RQT, |
| 454 | MLX5E_SINGLE_RQ_RQT, |
| 455 | MLX5E_NUM_RQT, |
| 456 | }; |
| 457 | |
| 458 | struct mlx5e_eth_addr_info { |
| 459 | u8 addr[ETH_ALEN + 2]; |
| 460 | u32 tt_vec; |
| 461 | struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT]; |
| 462 | }; |
| 463 | |
| 464 | #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE) |
| 465 | |
| 466 | struct mlx5e_eth_addr_db { |
| 467 | struct hlist_head netdev_uc[MLX5E_ETH_ADDR_HASH_SIZE]; |
| 468 | struct hlist_head netdev_mc[MLX5E_ETH_ADDR_HASH_SIZE]; |
| 469 | struct mlx5e_eth_addr_info broadcast; |
| 470 | struct mlx5e_eth_addr_info allmulti; |
| 471 | struct mlx5e_eth_addr_info promisc; |
| 472 | bool broadcast_enabled; |
| 473 | bool allmulti_enabled; |
| 474 | bool promisc_enabled; |
| 475 | }; |
| 476 | |
| 477 | enum { |
| 478 | MLX5E_STATE_ASYNC_EVENTS_ENABLE, |
| 479 | MLX5E_STATE_OPENED, |
| 480 | MLX5E_STATE_DESTROYING, |
| 481 | }; |
| 482 | |
| 483 | struct mlx5e_vlan_db { |
| 484 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
| 485 | struct mlx5_flow_rule *active_vlans_rule[VLAN_N_VID]; |
| 486 | struct mlx5_flow_rule *untagged_rule; |
| 487 | struct mlx5_flow_rule *any_vlan_rule; |
| 488 | bool filter_disabled; |
| 489 | }; |
| 490 | |
| 491 | struct mlx5e_flow_table { |
| 492 | int num_groups; |
| 493 | struct mlx5_flow_table *t; |
| 494 | struct mlx5_flow_group **g; |
| 495 | }; |
| 496 | |
| 497 | struct mlx5e_flow_tables { |
| 498 | struct mlx5_flow_namespace *ns; |
| 499 | struct mlx5e_flow_table vlan; |
| 500 | struct mlx5e_flow_table main; |
| 501 | }; |
| 502 | |
| 503 | struct mlx5e_priv { |
| 504 | /* priv data path fields - start */ |
| 505 | int default_vlan_prio; |
| 506 | struct mlx5e_sq **txq_to_sq_map; |
| 507 | int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC]; |
| 508 | /* priv data path fields - end */ |
| 509 | |
| 510 | unsigned long state; |
| 511 | struct mutex state_lock; /* Protects Interface state */ |
| 512 | struct mlx5_uar cq_uar; |
| 513 | u32 pdn; |
| 514 | u32 tdn; |
| 515 | struct mlx5_core_mr mr; |
| 516 | struct mlx5e_rq drop_rq; |
| 517 | |
| 518 | struct mlx5e_channel **channel; |
| 519 | u32 tisn[MLX5E_MAX_NUM_TC]; |
| 520 | u32 rqtn[MLX5E_NUM_RQT]; |
| 521 | u32 tirn[MLX5E_NUM_TT]; |
| 522 | |
| 523 | struct mlx5e_flow_tables fts; |
| 524 | struct mlx5e_eth_addr_db eth_addr; |
| 525 | struct mlx5e_vlan_db vlan; |
| 526 | |
| 527 | struct mlx5e_params params; |
| 528 | spinlock_t async_events_spinlock; /* sync hw events */ |
| 529 | struct work_struct update_carrier_work; |
| 530 | struct work_struct set_rx_mode_work; |
| 531 | struct delayed_work update_stats_work; |
| 532 | |
| 533 | struct mlx5_core_dev *mdev; |
| 534 | struct net_device *netdev; |
| 535 | struct mlx5e_stats stats; |
| 536 | struct mlx5e_tstamp tstamp; |
| 537 | }; |
| 538 | |
| 539 | #define MLX5E_NET_IP_ALIGN 2 |
| 540 | |
| 541 | struct mlx5e_tx_wqe { |
| 542 | struct mlx5_wqe_ctrl_seg ctrl; |
| 543 | struct mlx5_wqe_eth_seg eth; |
| 544 | }; |
| 545 | |
| 546 | struct mlx5e_rx_wqe { |
| 547 | struct mlx5_wqe_srq_next_seg next; |
| 548 | struct mlx5_wqe_data_seg data; |
| 549 | }; |
| 550 | |
| 551 | enum mlx5e_link_mode { |
| 552 | MLX5E_1000BASE_CX_SGMII = 0, |
| 553 | MLX5E_1000BASE_KX = 1, |
| 554 | MLX5E_10GBASE_CX4 = 2, |
| 555 | MLX5E_10GBASE_KX4 = 3, |
| 556 | MLX5E_10GBASE_KR = 4, |
| 557 | MLX5E_20GBASE_KR2 = 5, |
| 558 | MLX5E_40GBASE_CR4 = 6, |
| 559 | MLX5E_40GBASE_KR4 = 7, |
| 560 | MLX5E_56GBASE_R4 = 8, |
| 561 | MLX5E_10GBASE_CR = 12, |
| 562 | MLX5E_10GBASE_SR = 13, |
| 563 | MLX5E_10GBASE_ER = 14, |
| 564 | MLX5E_40GBASE_SR4 = 15, |
| 565 | MLX5E_40GBASE_LR4 = 16, |
| 566 | MLX5E_100GBASE_CR4 = 20, |
| 567 | MLX5E_100GBASE_SR4 = 21, |
| 568 | MLX5E_100GBASE_KR4 = 22, |
| 569 | MLX5E_100GBASE_LR4 = 23, |
| 570 | MLX5E_100BASE_TX = 24, |
| 571 | MLX5E_100BASE_T = 25, |
| 572 | MLX5E_10GBASE_T = 26, |
| 573 | MLX5E_25GBASE_CR = 27, |
| 574 | MLX5E_25GBASE_KR = 28, |
| 575 | MLX5E_25GBASE_SR = 29, |
| 576 | MLX5E_50GBASE_CR2 = 30, |
| 577 | MLX5E_50GBASE_KR2 = 31, |
| 578 | MLX5E_LINK_MODES_NUMBER, |
| 579 | }; |
| 580 | |
| 581 | #define MLX5E_PROT_MASK(link_mode) (1 << link_mode) |
| 582 | |
| 583 | void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw); |
| 584 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, |
| 585 | void *accel_priv, select_queue_fallback_t fallback); |
| 586 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); |
| 587 | |
| 588 | void mlx5e_completion_event(struct mlx5_core_cq *mcq); |
| 589 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); |
| 590 | int mlx5e_napi_poll(struct napi_struct *napi, int budget); |
| 591 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq); |
| 592 | int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); |
| 593 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); |
| 594 | struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); |
| 595 | |
| 596 | void mlx5e_update_stats(struct mlx5e_priv *priv); |
| 597 | |
| 598 | int mlx5e_create_flow_tables(struct mlx5e_priv *priv); |
| 599 | void mlx5e_destroy_flow_tables(struct mlx5e_priv *priv); |
| 600 | void mlx5e_init_eth_addr(struct mlx5e_priv *priv); |
| 601 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
| 602 | |
| 603 | void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp, |
| 604 | struct skb_shared_hwtstamps *hwts); |
| 605 | void mlx5e_timestamp_init(struct mlx5e_priv *priv); |
| 606 | void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv); |
| 607 | int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr); |
| 608 | int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr); |
| 609 | |
| 610 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, |
| 611 | u16 vid); |
| 612 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, |
| 613 | u16 vid); |
| 614 | void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); |
| 615 | void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); |
| 616 | |
| 617 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix); |
| 618 | |
| 619 | int mlx5e_open_locked(struct net_device *netdev); |
| 620 | int mlx5e_close_locked(struct net_device *netdev); |
| 621 | |
| 622 | static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq, |
| 623 | struct mlx5e_tx_wqe *wqe, int bf_sz) |
| 624 | { |
| 625 | u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; |
| 626 | |
| 627 | /* ensure wqe is visible to device before updating doorbell record */ |
| 628 | dma_wmb(); |
| 629 | |
| 630 | *sq->wq.db = cpu_to_be32(sq->pc); |
| 631 | |
| 632 | /* ensure doorbell record is visible to device before ringing the |
| 633 | * doorbell |
| 634 | */ |
| 635 | wmb(); |
| 636 | |
| 637 | if (bf_sz) { |
| 638 | __iowrite64_copy(sq->uar_bf_map + ofst, &wqe->ctrl, bf_sz); |
| 639 | |
| 640 | /* flush the write-combining mapped buffer */ |
| 641 | wmb(); |
| 642 | |
| 643 | } else { |
| 644 | mlx5_write64((__be32 *)&wqe->ctrl, sq->uar_map + ofst, NULL); |
| 645 | } |
| 646 | |
| 647 | sq->bf_offset ^= sq->bf_buf_size; |
| 648 | } |
| 649 | |
| 650 | static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) |
| 651 | { |
| 652 | struct mlx5_core_cq *mcq; |
| 653 | |
| 654 | mcq = &cq->mcq; |
| 655 | mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc); |
| 656 | } |
| 657 | |
| 658 | static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) |
| 659 | { |
| 660 | return min_t(int, mdev->priv.eq_table.num_comp_vectors, |
| 661 | MLX5E_MAX_NUM_CHANNELS); |
| 662 | } |
| 663 | |
| 664 | extern const struct ethtool_ops mlx5e_ethtool_ops; |
| 665 | u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev); |