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Fix indentation in print_thread_info_1
[deliverable/binutils-gdb.git] / opcodes / rx-decode.opc
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1/* -*- c -*- */
2/* Copyright (C) 2012-2020 Free Software Foundation, Inc.
3 Contributed by Red Hat.
4 Written by DJ Delorie.
5
6 This file is part of the GNU opcodes library.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
22
23#include "sysdep.h"
24#include <stdio.h>
25#include <stdlib.h>
26#include <string.h>
27#include "ansidecl.h"
28#include "opcode/rx.h"
29#include "libiberty.h"
30
31#define RX_OPCODE_BIG_ENDIAN 0
32
33typedef struct
34{
35 RX_Opcode_Decoded * rx;
36 int (* getbyte)(void *);
37 void * ptr;
38 unsigned char * op;
39} LocalData;
40
41static int trace = 0;
42
43#define BSIZE 0
44#define WSIZE 1
45#define LSIZE 2
46#define DSIZE 3
47
48/* These are for when the upper bits are "don't care" or "undefined". */
49static int bwl[4] =
50{
51 RX_Byte,
52 RX_Word,
53 RX_Long,
54 RX_Bad_Size /* Bogus instructions can have a size field set to 3. */
55};
56
57static int sbwl[4] =
58{
59 RX_SByte,
60 RX_SWord,
61 RX_Long,
62 RX_Bad_Size /* Bogus instructions can have a size field set to 3. */
63};
64
65static int ubw[4] =
66{
67 RX_UByte,
68 RX_UWord,
69 RX_Bad_Size,/* Bogus instructions can have a size field set to 2. */
70 RX_Bad_Size /* Bogus instructions can have a size field set to 3. */
71};
72
73static int memex[4] =
74{
75 RX_SByte,
76 RX_SWord,
77 RX_Long,
78 RX_UWord
79};
80
81static int _ld[2] =
82{
83 RX_Long,
84 RX_Double
85};
86
87#define ID(x) rx->id = RXO_##x
88#define OP(n,t,r,a) (rx->op[n].type = t, \
89 rx->op[n].reg = r, \
90 rx->op[n].addend = a )
91#define OPs(n,t,r,a,s) (OP (n,t,r,a), \
92 rx->op[n].size = s )
93
94/* This is for the BWL and BW bitfields. */
95static int SCALE[] = { 1, 2, 4, 0 };
96/* This is for the prefix size enum. */
97static int PSCALE[] = { 4, 1, 1, 1, 2, 2, 2, 3, 4, 8 };
98
99#define GET_SCALE(_indx) ((unsigned)(_indx) < ARRAY_SIZE (SCALE) ? SCALE[(_indx)] : 0)
100#define GET_PSCALE(_indx) ((unsigned)(_indx) < ARRAY_SIZE (PSCALE) ? PSCALE[(_indx)] : 0)
101
102static int flagmap[] = {0, 1, 2, 3, 0, 0, 0, 0,
103 16, 17, 0, 0, 0, 0, 0, 0 };
104
105static int dsp3map[] = { 8, 9, 10, 3, 4, 5, 6, 7 };
106
107/*
108 *C a constant (immediate) c
109 *R A register
110 *I Register indirect, no offset
111 *Is Register indirect, with offset
112 *D standard displacement: type (r,[r],dsp8,dsp16 code), register, BWL code
113 *P standard displacement: type (r,[r]), reg, assumes UByte
114 *Pm memex displacement: type (r,[r]), reg, memex code
115 *cc condition code. */
116
117#define DC(c) OP (0, RX_Operand_Immediate, 0, c)
118#define DR(r) OP (0, RX_Operand_Register, r, 0)
119#define DI(r,a) OP (0, RX_Operand_Indirect, r, a)
120#define DIs(r,a,s) OP (0, RX_Operand_Indirect, r, (a) * GET_SCALE (s))
121#define DD(t,r,s) rx_disp (0, t, r, bwl[s], ld);
122#define DF(r) OP (0, RX_Operand_Flag, flagmap[r], 0)
123#define DCR(r) OP (0, RX_Operand_DoubleCReg, r, 0)
124#define DDR(r) OP (0, RX_Operand_DoubleReg, r, 0)
125#define DDRH(r) OP (0, RX_Operand_DoubleRegH, r, 0)
126#define DDRL(r) OP (0, RX_Operand_DoubleRegL, r, 0)
127#define DCND(r) OP (0, RX_Operand_DoubleCond, r, 0)
128
129#define SC(i) OP (1, RX_Operand_Immediate, 0, i)
130#define SR(r) OP (1, RX_Operand_Register, r, 0)
131#define SRR(r) OP (1, RX_Operand_TwoReg, r, 0)
132#define SI(r,a) OP (1, RX_Operand_Indirect, r, a)
133#define SIs(r,a,s) OP (1, RX_Operand_Indirect, r, (a) * GET_SCALE (s))
134#define SD(t,r,s) rx_disp (1, t, r, bwl[s], ld);
135#define SP(t,r) rx_disp (1, t, r, (t!=3) ? RX_UByte : RX_Long, ld); P(t, 1);
136#define SPm(t,r,m) rx_disp (1, t, r, memex[m], ld); rx->op[1].size = memex[m];
137#define Scc(cc) OP (1, RX_Operand_Condition, cc, 0)
138#define SCR(r) OP (1, RX_Operand_DoubleCReg, r, 0)
139#define SDR(r) OP (1, RX_Operand_DoubleReg, r, 0)
140#define SDRH(r) OP (1, RX_Operand_DoubleRegH, r, 0)
141#define SDRL(r) OP (1, RX_Operand_DoubleRegL, r, 0)
142
143#define S2C(i) OP (2, RX_Operand_Immediate, 0, i)
144#define S2R(r) OP (2, RX_Operand_Register, r, 0)
145#define S2I(r,a) OP (2, RX_Operand_Indirect, r, a)
146#define S2Is(r,a,s) OP (2, RX_Operand_Indirect, r, (a) * GET_SCALE (s))
147#define S2D(t,r,s) rx_disp (2, t, r, bwl[s], ld);
148#define S2P(t,r) rx_disp (2, t, r, (t!=3) ? RX_UByte : RX_Long, ld); P(t, 2);
149#define S2Pm(t,r,m) rx_disp (2, t, r, memex[m], ld); rx->op[2].size = memex[m];
150#define S2cc(cc) OP (2, RX_Operand_Condition, cc, 0)
151#define S2DR(r) OP (2, RX_Operand_DoubleReg, r, 0)
152#define S2CR(r) OP (2, RX_Operand_DoubleCReg, r, 0)
153
154#define SDD(t,r,s) rx_disp (1, t, r, bwl, ld);
155
156#define BWL(sz) rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = bwl[sz]
157#define sBWL(sz) rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = sbwl[sz]
158#define uBW(sz) rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = ubw[sz]
159#define P(t, n) rx->op[n].size = (t!=3) ? RX_UByte : RX_Long;
160#define DL(sz) rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = _ld[sz]
161
162#define F(f) store_flags(rx, f)
163
164#define AU ATTRIBUTE_UNUSED
165#define GETBYTE() (ld->op [ld->rx->n_bytes++] = ld->getbyte (ld->ptr))
166
167#define SYNTAX(x) rx->syntax = x
168
169#define UNSUPPORTED() \
170 rx->syntax = "*unknown*"
171
172#define IMM(sf) immediate (sf, 0, ld)
173#define IMMex(sf) immediate (sf, 1, ld)
174
175static int
176immediate (int sfield, int ex, LocalData * ld)
177{
178 unsigned long i = 0, j;
179
180 switch (sfield)
181 {
182#define B ((unsigned long) GETBYTE())
183 case 0:
184#if RX_OPCODE_BIG_ENDIAN
185 i = B;
186 if (ex && (i & 0x80))
187 i -= 0x100;
188 i <<= 24;
189 i |= B << 16;
190 i |= B << 8;
191 i |= B;
192#else
193 i = B;
194 i |= B << 8;
195 i |= B << 16;
196 j = B;
197 if (ex && (j & 0x80))
198 j -= 0x100;
199 i |= j << 24;
200#endif
201 break;
202 case 3:
203#if RX_OPCODE_BIG_ENDIAN
204 i = B << 16;
205 i |= B << 8;
206 i |= B;
207#else
208 i = B;
209 i |= B << 8;
210 i |= B << 16;
211#endif
212 if (ex && (i & 0x800000))
213 i -= 0x1000000;
214 break;
215 case 2:
216#if RX_OPCODE_BIG_ENDIAN
217 i |= B << 8;
218 i |= B;
219#else
220 i |= B;
221 i |= B << 8;
222#endif
223 if (ex && (i & 0x8000))
224 i -= 0x10000;
225 break;
226 case 1:
227 i |= B;
228 if (ex && (i & 0x80))
229 i -= 0x100;
230 break;
231 default:
232 abort();
233 }
234 return i;
235}
236
237static void
238rx_disp (int n, int type, int reg, unsigned int size, LocalData * ld)
239{
240 int disp;
241
242 ld->rx->op[n].reg = reg;
243 switch (type)
244 {
245 case 3:
246 ld->rx->op[n].type = RX_Operand_Register;
247 break;
248 case 0:
249 ld->rx->op[n].type = RX_Operand_Zero_Indirect;
250 ld->rx->op[n].addend = 0;
251 break;
252 case 1:
253 ld->rx->op[n].type = RX_Operand_Indirect;
254 disp = GETBYTE ();
255 ld->rx->op[n].addend = disp * GET_PSCALE (size);
256 break;
257 case 2:
258 ld->rx->op[n].type = RX_Operand_Indirect;
259 disp = GETBYTE ();
260#if RX_OPCODE_BIG_ENDIAN
261 disp = disp * 256 + GETBYTE ();
262#else
263 disp = disp + GETBYTE () * 256;
264#endif
265 ld->rx->op[n].addend = disp * GET_PSCALE (size);
266 break;
267 default:
268 abort ();
269 }
270}
271
272#define xO 8
273#define xS 4
274#define xZ 2
275#define xC 1
276
277#define F_____
278#define F___ZC rx->flags_0 = rx->flags_s = xZ|xC;
279#define F__SZ_ rx->flags_0 = rx->flags_s = xS|xZ;
280#define F__SZC rx->flags_0 = rx->flags_s = xS|xZ|xC;
281#define F_0SZC rx->flags_0 = xO|xS|xZ|xC; rx->flags_s = xS|xZ|xC;
282#define F_O___ rx->flags_0 = rx->flags_s = xO;
283#define F_OS__ rx->flags_0 = rx->flags_s = xO|xS;
284#define F_OSZ_ rx->flags_0 = rx->flags_s = xO|xS|xZ;
285#define F_OSZC rx->flags_0 = rx->flags_s = xO|xS|xZ|xC;
286
287int
288rx_decode_opcode (unsigned long pc AU,
289 RX_Opcode_Decoded * rx,
290 int (* getbyte)(void *),
291 void * ptr)
292{
293 LocalData lds, * ld = &lds;
294 unsigned char op[20] = {0};
295
296 lds.rx = rx;
297 lds.getbyte = getbyte;
298 lds.ptr = ptr;
299 lds.op = op;
300
301 memset (rx, 0, sizeof (*rx));
302 BWL(LSIZE);
303
304/** VARY sz 00 01 10 */
305
306/*----------------------------------------------------------------------*/
307/* MOV */
308
309/** 0111 0101 0100 rdst mov%s #%1, %0 */
310 ID(mov); DR(rdst); SC(IMM (1)); F_____;
311
312/** 1111 10sd rdst im sz mov%s #%1, %0 */
313 ID(mov); DD(sd, rdst, sz);
314 if ((im == 1 && sz == 0)
315 || (im == 2 && sz == 1)
316 || (im == 0 && sz == 2))
317 {
318 BWL (sz);
319 SC(IMM(im));
320 }
321 else
322 {
323 sBWL (sz);
324 SC(IMMex(im));
325 }
326 F_____;
327
328/** 0110 0110 immm rdst mov%s #%1, %0 */
329 ID(mov); DR(rdst); SC(immm); F_____;
330
331/** 0011 11sz d dst sppp mov%s #%1, %0 */
332 ID(mov); sBWL (sz); DIs(dst, d*16+sppp, sz); SC(IMM(1)); F_____;
333
334/** 11sz sd ss rsrc rdst mov%s %1, %0 */
335 if (sd == 3 && ss == 3 && sz == 2 && rsrc == 0 && rdst == 0)
336 {
337 ID(nop2);
338 SYNTAX ("nop\t; mov.l\tr0, r0");
339 }
340 else
341 {
342 ID(mov); sBWL(sz); F_____;
343 if ((ss == 3) && (sd != 3))
344 {
345 SD(ss, rdst, sz); DD(sd, rsrc, sz);
346 }
347 else
348 {
349 SD(ss, rsrc, sz); DD(sd, rdst, sz);
350 }
351 }
352
353/** 10sz 1dsp a src b dst mov%s %1, %0 */
354 ID(mov); sBWL(sz); DR(dst); SIs(src, dsp*4+a*2+b, sz); F_____;
355
356/** 10sz 0dsp a dst b src mov%s %1, %0 */
357 ID(mov); sBWL(sz); DIs(dst, dsp*4+a*2+b, sz); SR(src); F_____;
358
359/** 1111 1110 01sz isrc bsrc rdst mov%s [%1, %2], %0 */
360 ID(movbi); sBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____;
361
362/** 1111 1110 00sz isrc bsrc rdst mov%s %0, [%1, %2] */
363 ID(movbir); sBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____;
364
365/** 1111 1110 11sz isrc bsrc rdst movu%s [%1, %2], %0 */
366 ID(movbi); uBW(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____;
367
368/** 1111 1101 0010 0p sz rdst rsrc mov%s %1, %0 */
369 ID(mov); sBWL (sz); SR(rsrc); F_____;
370 OP(0, p ? RX_Operand_Predec : RX_Operand_Postinc, rdst, 0);
371
372/** 1111 1101 0010 1p sz rsrc rdst mov%s %1, %0 */
373 ID(mov); sBWL (sz); DR(rdst); F_____;
374 OP(1, p ? RX_Operand_Predec : RX_Operand_Postinc, rsrc, 0);
375
376/** 1011 w dsp a src b dst movu%s %1, %0 */
377 ID(mov); uBW(w); DR(dst); SIs(src, dsp*4+a*2+b, w); F_____;
378
379/** 0101 1 s ss rsrc rdst movu%s %1, %0 */
380 ID(mov); uBW(s); SD(ss, rsrc, s); DR(rdst); F_____;
381
382/** 1111 1101 0011 1p sz rsrc rdst movu%s %1, %0 */
383 ID(mov); uBW (sz); DR(rdst); F_____;
384 OP(1, p ? RX_Operand_Predec : RX_Operand_Postinc, rsrc, 0);
385
386/*----------------------------------------------------------------------*/
387/* PUSH/POP */
388
389/** 0110 1111 dsta dstb popm %1-%2 */
390 ID(popm); SR(dsta); S2R(dstb); F_____;
391
392/** 0110 1110 dsta dstb pushm %1-%2 */
393 ID(pushm); SR(dsta); S2R(dstb); F_____;
394
395/** 0111 1110 1011 rdst pop %0 */
396 ID(mov); OP(1, RX_Operand_Postinc, 0, 0); DR(rdst); F_____;
397
398/** 0111 1110 10sz rsrc push%s %1 */
399 ID(mov); BWL(sz); OP(0, RX_Operand_Predec, 0, 0); SR(rsrc); F_____;
400
401/** 1111 01ss rsrc 10sz push%s %1 */
402 ID(mov); BWL(sz); OP(0, RX_Operand_Predec, 0, 0); SD(ss, rsrc, sz); F_____;
403
404/*----------------------------------------------------------------------*/
405/* XCHG */
406
407/** 1111 1100 0100 00ss rsrc rdst xchg %1%S1, %0 */
408 ID(xchg); DR(rdst); SP(ss, rsrc);
409
410/** 0000 0110 mx10 00ss 0001 0000 rsrc rdst xchg %1%S1, %0 */
411 ID(xchg); DR(rdst); SPm(ss, rsrc, mx);
412
413/*----------------------------------------------------------------------*/
414/* STZ/STNZ */
415
416/** 1111 1101 0111 im00 1110rdst stz #%1, %0 */
417 ID(stcc); SC(IMMex(im)); DR(rdst); S2cc(RXC_z);
418
419/** 1111 1101 0111 im00 1111rdst stnz #%1, %0 */
420 ID(stcc); SC(IMMex(im)); DR(rdst); S2cc(RXC_nz);
421
422/*----------------------------------------------------------------------*/
423/* RTSD */
424
425/** 0110 0111 rtsd #%1 */
426 ID(rtsd); SC(IMM(1) * 4);
427
428/** 0011 1111 rega regb rtsd #%1, %2-%0 */
429 ID(rtsd); SC(IMM(1) * 4); S2R(rega); DR(regb);
430
431/*----------------------------------------------------------------------*/
432/* AND */
433
434/** 0110 0100 immm rdst and #%1, %0 */
435 ID(and); SC(immm); DR(rdst); F__SZ_;
436
437/** 0111 01im 0010 rdst and #%1, %0 */
438 ID(and); SC(IMMex(im)); DR(rdst); F__SZ_;
439
440/** 0101 00ss rsrc rdst and %1%S1, %0 */
441 ID(and); SP(ss, rsrc); DR(rdst); F__SZ_;
442
443/** 0000 0110 mx01 00ss rsrc rdst and %1%S1, %0 */
444 ID(and); SPm(ss, rsrc, mx); DR(rdst); F__SZ_;
445
446/** 1111 1111 0100 rdst srca srcb and %2, %1, %0 */
447 ID(and); DR(rdst); SR(srcb); S2R(srca); F__SZ_;
448
449/*----------------------------------------------------------------------*/
450/* OR */
451
452/** 0110 0101 immm rdst or #%1, %0 */
453 ID(or); SC(immm); DR(rdst); F__SZ_;
454
455/** 0111 01im 0011 rdst or #%1, %0 */
456 ID(or); SC(IMMex(im)); DR(rdst); F__SZ_;
457
458/** 0101 01ss rsrc rdst or %1%S1, %0 */
459 ID(or); SP(ss, rsrc); DR(rdst); F__SZ_;
460
461/** 0000 0110 mx01 01ss rsrc rdst or %1%S1, %0 */
462 ID(or); SPm(ss, rsrc, mx); DR(rdst); F__SZ_;
463
464/** 1111 1111 0101 rdst srca srcb or %2, %1, %0 */
465 ID(or); DR(rdst); SR(srcb); S2R(srca); F__SZ_;
466
467/*----------------------------------------------------------------------*/
468/* XOR */
469
470/** 1111 1101 0111 im00 1101rdst xor #%1, %0 */
471 ID(xor); SC(IMMex(im)); DR(rdst); F__SZ_;
472
473/** 1111 1100 0011 01ss rsrc rdst xor %1%S1, %0 */
474 ID(xor); SP(ss, rsrc); DR(rdst); F__SZ_;
475
476/** 0000 0110 mx10 00ss 0000 1101 rsrc rdst xor %1%S1, %0 */
477 ID(xor); SPm(ss, rsrc, mx); DR(rdst); F__SZ_;
478
479/*----------------------------------------------------------------------*/
480/* NOT */
481
482/** 0111 1110 0000 rdst not %0 */
483 ID(xor); DR(rdst); SR(rdst); S2C(~0); F__SZ_;
484
485/** 1111 1100 0011 1011 rsrc rdst not %1, %0 */
486 ID(xor); DR(rdst); SR(rsrc); S2C(~0); F__SZ_;
487
488/*----------------------------------------------------------------------*/
489/* TST */
490
491/** 1111 1101 0111 im00 1100rdst tst #%1, %2 */
492 ID(and); SC(IMMex(im)); S2R(rdst); F__SZ_;
493
494/** 1111 1100 0011 00ss rsrc rdst tst %1%S1, %2 */
495 ID(and); SP(ss, rsrc); S2R(rdst); F__SZ_;
496
497/** 0000 0110 mx10 00ss 0000 1100 rsrc rdst tst %1%S1, %2 */
498 ID(and); SPm(ss, rsrc, mx); S2R(rdst); F__SZ_;
499
500/*----------------------------------------------------------------------*/
501/* NEG */
502
503/** 0111 1110 0001 rdst neg %0 */
504 ID(sub); DR(rdst); SC(0); S2R(rdst); F_OSZC;
505
506/** 1111 1100 0000 0111 rsrc rdst neg %2, %0 */
507 ID(sub); DR(rdst); SC(0); S2R(rsrc); F_OSZC;
508
509/*----------------------------------------------------------------------*/
510/* ADC */
511
512/** 1111 1101 0111 im00 0010rdst adc #%1, %0 */
513 ID(adc); SC(IMMex(im)); DR(rdst); F_OSZC;
514
515/** 1111 1100 0000 1011 rsrc rdst adc %1, %0 */
516 ID(adc); SR(rsrc); DR(rdst); F_OSZC;
517
518/** 0000 0110 1010 00ss 0000 0010 rsrc rdst adc %1%S1, %0 */
519 ID(adc); SPm(ss, rsrc, 2); DR(rdst); F_OSZC;
520
521/*----------------------------------------------------------------------*/
522/* ADD */
523
524/** 0110 0010 immm rdst add #%1, %0 */
525 ID(add); SC(immm); DR(rdst); F_OSZC;
526
527/** 0100 10ss rsrc rdst add %1%S1, %0 */
528 ID(add); SP(ss, rsrc); DR(rdst); F_OSZC;
529
530/** 0000 0110 mx00 10ss rsrc rdst add %1%S1, %0 */
531 ID(add); SPm(ss, rsrc, mx); DR(rdst); F_OSZC;
532
533/** 0111 00im rsrc rdst add #%1, %2, %0 */
534 ID(add); SC(IMMex(im)); S2R(rsrc); DR(rdst); F_OSZC;
535
536/** 1111 1111 0010 rdst srca srcb add %2, %1, %0 */
537 ID(add); DR(rdst); SR(srcb); S2R(srca); F_OSZC;
538
539/*----------------------------------------------------------------------*/
540/* CMP */
541
542/** 0110 0001 immm rdst cmp #%2, %1 */
543 ID(sub); S2C(immm); SR(rdst); F_OSZC;
544
545/** 0111 01im 0000 rsrc cmp #%2, %1%S1 */
546 ID(sub); SR(rsrc); S2C(IMMex(im)); F_OSZC;
547
548/** 0111 0101 0101 rsrc cmp #%2, %1 */
549 ID(sub); SR(rsrc); S2C(IMM(1)); F_OSZC;
550
551/** 0100 01ss rsrc rdst cmp %2%S2, %1 */
552 ID(sub); S2P(ss, rsrc); SR(rdst); F_OSZC;
553
554/** 0000 0110 mx00 01ss rsrc rdst cmp %2%S2, %1 */
555 ID(sub); S2Pm(ss, rsrc, mx); SR(rdst); F_OSZC;
556
557/*----------------------------------------------------------------------*/
558/* SUB */
559
560/** 0110 0000 immm rdst sub #%2, %0 */
561 ID(sub); S2C(immm); SR(rdst); DR(rdst); F_OSZC;
562
563/** 0100 00ss rsrc rdst sub %2%S2, %1 */
564 ID(sub); S2P(ss, rsrc); SR(rdst); DR(rdst); F_OSZC;
565
566/** 0000 0110 mx00 00ss rsrc rdst sub %2%S2, %1 */
567 ID(sub); S2Pm(ss, rsrc, mx); SR(rdst); DR(rdst); F_OSZC;
568
569/** 1111 1111 0000 rdst srca srcb sub %2, %1, %0 */
570 ID(sub); DR(rdst); SR(srcb); S2R(srca); F_OSZC;
571
572/*----------------------------------------------------------------------*/
573/* SBB */
574
575/** 1111 1100 0000 0011 rsrc rdst sbb %1, %0 */
576 ID(sbb); SR (rsrc); DR(rdst); F_OSZC;
577
578 /* FIXME: only supports .L */
579/** 0000 0110 mx10 00sp 0000 0000 rsrc rdst sbb %1%S1, %0 */
580 ID(sbb); SPm(sp, rsrc, mx); DR(rdst); F_OSZC;
581
582/*----------------------------------------------------------------------*/
583/* ABS */
584
585/** 0111 1110 0010 rdst abs %0 */
586 ID(abs); DR(rdst); SR(rdst); F_OSZ_;
587
588/** 1111 1100 0000 1111 rsrc rdst abs %1, %0 */
589 ID(abs); DR(rdst); SR(rsrc); F_OSZ_;
590
591/*----------------------------------------------------------------------*/
592/* MAX */
593
594/** 1111 1101 0111 im00 0100rdst max #%1, %0 */
595 int val = IMMex (im);
596 if (im == 0 && (unsigned) val == 0x80000000 && rdst == 0)
597 {
598 ID (nop7);
599 SYNTAX("nop\t; max\t#0x80000000, r0");
600 }
601 else
602 {
603 ID(max);
604 }
605 DR(rdst); SC(val);
606
607/** 1111 1100 0001 00ss rsrc rdst max %1%S1, %0 */
608 if (ss == 3 && rsrc == 0 && rdst == 0)
609 {
610 ID(nop3);
611 SYNTAX("nop\t; max\tr0, r0");
612 }
613 else
614 {
615 ID(max); SP(ss, rsrc); DR(rdst);
616 }
617
618/** 0000 0110 mx10 00ss 0000 0100 rsrc rdst max %1%S1, %0 */
619 ID(max); SPm(ss, rsrc, mx); DR(rdst);
620
621/*----------------------------------------------------------------------*/
622/* MIN */
623
624/** 1111 1101 0111 im00 0101rdst min #%1, %0 */
625 ID(min); DR(rdst); SC(IMMex(im));
626
627/** 1111 1100 0001 01ss rsrc rdst min %1%S1, %0 */
628 ID(min); SP(ss, rsrc); DR(rdst);
629
630/** 0000 0110 mx10 00ss 0000 0101 rsrc rdst min %1%S1, %0 */
631 ID(min); SPm(ss, rsrc, mx); DR(rdst);
632
633/*----------------------------------------------------------------------*/
634/* MUL */
635
636/** 0110 0011 immm rdst mul #%1, %0 */
637 if (immm == 1 && rdst == 0)
638 {
639 ID(nop2);
640 SYNTAX ("nop\t; mul\t#1, r0");
641 }
642 else
643 {
644 ID(mul);
645 }
646 DR(rdst); SC(immm); F_____;
647
648/** 0111 01im 0001rdst mul #%1, %0 */
649 int val = IMMex(im);
650 if (val == 1 && rdst == 0)
651 {
652 SYNTAX("nop\t; mul\t#1, r0");
653 switch (im)
654 {
655 case 2: ID(nop4); break;
656 case 3: ID(nop5); break;
657 case 0: ID(nop6); break;
658 default:
659 ID(mul);
660 SYNTAX("mul #%1, %0");
661 break;
662 }
663 }
664 else
665 {
666 ID(mul);
667 }
668 DR(rdst); SC(val); F_____;
669
670/** 0100 11ss rsrc rdst mul %1%S1, %0 */
671 ID(mul); SP(ss, rsrc); DR(rdst); F_____;
672
673/** 0000 0110 mx00 11ss rsrc rdst mul %1%S1, %0 */
674 ID(mul); SPm(ss, rsrc, mx); DR(rdst); F_____;
675
676/** 1111 1111 0011 rdst srca srcb mul %2, %1, %0 */
677 ID(mul); DR(rdst); SR(srcb); S2R(srca); F_____;
678
679/*----------------------------------------------------------------------*/
680/* EMUL */
681
682/** 1111 1101 0111 im00 0110rdst emul #%1, %0 */
683 ID(emul); DR(rdst); SC(IMMex(im));
684
685/** 1111 1100 0001 10ss rsrc rdst emul %1%S1, %0 */
686 ID(emul); SP(ss, rsrc); DR(rdst);
687
688/** 0000 0110 mx10 00ss 0000 0110 rsrc rdst emul %1%S1, %0 */
689 ID(emul); SPm(ss, rsrc, mx); DR(rdst);
690
691/*----------------------------------------------------------------------*/
692/* EMULU */
693
694/** 1111 1101 0111 im00 0111rdst emulu #%1, %0 */
695 ID(emulu); DR(rdst); SC(IMMex(im));
696
697/** 1111 1100 0001 11ss rsrc rdst emulu %1%S1, %0 */
698 ID(emulu); SP(ss, rsrc); DR(rdst);
699
700/** 0000 0110 mx10 00ss 0000 0111 rsrc rdst emulu %1%S1, %0 */
701 ID(emulu); SPm(ss, rsrc, mx); DR(rdst);
702
703/*----------------------------------------------------------------------*/
704/* DIV */
705
706/** 1111 1101 0111 im00 1000rdst div #%1, %0 */
707 ID(div); DR(rdst); SC(IMMex(im)); F_O___;
708
709/** 1111 1100 0010 00ss rsrc rdst div %1%S1, %0 */
710 ID(div); SP(ss, rsrc); DR(rdst); F_O___;
711
712/** 0000 0110 mx10 00ss 0000 1000 rsrc rdst div %1%S1, %0 */
713 ID(div); SPm(ss, rsrc, mx); DR(rdst); F_O___;
714
715/*----------------------------------------------------------------------*/
716/* DIVU */
717
718/** 1111 1101 0111 im00 1001rdst divu #%1, %0 */
719 ID(divu); DR(rdst); SC(IMMex(im)); F_O___;
720
721/** 1111 1100 0010 01ss rsrc rdst divu %1%S1, %0 */
722 ID(divu); SP(ss, rsrc); DR(rdst); F_O___;
723
724/** 0000 0110 mx10 00ss 0000 1001 rsrc rdst divu %1%S1, %0 */
725 ID(divu); SPm(ss, rsrc, mx); DR(rdst); F_O___;
726
727/*----------------------------------------------------------------------*/
728/* SHIFT */
729
730/** 0110 110i mmmm rdst shll #%2, %0 */
731 ID(shll); S2C(i*16+mmmm); SR(rdst); DR(rdst); F_OSZC;
732
733/** 1111 1101 0110 0010 rsrc rdst shll %2, %0 */
734 ID(shll); S2R(rsrc); SR(rdst); DR(rdst); F_OSZC;
735
736/** 1111 1101 110immmm rsrc rdst shll #%2, %1, %0 */
737 ID(shll); S2C(immmm); SR(rsrc); DR(rdst); F_OSZC;
738
739
740/** 0110 101i mmmm rdst shar #%2, %0 */
741 ID(shar); S2C(i*16+mmmm); SR(rdst); DR(rdst); F_0SZC;
742
743/** 1111 1101 0110 0001 rsrc rdst shar %2, %0 */
744 ID(shar); S2R(rsrc); SR(rdst); DR(rdst); F_0SZC;
745
746/** 1111 1101 101immmm rsrc rdst shar #%2, %1, %0 */
747 ID(shar); S2C(immmm); SR(rsrc); DR(rdst); F_0SZC;
748
749
750/** 0110 100i mmmm rdst shlr #%2, %0 */
751 ID(shlr); S2C(i*16+mmmm); SR(rdst); DR(rdst); F__SZC;
752
753/** 1111 1101 0110 0000 rsrc rdst shlr %2, %0 */
754 ID(shlr); S2R(rsrc); SR(rdst); DR(rdst); F__SZC;
755
756/** 1111 1101 100immmm rsrc rdst shlr #%2, %1, %0 */
757 ID(shlr); S2C(immmm); SR(rsrc); DR(rdst); F__SZC;
758
759/*----------------------------------------------------------------------*/
760/* ROTATE */
761
762/** 0111 1110 0101 rdst rolc %0 */
763 ID(rolc); DR(rdst); F__SZC;
764
765/** 0111 1110 0100 rdst rorc %0 */
766 ID(rorc); DR(rdst); F__SZC;
767
768/** 1111 1101 0110 111i mmmm rdst rotl #%1, %0 */
769 ID(rotl); SC(i*16+mmmm); DR(rdst); F__SZC;
770
771/** 1111 1101 0110 0110 rsrc rdst rotl %1, %0 */
772 ID(rotl); SR(rsrc); DR(rdst); F__SZC;
773
774/** 1111 1101 0110 110i mmmm rdst rotr #%1, %0 */
775 ID(rotr); SC(i*16+mmmm); DR(rdst); F__SZC;
776
777/** 1111 1101 0110 0100 rsrc rdst rotr %1, %0 */
778 ID(rotr); SR(rsrc); DR(rdst); F__SZC;
779
780/** 1111 1101 0110 0101 rsrc rdst revw %1, %0 */
781 ID(revw); SR(rsrc); DR(rdst);
782
783/** 1111 1101 0110 0111 rsrc rdst revl %1, %0 */
784 ID(revl); SR(rsrc); DR(rdst);
785
786/*----------------------------------------------------------------------*/
787/* BRANCH */
788
789/** 0001 n dsp b%1.s %a0 */
790 ID(branch); Scc(n); DC(pc + dsp3map[dsp]);
791
792/** 0010 cond b%1.b %a0 */
793 ID(branch); Scc(cond); DC(pc + IMMex (1));
794
795/** 0011 101c b%1.w %a0 */
796 ID(branch); Scc(c); DC(pc + IMMex (2));
797
798
799/** 0000 1dsp bra.s %a0 */
800 ID(branch); DC(pc + dsp3map[dsp]);
801
802/** 0010 1110 bra.b %a0 */
803 ID(branch); DC(pc + IMMex(1));
804
805/** 0011 1000 bra.w %a0 */
806 ID(branch); DC(pc + IMMex(2));
807
808/** 0000 0100 bra.a %a0 */
809 ID(branch); DC(pc + IMMex(3));
810
811/** 0111 1111 0100 rsrc bra.l %0 */
812 ID(branchrel); DR(rsrc);
813
814
815/** 0111 1111 0000 rsrc jmp %0 */
816 ID(branch); DR(rsrc);
817
818/** 0111 1111 0001 rsrc jsr %0 */
819 ID(jsr); DR(rsrc);
820
821/** 0011 1001 bsr.w %a0 */
822 ID(jsr); DC(pc + IMMex(2));
823
824/** 0000 0101 bsr.a %a0 */
825 ID(jsr); DC(pc + IMMex(3));
826
827/** 0111 1111 0101 rsrc bsr.l %0 */
828 ID(jsrrel); DR(rsrc);
829
830/** 0000 0010 rts */
831 ID(rts);
832
833/*----------------------------------------------------------------------*/
834/* NOP */
835
836/** 0000 0011 nop */
837 ID(nop);
838
839/*----------------------------------------------------------------------*/
840/* STRING FUNCTIONS */
841
842/** 0111 1111 1000 0011 scmpu */
843 ID(scmpu); F___ZC;
844
845/** 0111 1111 1000 0111 smovu */
846 ID(smovu);
847
848/** 0111 1111 1000 1011 smovb */
849 ID(smovb);
850
851/** 0111 1111 1000 00sz suntil%s */
852 ID(suntil); BWL(sz); F___ZC;
853
854/** 0111 1111 1000 01sz swhile%s */
855 ID(swhile); BWL(sz); F___ZC;
856
857/** 0111 1111 1000 1111 smovf */
858 ID(smovf);
859
860/** 0111 1111 1000 10sz sstr%s */
861 ID(sstr); BWL(sz);
862
863/*----------------------------------------------------------------------*/
864/* RMPA */
865
866/** 0111 1111 1000 11sz rmpa%s */
867 ID(rmpa); BWL(sz); F_OS__;
868
869/*----------------------------------------------------------------------*/
870/* HI/LO stuff */
871
872/** 1111 1101 0000 a000 srca srcb mulhi %1, %2, %0 */
873 ID(mulhi); DR(a+32); SR(srca); S2R(srcb); F_____;
874
875/** 1111 1101 0000 a001 srca srcb mullo %1, %2, %0 */
876 ID(mullo); DR(a+32); SR(srca); S2R(srcb); F_____;
877
878/** 1111 1101 0000 a100 srca srcb machi %1, %2, %0 */
879 ID(machi); DR(a+32); SR(srca); S2R(srcb); F_____;
880
881/** 1111 1101 0000 a101 srca srcb maclo %1, %2, %0 */
882 ID(maclo); DR(a+32); SR(srca); S2R(srcb); F_____;
883
884/** 1111 1101 0001 0111 a000 rsrc mvtachi %1, %0 */
885 ID(mvtachi); DR(a+32); SR(rsrc); F_____;
886
887/** 1111 1101 0001 0111 a001 rsrc mvtaclo %1, %0 */
888 ID(mvtaclo); DR(a+32); SR(rsrc); F_____;
889
890/** 1111 1101 0001 111i a m00 rdst mvfachi #%2, %1, %0 */
891 ID(mvfachi); S2C(((i^1)<<1)|m); SR(a+32); DR(rdst); F_____;
892
893/** 1111 1101 0001 111i a m10 rdst mvfacmi #%2, %1, %0 */
894 ID(mvfacmi); S2C(((i^1)<<1)|m); SR(a+32); DR(rdst); F_____;
895
896/** 1111 1101 0001 111i a m01 rdst mvfaclo #%2, %1, %0 */
897 ID(mvfaclo); S2C(((i^1)<<1)|m); SR(a+32); DR(rdst); F_____;
898
899/** 1111 1101 0001 1000 a00i 0000 racw #%1, %0 */
900 ID(racw); SC(i+1); DR(a+32); F_____;
901
902/*----------------------------------------------------------------------*/
903/* SAT */
904
905/** 0111 1110 0011 rdst sat %0 */
906 ID(sat); DR (rdst);
907
908/** 0111 1111 1001 0011 satr */
909 ID(satr);
910
911/*----------------------------------------------------------------------*/
912/* FLOAT */
913
914/** 1111 1101 0111 0010 0010 rdst fadd #%1, %0 */
915 ID(fadd); DR(rdst); SC(IMM(0)); F__SZ_;
916
917/** 1111 1100 1000 10sd rsrc rdst fadd %1%S1, %0 */
918 ID(fadd); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
919
920/** 1111 1101 0111 0010 0001 rdst fcmp #%1, %0 */
921 ID(fcmp); DR(rdst); SC(IMM(0)); F_OSZ_;
922
923/** 1111 1100 1000 01sd rsrc rdst fcmp %1%S1, %0 */
924 ID(fcmp); DR(rdst); SD(sd, rsrc, LSIZE); F_OSZ_;
925
926/** 1111 1101 0111 0010 0000 rdst fsub #%1, %0 */
927 ID(fsub); DR(rdst); SC(IMM(0)); F__SZ_;
928
929/** 1111 1100 1000 00sd rsrc rdst fsub %1%S1, %0 */
930 ID(fsub); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
931
932/** 1111 1100 1001 01sd rsrc rdst ftoi %1%S1, %0 */
933 ID(ftoi); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
934
935/** 1111 1101 0111 0010 0011 rdst fmul #%1, %0 */
936 ID(fmul); DR(rdst); SC(IMM(0)); F__SZ_;
937
938/** 1111 1100 1000 11sd rsrc rdst fmul %1%S1, %0 */
939 ID(fmul); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
940
941/** 1111 1101 0111 0010 0100 rdst fdiv #%1, %0 */
942 ID(fdiv); DR(rdst); SC(IMM(0)); F__SZ_;
943
944/** 1111 1100 1001 00sd rsrc rdst fdiv %1%S1, %0 */
945 ID(fdiv); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
946
947/** 1111 1100 1001 10sd rsrc rdst round %1%S1, %0 */
948 ID(round); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
949
950/** 1111 1100 0100 01sd rsrc rdst itof %1%S1, %0 */
951 ID(itof); DR (rdst); SP(sd, rsrc); F__SZ_;
952
953/** 0000 0110 mx10 00sd 0001 0001 rsrc rdst itof %1%S1, %0 */
954 ID(itof); DR (rdst); SPm(sd, rsrc, mx); F__SZ_;
955
956/*----------------------------------------------------------------------*/
957/* BIT OPS */
958
959/** 1111 00sd rdst 0bit bset #%1, %0%S0 */
960 ID(bset); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE); F_____;
961
962/** 1111 1100 0110 00sd rdst rsrc bset %1, %0%S0 */
963 ID(bset); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE); F_____;
964 if (sd == 3) /* bset reg,reg */
965 BWL(LSIZE);
966
967/** 0111 100b ittt rdst bset #%1, %0 */
968 ID(bset); BWL(LSIZE); SC(b*16+ittt); DR(rdst); F_____;
969
970
971/** 1111 00sd rdst 1bit bclr #%1, %0%S0 */
972 ID(bclr); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE); F_____;
973
974/** 1111 1100 0110 01sd rdst rsrc bclr %1, %0%S0 */
975 ID(bclr); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE); F_____;
976 if (sd == 3) /* bset reg,reg */
977 BWL(LSIZE);
978
979/** 0111 101b ittt rdst bclr #%1, %0 */
980 ID(bclr); BWL(LSIZE); SC(b*16+ittt); DR(rdst); F_____;
981
982
983/** 1111 01sd rdst 0bit btst #%2, %1%S1 */
984 ID(btst); BWL(BSIZE); S2C(bit); SD(sd, rdst, BSIZE); F___ZC;
985
986/** 1111 1100 0110 10sd rdst rsrc btst %2, %1%S1 */
987 ID(btst); BWL(BSIZE); S2R(rsrc); SD(sd, rdst, BSIZE); F___ZC;
988 if (sd == 3) /* bset reg,reg */
989 BWL(LSIZE);
990
991/** 0111 110b ittt rdst btst #%2, %1 */
992 ID(btst); BWL(LSIZE); S2C(b*16+ittt); SR(rdst); F___ZC;
993
994
995/** 1111 1100 111bit sd rdst 1111 bnot #%1, %0%S0 */
996 ID(bnot); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE);
997
998/** 1111 1100 0110 11sd rdst rsrc bnot %1, %0%S0 */
999 ID(bnot); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE);
1000 if (sd == 3) /* bset reg,reg */
1001 BWL(LSIZE);
1002
1003/** 1111 1101 111bittt 1111 rdst bnot #%1, %0 */
1004 ID(bnot); BWL(LSIZE); SC(bittt); DR(rdst);
1005
1006
1007/** 1111 1100 111bit sd rdst cond bm%2 #%1, %0%S0 */
1008 ID(bmcc); BWL(BSIZE); S2cc(cond); SC(bit); DD(sd, rdst, BSIZE);
1009
1010/** 1111 1101 111 bittt cond rdst bm%2 #%1, %0%S0 */
1011 ID(bmcc); BWL(LSIZE); S2cc(cond); SC(bittt); DR(rdst);
1012
1013/*----------------------------------------------------------------------*/
1014/* CONTROL REGISTERS */
1015
1016/** 0111 1111 1011 rdst clrpsw %0 */
1017 ID(clrpsw); DF(rdst);
1018
1019/** 0111 1111 1010 rdst setpsw %0 */
1020 ID(setpsw); DF(rdst);
1021
1022/** 0111 0101 0111 0000 0000 immm mvtipl #%1 */
1023 ID(mvtipl); SC(immm);
1024
1025/** 0111 1110 111 crdst popc %0 */
1026 ID(mov); OP(1, RX_Operand_Postinc, 0, 0); DR(crdst + 16);
1027
1028/** 0111 1110 110 crsrc pushc %1 */
1029 ID(mov); OP(0, RX_Operand_Predec, 0, 0); SR(crsrc + 16);
1030
1031/** 1111 1101 0111 im11 000crdst mvtc #%1, %0 */
1032 ID(mov); SC(IMMex(im)); DR(crdst + 16);
1033
1034/** 1111 1101 0110 100c rsrc rdst mvtc %1, %0 */
1035 ID(mov); SR(rsrc); DR(c*16+rdst + 16);
1036
1037/** 1111 1101 0110 101s rsrc rdst mvfc %1, %0 */
1038 ID(mov); SR((s*16+rsrc) + 16); DR(rdst);
1039
1040/*----------------------------------------------------------------------*/
1041/* INTERRUPTS */
1042
1043/** 0111 1111 1001 0100 rtfi */
1044 ID(rtfi);
1045
1046/** 0111 1111 1001 0101 rte */
1047 ID(rte);
1048
1049/** 0000 0000 brk */
1050 ID(brk);
1051
1052/** 0000 0001 dbt */
1053 ID(dbt);
1054
1055/** 0111 0101 0110 0000 int #%1 */
1056 ID(int); SC(IMM(1));
1057
1058/** 0111 1111 1001 0110 wait */
1059 ID(wait);
1060
1061/*----------------------------------------------------------------------*/
1062/* SCcnd */
1063
1064/** 1111 1100 1101 sz sd rdst cond sc%1%s %0 */
1065 ID(sccnd); BWL(sz); DD (sd, rdst, sz); Scc(cond);
1066
1067/*----------------------------------------------------------------------*/
1068/* RXv2 enhanced */
1069
1070/** 1111 1101 0010 0111 rdst rsrc movco %1, [%0] */
1071 ID(movco); SR(rsrc); DR(rdst); F_____;
1072
1073/** 1111 1101 0010 1111 rsrc rdst movli [%1], %0 */
1074 ID(movli); SR(rsrc); DR(rdst); F_____;
1075
1076/** 1111 1100 0100 1011 rsrc rdst stz %1, %0 */
1077 ID(stcc); SR(rsrc); DR(rdst); S2cc(RXC_z);
1078
1079/** 1111 1100 0100 1111 rsrc rdst stnz %1, %0 */
1080 ID(stcc); SR(rsrc); DR(rdst); S2cc(RXC_nz);
1081
1082/** 1111 1101 0000 a111 srca srcb emaca %1, %2, %0 */
1083 ID(emaca); DR(a+32); SR(srca); S2R(srcb); F_____;
1084
1085/** 1111 1101 0100 a111 srca srcb emsba %1, %2, %0 */
1086 ID(emsba); DR(a+32); SR(srca); S2R(srcb); F_____;
1087
1088/** 1111 1101 0000 a011 srca srcb emula %1, %2, %0 */
1089 ID(emula); DR(a+32); SR(srca); S2R(srcb); F_____;
1090
1091/** 1111 1101 0000 a110 srca srcb maclh %1, %2, %0 */
1092 ID(maclh); DR(a+32); SR(srca); S2R(srcb); F_____;
1093
1094/** 1111 1101 0100 a100 srca srcb msbhi %1, %2, %0 */
1095 ID(msbhi); DR(a+32); SR(srca); S2R(srcb); F_____;
1096
1097/** 1111 1101 0100 a110 srca srcb msblh %1, %2, %0 */
1098 ID(msblh); DR(a+32); SR(srca); S2R(srcb); F_____;
1099
1100/** 1111 1101 0100 a101 srca srcb msblo %1, %2, %0 */
1101 ID(msblo); DR(a+32); SR(srca); S2R(srcb); F_____;
1102
1103/** 1111 1101 0000 a010 srca srcb mullh %1, %2, %0 */
1104 ID(mullh); DR(a+32); SR(srca); S2R(srcb); F_____;
1105
1106/** 1111 1101 0001 111i a m11 rdst mvfacgu #%2, %1, %0 */
1107 ID(mvfacgu); S2C(((i^1)<<1)|m); SR(a+32); DR(rdst); F_____;
1108
1109/** 1111 1101 0001 0111 a011 rdst mvtacgu %0, %1 */
1110 ID(mvtacgu); DR(a+32); SR(rdst); F_____;
1111
1112/** 1111 1101 0001 1001 a00i 0000 racl #%1, %0 */
1113 ID(racl); SC(i+1); DR(a+32); F_____;
1114
1115/** 1111 1101 0001 1001 a10i 0000 rdacl #%1, %0 */
1116 ID(rdacl); SC(i+1); DR(a+32); F_____;
1117
1118/** 1111 1101 0001 1000 a10i 0000 rdacw #%1, %0 */
1119 ID(rdacw); SC(i+1); DR(a+32); F_____;
1120
1121/** 1111 1111 1010 rdst srca srcb fadd %2, %1, %0 */
1122 ID(fadd); DR(rdst); SR(srcb); S2R(srca); F__SZ_;
1123
1124/** 1111 1111 1000 rdst srca srcb fsub %2, %1, %0 */
1125 ID(fsub); DR(rdst); SR(srcb); S2R(srca); F__SZ_;
1126
1127/** 1111 1111 1011 rdst srca srcb fmul %2, %1, %0 */
1128 ID(fmul); DR(rdst); SR(srcb); S2R(srca); F__SZ_;
1129
1130/** 1111 1100 1010 00sd rsrc rdst fsqrt %1%S1, %0 */
1131 ID(fsqrt); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
1132
1133/** 1111 1100 1010 01sd rsrc rdst ftou %1%S1, %0 */
1134 ID(ftou); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
1135
1136/** 1111 1100 0101 01sd rsrc rdst utof %1%S1, %0 */
1137 ID(utof); DR (rdst); SP(sd, rsrc); F__SZ_;
1138
1139/** 0000 0110 mx10 00sd 0001 0101 rsrc rdst utof %1%S1, %0 */
1140 ID(utof); DR (rdst); SPm(sd, rsrc, mx); F__SZ_;
1141
1142/*----------------------------------------------------------------------*/
1143/* RXv3 enhanced */
1144
1145/** 1111 1111 0110 rdst srca srcb xor %2, %1, %0 */
1146 ID(xor); DR(rdst); SR(srcb); S2R(srca); F__SZ_;
1147
1148/** 1111 1100 0101 1110 rsrc rdst bfmov %bf */
1149 ID(bfmov); DR(rdst); SR(rsrc); S2C(IMM(2)); F_____;
1150
1151/** 1111 1100 0101 1010 rsrc rdst bfmovz %bf */
1152 ID(bfmovz); DR(rdst); SR(rsrc); S2C(IMM(2)); F_____;
1153
1154/** 1111 1101 0111 0110 1101 rsrc 0000 0000 rstr %1 */
1155 ID(rstr); SR(rsrc); F_____;
1156
1157/** 1111 1101 0111 0110 1111 0000 rstr #%1 */
1158 ID(rstr); SC(IMM(1)); F_____;
1159
1160/** 1111 1101 0111 0110 1100 rsrc 0000 0000 save %1 */
1161 ID(save); SR(rsrc); F_____;
1162
1163/** 1111 1101 0111 0110 1110 0000 save #%1 */
1164 ID(save); SC(IMM(1)); F_____;
1165
1166/** 1111 1101 0111 0111 1000 rsrc rdst 001s dmov%s %1, %0 */
1167 ID(dmov); DDRH(rdst); SR(rsrc); DL(s); F_____;
1168
1169/** 1111 1101 0111 0111 1000 rsrc rdst 0000 dmov.l %1, %0 */
1170 ID(dmov); DDRL(rdst); SR(rsrc); F_____;
1171
1172/** 1111 1101 0111 0101 1000 rdst rsrc 0010 dmov.l %1, %0 */
1173 ID(dmov); DR(rdst); SDRH(rsrc); F_____;
1174
1175/** 1111 1101 0111 0101 1000 rdst rsrc 0000 dmov.l %1, %0 */
1176 ID(dmov); DR(rdst); SDRL(rsrc); F_____;
1177
1178/** 0111 0110 1001 0000 rsrc 1100 rdst 0000 dmov.d %1, %0 */
1179 ID(dmov); DDR(rdst); SDR(rsrc); F_____;
1180
1181/** 1111 1100 0111 1000 rdst 1000 rsrc 0000 dmov.d %1, %0 */
1182 ID(dmov); DD(0, rdst, 0); SDR(rsrc); F_____;
1183
1184/** 1111 1100 0111 10sz rdst 1000 dmov.d %1, %0 */
1185 int rsrc;
1186 rx_disp(0, sz, rdst, RX_Double, ld);
1187 rsrc = GETBYTE();
1188 if (rsrc & 0x0f)
1189 UNSUPPORTED();
1190 else {
1191 ID(dmov); SDR(rsrc >> 4); F_____;
1192 }
1193
1194/** 1111 1100 1100 1000 rsrc 1000 rdst 0000 dmov.d %1, %0 */
1195 ID(dmov); SD(sd, rsrc, 0) ; DDR(rdst); F_____;
1196
1197/** 1111 1100 1100 10sz rsrc 1000 dmov.d %1, %0 */
1198 int rdst;
1199 rx_disp(1, sz, rsrc, RX_Double, ld);
1200 rdst = GETBYTE();
1201 if (rdst & 0x0f)
1202 UNSUPPORTED();
1203 else {
1204 ID(dmov); DDR(rdst >> 4); F_____;
1205 }
1206
1207/** 1111 1001 0000 0011 rdst 001s dmov%s #%1, %0 */
1208 ID(dmov); DDRH(rdst); DL(s); SC(IMMex(0)); F_____;
1209
1210/** 1111 1001 0000 0011 rdst 0000 dmov.l #%1, %0 */
1211 ID(dmov); DDRL(rdst); SC(IMMex(0)); F_____;
1212
1213/** 0111 0101 1011 1000 rdst rnum dpopm.d %1-%2 */
1214 ID(dpopm); SDR(rdst); S2DR(rdst + rnum); F_____;
1215
1216/** 0111 0101 1010 1000 rdst rnum dpopm.l %1-%2 */
1217 ID(dpopm); SCR(rdst); S2CR(rdst + rnum); F_____;
1218
1219/** 0111 0101 1011 0000 rdst rnum dpushm.d %1-%2 */
1220 ID(dpushm); SDR(rdst); S2DR(rdst + rnum); F_____;
1221
1222/** 0111 0101 1010 0000 rdst rnum dpushm.l %1-%2 */
1223 ID(dpushm); SCR(rdst); S2CR(rdst + rnum); F_____;
1224
1225/** 1111 1101 0111 0101 1000 rdst rsrc 0100 mvfdc %1, %0 */
1226 ID(mvfdc); DR(rdst); SCR(rsrc); F_____;
1227
1228/** 0111 0101 1001 0000 0001 1011 mvfdr */
1229 ID(mvfdr); F_____;
1230
1231/** 1111 1101 0111 0111 1000 rdst rsrc 0100 mvtdc %1, %0 */
1232 ID(mvtdc); DCR(rdst); SR(rsrc); F_____;
1233
1234/** 0111 0110 1001 0000 rsrc 1100 rdst 0001 dabs %1, %0 */
1235 ID(dabs); DDR(rdst); SDR(rsrc); F_____;
1236
1237/** 0111 0110 1001 0000 srcb 0000 rdst srca dadd %1, %2, %0 */
1238 ID(dadd); DDR(rdst); SDR(srca); S2DR(srcb); F_____;
1239
1240/** 0111 0110 1001 0000 srcb 1000 cond srca dcmp%0 %1, %2 */
1241 ID(dcmp); DCND(cond); SDR(srca); S2DR(srcb); F_____;
1242
1243/** 0111 0110 1001 0000 srcb 0101 rdst srca ddiv %1, %2, %0 */
1244 ID(ddiv); DDR(rdst); SDR(srca); S2DR(srcb); F_____;
1245
1246/** 0111 0110 1001 0000 srcb 0010 rdst srca dmul %1, %2, %0 */
1247 ID(dmul); DDR(rdst); SDR(srca); S2DR(srcb); F_____;
1248
1249/** 0111 0110 1001 0000 rsrc 1100 rdst 0010 dneg %1, %0 */
1250 ID(dneg); DDR(rdst); SDR(rsrc); F_____;
1251
1252/** 0111 0110 1001 0000 rsrc 1101 rdst 1101 dround %1, %0 */
1253 ID(dround); DDR(rdst); SDR(rsrc); F_____;
1254
1255/** 0111 0110 1001 0000 rsrc 1101 rdst 0000 dsqrt %1, %0 */
1256 ID(dsqrt); DDR(rdst); SDR(rsrc); F_____;
1257
1258/** 0111 0110 1001 0000 srcb 0001 rdst srca dsub %1, %2, %0 */
1259 ID(dsub); DDR(rdst); SDR(srca); S2DR(srcb); F_____;
1260
1261/** 0111 0110 1001 0000 rsrc 1101 rdst 1100 dtof %1, %0 */
1262 ID(dtof); DDR(rdst); SDR(rsrc); F_____;
1263
1264/** 0111 0110 1001 0000 rsrc 1101 rdst 1000 dtoi %1, %0 */
1265 ID(dtoi); DDR(rdst); SDR(rsrc); F_____;
1266
1267/** 0111 0110 1001 0000 rsrc 1101 rdst 1001 dtou %1, %0 */
1268 ID(dtou); DDR(rdst); SDR(rsrc); F_____;
1269
1270/** 1111 1101 0111 0111 1000 rsrc rdst 1010 ftod %1, %0 */
1271 ID(ftod); DDR(rdst); SR(rsrc); F_____;
1272
1273/** 1111 1101 0111 0111 1000 rsrc rdst 1001 itod %1, %0 */
1274 ID(itod); DDR(rdst); SR(rsrc); F_____;
1275
1276/** 1111 1101 0111 0111 1000 rsrc rdst 1101 utod %1, %0 */
1277 ID(dsqrt); DDR(rdst); SR(rsrc); F_____;
1278
1279/** */
1280
1281 return rx->n_bytes;
1282}
GDB Binutils - Deliverables
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