| 1 | /* collection of junk waiting time to sort out |
| 2 | Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. |
| 3 | Contributed by Cygnus Support. |
| 4 | |
| 5 | This file is part of the GNU Simulators. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 2, or (at your option) |
| 10 | any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License along |
| 18 | with this program; if not, write to the Free Software Foundation, Inc., |
| 19 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
| 20 | |
| 21 | #ifndef M32R_SIM_H |
| 22 | #define M32R_SIM_H |
| 23 | |
| 24 | /* Register numbers used in gdb interface. */ |
| 25 | #define PC_REGNUM 21 |
| 26 | #define ACCL_REGNUM 22 |
| 27 | #define ACCH_REGNUM 23 |
| 28 | \f |
| 29 | /* Misc. profile data. */ |
| 30 | |
| 31 | typedef struct { |
| 32 | /* nop insn slot filler count */ |
| 33 | unsigned int fillnop_count; |
| 34 | /* number of parallel insns */ |
| 35 | unsigned int parallel_count; |
| 36 | |
| 37 | /* FIXME: generalize this to handle all insn lengths, move to common. */ |
| 38 | /* number of short insns, not including parallel ones */ |
| 39 | unsigned int short_count; |
| 40 | /* number of long insns */ |
| 41 | unsigned int long_count; |
| 42 | |
| 43 | /* Working area for computing cycle counts. */ |
| 44 | unsigned long insn_cycles; |
| 45 | unsigned long cti_stall; |
| 46 | unsigned long load_stall; |
| 47 | unsigned long biggest_cycles; |
| 48 | } M32R_MISC_PROFILE; |
| 49 | |
| 50 | /* Initialize the working area. */ |
| 51 | void m32r_init_insn_cycles (SIM_CPU *, int); |
| 52 | /* Update the totals for the insn. */ |
| 53 | void m32r_record_insn_cycles (SIM_CPU *, int); |
| 54 | |
| 55 | /* This is invoked by the nop pattern in the .cpu file. */ |
| 56 | #define PROFILE_COUNT_FILLNOPS(cpu, addr) \ |
| 57 | do { \ |
| 58 | if (PROFILE_INSN_P (cpu) \ |
| 59 | && (addr & 3) != 0) \ |
| 60 | ++ CPU_M32R_MISC_PROFILE (cpu).fillnop_count; \ |
| 61 | } while (0) |
| 62 | |
| 63 | /* This is invoked by the execute section of mloop{,x}.in. */ |
| 64 | #define PROFILE_COUNT_PARINSNS(cpu) \ |
| 65 | do { \ |
| 66 | if (PROFILE_INSN_P (cpu)) \ |
| 67 | ++ CPU_M32R_MISC_PROFILE (cpu).parallel_count; \ |
| 68 | } while (0) |
| 69 | |
| 70 | /* This is invoked by the execute section of mloop{,x}.in. */ |
| 71 | #define PROFILE_COUNT_SHORTINSNS(cpu) \ |
| 72 | do { \ |
| 73 | if (PROFILE_INSN_P (cpu)) \ |
| 74 | ++ CPU_M32R_MISC_PROFILE (cpu).short_count; \ |
| 75 | } while (0) |
| 76 | |
| 77 | /* This is invoked by the execute section of mloop{,x}.in. */ |
| 78 | #define PROFILE_COUNT_LONGINSNS(cpu) \ |
| 79 | do { \ |
| 80 | if (PROFILE_INSN_P (cpu)) \ |
| 81 | ++ CPU_M32R_MISC_PROFILE (cpu).long_count; \ |
| 82 | } while (0) |
| 83 | \f |
| 84 | #define GETTWI GETTSI |
| 85 | #define SETTWI SETTSI |
| 86 | \f |
| 87 | /* Additional execution support. */ |
| 88 | |
| 89 | /* Result of semantic function is one of |
| 90 | - next address, branch only |
| 91 | - NEW_PC_SKIP, sc/snc insn |
| 92 | - NEW_PC_2, 2 byte non-branch non-sc/snc insn |
| 93 | - NEW_PC_4, 4 byte non-branch insn |
| 94 | The special values have bit 1 set so it's cheap to distinguish them. |
| 95 | This works because all cti's are defined to zero the bottom two bits. */ |
| 96 | /* FIXME: replace 0xffff0001 with 1? */ |
| 97 | #define NEW_PC_BASE 0xffff0001 |
| 98 | #define NEW_PC_SKIP NEW_PC_BASE |
| 99 | #define NEW_PC_2 (NEW_PC_BASE + 2) |
| 100 | #define NEW_PC_4 (NEW_PC_BASE + 4) |
| 101 | #define NEW_PC_BRANCH_P(addr) (((addr) & 1) == 0) |
| 102 | |
| 103 | /* start-sanitize-m32rx */ |
| 104 | /* Modify "next pc" handling to handle parallel execution. */ |
| 105 | #ifdef WANT_CPU_M32RX |
| 106 | #undef SEM_NEXT_PC |
| 107 | #define SEM_NEXT_PC(abuf, len) (NEW_PC_BASE + (len)) |
| 108 | #endif |
| 109 | /* end-sanitize-m32rx */ |
| 110 | |
| 111 | /* This macro is emitted by the generator to record branch addresses. */ |
| 112 | #define BRANCH_NEW_PC(var, addr) \ |
| 113 | do { var = (addr); } while (0) |
| 114 | \f |
| 115 | /* Hardware/device support. */ |
| 116 | |
| 117 | /* Exception, Interrupt, and Trap addresses */ |
| 118 | #define EIT_SYSBREAK_ADDR 0x10 |
| 119 | #define EIT_RSVD_INSN_ADDR 0x20 |
| 120 | #define EIT_ADDR_EXCP_ADDR 0x30 |
| 121 | #define EIT_TRAP_BASE_ADDR 0x40 |
| 122 | #define EIT_EXTERN_ADDR 0x80 |
| 123 | #define EIT_RESET_ADDR 0x7ffffff0 |
| 124 | #define EIT_WAKEUP_ADDR 0x7ffffff0 |
| 125 | |
| 126 | /* Special purpose traps. */ |
| 127 | #define TRAP_SYSCALL 0 |
| 128 | #define TRAP_BREAKPOINT 1 |
| 129 | |
| 130 | /* Support for the MSPR register (Cache Purge Control Register) |
| 131 | and the MCCR register (Cache Control Register) are needed in order for |
| 132 | overlays to work correctly with the scache. |
| 133 | MSPR no longer exists but is supported for upward compatibility with |
| 134 | early overlay support. */ |
| 135 | |
| 136 | /* Cache Purge Control (only exists on early versions of chips) */ |
| 137 | #define MSPR_ADDR 0xfffffff7 |
| 138 | #define MSPR_PURGE 1 |
| 139 | |
| 140 | /* Lock Control Register (not supported) */ |
| 141 | #define MLCR_ADDR 0xfffffff7 |
| 142 | #define MLCR_LM 1 |
| 143 | |
| 144 | /* Power Management Control Register (not supported) */ |
| 145 | #define MPMR_ADDR 0xfffffffb |
| 146 | |
| 147 | /* Cache Control Register */ |
| 148 | #define MCCR_ADDR 0xffffffff |
| 149 | #define MCCR_CP 0x80 |
| 150 | /* not supported */ |
| 151 | #define MCCR_CM0 2 |
| 152 | #define MCCR_CM1 1 |
| 153 | |
| 154 | /* Serial device addresses. */ |
| 155 | #define UART_INCHAR_ADDR 0xff102013 |
| 156 | #define UART_OUTCHAR_ADDR 0xff10200f |
| 157 | #define UART_STATUS_ADDR 0xff102006 |
| 158 | #define UART_INPUT_EMPTY 0x4 |
| 159 | #define UART_OUTPUT_EMPTY 0x1 |
| 160 | |
| 161 | /* Start address and length of all device support. */ |
| 162 | #define M32R_DEVICE_ADDR 0xff000000 |
| 163 | #define M32R_DEVICE_LEN 0x00ffffff |
| 164 | |
| 165 | /* sim_core_attach device argument. */ |
| 166 | extern device m32r_devices; |
| 167 | |
| 168 | /* FIXME: Temporary, until device support ready. */ |
| 169 | struct _device { int foo; }; |
| 170 | |
| 171 | /* Handle the trap insn. */ |
| 172 | USI m32r_trap (SIM_CPU *, PCADDR, int); |
| 173 | |
| 174 | #endif /* M32R_SIM_H */ |