Documentation/devicetree/bindings/display/msm/dsi.txt

   1 Qualcomm Technologies Inc. adreno/snapdragon DSI output
   2
   3 DSI Controller:
   4 Required properties:
   5 - compatible:
   6   * "qcom,mdss-dsi-ctrl"
   7 - reg: Physical base address and length of the registers of controller
   8 - reg-names: The names of register regions. The following regions are required:
   9   * "dsi_ctrl"
  10 - qcom,dsi-host-index: The ID of DSI controller hardware instance. This should
  11   be 0 or 1, since we have 2 DSI controllers at most for now.
  12 - interrupts: The interrupt signal from the DSI block.
  13 - power-domains: Should be <&mmcc MDSS_GDSC>.
  14 - clocks: device clocks
  15   See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
  16 - clock-names: the following clocks are required:
  17   * "mdp_core_clk"
  18   * "iface_clk"
  19   * "bus_clk"
  20   * "core_mmss_clk"
  21   * "byte_clk"
  22   * "pixel_clk"
  23   * "core_clk"
  24   For DSIv2, we need an additional clock:
  25    * "src_clk"
  26 - vdd-supply: phandle to vdd regulator device node
  27 - vddio-supply: phandle to vdd-io regulator device node
  28 - vdda-supply: phandle to vdda regulator device node
  29 - qcom,dsi-phy: phandle to DSI PHY device node
  30 - syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)
  31
  32 Optional properties:
  33 - panel@0: Node of panel connected to this DSI controller.
  34   See files in Documentation/devicetree/bindings/display/panel/ for each supported
  35   panel.
  36 - qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
  37   driving a panel which needs 2 DSI links.
  38 - qcom,master-dsi: Boolean value indicating if the DSI controller is driving
  39   the master link of the 2-DSI panel.
  40 - qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is
  41   driving a 2-DSI panel whose 2 links need receive command simultaneously.
  42 - interrupt-parent: phandle to the MDP block if the interrupt signal is routed
  43   through MDP block
  44 - pinctrl-names: the pin control state names; should contain "default"
  45 - pinctrl-0: the default pinctrl state (active)
  46 - pinctrl-n: the "sleep" pinctrl state
  47 - port: DSI controller output port. This contains one endpoint subnode, with its
  48   remote-endpoint set to the phandle of the connected panel's endpoint.
  49   See Documentation/devicetree/bindings/graph.txt for device graph info.
  50
  51 DSI PHY:
  52 Required properties:
  53 - compatible: Could be the following
  54   * "qcom,dsi-phy-28nm-hpm"
  55   * "qcom,dsi-phy-28nm-lp"
  56   * "qcom,dsi-phy-20nm"
  57   * "qcom,dsi-phy-28nm-8960"
  58 - reg: Physical base address and length of the registers of PLL, PHY and PHY
  59   regulator
  60 - reg-names: The names of register regions. The following regions are required:
  61   * "dsi_pll"
  62   * "dsi_phy"
  63   * "dsi_phy_regulator"
  64 - qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should
  65   be 0 or 1, since we have 2 DSI PHYs at most for now.
  66 - power-domains: Should be <&mmcc MDSS_GDSC>.
  67 - clocks: device clocks
  68   See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
  69 - clock-names: the following clocks are required:
  70   * "iface_clk"
  71 - vddio-supply: phandle to vdd-io regulator device node
  72
  73 Optional properties:
  74 - qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
  75   regulator is wanted.
  76
  77 Example:
  78         mdss_dsi0: qcom,mdss_dsi@fd922800 {
  79                 compatible = "qcom,mdss-dsi-ctrl";
  80                 qcom,dsi-host-index = <0>;
  81                 interrupt-parent = <&mdss_mdp>;
  82                 interrupts = <4 0>;
  83                 reg-names = "dsi_ctrl";
  84                 reg = <0xfd922800 0x200>;
  85                 power-domains = <&mmcc MDSS_GDSC>;
  86                 clock-names =
  87                         "bus_clk",
  88                         "byte_clk",
  89                         "core_clk",
  90                         "core_mmss_clk",
  91                         "iface_clk",
  92                         "mdp_core_clk",
  93                         "pixel_clk";
  94                 clocks =
  95                         <&mmcc MDSS_AXI_CLK>,
  96                         <&mmcc MDSS_BYTE0_CLK>,
  97                         <&mmcc MDSS_ESC0_CLK>,
  98                         <&mmcc MMSS_MISC_AHB_CLK>,
  99                         <&mmcc MDSS_AHB_CLK>,
 100                         <&mmcc MDSS_MDP_CLK>,
 101                         <&mmcc MDSS_PCLK0_CLK>;
 102                 vdda-supply = <&pma8084_l2>;
 103                 vdd-supply = <&pma8084_l22>;
 104                 vddio-supply = <&pma8084_l12>;
 105
 106                 qcom,dsi-phy = <&mdss_dsi_phy0>;
 107
 108                 qcom,dual-dsi-mode;
 109                 qcom,master-dsi;
 110                 qcom,sync-dual-dsi;
 111
 112                 pinctrl-names = "default", "sleep";
 113                 pinctrl-0 = <&mdss_dsi_active>;
 114                 pinctrl-1 = <&mdss_dsi_suspend>;
 115
 116                 panel: panel@0 {
 117                         compatible = "sharp,lq101r1sx01";
 118                         reg = <0>;
 119                         link2 = <&secondary>;
 120
 121                         power-supply = <...>;
 122                         backlight = <...>;
 123
 124                         port {
 125                                 panel_in: endpoint {
 126                                         remote-endpoint = <&dsi0_out>;
 127                                 };
 128                         };
 129                 };
 130
 131                 port {
 132                         dsi0_out: endpoint {
 133                                 remote-endpoint = <&panel_in>;
 134                         };
 135                 };
 136         };
 137
 138         mdss_dsi_phy0: qcom,mdss_dsi_phy@fd922a00 {
 139                 compatible = "qcom,dsi-phy-28nm-hpm";
 140                 qcom,dsi-phy-index = <0>;
 141                 reg-names =
 142                         "dsi_pll",
 143                         "dsi_phy",
 144                         "dsi_phy_regulator";
 145                 reg =   <0xfd922a00 0xd4>,
 146                         <0xfd922b00 0x2b0>,
 147                         <0xfd922d80 0x7b>;
 148                 clock-names = "iface_clk";
 149                 clocks = <&mmcc MDSS_AHB_CLK>;
 150                 vddio-supply = <&pma8084_l12>;
 151
 152                 qcom,dsi-phy-regulator-ldo-mode;
 153         };