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[deliverable/linux.git] / Documentation / devicetree / bindings / display / rockchip / rockchip-vop.txt
1 device-tree bindings for rockchip soc display controller (vop)
2
3 VOP (Visual Output Processor) is the Display Controller for the Rockchip
4 series of SoCs which transfers the image data from a video memory
5 buffer to an external LCD interface.
6
7 Required properties:
8 - compatible: value should be one of the following
9 "rockchip,rk3288-vop";
10 "rockchip,rk3036-vop";
11
12 - interrupts: should contain a list of all VOP IP block interrupts in the
13 order: VSYNC, LCD_SYSTEM. The interrupt specifier
14 format depends on the interrupt controller used.
15
16 - clocks: must include clock specifiers corresponding to entries in the
17 clock-names property.
18
19 - clock-names: Must contain
20 aclk_vop: for ddr buffer transfer.
21 hclk_vop: for ahb bus to R/W the phy regs.
22 dclk_vop: pixel clock.
23
24 - resets: Must contain an entry for each entry in reset-names.
25 See ../reset/reset.txt for details.
26 - reset-names: Must include the following entries:
27 - axi
28 - ahb
29 - dclk
30
31 - iommus: required a iommu node
32
33 - port: A port node with endpoint definitions as defined in
34 Documentation/devicetree/bindings/media/video-interfaces.txt.
35
36 Example:
37 SoC specific DT entry:
38 vopb: vopb@ff930000 {
39 compatible = "rockchip,rk3288-vop";
40 reg = <0xff930000 0x19c>;
41 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
42 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
43 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
44 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
45 reset-names = "axi", "ahb", "dclk";
46 iommus = <&vopb_mmu>;
47 vopb_out: port {
48 #address-cells = <1>;
49 #size-cells = <0>;
50 vopb_out_edp: endpoint@0 {
51 reg = <0>;
52 remote-endpoint=<&edp_in_vopb>;
53 };
54 vopb_out_hdmi: endpoint@1 {
55 reg = <1>;
56 remote-endpoint=<&hdmi_in_vopb>;
57 };
58 };
59 };
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