Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt

   1 Allwinner A10 Display Pipeline
   2 ==============================
   3
   4 The Allwinner A10 Display pipeline is composed of several components
   5 that are going to be documented below:
   6
   7 TV Encoder
   8 ----------
   9
  10 The TV Encoder supports the composite and VGA output. It is one end of
  11 the pipeline.
  12
  13 Required properties:
  14  - compatible: value should be "allwinner,sun4i-a10-tv-encoder".
  15  - reg: base address and size of memory-mapped region
  16  - clocks: the clocks driving the TV encoder
  17  - resets: phandle to the reset controller driving the encoder
  18
  19 - ports: A ports node with endpoint definitions as defined in
  20   Documentation/devicetree/bindings/media/video-interfaces.txt. The
  21   first port should be the input endpoint.
  22
  23 TCON
  24 ----
  25
  26 The TCON acts as a timing controller for RGB, LVDS and TV interfaces.
  27
  28 Required properties:
  29  - compatible: value should be "allwinner,sun5i-a13-tcon".
  30  - reg: base address and size of memory-mapped region
  31  - interrupts: interrupt associated to this IP
  32  - clocks: phandles to the clocks feeding the TCON. Three are needed:
  33    - 'ahb': the interface clocks
  34    - 'tcon-ch0': The clock driving the TCON channel 0
  35    - 'tcon-ch1': The clock driving the TCON channel 1
  36  - resets: phandles to the reset controllers driving the encoder
  37    - "lcd": the reset line for the TCON channel 0
  38
  39  - clock-names: the clock names mentioned above
  40  - reset-names: the reset names mentioned above
  41  - clock-output-names: Name of the pixel clock created
  42
  43 - ports: A ports node with endpoint definitions as defined in
  44   Documentation/devicetree/bindings/media/video-interfaces.txt. The
  45   first port should be the input endpoint, the second one the output
  46
  47   The output should have two endpoints. The first is the block
  48   connected to the TCON channel 0 (usually a panel or a bridge), the
  49   second the block connected to the TCON channel 1 (usually the TV
  50   encoder)
  51
  52
  53 Display Engine Backend
  54 ----------------------
  55
  56 The display engine backend exposes layers and sprites to the
  57 system.
  58
  59 Required properties:
  60   - compatible: value must be one of:
  61     * allwinner,sun5i-a13-display-backend
  62   - reg: base address and size of the memory-mapped region.
  63   - clocks: phandles to the clocks feeding the frontend and backend
  64     * ahb: the backend interface clock
  65     * mod: the backend module clock
  66     * ram: the backend DRAM clock
  67   - clock-names: the clock names mentioned above
  68   - resets: phandles to the reset controllers driving the backend
  69
  70 - ports: A ports node with endpoint definitions as defined in
  71   Documentation/devicetree/bindings/media/video-interfaces.txt. The
  72   first port should be the input endpoints, the second one the output
  73
  74 Display Engine Frontend
  75 -----------------------
  76
  77 The display engine frontend does formats conversion, scaling,
  78 deinterlacing and color space conversion.
  79
  80 Required properties:
  81   - compatible: value must be one of:
  82     * allwinner,sun5i-a13-display-frontend
  83   - reg: base address and size of the memory-mapped region.
  84   - interrupts: interrupt associated to this IP
  85   - clocks: phandles to the clocks feeding the frontend and backend
  86     * ahb: the backend interface clock
  87     * mod: the backend module clock
  88     * ram: the backend DRAM clock
  89   - clock-names: the clock names mentioned above
  90   - resets: phandles to the reset controllers driving the backend
  91
  92 - ports: A ports node with endpoint definitions as defined in
  93   Documentation/devicetree/bindings/media/video-interfaces.txt. The
  94   first port should be the input endpoints, the second one the outputs
  95
  96
  97 Display Engine Pipeline
  98 -----------------------
  99
 100 The display engine pipeline (and its entry point, since it can be
 101 either directly the backend or the frontend) is represented as an
 102 extra node.
 103
 104 Required properties:
 105   - compatible: value must be one of:
 106     * allwinner,sun5i-a13-display-engine
 107
 108   - allwinner,pipelines: list of phandle to the display engine
 109     frontends available.
 110
 111 Example:
 112
 113 panel: panel {
 114         compatible = "olimex,lcd-olinuxino-43-ts";
 115         #address-cells = <1>;
 116         #size-cells = <0>;
 117
 118         port {
 119                 #address-cells = <1>;
 120                 #size-cells = <0>;
 121
 122                 panel_input: endpoint {
 123                         remote-endpoint = <&tcon0_out_panel>;
 124                 };
 125         };
 126 };
 127
 128 tve0: tv-encoder@01c0a000 {
 129         compatible = "allwinner,sun4i-a10-tv-encoder";
 130         reg = <0x01c0a000 0x1000>;
 131         clocks = <&ahb_gates 34>;
 132         resets = <&tcon_ch0_clk 0>;
 133
 134         port {
 135                 #address-cells = <1>;
 136                 #size-cells = <0>;
 137
 138                 tve0_in_tcon0: endpoint@0 {
 139                         reg = <0>;
 140                         remote-endpoint = <&tcon0_out_tve0>;
 141                 };
 142         };
 143 };
 144
 145 tcon0: lcd-controller@1c0c000 {
 146         compatible = "allwinner,sun5i-a13-tcon";
 147         reg = <0x01c0c000 0x1000>;
 148         interrupts = <44>;
 149         resets = <&tcon_ch0_clk 1>;
 150         reset-names = "lcd";
 151         clocks = <&ahb_gates 36>,
 152                  <&tcon_ch0_clk>,
 153                  <&tcon_ch1_clk>;
 154         clock-names = "ahb",
 155                       "tcon-ch0",
 156                       "tcon-ch1";
 157         clock-output-names = "tcon-pixel-clock";
 158
 159         ports {
 160                 #address-cells = <1>;
 161                 #size-cells = <0>;
 162
 163                 tcon0_in: port@0 {
 164                         #address-cells = <1>;
 165                         #size-cells = <0>;
 166                         reg = <0>;
 167
 168                         tcon0_in_be0: endpoint@0 {
 169                                 reg = <0>;
 170                                 remote-endpoint = <&be0_out_tcon0>;
 171                         };
 172                 };
 173
 174                 tcon0_out: port@1 {
 175                         #address-cells = <1>;
 176                         #size-cells = <0>;
 177                         reg = <1>;
 178
 179                         tcon0_out_panel: endpoint@0 {
 180                                 reg = <0>;
 181                                 remote-endpoint = <&panel_input>;
 182                         };
 183
 184                         tcon0_out_tve0: endpoint@1 {
 185                                 reg = <1>;
 186                                 remote-endpoint = <&tve0_in_tcon0>;
 187                         };
 188                 };
 189         };
 190 };
 191
 192 fe0: display-frontend@1e00000 {
 193         compatible = "allwinner,sun5i-a13-display-frontend";
 194         reg = <0x01e00000 0x20000>;
 195         interrupts = <47>;
 196         clocks = <&ahb_gates 46>, <&de_fe_clk>,
 197                  <&dram_gates 25>;
 198         clock-names = "ahb", "mod",
 199                       "ram";
 200         resets = <&de_fe_clk>;
 201
 202         ports {
 203                 #address-cells = <1>;
 204                 #size-cells = <0>;
 205
 206                 fe0_out: port@1 {
 207                         #address-cells = <1>;
 208                         #size-cells = <0>;
 209                         reg = <1>;
 210
 211                         fe0_out_be0: endpoint {
 212                                 remote-endpoint = <&be0_in_fe0>;
 213                         };
 214                 };
 215         };
 216 };
 217
 218 be0: display-backend@1e60000 {
 219         compatible = "allwinner,sun5i-a13-display-backend";
 220         reg = <0x01e60000 0x10000>;
 221         clocks = <&ahb_gates 44>, <&de_be_clk>,
 222                  <&dram_gates 26>;
 223         clock-names = "ahb", "mod",
 224                       "ram";
 225         resets = <&de_be_clk>;
 226
 227         ports {
 228                 #address-cells = <1>;
 229                 #size-cells = <0>;
 230
 231                 be0_in: port@0 {
 232                         #address-cells = <1>;
 233                         #size-cells = <0>;
 234                         reg = <0>;
 235
 236                         be0_in_fe0: endpoint@0 {
 237                                 reg = <0>;
 238                                 remote-endpoint = <&fe0_out_be0>;
 239                         };
 240                 };
 241
 242                 be0_out: port@1 {
 243                         #address-cells = <1>;
 244                         #size-cells = <0>;
 245                         reg = <1>;
 246
 247                         be0_out_tcon0: endpoint@0 {
 248                                 reg = <0>;
 249                                 remote-endpoint = <&tcon0_in_be0>;
 250                         };
 251                 };
 252         };
 253 };
 254
 255 display-engine {
 256         compatible = "allwinner,sun5i-a13-display-engine";
 257         allwinner,pipelines = <&fe0>;
 258 };