Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt

   1 * Freescale Smart Direct Memory Access (SDMA) Controller for i.MX
   2
   3 Required properties:
   4 - compatible : Should be one of
   5       "fsl,imx25-sdma"
   6       "fsl,imx31-sdma", "fsl,imx31-to1-sdma", "fsl,imx31-to2-sdma"
   7       "fsl,imx35-sdma", "fsl,imx35-to1-sdma", "fsl,imx35-to2-sdma"
   8       "fsl,imx51-sdma"
   9       "fsl,imx53-sdma"
  10       "fsl,imx6q-sdma"
  11   The -to variants should be preferred since they allow to determine the
  12   correct ROM script addresses needed for the driver to work without additional
  13   firmware.
  14 - reg : Should contain SDMA registers location and length
  15 - interrupts : Should contain SDMA interrupt
  16 - #dma-cells : Must be <3>.
  17   The first cell specifies the DMA request/event ID.  See details below
  18   about the second and third cell.
  19 - fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM
  20   scripts firmware
  21
  22 The second cell of dma phandle specifies the peripheral type of DMA transfer.
  23 The full ID of peripheral types can be found below.
  24
  25         ID      transfer type
  26         ---------------------
  27         0       MCU domain SSI
  28         1       Shared SSI
  29         2       MMC
  30         3       SDHC
  31         4       MCU domain UART
  32         5       Shared UART
  33         6       FIRI
  34         7       MCU domain CSPI
  35         8       Shared CSPI
  36         9       SIM
  37         10      ATA
  38         11      CCM
  39         12      External peripheral
  40         13      Memory Stick Host Controller
  41         14      Shared Memory Stick Host Controller
  42         15      DSP
  43         16      Memory
  44         17      FIFO type Memory
  45         18      SPDIF
  46         19      IPU Memory
  47         20      ASRC
  48         21      ESAI
  49         22      SSI Dual FIFO   (needs firmware ver >= 2)
  50         23      Shared ASRC
  51         24      SAI
  52
  53 The third cell specifies the transfer priority as below.
  54
  55         ID      transfer priority
  56         -------------------------
  57         0       High
  58         1       Medium
  59         2       Low
  60
  61 Optional properties:
  62
  63 - gpr : The phandle to the General Purpose Register (GPR) node.
  64 - fsl,sdma-event-remap : Register bits of sdma event remap, the format is
  65   <reg shift val>.
  66     reg is the GPR register offset.
  67     shift is the bit position inside the GPR register.
  68     val is the value of the bit (0 or 1).
  69
  70 Examples:
  71
  72 sdma@83fb0000 {
  73         compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
  74         reg = <0x83fb0000 0x4000>;
  75         interrupts = <6>;
  76         #dma-cells = <3>;
  77         fsl,sdma-ram-script-name = "sdma-imx51.bin";
  78 };
  79
  80 DMA clients connected to the i.MX SDMA controller must use the format
  81 described in the dma.txt file.
  82
  83 Examples:
  84
  85 ssi2: ssi@70014000 {
  86         compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
  87         reg = <0x70014000 0x4000>;
  88         interrupts = <30>;
  89         clocks = <&clks 49>;
  90         dmas = <&sdma 24 1 0>,
  91                <&sdma 25 1 0>;
  92         dma-names = "rx", "tx";
  93         fsl,fifo-depth = <15>;
  94 };
  95
  96 Using the fsl,sdma-event-remap property:
  97
  98 If we want to use SDMA on the SAI1 port on a MX6SX:
  99
 100 &sdma {
 101         gpr = <&gpr>;
 102         /* SDMA events remap for SAI1_RX and SAI1_TX */
 103         fsl,sdma-event-remap = <0 15 1>, <0 16 1>;
 104 };
 105
 106 The fsl,sdma-event-remap property in this case has two values:
 107 - <0 15 1> means that the offset is 0, so GPR0 is the register of the
 108 SDMA remap. Bit 15 of GPR0 selects between UART4_RX and SAI1_RX.
 109 Setting bit 15 to 1 selects SAI1_RX.
 110 - <0 16 1> means that the offset is 0, so GPR0 is the register of the
 111 SDMA remap. Bit 16 of GPR0 selects between UART4_TX and SAI1_TX.
 112 Setting bit 16 to 1 selects SAI1_TX.