Documentation/devicetree/bindings/net/rockchip-dwmac.txt

   1 Rockchip SoC RK3288 10/100/1000 Ethernet driver(GMAC)
   2
   3 The device node has following properties.
   4
   5 Required properties:
   6  - compatible: Can be one of "rockchip,rk3228-gmac", "rockchip,rk3288-gmac",
   7                              "rockchip,rk3368-gmac"
   8  - reg: addresses and length of the register sets for the device.
   9  - interrupts: Should contain the GMAC interrupts.
  10  - interrupt-names: Should contain the interrupt names "macirq".
  11  - rockchip,grf: phandle to the syscon grf used to control speed and mode.
  12  - clocks: <&cru SCLK_MAC>: clock selector for main clock, from PLL or PHY.
  13            <&cru SCLK_MAC_PLL>: PLL clock for SCLK_MAC
  14            <&cru SCLK_MAC_RX>: clock gate for RX
  15            <&cru SCLK_MAC_TX>: clock gate for TX
  16            <&cru SCLK_MACREF>: clock gate for RMII referce clock
  17            <&cru SCLK_MACREF_OUT> clock gate for RMII reference clock output
  18            <&cru ACLK_GMAC>: AXI clock gate for GMAC
  19            <&cru PCLK_GMAC>: APB clock gate for GMAC
  20  - clock-names: One name for each entry in the clocks property.
  21  - phy-mode: See ethernet.txt file in the same directory.
  22  - pinctrl-names: Names corresponding to the numbered pinctrl states.
  23  - pinctrl-0: pin-control mode. can be <&rgmii_pins> or <&rmii_pins>.
  24  - clock_in_out: For RGMII, it must be "input", means main clock(125MHz)
  25    is not sourced from SoC's PLL, but input from PHY; For RMII, "input" means
  26    PHY provides the reference clock(50MHz), "output" means GMAC provides the
  27    reference clock.
  28  - snps,reset-gpio       gpio number for phy reset.
  29  - snps,reset-active-low boolean flag to indicate if phy reset is active low.
  30  - assigned-clocks: main clock, should be <&cru SCLK_MAC>;
  31  - assigned-clock-parents = parent of main clock.
  32    can be <&ext_gmac> or <&cru SCLK_MAC_PLL>.
  33
  34 Optional properties:
  35  - tx_delay: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default.
  36  - rx_delay: Delay value for RXD timing. Range value is 0~0x7F, 0x10 as default.
  37  - phy-supply: phandle to a regulator if the PHY needs one
  38
  39 Example:
  40
  41 gmac: ethernet@ff290000 {
  42         compatible = "rockchip,rk3288-gmac";
  43         reg = <0xff290000 0x10000>;
  44         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
  45         interrupt-names = "macirq";
  46         rockchip,grf = <&grf>;
  47         clocks = <&cru SCLK_MAC>,
  48                 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
  49                 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
  50                 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
  51         clock-names = "stmmaceth",
  52                 "mac_clk_rx", "mac_clk_tx",
  53                 "clk_mac_ref", "clk_mac_refout",
  54                 "aclk_mac", "pclk_mac";
  55         phy-mode = "rgmii";
  56         pinctrl-names = "default";
  57         pinctrl-0 = <&rgmii_pins /*&rmii_pins*/>;
  58
  59         clock_in_out = "input";
  60         snps,reset-gpio = <&gpio4 7 0>;
  61         snps,reset-active-low;
  62
  63         assigned-clocks = <&cru SCLK_MAC>;
  64         assigned-clock-parents = <&ext_gmac>;
  65         tx_delay = <0x30>;
  66         rx_delay = <0x10>;
  67
  68         status = "ok";
  69 };