Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt

   1 * Allwinner A1X Pin Controller
   2
   3 The pins controlled by sunXi pin controller are organized in banks,
   4 each bank has 32 pins.  Each pin has 7 multiplexing functions, with
   5 the first two functions being GPIO in and out. The configuration on
   6 the pins includes drive strength and pull-up.
   7
   8 Required properties:
   9 - compatible: Should be one of the followings (depending on you SoC):
  10   "allwinner,sun4i-a10-pinctrl"
  11   "allwinner,sun5i-a10s-pinctrl"
  12   "allwinner,sun5i-a13-pinctrl"
  13   "allwinner,sun6i-a31-pinctrl"
  14   "allwinner,sun6i-a31s-pinctrl"
  15   "allwinner,sun6i-a31-r-pinctrl"
  16   "allwinner,sun7i-a20-pinctrl"
  17   "allwinner,sun8i-a23-pinctrl"
  18   "allwinner,sun8i-a23-r-pinctrl"
  19   "allwinner,sun8i-a33-pinctrl"
  20   "allwinner,sun9i-a80-pinctrl"
  21   "allwinner,sun9i-a80-r-pinctrl"
  22   "allwinner,sun8i-a83t-pinctrl"
  23   "allwinner,sun8i-h3-pinctrl"
  24
  25 - reg: Should contain the register physical address and length for the
  26   pin controller.
  27
  28 Please refer to pinctrl-bindings.txt in this directory for details of the
  29 common pinctrl bindings used by client devices.
  30
  31 A pinctrl node should contain at least one subnodes representing the
  32 pinctrl groups available on the machine. Each subnode will list the
  33 pins it needs, and how they should be configured, with regard to muxer
  34 configuration, drive strength and pullups. If one of these options is
  35 not set, its actual value will be unspecified.
  36
  37 Required subnode-properties:
  38
  39 - allwinner,pins: List of strings containing the pin name.
  40 - allwinner,function: Function to mux the pins listed above to.
  41
  42 Optional subnode-properties:
  43 - allwinner,drive: Integer. Represents the current sent to the pin
  44     0: 10 mA
  45     1: 20 mA
  46     2: 30 mA
  47     3: 40 mA
  48 - allwinner,pull: Integer.
  49     0: No resistor
  50     1: Pull-up resistor
  51     2: Pull-down resistor
  52
  53 Examples:
  54
  55 pio: pinctrl@01c20800 {
  56         compatible = "allwinner,sun5i-a13-pinctrl";
  57         reg = <0x01c20800 0x400>;
  58         #address-cells = <1>;
  59         #size-cells = <0>;
  60
  61         uart1_pins_a: uart1@0 {
  62                 allwinner,pins = "PE10", "PE11";
  63                 allwinner,function = "uart1";
  64                 allwinner,drive = <0>;
  65                 allwinner,pull = <0>;
  66         };
  67
  68         uart1_pins_b: uart1@1 {
  69                 allwinner,pins = "PG3", "PG4";
  70                 allwinner,function = "uart1";
  71                 allwinner,drive = <0>;
  72                 allwinner,pull = <0>;
  73         };
  74 };
  75
  76
  77 GPIO and interrupt controller
  78 -----------------------------
  79
  80 This hardware also acts as a GPIO controller and an interrupt
  81 controller.
  82
  83 Consumers that would want to refer to one or the other (or both)
  84 should provide through the usual *-gpios and interrupts properties a
  85 cell with 3 arguments, first the number of the bank, then the pin
  86 inside that bank, and finally the flags for the GPIO/interrupts.
  87
  88 Example:
  89
  90 xio: gpio@38 {
  91         compatible = "nxp,pcf8574a";
  92         reg = <0x38>;
  93
  94         gpio-controller;
  95         #gpio-cells = <2>;
  96
  97         interrupt-parent = <&pio>;
  98         interrupts = <6 0 IRQ_TYPE_EDGE_FALLING>;
  99         interrupt-controller;
 100         #interrupt-cells = <2>;
 101 };
 102
 103 reg_usb1_vbus: usb1-vbus {
 104         compatible = "regulator-fixed";
 105         regulator-name = "usb1-vbus";
 106         regulator-min-microvolt = <5000000>;
 107         regulator-max-microvolt = <5000000>;
 108         gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>;
 109 };