Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt

   1 * Mediatek MT65XX Pin Controller
   2
   3 The Mediatek's Pin controller is used to control SoC pins.
   4
   5 Required properties:
   6 - compatible: value should be one of the following.
   7         "mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl.
   8         "mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.
   9         "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
  10         "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
  11         "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
  12 - pins-are-numbered: Specify the subnodes are using numbered pinmux to
  13   specify pins.
  14 - gpio-controller : Marks the device node as a gpio controller.
  15 - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
  16   binding is used, the amount of cells must be specified as 2. See the below
  17   mentioned gpio binding representation for description of particular cells.
  18
  19         Eg: <&pio 6 0>
  20         <[phandle of the gpio controller node]
  21         [line number within the gpio controller]
  22         [flags]>
  23
  24         Values for gpio specifier:
  25         - Line number: is a value between 0 to 202.
  26         - Flags:  bit field of flags, as defined in <dt-bindings/gpio/gpio.h>.
  27             Only the following flags are supported:
  28             0 - GPIO_ACTIVE_HIGH
  29             1 - GPIO_ACTIVE_LOW
  30
  31 Optional properties:
  32 - mediatek,pctl-regmap: Should be a phandle of the syscfg node.
  33 - reg: physicall address base for EINT registers
  34 - interrupt-controller: Marks the device node as an interrupt controller
  35 - #interrupt-cells: Should be two.
  36 - interrupts : The interrupt outputs from the controller.
  37
  38 Please refer to pinctrl-bindings.txt in this directory for details of the
  39 common pinctrl bindings used by client devices.
  40
  41 Subnode format
  42 A pinctrl node should contain at least one subnodes representing the
  43 pinctrl groups available on the machine. Each subnode will list the
  44 pins it needs, and how they should be configured, with regard to muxer
  45 configuration, pullups, drive strength, input enable/disable and input schmitt.
  46
  47     node {
  48         pinmux = <PIN_NUMBER_PINMUX>;
  49         GENERIC_PINCONFIG;
  50     };
  51
  52 Required properties:
  53 - pinmux: integer array, represents gpio pin number and mux setting.
  54     Supported pin number and mux varies for different SoCs, and are defined
  55     as macros in boot/dts/<soc>-pinfunc.h directly.
  56
  57 Optional properties:
  58 - GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable,
  59     bias-pull-down, bias-pull-up, input-enable, input-disable, output-low, output-high,
  60     input-schmitt-enable, input-schmitt-disable and drive-strength are valid.
  61
  62     Some special pins have extra pull up strength, there are R0 and R1 pull-up
  63     resistors available, but for user, it's only need to set R1R0 as 00, 01, 10 or 11.
  64     So when config bias-pull-up, it support arguments for those special pins.
  65     Some macros have been defined for this usage, such as MTK_PUPD_SET_R1R0_00.
  66     See dt-bindings/pinctrl/mt65xx.h.
  67
  68     When config drive-strength, it can support some arguments, such as
  69     MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h.
  70
  71 Examples:
  72
  73 #include "mt8135-pinfunc.h"
  74
  75 ...
  76 {
  77         syscfg_pctl_a: syscfg_pctl_a@10005000 {
  78                 compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
  79                 reg = <0 0x10005000 0 0x1000>;
  80         };
  81
  82         syscfg_pctl_b: syscfg_pctl_b@1020C020 {
  83                 compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
  84                 reg = <0 0x1020C020 0 0x1000>;
  85         };
  86
  87         pinctrl@01c20800 {
  88                 compatible = "mediatek,mt8135-pinctrl";
  89                 reg = <0 0x1000B000 0 0x1000>;
  90                 mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;
  91                 pins-are-numbered;
  92                 gpio-controller;
  93                 #gpio-cells = <2>;
  94                 interrupt-controller;
  95                 #interrupt-cells = <2>;
  96                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
  97                                 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
  98                                 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
  99
 100                 i2c0_pins_a: i2c0@0 {
 101                         pins1 {
 102                                 pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
 103                                          <MT8135_PIN_101_SCL0__FUNC_SCL0>;
 104                                 bias-disable;
 105                         };
 106                 };
 107
 108                 i2c1_pins_a: i2c1@0 {
 109                         pins {
 110                                 pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
 111                                          <MT8135_PIN_196_SCL1__FUNC_SCL1>;
 112                                 bias-pull-up = <55>;
 113                         };
 114                 };
 115
 116                 i2c2_pins_a: i2c2@0 {
 117                         pins1 {
 118                                 pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
 119                                 bias-pull-down;
 120                         };
 121
 122                         pins2 {
 123                                 pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
 124                                 bias-pull-up;
 125                         };
 126                 };
 127
 128                 i2c3_pins_a: i2c3@0 {
 129                         pins1 {
 130                                 pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,
 131                                          <MT8135_PIN_41_DAC_WS__FUNC_GPIO41>;
 132                                 bias-pull-up = <55>;
 133                         };
 134
 135                         pins2 {
 136                                 pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>,
 137                                          <MT8135_PIN_36_SDA3__FUNC_SDA3>;
 138                                 output-low;
 139                                 bias-pull-up = <55>;
 140                         };
 141
 142                         pins3 {
 143                                 pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>,
 144                                          <MT8135_PIN_60_JTDI__FUNC_JTDI>;
 145                                 drive-strength = <32>;
 146                         };
 147                 };
 148
 149                 ...
 150         }
 151 };