Merge branches 'acpi-soc', 'acpi-misc', 'acpi-pci' and 'device-properties'
[deliverable/linux.git] / Documentation / devicetree / bindings / pinctrl / st,stm32-pinctrl.txt
1 * STM32 GPIO and Pin Mux/Config controller
2
3 STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
4 controller. It controls the input/output settings on the available pins and
5 also provides ability to multiplex and configure the output of various on-chip
6 controllers onto these pads.
7
8 Pin controller node:
9 Required properies:
10 - compatible: value should be one of the following:
11 (a) "st,stm32f429-pinctrl"
12 - #address-cells: The value of this property must be 1
13 - #size-cells : The value of this property must be 1
14 - ranges : defines mapping between pin controller node (parent) to
15 gpio-bank node (children).
16 - pins-are-numbered: Specify the subnodes are using numbered pinmux to
17 specify pins.
18
19 GPIO controller/bank node:
20 Required properties:
21 - gpio-controller : Indicates this device is a GPIO controller
22 - #gpio-cells : Should be two.
23 The first cell is the pin number
24 The second one is the polarity:
25 - 0 for active high
26 - 1 for active low
27 - reg : The gpio address range, relative to the pinctrl range
28 - clocks : clock that drives this bank
29 - st,bank-name : Should be a name string for this bank as specified in
30 the datasheet
31
32 Optional properties:
33 - reset: : Reference to the reset controller
34
35 Example:
36 #include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
37 ...
38
39 pin-controller {
40 #address-cells = <1>;
41 #size-cells = <1>;
42 compatible = "st,stm32f429-pinctrl";
43 ranges = <0 0x40020000 0x3000>;
44 pins-are-numbered;
45
46 gpioa: gpio@40020000 {
47 gpio-controller;
48 #gpio-cells = <2>;
49 reg = <0x0 0x400>;
50 resets = <&reset_ahb1 0>;
51 st,bank-name = "GPIOA";
52 };
53 ...
54 pin-functions nodes follow...
55 };
56
57 Contents of function subnode node:
58 ----------------------------------
59 Subnode format
60 A pinctrl node should contain at least one subnode representing the
61 pinctrl group available on the machine. Each subnode will list the
62 pins it needs, and how they should be configured, with regard to muxer
63 configuration, pullups, drive, output high/low and output speed.
64
65 node {
66 pinmux = <PIN_NUMBER_PINMUX>;
67 GENERIC_PINCONFIG;
68 };
69
70 Required properties:
71 - pinmux: integer array, represents gpio pin number and mux setting.
72 Supported pin number and mux varies for different SoCs, and are defined in
73 dt-bindings/pinctrl/<soc>-pinfunc.h directly.
74 These defines are calculated as:
75 ((port * 16 + line) << 8) | function
76 With:
77 - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
78 - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
79 - function: The function number, can be:
80 * 0 : GPIO
81 * 1 : Alternate Function 0
82 * 2 : Alternate Function 1
83 * 3 : Alternate Function 2
84 * ...
85 * 16 : Alternate Function 15
86 * 17 : Analog
87
88 Optional properties:
89 - GENERIC_PINCONFIG: is the generic pinconfig options to use.
90 Available options are:
91 - bias-disable,
92 - bias-pull-down,
93 - bias-pull-up,
94 - drive-push-pull,
95 - drive-open-drain,
96 - output-low
97 - output-high
98 - slew-rate = <x>, with x being:
99 < 0 > : Low speed
100 < 1 > : Medium speed
101 < 2 > : Fast speed
102 < 3 > : High speed
103
104 Example:
105
106 pin-controller {
107 ...
108 usart1_pins_a: usart1@0 {
109 pins1 {
110 pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
111 bias-disable;
112 drive-push-pull;
113 slew-rate = <0>;
114 };
115 pins2 {
116 pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
117 bias-disable;
118 };
119 };
120 };
121
122 &usart1 {
123 pinctrl-0 = <&usart1_pins_a>;
124 pinctrl-names = "default";
125 status = "okay";
126 };
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