1 ============================
2 LINUX KERNEL MEMORY BARRIERS
3 ============================
5 By: David Howells <dhowells@redhat.com>
6 Paul E. McKenney <paulmck@linux.vnet.ibm.com>
10 (*) Abstract memory access model.
15 (*) What are memory barriers?
17 - Varieties of memory barrier.
18 - What may not be assumed about memory barriers?
19 - Data dependency barriers.
20 - Control dependencies.
21 - SMP barrier pairing.
22 - Examples of memory barrier sequences.
23 - Read memory barriers vs load speculation.
26 (*) Explicit kernel barriers.
29 - CPU memory barriers.
32 (*) Implicit kernel memory barriers.
35 - Interrupt disabling functions.
36 - Sleep and wake-up functions.
37 - Miscellaneous functions.
39 (*) Inter-CPU locking barrier effects.
41 - Locks vs memory accesses.
42 - Locks vs I/O accesses.
44 (*) Where are memory barriers needed?
46 - Interprocessor interaction.
51 (*) Kernel I/O barrier effects.
53 (*) Assumed minimum execution ordering model.
55 (*) The effects of the cpu cache.
58 - Cache coherency vs DMA.
59 - Cache coherency vs MMIO.
61 (*) The things CPUs get up to.
63 - And then there's the Alpha.
72 ============================
73 ABSTRACT MEMORY ACCESS MODEL
74 ============================
76 Consider the following abstract model of the system:
81 +-------+ : +--------+ : +-------+
84 | CPU 1 |<----->| Memory |<----->| CPU 2 |
87 +-------+ : +--------+ : +-------+
95 +---------->| Device |<----------+
101 Each CPU executes a program that generates memory access operations. In the
102 abstract CPU, memory operation ordering is very relaxed, and a CPU may actually
103 perform the memory operations in any order it likes, provided program causality
104 appears to be maintained. Similarly, the compiler may also arrange the
105 instructions it emits in any order it likes, provided it doesn't affect the
106 apparent operation of the program.
108 So in the above diagram, the effects of the memory operations performed by a
109 CPU are perceived by the rest of the system as the operations cross the
110 interface between the CPU and rest of the system (the dotted lines).
113 For example, consider the following sequence of events:
116 =============== ===============
121 The set of accesses as seen by the memory system in the middle can be arranged
122 in 24 different combinations:
124 STORE A=3, STORE B=4, y=LOAD A->3, x=LOAD B->4
125 STORE A=3, STORE B=4, x=LOAD B->4, y=LOAD A->3
126 STORE A=3, y=LOAD A->3, STORE B=4, x=LOAD B->4
127 STORE A=3, y=LOAD A->3, x=LOAD B->2, STORE B=4
128 STORE A=3, x=LOAD B->2, STORE B=4, y=LOAD A->3
129 STORE A=3, x=LOAD B->2, y=LOAD A->3, STORE B=4
130 STORE B=4, STORE A=3, y=LOAD A->3, x=LOAD B->4
134 and can thus result in four different combinations of values:
142 Furthermore, the stores committed by a CPU to the memory system may not be
143 perceived by the loads made by another CPU in the same order as the stores were
147 As a further example, consider this sequence of events:
150 =============== ===============
151 { A == 1, B == 2, C = 3, P == &A, Q == &C }
155 There is an obvious data dependency here, as the value loaded into D depends on
156 the address retrieved from P by CPU 2. At the end of the sequence, any of the
157 following results are possible:
159 (Q == &A) and (D == 1)
160 (Q == &B) and (D == 2)
161 (Q == &B) and (D == 4)
163 Note that CPU 2 will never try and load C into D because the CPU will load P
164 into Q before issuing the load of *Q.
170 Some devices present their control interfaces as collections of memory
171 locations, but the order in which the control registers are accessed is very
172 important. For instance, imagine an ethernet card with a set of internal
173 registers that are accessed through an address port register (A) and a data
174 port register (D). To read internal register 5, the following code might then
180 but this might show up as either of the following two sequences:
182 STORE *A = 5, x = LOAD *D
183 x = LOAD *D, STORE *A = 5
185 the second of which will almost certainly result in a malfunction, since it set
186 the address _after_ attempting to read the register.
192 There are some minimal guarantees that may be expected of a CPU:
194 (*) On any given CPU, dependent memory accesses will be issued in order, with
195 respect to itself. This means that for:
197 WRITE_ONCE(Q, P); smp_read_barrier_depends(); D = READ_ONCE(*Q);
199 the CPU will issue the following memory operations:
201 Q = LOAD P, D = LOAD *Q
203 and always in that order. On most systems, smp_read_barrier_depends()
204 does nothing, but it is required for DEC Alpha. The READ_ONCE()
205 and WRITE_ONCE() are required to prevent compiler mischief. Please
206 note that you should normally use something like rcu_dereference()
207 instead of open-coding smp_read_barrier_depends().
209 (*) Overlapping loads and stores within a particular CPU will appear to be
210 ordered within that CPU. This means that for:
212 a = READ_ONCE(*X); WRITE_ONCE(*X, b);
214 the CPU will only issue the following sequence of memory operations:
216 a = LOAD *X, STORE *X = b
220 WRITE_ONCE(*X, c); d = READ_ONCE(*X);
222 the CPU will only issue:
224 STORE *X = c, d = LOAD *X
226 (Loads and stores overlap if they are targeted at overlapping pieces of
229 And there are a number of things that _must_ or _must_not_ be assumed:
231 (*) It _must_not_ be assumed that the compiler will do what you want
232 with memory references that are not protected by READ_ONCE() and
233 WRITE_ONCE(). Without them, the compiler is within its rights to
234 do all sorts of "creative" transformations, which are covered in
235 the Compiler Barrier section.
237 (*) It _must_not_ be assumed that independent loads and stores will be issued
238 in the order given. This means that for:
240 X = *A; Y = *B; *D = Z;
242 we may get any of the following sequences:
244 X = LOAD *A, Y = LOAD *B, STORE *D = Z
245 X = LOAD *A, STORE *D = Z, Y = LOAD *B
246 Y = LOAD *B, X = LOAD *A, STORE *D = Z
247 Y = LOAD *B, STORE *D = Z, X = LOAD *A
248 STORE *D = Z, X = LOAD *A, Y = LOAD *B
249 STORE *D = Z, Y = LOAD *B, X = LOAD *A
251 (*) It _must_ be assumed that overlapping memory accesses may be merged or
252 discarded. This means that for:
254 X = *A; Y = *(A + 4);
256 we may get any one of the following sequences:
258 X = LOAD *A; Y = LOAD *(A + 4);
259 Y = LOAD *(A + 4); X = LOAD *A;
260 {X, Y} = LOAD {*A, *(A + 4) };
264 *A = X; *(A + 4) = Y;
268 STORE *A = X; STORE *(A + 4) = Y;
269 STORE *(A + 4) = Y; STORE *A = X;
270 STORE {*A, *(A + 4) } = {X, Y};
272 And there are anti-guarantees:
274 (*) These guarantees do not apply to bitfields, because compilers often
275 generate code to modify these using non-atomic read-modify-write
276 sequences. Do not attempt to use bitfields to synchronize parallel
279 (*) Even in cases where bitfields are protected by locks, all fields
280 in a given bitfield must be protected by one lock. If two fields
281 in a given bitfield are protected by different locks, the compiler's
282 non-atomic read-modify-write sequences can cause an update to one
283 field to corrupt the value of an adjacent field.
285 (*) These guarantees apply only to properly aligned and sized scalar
286 variables. "Properly sized" currently means variables that are
287 the same size as "char", "short", "int" and "long". "Properly
288 aligned" means the natural alignment, thus no constraints for
289 "char", two-byte alignment for "short", four-byte alignment for
290 "int", and either four-byte or eight-byte alignment for "long",
291 on 32-bit and 64-bit systems, respectively. Note that these
292 guarantees were introduced into the C11 standard, so beware when
293 using older pre-C11 compilers (for example, gcc 4.6). The portion
294 of the standard containing this guarantee is Section 3.14, which
295 defines "memory location" as follows:
298 either an object of scalar type, or a maximal sequence
299 of adjacent bit-fields all having nonzero width
301 NOTE 1: Two threads of execution can update and access
302 separate memory locations without interfering with
305 NOTE 2: A bit-field and an adjacent non-bit-field member
306 are in separate memory locations. The same applies
307 to two bit-fields, if one is declared inside a nested
308 structure declaration and the other is not, or if the two
309 are separated by a zero-length bit-field declaration,
310 or if they are separated by a non-bit-field member
311 declaration. It is not safe to concurrently update two
312 bit-fields in the same structure if all members declared
313 between them are also bit-fields, no matter what the
314 sizes of those intervening bit-fields happen to be.
317 =========================
318 WHAT ARE MEMORY BARRIERS?
319 =========================
321 As can be seen above, independent memory operations are effectively performed
322 in random order, but this can be a problem for CPU-CPU interaction and for I/O.
323 What is required is some way of intervening to instruct the compiler and the
324 CPU to restrict the order.
326 Memory barriers are such interventions. They impose a perceived partial
327 ordering over the memory operations on either side of the barrier.
329 Such enforcement is important because the CPUs and other devices in a system
330 can use a variety of tricks to improve performance, including reordering,
331 deferral and combination of memory operations; speculative loads; speculative
332 branch prediction and various types of caching. Memory barriers are used to
333 override or suppress these tricks, allowing the code to sanely control the
334 interaction of multiple CPUs and/or devices.
337 VARIETIES OF MEMORY BARRIER
338 ---------------------------
340 Memory barriers come in four basic varieties:
342 (1) Write (or store) memory barriers.
344 A write memory barrier gives a guarantee that all the STORE operations
345 specified before the barrier will appear to happen before all the STORE
346 operations specified after the barrier with respect to the other
347 components of the system.
349 A write barrier is a partial ordering on stores only; it is not required
350 to have any effect on loads.
352 A CPU can be viewed as committing a sequence of store operations to the
353 memory system as time progresses. All stores before a write barrier will
354 occur in the sequence _before_ all the stores after the write barrier.
356 [!] Note that write barriers should normally be paired with read or data
357 dependency barriers; see the "SMP barrier pairing" subsection.
360 (2) Data dependency barriers.
362 A data dependency barrier is a weaker form of read barrier. In the case
363 where two loads are performed such that the second depends on the result
364 of the first (eg: the first load retrieves the address to which the second
365 load will be directed), a data dependency barrier would be required to
366 make sure that the target of the second load is updated before the address
367 obtained by the first load is accessed.
369 A data dependency barrier is a partial ordering on interdependent loads
370 only; it is not required to have any effect on stores, independent loads
371 or overlapping loads.
373 As mentioned in (1), the other CPUs in the system can be viewed as
374 committing sequences of stores to the memory system that the CPU being
375 considered can then perceive. A data dependency barrier issued by the CPU
376 under consideration guarantees that for any load preceding it, if that
377 load touches one of a sequence of stores from another CPU, then by the
378 time the barrier completes, the effects of all the stores prior to that
379 touched by the load will be perceptible to any loads issued after the data
382 See the "Examples of memory barrier sequences" subsection for diagrams
383 showing the ordering constraints.
385 [!] Note that the first load really has to have a _data_ dependency and
386 not a control dependency. If the address for the second load is dependent
387 on the first load, but the dependency is through a conditional rather than
388 actually loading the address itself, then it's a _control_ dependency and
389 a full read barrier or better is required. See the "Control dependencies"
390 subsection for more information.
392 [!] Note that data dependency barriers should normally be paired with
393 write barriers; see the "SMP barrier pairing" subsection.
396 (3) Read (or load) memory barriers.
398 A read barrier is a data dependency barrier plus a guarantee that all the
399 LOAD operations specified before the barrier will appear to happen before
400 all the LOAD operations specified after the barrier with respect to the
401 other components of the system.
403 A read barrier is a partial ordering on loads only; it is not required to
404 have any effect on stores.
406 Read memory barriers imply data dependency barriers, and so can substitute
409 [!] Note that read barriers should normally be paired with write barriers;
410 see the "SMP barrier pairing" subsection.
413 (4) General memory barriers.
415 A general memory barrier gives a guarantee that all the LOAD and STORE
416 operations specified before the barrier will appear to happen before all
417 the LOAD and STORE operations specified after the barrier with respect to
418 the other components of the system.
420 A general memory barrier is a partial ordering over both loads and stores.
422 General memory barriers imply both read and write memory barriers, and so
423 can substitute for either.
426 And a couple of implicit varieties:
428 (5) ACQUIRE operations.
430 This acts as a one-way permeable barrier. It guarantees that all memory
431 operations after the ACQUIRE operation will appear to happen after the
432 ACQUIRE operation with respect to the other components of the system.
433 ACQUIRE operations include LOCK operations and smp_load_acquire()
436 Memory operations that occur before an ACQUIRE operation may appear to
437 happen after it completes.
439 An ACQUIRE operation should almost always be paired with a RELEASE
443 (6) RELEASE operations.
445 This also acts as a one-way permeable barrier. It guarantees that all
446 memory operations before the RELEASE operation will appear to happen
447 before the RELEASE operation with respect to the other components of the
448 system. RELEASE operations include UNLOCK operations and
449 smp_store_release() operations.
451 Memory operations that occur after a RELEASE operation may appear to
452 happen before it completes.
454 The use of ACQUIRE and RELEASE operations generally precludes the need
455 for other sorts of memory barrier (but note the exceptions mentioned in
456 the subsection "MMIO write barrier"). In addition, a RELEASE+ACQUIRE
457 pair is -not- guaranteed to act as a full memory barrier. However, after
458 an ACQUIRE on a given variable, all memory accesses preceding any prior
459 RELEASE on that same variable are guaranteed to be visible. In other
460 words, within a given variable's critical section, all accesses of all
461 previous critical sections for that variable are guaranteed to have
464 This means that ACQUIRE acts as a minimal "acquire" operation and
465 RELEASE acts as a minimal "release" operation.
468 Memory barriers are only required where there's a possibility of interaction
469 between two CPUs or between a CPU and a device. If it can be guaranteed that
470 there won't be any such interaction in any particular piece of code, then
471 memory barriers are unnecessary in that piece of code.
474 Note that these are the _minimum_ guarantees. Different architectures may give
475 more substantial guarantees, but they may _not_ be relied upon outside of arch
479 WHAT MAY NOT BE ASSUMED ABOUT MEMORY BARRIERS?
480 ----------------------------------------------
482 There are certain things that the Linux kernel memory barriers do not guarantee:
484 (*) There is no guarantee that any of the memory accesses specified before a
485 memory barrier will be _complete_ by the completion of a memory barrier
486 instruction; the barrier can be considered to draw a line in that CPU's
487 access queue that accesses of the appropriate type may not cross.
489 (*) There is no guarantee that issuing a memory barrier on one CPU will have
490 any direct effect on another CPU or any other hardware in the system. The
491 indirect effect will be the order in which the second CPU sees the effects
492 of the first CPU's accesses occur, but see the next point:
494 (*) There is no guarantee that a CPU will see the correct order of effects
495 from a second CPU's accesses, even _if_ the second CPU uses a memory
496 barrier, unless the first CPU _also_ uses a matching memory barrier (see
497 the subsection on "SMP Barrier Pairing").
499 (*) There is no guarantee that some intervening piece of off-the-CPU
500 hardware[*] will not reorder the memory accesses. CPU cache coherency
501 mechanisms should propagate the indirect effects of a memory barrier
502 between CPUs, but might not do so in order.
504 [*] For information on bus mastering DMA and coherency please read:
506 Documentation/PCI/pci.txt
507 Documentation/DMA-API-HOWTO.txt
508 Documentation/DMA-API.txt
511 DATA DEPENDENCY BARRIERS
512 ------------------------
514 The usage requirements of data dependency barriers are a little subtle, and
515 it's not always obvious that they're needed. To illustrate, consider the
516 following sequence of events:
519 =============== ===============
520 { A == 1, B == 2, C = 3, P == &A, Q == &C }
527 There's a clear data dependency here, and it would seem that by the end of the
528 sequence, Q must be either &A or &B, and that:
530 (Q == &A) implies (D == 1)
531 (Q == &B) implies (D == 4)
533 But! CPU 2's perception of P may be updated _before_ its perception of B, thus
534 leading to the following situation:
536 (Q == &B) and (D == 2) ????
538 Whilst this may seem like a failure of coherency or causality maintenance, it
539 isn't, and this behaviour can be observed on certain real CPUs (such as the DEC
542 To deal with this, a data dependency barrier or better must be inserted
543 between the address load and the data load:
546 =============== ===============
547 { A == 1, B == 2, C = 3, P == &A, Q == &C }
552 <data dependency barrier>
555 This enforces the occurrence of one of the two implications, and prevents the
556 third possibility from arising.
558 [!] Note that this extremely counterintuitive situation arises most easily on
559 machines with split caches, so that, for example, one cache bank processes
560 even-numbered cache lines and the other bank processes odd-numbered cache
561 lines. The pointer P might be stored in an odd-numbered cache line, and the
562 variable B might be stored in an even-numbered cache line. Then, if the
563 even-numbered bank of the reading CPU's cache is extremely busy while the
564 odd-numbered bank is idle, one can see the new value of the pointer P (&B),
565 but the old value of the variable B (2).
568 Another example of where data dependency barriers might be required is where a
569 number is read from memory and then used to calculate the index for an array
573 =============== ===============
574 { M[0] == 1, M[1] == 2, M[3] = 3, P == 0, Q == 3 }
579 <data dependency barrier>
583 The data dependency barrier is very important to the RCU system,
584 for example. See rcu_assign_pointer() and rcu_dereference() in
585 include/linux/rcupdate.h. This permits the current target of an RCU'd
586 pointer to be replaced with a new modified target, without the replacement
587 target appearing to be incompletely initialised.
589 See also the subsection on "Cache Coherency" for a more thorough example.
595 A load-load control dependency requires a full read memory barrier, not
596 simply a data dependency barrier to make it work correctly. Consider the
597 following bit of code:
601 <data dependency barrier> /* BUG: No data dependency!!! */
605 This will not have the desired effect because there is no actual data
606 dependency, but rather a control dependency that the CPU may short-circuit
607 by attempting to predict the outcome in advance, so that other CPUs see
608 the load from b as having happened before the load from a. In such a
609 case what's actually required is:
617 However, stores are not speculated. This means that ordering -is- provided
618 for load-store control dependencies, as in the following example:
625 Control dependencies pair normally with other types of barriers. That
626 said, please note that READ_ONCE() is not optional! Without the
627 READ_ONCE(), the compiler might combine the load from 'a' with other
628 loads from 'a', and the store to 'b' with other stores to 'b', with
629 possible highly counterintuitive effects on ordering.
631 Worse yet, if the compiler is able to prove (say) that the value of
632 variable 'a' is always non-zero, it would be well within its rights
633 to optimize the original example by eliminating the "if" statement
637 b = p; /* BUG: Compiler and CPU can both reorder!!! */
639 So don't leave out the READ_ONCE().
641 It is tempting to try to enforce ordering on identical stores on both
642 branches of the "if" statement as follows:
655 Unfortunately, current compilers will transform this as follows at high
660 WRITE_ONCE(b, p); /* BUG: No ordering vs. load from a!!! */
662 /* WRITE_ONCE(b, p); -- moved up, BUG!!! */
665 /* WRITE_ONCE(b, p); -- moved up, BUG!!! */
669 Now there is no conditional between the load from 'a' and the store to
670 'b', which means that the CPU is within its rights to reorder them:
671 The conditional is absolutely required, and must be present in the
672 assembly code even after all compiler optimizations have been applied.
673 Therefore, if you need ordering in this example, you need explicit
674 memory barriers, for example, smp_store_release():
678 smp_store_release(&b, p);
681 smp_store_release(&b, p);
685 In contrast, without explicit memory barriers, two-legged-if control
686 ordering is guaranteed only when the stores differ, for example:
697 The initial READ_ONCE() is still required to prevent the compiler from
698 proving the value of 'a'.
700 In addition, you need to be careful what you do with the local variable 'q',
701 otherwise the compiler might be able to guess the value and again remove
702 the needed conditional. For example:
713 If MAX is defined to be 1, then the compiler knows that (q % MAX) is
714 equal to zero, in which case the compiler is within its rights to
715 transform the above code into the following:
721 Given this transformation, the CPU is not required to respect the ordering
722 between the load from variable 'a' and the store to variable 'b'. It is
723 tempting to add a barrier(), but this does not help. The conditional
724 is gone, and the barrier won't bring it back. Therefore, if you are
725 relying on this ordering, you should make sure that MAX is greater than
726 one, perhaps as follows:
729 BUILD_BUG_ON(MAX <= 1); /* Order load from a with store to b. */
738 Please note once again that the stores to 'b' differ. If they were
739 identical, as noted earlier, the compiler could pull this store outside
740 of the 'if' statement.
742 You must also be careful not to rely too much on boolean short-circuit
743 evaluation. Consider this example:
749 Because the first condition cannot fault and the second condition is
750 always true, the compiler can transform this example as following,
751 defeating control dependency:
756 This example underscores the need to ensure that the compiler cannot
757 out-guess your code. More generally, although READ_ONCE() does force
758 the compiler to actually emit code for a given load, it does not force
759 the compiler to use the results.
761 Finally, control dependencies do -not- provide transitivity. This is
762 demonstrated by two related examples, with the initial values of
763 x and y both being zero:
766 ======================= =======================
767 r1 = READ_ONCE(x); r2 = READ_ONCE(y);
768 if (r1 > 0) if (r2 > 0)
769 WRITE_ONCE(y, 1); WRITE_ONCE(x, 1);
771 assert(!(r1 == 1 && r2 == 1));
773 The above two-CPU example will never trigger the assert(). However,
774 if control dependencies guaranteed transitivity (which they do not),
775 then adding the following CPU would guarantee a related assertion:
778 =====================
781 assert(!(r1 == 2 && r2 == 1 && x == 2)); /* FAILS!!! */
783 But because control dependencies do -not- provide transitivity, the above
784 assertion can fail after the combined three-CPU example completes. If you
785 need the three-CPU example to provide ordering, you will need smp_mb()
786 between the loads and stores in the CPU 0 and CPU 1 code fragments,
787 that is, just before or just after the "if" statements. Furthermore,
788 the original two-CPU example is very fragile and should be avoided.
790 These two examples are the LB and WWC litmus tests from this paper:
791 http://www.cl.cam.ac.uk/users/pes20/ppc-supplemental/test6.pdf and this
792 site: https://www.cl.cam.ac.uk/~pes20/ppcmem/index.html.
796 (*) Control dependencies can order prior loads against later stores.
797 However, they do -not- guarantee any other sort of ordering:
798 Not prior loads against later loads, nor prior stores against
799 later anything. If you need these other forms of ordering,
800 use smp_rmb(), smp_wmb(), or, in the case of prior stores and
801 later loads, smp_mb().
803 (*) If both legs of the "if" statement begin with identical stores
804 to the same variable, a barrier() statement is required at the
805 beginning of each leg of the "if" statement.
807 (*) Control dependencies require at least one run-time conditional
808 between the prior load and the subsequent store, and this
809 conditional must involve the prior load. If the compiler is able
810 to optimize the conditional away, it will have also optimized
811 away the ordering. Careful use of READ_ONCE() and WRITE_ONCE()
812 can help to preserve the needed conditional.
814 (*) Control dependencies require that the compiler avoid reordering the
815 dependency into nonexistence. Careful use of READ_ONCE() or
816 atomic{,64}_read() can help to preserve your control dependency.
817 Please see the Compiler Barrier section for more information.
819 (*) Control dependencies pair normally with other types of barriers.
821 (*) Control dependencies do -not- provide transitivity. If you
822 need transitivity, use smp_mb().
828 When dealing with CPU-CPU interactions, certain types of memory barrier should
829 always be paired. A lack of appropriate pairing is almost certainly an error.
831 General barriers pair with each other, though they also pair with most
832 other types of barriers, albeit without transitivity. An acquire barrier
833 pairs with a release barrier, but both may also pair with other barriers,
834 including of course general barriers. A write barrier pairs with a data
835 dependency barrier, a control dependency, an acquire barrier, a release
836 barrier, a read barrier, or a general barrier. Similarly a read barrier,
837 control dependency, or a data dependency barrier pairs with a write
838 barrier, an acquire barrier, a release barrier, or a general barrier:
841 =============== ===============
844 WRITE_ONCE(b, 2); x = READ_ONCE(b);
851 =============== ===============================
854 WRITE_ONCE(b, &a); x = READ_ONCE(b);
855 <data dependency barrier>
861 =============== ===============================
864 WRITE_ONCE(y, 1); if (r2 = READ_ONCE(x)) {
865 <implicit control dependency>
869 assert(r1 == 0 || r2 == 0);
871 Basically, the read barrier always has to be there, even though it can be of
874 [!] Note that the stores before the write barrier would normally be expected to
875 match the loads after the read barrier or the data dependency barrier, and vice
879 =================== ===================
880 WRITE_ONCE(a, 1); }---- --->{ v = READ_ONCE(c);
881 WRITE_ONCE(b, 2); } \ / { w = READ_ONCE(d);
882 <write barrier> \ <read barrier>
883 WRITE_ONCE(c, 3); } / \ { x = READ_ONCE(a);
884 WRITE_ONCE(d, 4); }---- --->{ y = READ_ONCE(b);
887 EXAMPLES OF MEMORY BARRIER SEQUENCES
888 ------------------------------------
890 Firstly, write barriers act as partial orderings on store operations.
891 Consider the following sequence of events:
894 =======================
902 This sequence of events is committed to the memory coherence system in an order
903 that the rest of the system might perceive as the unordered set of { STORE A,
904 STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E
909 | |------>| C=3 | } /\
910 | | : +------+ }----- \ -----> Events perceptible to
911 | | : | A=1 | } \/ the rest of the system
913 | CPU 1 | : | B=2 | }
915 | | wwwwwwwwwwwwwwww } <--- At this point the write barrier
916 | | +------+ } requires all stores prior to the
917 | | : | E=5 | } barrier to be committed before
918 | | : +------+ } further stores may take place
923 | Sequence in which stores are committed to the
924 | memory system by CPU 1
928 Secondly, data dependency barriers act as partial orderings on data-dependent
929 loads. Consider the following sequence of events:
932 ======================= =======================
933 { B = 7; X = 9; Y = 8; C = &Y }
938 STORE D = 4 LOAD C (gets &B)
941 Without intervention, CPU 2 may perceive the events on CPU 1 in some
942 effectively random order, despite the write barrier issued by CPU 1:
945 | | +------+ +-------+ | Sequence of update
946 | |------>| B=2 |----- --->| Y->8 | | of perception on
947 | | : +------+ \ +-------+ | CPU 2
948 | CPU 1 | : | A=1 | \ --->| C->&Y | V
949 | | +------+ | +-------+
950 | | wwwwwwwwwwwwwwww | : :
952 | | : | C=&B |--- | : : +-------+
953 | | : +------+ \ | +-------+ | |
954 | |------>| D=4 | ----------->| C->&B |------>| |
955 | | +------+ | +-------+ | |
956 +-------+ : : | : : | |
960 Apparently incorrect ---> | | B->7 |------>| |
961 perception of B (!) | +-------+ | |
964 The load of X holds ---> \ | X->9 |------>| |
965 up the maintenance \ +-------+ | |
966 of coherence of B ----->| B->2 | +-------+
971 In the above example, CPU 2 perceives that B is 7, despite the load of *C
972 (which would be B) coming after the LOAD of C.
974 If, however, a data dependency barrier were to be placed between the load of C
975 and the load of *C (ie: B) on CPU 2:
978 ======================= =======================
979 { B = 7; X = 9; Y = 8; C = &Y }
984 STORE D = 4 LOAD C (gets &B)
985 <data dependency barrier>
988 then the following will occur:
991 | | +------+ +-------+
992 | |------>| B=2 |----- --->| Y->8 |
993 | | : +------+ \ +-------+
994 | CPU 1 | : | A=1 | \ --->| C->&Y |
995 | | +------+ | +-------+
996 | | wwwwwwwwwwwwwwww | : :
998 | | : | C=&B |--- | : : +-------+
999 | | : +------+ \ | +-------+ | |
1000 | |------>| D=4 | ----------->| C->&B |------>| |
1001 | | +------+ | +-------+ | |
1002 +-------+ : : | : : | |
1006 | | X->9 |------>| |
1008 Makes sure all effects ---> \ ddddddddddddddddd | |
1009 prior to the store of C \ +-------+ | |
1010 are perceptible to ----->| B->2 |------>| |
1011 subsequent loads +-------+ | |
1015 And thirdly, a read barrier acts as a partial order on loads. Consider the
1016 following sequence of events:
1019 ======================= =======================
1027 Without intervention, CPU 2 may then choose to perceive the events on CPU 1 in
1028 some effectively random order, despite the write barrier issued by CPU 1:
1031 | | +------+ +-------+
1032 | |------>| A=1 |------ --->| A->0 |
1033 | | +------+ \ +-------+
1034 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1035 | | +------+ | +-------+
1036 | |------>| B=2 |--- | : :
1037 | | +------+ \ | : : +-------+
1038 +-------+ : : \ | +-------+ | |
1039 ---------->| B->2 |------>| |
1040 | +-------+ | CPU 2 |
1041 | | A->0 |------>| |
1051 If, however, a read barrier were to be placed between the load of B and the
1055 ======================= =======================
1064 then the partial ordering imposed by CPU 1 will be perceived correctly by CPU
1068 | | +------+ +-------+
1069 | |------>| A=1 |------ --->| A->0 |
1070 | | +------+ \ +-------+
1071 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1072 | | +------+ | +-------+
1073 | |------>| B=2 |--- | : :
1074 | | +------+ \ | : : +-------+
1075 +-------+ : : \ | +-------+ | |
1076 ---------->| B->2 |------>| |
1077 | +-------+ | CPU 2 |
1080 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
1081 barrier causes all effects \ +-------+ | |
1082 prior to the storage of B ---->| A->1 |------>| |
1083 to be perceptible to CPU 2 +-------+ | |
1087 To illustrate this more completely, consider what could happen if the code
1088 contained a load of A either side of the read barrier:
1091 ======================= =======================
1097 LOAD A [first load of A]
1099 LOAD A [second load of A]
1101 Even though the two loads of A both occur after the load of B, they may both
1102 come up with different values:
1105 | | +------+ +-------+
1106 | |------>| A=1 |------ --->| A->0 |
1107 | | +------+ \ +-------+
1108 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1109 | | +------+ | +-------+
1110 | |------>| B=2 |--- | : :
1111 | | +------+ \ | : : +-------+
1112 +-------+ : : \ | +-------+ | |
1113 ---------->| B->2 |------>| |
1114 | +-------+ | CPU 2 |
1118 | | A->0 |------>| 1st |
1120 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
1121 barrier causes all effects \ +-------+ | |
1122 prior to the storage of B ---->| A->1 |------>| 2nd |
1123 to be perceptible to CPU 2 +-------+ | |
1127 But it may be that the update to A from CPU 1 becomes perceptible to CPU 2
1128 before the read barrier completes anyway:
1131 | | +------+ +-------+
1132 | |------>| A=1 |------ --->| A->0 |
1133 | | +------+ \ +-------+
1134 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1135 | | +------+ | +-------+
1136 | |------>| B=2 |--- | : :
1137 | | +------+ \ | : : +-------+
1138 +-------+ : : \ | +-------+ | |
1139 ---------->| B->2 |------>| |
1140 | +-------+ | CPU 2 |
1144 ---->| A->1 |------>| 1st |
1146 rrrrrrrrrrrrrrrrr | |
1148 | A->1 |------>| 2nd |
1153 The guarantee is that the second load will always come up with A == 1 if the
1154 load of B came up with B == 2. No such guarantee exists for the first load of
1155 A; that may come up with either A == 0 or A == 1.
1158 READ MEMORY BARRIERS VS LOAD SPECULATION
1159 ----------------------------------------
1161 Many CPUs speculate with loads: that is they see that they will need to load an
1162 item from memory, and they find a time where they're not using the bus for any
1163 other loads, and so do the load in advance - even though they haven't actually
1164 got to that point in the instruction execution flow yet. This permits the
1165 actual load instruction to potentially complete immediately because the CPU
1166 already has the value to hand.
1168 It may turn out that the CPU didn't actually need the value - perhaps because a
1169 branch circumvented the load - in which case it can discard the value or just
1170 cache it for later use.
1175 ======================= =======================
1177 DIVIDE } Divide instructions generally
1178 DIVIDE } take a long time to perform
1181 Which might appear as this:
1185 --->| B->2 |------>| |
1189 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1190 division speculates on the +-------+ ~ | |
1194 Once the divisions are complete --> : : ~-->| |
1195 the CPU can then perform the : : | |
1196 LOAD with immediate effect : : +-------+
1199 Placing a read barrier or a data dependency barrier just before the second
1203 ======================= =======================
1210 will force any value speculatively obtained to be reconsidered to an extent
1211 dependent on the type of barrier used. If there was no change made to the
1212 speculated memory location, then the speculated value will just be used:
1216 --->| B->2 |------>| |
1220 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1221 division speculates on the +-------+ ~ | |
1226 rrrrrrrrrrrrrrrr~ | |
1233 but if there was an update or an invalidation from another CPU pending, then
1234 the speculation will be cancelled and the value reloaded:
1238 --->| B->2 |------>| |
1242 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1243 division speculates on the +-------+ ~ | |
1248 rrrrrrrrrrrrrrrrr | |
1250 The speculation is discarded ---> --->| A->1 |------>| |
1251 and an updated value is +-------+ | |
1252 retrieved : : +-------+
1258 Transitivity is a deeply intuitive notion about ordering that is not
1259 always provided by real computer systems. The following example
1260 demonstrates transitivity (also called "cumulativity"):
1263 ======================= ======================= =======================
1265 STORE X=1 LOAD X STORE Y=1
1266 <general barrier> <general barrier>
1269 Suppose that CPU 2's load from X returns 1 and its load from Y returns 0.
1270 This indicates that CPU 2's load from X in some sense follows CPU 1's
1271 store to X and that CPU 2's load from Y in some sense preceded CPU 3's
1272 store to Y. The question is then "Can CPU 3's load from X return 0?"
1274 Because CPU 2's load from X in some sense came after CPU 1's store, it
1275 is natural to expect that CPU 3's load from X must therefore return 1.
1276 This expectation is an example of transitivity: if a load executing on
1277 CPU A follows a load from the same variable executing on CPU B, then
1278 CPU A's load must either return the same value that CPU B's load did,
1279 or must return some later value.
1281 In the Linux kernel, use of general memory barriers guarantees
1282 transitivity. Therefore, in the above example, if CPU 2's load from X
1283 returns 1 and its load from Y returns 0, then CPU 3's load from X must
1286 However, transitivity is -not- guaranteed for read or write barriers.
1287 For example, suppose that CPU 2's general barrier in the above example
1288 is changed to a read barrier as shown below:
1291 ======================= ======================= =======================
1293 STORE X=1 LOAD X STORE Y=1
1294 <read barrier> <general barrier>
1297 This substitution destroys transitivity: in this example, it is perfectly
1298 legal for CPU 2's load from X to return 1, its load from Y to return 0,
1299 and CPU 3's load from X to return 0.
1301 The key point is that although CPU 2's read barrier orders its pair
1302 of loads, it does not guarantee to order CPU 1's store. Therefore, if
1303 this example runs on a system where CPUs 1 and 2 share a store buffer
1304 or a level of cache, CPU 2 might have early access to CPU 1's writes.
1305 General barriers are therefore required to ensure that all CPUs agree
1306 on the combined order of CPU 1's and CPU 2's accesses.
1308 To reiterate, if your code requires transitivity, use general barriers
1312 ========================
1313 EXPLICIT KERNEL BARRIERS
1314 ========================
1316 The Linux kernel has a variety of different barriers that act at different
1319 (*) Compiler barrier.
1321 (*) CPU memory barriers.
1323 (*) MMIO write barrier.
1329 The Linux kernel has an explicit compiler barrier function that prevents the
1330 compiler from moving the memory accesses either side of it to the other side:
1334 This is a general barrier -- there are no read-read or write-write
1335 variants of barrier(). However, READ_ONCE() and WRITE_ONCE() can be
1336 thought of as weak forms of barrier() that affect only the specific
1337 accesses flagged by the READ_ONCE() or WRITE_ONCE().
1339 The barrier() function has the following effects:
1341 (*) Prevents the compiler from reordering accesses following the
1342 barrier() to precede any accesses preceding the barrier().
1343 One example use for this property is to ease communication between
1344 interrupt-handler code and the code that was interrupted.
1346 (*) Within a loop, forces the compiler to load the variables used
1347 in that loop's conditional on each pass through that loop.
1349 The READ_ONCE() and WRITE_ONCE() functions can prevent any number of
1350 optimizations that, while perfectly safe in single-threaded code, can
1351 be fatal in concurrent code. Here are some examples of these sorts
1354 (*) The compiler is within its rights to reorder loads and stores
1355 to the same variable, and in some cases, the CPU is within its
1356 rights to reorder loads to the same variable. This means that
1362 Might result in an older value of x stored in a[1] than in a[0].
1363 Prevent both the compiler and the CPU from doing this as follows:
1365 a[0] = READ_ONCE(x);
1366 a[1] = READ_ONCE(x);
1368 In short, READ_ONCE() and WRITE_ONCE() provide cache coherence for
1369 accesses from multiple CPUs to a single variable.
1371 (*) The compiler is within its rights to merge successive loads from
1372 the same variable. Such merging can cause the compiler to "optimize"
1376 do_something_with(tmp);
1378 into the following code, which, although in some sense legitimate
1379 for single-threaded code, is almost certainly not what the developer
1384 do_something_with(tmp);
1386 Use READ_ONCE() to prevent the compiler from doing this to you:
1388 while (tmp = READ_ONCE(a))
1389 do_something_with(tmp);
1391 (*) The compiler is within its rights to reload a variable, for example,
1392 in cases where high register pressure prevents the compiler from
1393 keeping all data of interest in registers. The compiler might
1394 therefore optimize the variable 'tmp' out of our previous example:
1397 do_something_with(tmp);
1399 This could result in the following code, which is perfectly safe in
1400 single-threaded code, but can be fatal in concurrent code:
1403 do_something_with(a);
1405 For example, the optimized version of this code could result in
1406 passing a zero to do_something_with() in the case where the variable
1407 a was modified by some other CPU between the "while" statement and
1408 the call to do_something_with().
1410 Again, use READ_ONCE() to prevent the compiler from doing this:
1412 while (tmp = READ_ONCE(a))
1413 do_something_with(tmp);
1415 Note that if the compiler runs short of registers, it might save
1416 tmp onto the stack. The overhead of this saving and later restoring
1417 is why compilers reload variables. Doing so is perfectly safe for
1418 single-threaded code, so you need to tell the compiler about cases
1419 where it is not safe.
1421 (*) The compiler is within its rights to omit a load entirely if it knows
1422 what the value will be. For example, if the compiler can prove that
1423 the value of variable 'a' is always zero, it can optimize this code:
1426 do_something_with(tmp);
1432 This transformation is a win for single-threaded code because it
1433 gets rid of a load and a branch. The problem is that the compiler
1434 will carry out its proof assuming that the current CPU is the only
1435 one updating variable 'a'. If variable 'a' is shared, then the
1436 compiler's proof will be erroneous. Use READ_ONCE() to tell the
1437 compiler that it doesn't know as much as it thinks it does:
1439 while (tmp = READ_ONCE(a))
1440 do_something_with(tmp);
1442 But please note that the compiler is also closely watching what you
1443 do with the value after the READ_ONCE(). For example, suppose you
1444 do the following and MAX is a preprocessor macro with the value 1:
1446 while ((tmp = READ_ONCE(a)) % MAX)
1447 do_something_with(tmp);
1449 Then the compiler knows that the result of the "%" operator applied
1450 to MAX will always be zero, again allowing the compiler to optimize
1451 the code into near-nonexistence. (It will still load from the
1454 (*) Similarly, the compiler is within its rights to omit a store entirely
1455 if it knows that the variable already has the value being stored.
1456 Again, the compiler assumes that the current CPU is the only one
1457 storing into the variable, which can cause the compiler to do the
1458 wrong thing for shared variables. For example, suppose you have
1462 /* Code that does not store to variable a. */
1465 The compiler sees that the value of variable 'a' is already zero, so
1466 it might well omit the second store. This would come as a fatal
1467 surprise if some other CPU might have stored to variable 'a' in the
1470 Use WRITE_ONCE() to prevent the compiler from making this sort of
1474 /* Code that does not store to variable a. */
1477 (*) The compiler is within its rights to reorder memory accesses unless
1478 you tell it not to. For example, consider the following interaction
1479 between process-level code and an interrupt handler:
1481 void process_level(void)
1483 msg = get_message();
1487 void interrupt_handler(void)
1490 process_message(msg);
1493 There is nothing to prevent the compiler from transforming
1494 process_level() to the following, in fact, this might well be a
1495 win for single-threaded code:
1497 void process_level(void)
1500 msg = get_message();
1503 If the interrupt occurs between these two statement, then
1504 interrupt_handler() might be passed a garbled msg. Use WRITE_ONCE()
1505 to prevent this as follows:
1507 void process_level(void)
1509 WRITE_ONCE(msg, get_message());
1510 WRITE_ONCE(flag, true);
1513 void interrupt_handler(void)
1515 if (READ_ONCE(flag))
1516 process_message(READ_ONCE(msg));
1519 Note that the READ_ONCE() and WRITE_ONCE() wrappers in
1520 interrupt_handler() are needed if this interrupt handler can itself
1521 be interrupted by something that also accesses 'flag' and 'msg',
1522 for example, a nested interrupt or an NMI. Otherwise, READ_ONCE()
1523 and WRITE_ONCE() are not needed in interrupt_handler() other than
1524 for documentation purposes. (Note also that nested interrupts
1525 do not typically occur in modern Linux kernels, in fact, if an
1526 interrupt handler returns with interrupts enabled, you will get a
1529 You should assume that the compiler can move READ_ONCE() and
1530 WRITE_ONCE() past code not containing READ_ONCE(), WRITE_ONCE(),
1531 barrier(), or similar primitives.
1533 This effect could also be achieved using barrier(), but READ_ONCE()
1534 and WRITE_ONCE() are more selective: With READ_ONCE() and
1535 WRITE_ONCE(), the compiler need only forget the contents of the
1536 indicated memory locations, while with barrier() the compiler must
1537 discard the value of all memory locations that it has currented
1538 cached in any machine registers. Of course, the compiler must also
1539 respect the order in which the READ_ONCE()s and WRITE_ONCE()s occur,
1540 though the CPU of course need not do so.
1542 (*) The compiler is within its rights to invent stores to a variable,
1543 as in the following example:
1550 The compiler might save a branch by optimizing this as follows:
1556 In single-threaded code, this is not only safe, but also saves
1557 a branch. Unfortunately, in concurrent code, this optimization
1558 could cause some other CPU to see a spurious value of 42 -- even
1559 if variable 'a' was never zero -- when loading variable 'b'.
1560 Use WRITE_ONCE() to prevent this as follows:
1567 The compiler can also invent loads. These are usually less
1568 damaging, but they can result in cache-line bouncing and thus in
1569 poor performance and scalability. Use READ_ONCE() to prevent
1572 (*) For aligned memory locations whose size allows them to be accessed
1573 with a single memory-reference instruction, prevents "load tearing"
1574 and "store tearing," in which a single large access is replaced by
1575 multiple smaller accesses. For example, given an architecture having
1576 16-bit store instructions with 7-bit immediate fields, the compiler
1577 might be tempted to use two 16-bit store-immediate instructions to
1578 implement the following 32-bit store:
1582 Please note that GCC really does use this sort of optimization,
1583 which is not surprising given that it would likely take more
1584 than two instructions to build the constant and then store it.
1585 This optimization can therefore be a win in single-threaded code.
1586 In fact, a recent bug (since fixed) caused GCC to incorrectly use
1587 this optimization in a volatile store. In the absence of such bugs,
1588 use of WRITE_ONCE() prevents store tearing in the following example:
1590 WRITE_ONCE(p, 0x00010002);
1592 Use of packed structures can also result in load and store tearing,
1595 struct __attribute__((__packed__)) foo {
1600 struct foo foo1, foo2;
1607 Because there are no READ_ONCE() or WRITE_ONCE() wrappers and no
1608 volatile markings, the compiler would be well within its rights to
1609 implement these three assignment statements as a pair of 32-bit
1610 loads followed by a pair of 32-bit stores. This would result in
1611 load tearing on 'foo1.b' and store tearing on 'foo2.b'. READ_ONCE()
1612 and WRITE_ONCE() again prevent tearing in this example:
1615 WRITE_ONCE(foo2.b, READ_ONCE(foo1.b));
1618 All that aside, it is never necessary to use READ_ONCE() and
1619 WRITE_ONCE() on a variable that has been marked volatile. For example,
1620 because 'jiffies' is marked volatile, it is never necessary to
1621 say READ_ONCE(jiffies). The reason for this is that READ_ONCE() and
1622 WRITE_ONCE() are implemented as volatile casts, which has no effect when
1623 its argument is already marked volatile.
1625 Please note that these compiler barriers have no direct effect on the CPU,
1626 which may then reorder things however it wishes.
1632 The Linux kernel has eight basic CPU memory barriers:
1634 TYPE MANDATORY SMP CONDITIONAL
1635 =============== ======================= ===========================
1636 GENERAL mb() smp_mb()
1637 WRITE wmb() smp_wmb()
1638 READ rmb() smp_rmb()
1639 DATA DEPENDENCY read_barrier_depends() smp_read_barrier_depends()
1642 All memory barriers except the data dependency barriers imply a compiler
1643 barrier. Data dependencies do not impose any additional compiler ordering.
1645 Aside: In the case of data dependencies, the compiler would be expected
1646 to issue the loads in the correct order (eg. `a[b]` would have to load
1647 the value of b before loading a[b]), however there is no guarantee in
1648 the C specification that the compiler may not speculate the value of b
1649 (eg. is equal to 1) and load a before b (eg. tmp = a[1]; if (b != 1)
1650 tmp = a[b]; ). There is also the problem of a compiler reloading b after
1651 having loaded a[b], thus having a newer copy of b than a[b]. A consensus
1652 has not yet been reached about these problems, however the READ_ONCE()
1653 macro is a good place to start looking.
1655 SMP memory barriers are reduced to compiler barriers on uniprocessor compiled
1656 systems because it is assumed that a CPU will appear to be self-consistent,
1657 and will order overlapping accesses correctly with respect to itself.
1659 [!] Note that SMP memory barriers _must_ be used to control the ordering of
1660 references to shared memory on SMP systems, though the use of locking instead
1663 Mandatory barriers should not be used to control SMP effects, since mandatory
1664 barriers unnecessarily impose overhead on UP systems. They may, however, be
1665 used to control MMIO effects on accesses through relaxed memory I/O windows.
1666 These are required even on non-SMP systems as they affect the order in which
1667 memory operations appear to a device by prohibiting both the compiler and the
1668 CPU from reordering them.
1671 There are some more advanced barrier functions:
1673 (*) smp_store_mb(var, value)
1675 This assigns the value to the variable and then inserts a full memory
1676 barrier after it, depending on the function. It isn't guaranteed to
1677 insert anything more than a compiler barrier in a UP compilation.
1680 (*) smp_mb__before_atomic();
1681 (*) smp_mb__after_atomic();
1683 These are for use with atomic (such as add, subtract, increment and
1684 decrement) functions that don't return a value, especially when used for
1685 reference counting. These functions do not imply memory barriers.
1687 These are also used for atomic bitop functions that do not return a
1688 value (such as set_bit and clear_bit).
1690 As an example, consider a piece of code that marks an object as being dead
1691 and then decrements the object's reference count:
1694 smp_mb__before_atomic();
1695 atomic_dec(&obj->ref_count);
1697 This makes sure that the death mark on the object is perceived to be set
1698 *before* the reference counter is decremented.
1700 See Documentation/atomic_ops.txt for more information. See the "Atomic
1701 operations" subsection for information on where to use these.
1704 (*) lockless_dereference();
1705 This can be thought of as a pointer-fetch wrapper around the
1706 smp_read_barrier_depends() data-dependency barrier.
1708 This is also similar to rcu_dereference(), but in cases where
1709 object lifetime is handled by some mechanism other than RCU, for
1710 example, when the objects removed only when the system goes down.
1711 In addition, lockless_dereference() is used in some data structures
1712 that can be used both with and without RCU.
1718 These are for use with consistent memory to guarantee the ordering
1719 of writes or reads of shared memory accessible to both the CPU and a
1722 For example, consider a device driver that shares memory with a device
1723 and uses a descriptor status value to indicate if the descriptor belongs
1724 to the device or the CPU, and a doorbell to notify it when new
1725 descriptors are available:
1727 if (desc->status != DEVICE_OWN) {
1728 /* do not read data until we own descriptor */
1731 /* read/modify data */
1732 read_data = desc->data;
1733 desc->data = write_data;
1735 /* flush modifications before status update */
1738 /* assign ownership */
1739 desc->status = DEVICE_OWN;
1741 /* force memory to sync before notifying device via MMIO */
1744 /* notify device of new descriptors */
1745 writel(DESC_NOTIFY, doorbell);
1748 The dma_rmb() allows us guarantee the device has released ownership
1749 before we read the data from the descriptor, and the dma_wmb() allows
1750 us to guarantee the data is written to the descriptor before the device
1751 can see it now has ownership. The wmb() is needed to guarantee that the
1752 cache coherent memory writes have completed before attempting a write to
1753 the cache incoherent MMIO region.
1755 See Documentation/DMA-API.txt for more information on consistent memory.
1760 The Linux kernel also has a special barrier for use with memory-mapped I/O
1765 This is a variation on the mandatory write barrier that causes writes to weakly
1766 ordered I/O regions to be partially ordered. Its effects may go beyond the
1767 CPU->Hardware interface and actually affect the hardware at some level.
1769 See the subsection "Locks vs I/O accesses" for more information.
1772 ===============================
1773 IMPLICIT KERNEL MEMORY BARRIERS
1774 ===============================
1776 Some of the other functions in the linux kernel imply memory barriers, amongst
1777 which are locking and scheduling functions.
1779 This specification is a _minimum_ guarantee; any particular architecture may
1780 provide more substantial guarantees, but these may not be relied upon outside
1781 of arch specific code.
1787 The Linux kernel has a number of locking constructs:
1795 In all cases there are variants on "ACQUIRE" operations and "RELEASE" operations
1796 for each construct. These operations all imply certain barriers:
1798 (1) ACQUIRE operation implication:
1800 Memory operations issued after the ACQUIRE will be completed after the
1801 ACQUIRE operation has completed.
1803 Memory operations issued before the ACQUIRE may be completed after
1804 the ACQUIRE operation has completed. An smp_mb__before_spinlock(),
1805 combined with a following ACQUIRE, orders prior stores against
1806 subsequent loads and stores. Note that this is weaker than smp_mb()!
1807 The smp_mb__before_spinlock() primitive is free on many architectures.
1809 (2) RELEASE operation implication:
1811 Memory operations issued before the RELEASE will be completed before the
1812 RELEASE operation has completed.
1814 Memory operations issued after the RELEASE may be completed before the
1815 RELEASE operation has completed.
1817 (3) ACQUIRE vs ACQUIRE implication:
1819 All ACQUIRE operations issued before another ACQUIRE operation will be
1820 completed before that ACQUIRE operation.
1822 (4) ACQUIRE vs RELEASE implication:
1824 All ACQUIRE operations issued before a RELEASE operation will be
1825 completed before the RELEASE operation.
1827 (5) Failed conditional ACQUIRE implication:
1829 Certain locking variants of the ACQUIRE operation may fail, either due to
1830 being unable to get the lock immediately, or due to receiving an unblocked
1831 signal whilst asleep waiting for the lock to become available. Failed
1832 locks do not imply any sort of barrier.
1834 [!] Note: one of the consequences of lock ACQUIREs and RELEASEs being only
1835 one-way barriers is that the effects of instructions outside of a critical
1836 section may seep into the inside of the critical section.
1838 An ACQUIRE followed by a RELEASE may not be assumed to be full memory barrier
1839 because it is possible for an access preceding the ACQUIRE to happen after the
1840 ACQUIRE, and an access following the RELEASE to happen before the RELEASE, and
1841 the two accesses can themselves then cross:
1850 ACQUIRE M, STORE *B, STORE *A, RELEASE M
1852 When the ACQUIRE and RELEASE are a lock acquisition and release,
1853 respectively, this same reordering can occur if the lock's ACQUIRE and
1854 RELEASE are to the same lock variable, but only from the perspective of
1855 another CPU not holding that lock. In short, a ACQUIRE followed by an
1856 RELEASE may -not- be assumed to be a full memory barrier.
1858 Similarly, the reverse case of a RELEASE followed by an ACQUIRE does
1859 not imply a full memory barrier. Therefore, the CPU's execution of the
1860 critical sections corresponding to the RELEASE and the ACQUIRE can cross,
1870 ACQUIRE N, STORE *B, STORE *A, RELEASE M
1872 It might appear that this reordering could introduce a deadlock.
1873 However, this cannot happen because if such a deadlock threatened,
1874 the RELEASE would simply complete, thereby avoiding the deadlock.
1878 One key point is that we are only talking about the CPU doing
1879 the reordering, not the compiler. If the compiler (or, for
1880 that matter, the developer) switched the operations, deadlock
1883 But suppose the CPU reordered the operations. In this case,
1884 the unlock precedes the lock in the assembly code. The CPU
1885 simply elected to try executing the later lock operation first.
1886 If there is a deadlock, this lock operation will simply spin (or
1887 try to sleep, but more on that later). The CPU will eventually
1888 execute the unlock operation (which preceded the lock operation
1889 in the assembly code), which will unravel the potential deadlock,
1890 allowing the lock operation to succeed.
1892 But what if the lock is a sleeplock? In that case, the code will
1893 try to enter the scheduler, where it will eventually encounter
1894 a memory barrier, which will force the earlier unlock operation
1895 to complete, again unraveling the deadlock. There might be
1896 a sleep-unlock race, but the locking primitive needs to resolve
1897 such races properly in any case.
1899 Locks and semaphores may not provide any guarantee of ordering on UP compiled
1900 systems, and so cannot be counted on in such a situation to actually achieve
1901 anything at all - especially with respect to I/O accesses - unless combined
1902 with interrupt disabling operations.
1904 See also the section on "Inter-CPU locking barrier effects".
1907 As an example, consider the following:
1918 The following sequence of events is acceptable:
1920 ACQUIRE, {*F,*A}, *E, {*C,*D}, *B, RELEASE
1922 [+] Note that {*F,*A} indicates a combined access.
1924 But none of the following are:
1926 {*F,*A}, *B, ACQUIRE, *C, *D, RELEASE, *E
1927 *A, *B, *C, ACQUIRE, *D, RELEASE, *E, *F
1928 *A, *B, ACQUIRE, *C, RELEASE, *D, *E, *F
1929 *B, ACQUIRE, *C, *D, RELEASE, {*F,*A}, *E
1933 INTERRUPT DISABLING FUNCTIONS
1934 -----------------------------
1936 Functions that disable interrupts (ACQUIRE equivalent) and enable interrupts
1937 (RELEASE equivalent) will act as compiler barriers only. So if memory or I/O
1938 barriers are required in such a situation, they must be provided from some
1942 SLEEP AND WAKE-UP FUNCTIONS
1943 ---------------------------
1945 Sleeping and waking on an event flagged in global data can be viewed as an
1946 interaction between two pieces of data: the task state of the task waiting for
1947 the event and the global data used to indicate the event. To make sure that
1948 these appear to happen in the right order, the primitives to begin the process
1949 of going to sleep, and the primitives to initiate a wake up imply certain
1952 Firstly, the sleeper normally follows something like this sequence of events:
1955 set_current_state(TASK_UNINTERRUPTIBLE);
1956 if (event_indicated)
1961 A general memory barrier is interpolated automatically by set_current_state()
1962 after it has altered the task state:
1965 ===============================
1966 set_current_state();
1968 STORE current->state
1970 LOAD event_indicated
1972 set_current_state() may be wrapped by:
1975 prepare_to_wait_exclusive();
1977 which therefore also imply a general memory barrier after setting the state.
1978 The whole sequence above is available in various canned forms, all of which
1979 interpolate the memory barrier in the right place:
1982 wait_event_interruptible();
1983 wait_event_interruptible_exclusive();
1984 wait_event_interruptible_timeout();
1985 wait_event_killable();
1986 wait_event_timeout();
1991 Secondly, code that performs a wake up normally follows something like this:
1993 event_indicated = 1;
1994 wake_up(&event_wait_queue);
1998 event_indicated = 1;
1999 wake_up_process(event_daemon);
2001 A write memory barrier is implied by wake_up() and co. if and only if they wake
2002 something up. The barrier occurs before the task state is cleared, and so sits
2003 between the STORE to indicate the event and the STORE to set TASK_RUNNING:
2006 =============================== ===============================
2007 set_current_state(); STORE event_indicated
2008 smp_store_mb(); wake_up();
2009 STORE current->state <write barrier>
2010 <general barrier> STORE current->state
2011 LOAD event_indicated
2013 To repeat, this write memory barrier is present if and only if something
2014 is actually awakened. To see this, consider the following sequence of
2015 events, where X and Y are both initially zero:
2018 =============================== ===============================
2019 X = 1; STORE event_indicated
2020 smp_mb(); wake_up();
2021 Y = 1; wait_event(wq, Y == 1);
2022 wake_up(); load from Y sees 1, no memory barrier
2023 load from X might see 0
2025 In contrast, if a wakeup does occur, CPU 2's load from X would be guaranteed
2028 The available waker functions include:
2034 wake_up_interruptible();
2035 wake_up_interruptible_all();
2036 wake_up_interruptible_nr();
2037 wake_up_interruptible_poll();
2038 wake_up_interruptible_sync();
2039 wake_up_interruptible_sync_poll();
2041 wake_up_locked_poll();
2047 [!] Note that the memory barriers implied by the sleeper and the waker do _not_
2048 order multiple stores before the wake-up with respect to loads of those stored
2049 values after the sleeper has called set_current_state(). For instance, if the
2052 set_current_state(TASK_INTERRUPTIBLE);
2053 if (event_indicated)
2055 __set_current_state(TASK_RUNNING);
2056 do_something(my_data);
2061 event_indicated = 1;
2062 wake_up(&event_wait_queue);
2064 there's no guarantee that the change to event_indicated will be perceived by
2065 the sleeper as coming after the change to my_data. In such a circumstance, the
2066 code on both sides must interpolate its own memory barriers between the
2067 separate data accesses. Thus the above sleeper ought to do:
2069 set_current_state(TASK_INTERRUPTIBLE);
2070 if (event_indicated) {
2072 do_something(my_data);
2075 and the waker should do:
2079 event_indicated = 1;
2080 wake_up(&event_wait_queue);
2083 MISCELLANEOUS FUNCTIONS
2084 -----------------------
2086 Other functions that imply barriers:
2088 (*) schedule() and similar imply full memory barriers.
2091 ===================================
2092 INTER-CPU ACQUIRING BARRIER EFFECTS
2093 ===================================
2095 On SMP systems locking primitives give a more substantial form of barrier: one
2096 that does affect memory access ordering on other CPUs, within the context of
2097 conflict on any particular lock.
2100 ACQUIRES VS MEMORY ACCESSES
2101 ---------------------------
2103 Consider the following: the system has a pair of spinlocks (M) and (Q), and
2104 three CPUs; then should the following sequence of events occur:
2107 =============================== ===============================
2108 WRITE_ONCE(*A, a); WRITE_ONCE(*E, e);
2110 WRITE_ONCE(*B, b); WRITE_ONCE(*F, f);
2111 WRITE_ONCE(*C, c); WRITE_ONCE(*G, g);
2113 WRITE_ONCE(*D, d); WRITE_ONCE(*H, h);
2115 Then there is no guarantee as to what order CPU 3 will see the accesses to *A
2116 through *H occur in, other than the constraints imposed by the separate locks
2117 on the separate CPUs. It might, for example, see:
2119 *E, ACQUIRE M, ACQUIRE Q, *G, *C, *F, *A, *B, RELEASE Q, *D, *H, RELEASE M
2121 But it won't see any of:
2123 *B, *C or *D preceding ACQUIRE M
2124 *A, *B or *C following RELEASE M
2125 *F, *G or *H preceding ACQUIRE Q
2126 *E, *F or *G following RELEASE Q
2130 ACQUIRES VS I/O ACCESSES
2131 ------------------------
2133 Under certain circumstances (especially involving NUMA), I/O accesses within
2134 two spinlocked sections on two different CPUs may be seen as interleaved by the
2135 PCI bridge, because the PCI bridge does not necessarily participate in the
2136 cache-coherence protocol, and is therefore incapable of issuing the required
2137 read memory barriers.
2142 =============================== ===============================
2152 may be seen by the PCI bridge as follows:
2154 STORE *ADDR = 0, STORE *ADDR = 4, STORE *DATA = 1, STORE *DATA = 5
2156 which would probably cause the hardware to malfunction.
2159 What is necessary here is to intervene with an mmiowb() before dropping the
2160 spinlock, for example:
2163 =============================== ===============================
2175 this will ensure that the two stores issued on CPU 1 appear at the PCI bridge
2176 before either of the stores issued on CPU 2.
2179 Furthermore, following a store by a load from the same device obviates the need
2180 for the mmiowb(), because the load forces the store to complete before the load
2184 =============================== ===============================
2195 See Documentation/DocBook/deviceiobook.tmpl for more information.
2198 =================================
2199 WHERE ARE MEMORY BARRIERS NEEDED?
2200 =================================
2202 Under normal operation, memory operation reordering is generally not going to
2203 be a problem as a single-threaded linear piece of code will still appear to
2204 work correctly, even if it's in an SMP kernel. There are, however, four
2205 circumstances in which reordering definitely _could_ be a problem:
2207 (*) Interprocessor interaction.
2209 (*) Atomic operations.
2211 (*) Accessing devices.
2216 INTERPROCESSOR INTERACTION
2217 --------------------------
2219 When there's a system with more than one processor, more than one CPU in the
2220 system may be working on the same data set at the same time. This can cause
2221 synchronisation problems, and the usual way of dealing with them is to use
2222 locks. Locks, however, are quite expensive, and so it may be preferable to
2223 operate without the use of a lock if at all possible. In such a case
2224 operations that affect both CPUs may have to be carefully ordered to prevent
2227 Consider, for example, the R/W semaphore slow path. Here a waiting process is
2228 queued on the semaphore, by virtue of it having a piece of its stack linked to
2229 the semaphore's list of waiting processes:
2231 struct rw_semaphore {
2234 struct list_head waiters;
2237 struct rwsem_waiter {
2238 struct list_head list;
2239 struct task_struct *task;
2242 To wake up a particular waiter, the up_read() or up_write() functions have to:
2244 (1) read the next pointer from this waiter's record to know as to where the
2245 next waiter record is;
2247 (2) read the pointer to the waiter's task structure;
2249 (3) clear the task pointer to tell the waiter it has been given the semaphore;
2251 (4) call wake_up_process() on the task; and
2253 (5) release the reference held on the waiter's task struct.
2255 In other words, it has to perform this sequence of events:
2257 LOAD waiter->list.next;
2263 and if any of these steps occur out of order, then the whole thing may
2266 Once it has queued itself and dropped the semaphore lock, the waiter does not
2267 get the lock again; it instead just waits for its task pointer to be cleared
2268 before proceeding. Since the record is on the waiter's stack, this means that
2269 if the task pointer is cleared _before_ the next pointer in the list is read,
2270 another CPU might start processing the waiter and might clobber the waiter's
2271 stack before the up*() function has a chance to read the next pointer.
2273 Consider then what might happen to the above sequence of events:
2276 =============================== ===============================
2283 Woken up by other event
2288 foo() clobbers *waiter
2290 LOAD waiter->list.next;
2293 This could be dealt with using the semaphore lock, but then the down_xxx()
2294 function has to needlessly get the spinlock again after being woken up.
2296 The way to deal with this is to insert a general SMP memory barrier:
2298 LOAD waiter->list.next;
2305 In this case, the barrier makes a guarantee that all memory accesses before the
2306 barrier will appear to happen before all the memory accesses after the barrier
2307 with respect to the other CPUs on the system. It does _not_ guarantee that all
2308 the memory accesses before the barrier will be complete by the time the barrier
2309 instruction itself is complete.
2311 On a UP system - where this wouldn't be a problem - the smp_mb() is just a
2312 compiler barrier, thus making sure the compiler emits the instructions in the
2313 right order without actually intervening in the CPU. Since there's only one
2314 CPU, that CPU's dependency ordering logic will take care of everything else.
2320 Whilst they are technically interprocessor interaction considerations, atomic
2321 operations are noted specially as some of them imply full memory barriers and
2322 some don't, but they're very heavily relied on as a group throughout the
2325 Any atomic operation that modifies some state in memory and returns information
2326 about the state (old or new) implies an SMP-conditional general memory barrier
2327 (smp_mb()) on each side of the actual operation (with the exception of
2328 explicit lock operations, described later). These include:
2331 atomic_xchg(); atomic_long_xchg();
2332 atomic_inc_return(); atomic_long_inc_return();
2333 atomic_dec_return(); atomic_long_dec_return();
2334 atomic_add_return(); atomic_long_add_return();
2335 atomic_sub_return(); atomic_long_sub_return();
2336 atomic_inc_and_test(); atomic_long_inc_and_test();
2337 atomic_dec_and_test(); atomic_long_dec_and_test();
2338 atomic_sub_and_test(); atomic_long_sub_and_test();
2339 atomic_add_negative(); atomic_long_add_negative();
2341 test_and_clear_bit();
2342 test_and_change_bit();
2346 atomic_cmpxchg(); atomic_long_cmpxchg();
2347 atomic_add_unless(); atomic_long_add_unless();
2349 These are used for such things as implementing ACQUIRE-class and RELEASE-class
2350 operations and adjusting reference counters towards object destruction, and as
2351 such the implicit memory barrier effects are necessary.
2354 The following operations are potential problems as they do _not_ imply memory
2355 barriers, but might be used for implementing such things as RELEASE-class
2363 With these the appropriate explicit memory barrier should be used if necessary
2364 (smp_mb__before_atomic() for instance).
2367 The following also do _not_ imply memory barriers, and so may require explicit
2368 memory barriers under some circumstances (smp_mb__before_atomic() for
2376 If they're used for statistics generation, then they probably don't need memory
2377 barriers, unless there's a coupling between statistical data.
2379 If they're used for reference counting on an object to control its lifetime,
2380 they probably don't need memory barriers because either the reference count
2381 will be adjusted inside a locked section, or the caller will already hold
2382 sufficient references to make the lock, and thus a memory barrier unnecessary.
2384 If they're used for constructing a lock of some description, then they probably
2385 do need memory barriers as a lock primitive generally has to do things in a
2388 Basically, each usage case has to be carefully considered as to whether memory
2389 barriers are needed or not.
2391 The following operations are special locking primitives:
2393 test_and_set_bit_lock();
2395 __clear_bit_unlock();
2397 These implement ACQUIRE-class and RELEASE-class operations. These should be used in
2398 preference to other operations when implementing locking primitives, because
2399 their implementations can be optimised on many architectures.
2401 [!] Note that special memory barrier primitives are available for these
2402 situations because on some CPUs the atomic instructions used imply full memory
2403 barriers, and so barrier instructions are superfluous in conjunction with them,
2404 and in such cases the special barrier primitives will be no-ops.
2406 See Documentation/atomic_ops.txt for more information.
2412 Many devices can be memory mapped, and so appear to the CPU as if they're just
2413 a set of memory locations. To control such a device, the driver usually has to
2414 make the right memory accesses in exactly the right order.
2416 However, having a clever CPU or a clever compiler creates a potential problem
2417 in that the carefully sequenced accesses in the driver code won't reach the
2418 device in the requisite order if the CPU or the compiler thinks it is more
2419 efficient to reorder, combine or merge accesses - something that would cause
2420 the device to malfunction.
2422 Inside of the Linux kernel, I/O should be done through the appropriate accessor
2423 routines - such as inb() or writel() - which know how to make such accesses
2424 appropriately sequential. Whilst this, for the most part, renders the explicit
2425 use of memory barriers unnecessary, there are a couple of situations where they
2428 (1) On some systems, I/O stores are not strongly ordered across all CPUs, and
2429 so for _all_ general drivers locks should be used and mmiowb() must be
2430 issued prior to unlocking the critical section.
2432 (2) If the accessor functions are used to refer to an I/O memory window with
2433 relaxed memory access properties, then _mandatory_ memory barriers are
2434 required to enforce ordering.
2436 See Documentation/DocBook/deviceiobook.tmpl for more information.
2442 A driver may be interrupted by its own interrupt service routine, and thus the
2443 two parts of the driver may interfere with each other's attempts to control or
2446 This may be alleviated - at least in part - by disabling local interrupts (a
2447 form of locking), such that the critical operations are all contained within
2448 the interrupt-disabled section in the driver. Whilst the driver's interrupt
2449 routine is executing, the driver's core may not run on the same CPU, and its
2450 interrupt is not permitted to happen again until the current interrupt has been
2451 handled, thus the interrupt handler does not need to lock against that.
2453 However, consider a driver that was talking to an ethernet card that sports an
2454 address register and a data register. If that driver's core talks to the card
2455 under interrupt-disablement and then the driver's interrupt handler is invoked:
2466 The store to the data register might happen after the second store to the
2467 address register if ordering rules are sufficiently relaxed:
2469 STORE *ADDR = 3, STORE *ADDR = 4, STORE *DATA = y, q = LOAD *DATA
2472 If ordering rules are relaxed, it must be assumed that accesses done inside an
2473 interrupt disabled section may leak outside of it and may interleave with
2474 accesses performed in an interrupt - and vice versa - unless implicit or
2475 explicit barriers are used.
2477 Normally this won't be a problem because the I/O accesses done inside such
2478 sections will include synchronous load operations on strictly ordered I/O
2479 registers that form implicit I/O barriers. If this isn't sufficient then an
2480 mmiowb() may need to be used explicitly.
2483 A similar situation may occur between an interrupt routine and two routines
2484 running on separate CPUs that communicate with each other. If such a case is
2485 likely, then interrupt-disabling locks should be used to guarantee ordering.
2488 ==========================
2489 KERNEL I/O BARRIER EFFECTS
2490 ==========================
2492 When accessing I/O memory, drivers should use the appropriate accessor
2497 These are intended to talk to I/O space rather than memory space, but
2498 that's primarily a CPU-specific concept. The i386 and x86_64 processors do
2499 indeed have special I/O space access cycles and instructions, but many
2500 CPUs don't have such a concept.
2502 The PCI bus, amongst others, defines an I/O space concept which - on such
2503 CPUs as i386 and x86_64 - readily maps to the CPU's concept of I/O
2504 space. However, it may also be mapped as a virtual I/O space in the CPU's
2505 memory map, particularly on those CPUs that don't support alternate I/O
2508 Accesses to this space may be fully synchronous (as on i386), but
2509 intermediary bridges (such as the PCI host bridge) may not fully honour
2512 They are guaranteed to be fully ordered with respect to each other.
2514 They are not guaranteed to be fully ordered with respect to other types of
2515 memory and I/O operation.
2517 (*) readX(), writeX():
2519 Whether these are guaranteed to be fully ordered and uncombined with
2520 respect to each other on the issuing CPU depends on the characteristics
2521 defined for the memory window through which they're accessing. On later
2522 i386 architecture machines, for example, this is controlled by way of the
2525 Ordinarily, these will be guaranteed to be fully ordered and uncombined,
2526 provided they're not accessing a prefetchable device.
2528 However, intermediary hardware (such as a PCI bridge) may indulge in
2529 deferral if it so wishes; to flush a store, a load from the same location
2530 is preferred[*], but a load from the same device or from configuration
2531 space should suffice for PCI.
2533 [*] NOTE! attempting to load from the same location as was written to may
2534 cause a malfunction - consider the 16550 Rx/Tx serial registers for
2537 Used with prefetchable I/O memory, an mmiowb() barrier may be required to
2538 force stores to be ordered.
2540 Please refer to the PCI specification for more information on interactions
2541 between PCI transactions.
2543 (*) readX_relaxed(), writeX_relaxed()
2545 These are similar to readX() and writeX(), but provide weaker memory
2546 ordering guarantees. Specifically, they do not guarantee ordering with
2547 respect to normal memory accesses (e.g. DMA buffers) nor do they guarantee
2548 ordering with respect to LOCK or UNLOCK operations. If the latter is
2549 required, an mmiowb() barrier can be used. Note that relaxed accesses to
2550 the same peripheral are guaranteed to be ordered with respect to each
2553 (*) ioreadX(), iowriteX()
2555 These will perform appropriately for the type of access they're actually
2556 doing, be it inX()/outX() or readX()/writeX().
2559 ========================================
2560 ASSUMED MINIMUM EXECUTION ORDERING MODEL
2561 ========================================
2563 It has to be assumed that the conceptual CPU is weakly-ordered but that it will
2564 maintain the appearance of program causality with respect to itself. Some CPUs
2565 (such as i386 or x86_64) are more constrained than others (such as powerpc or
2566 frv), and so the most relaxed case (namely DEC Alpha) must be assumed outside
2567 of arch-specific code.
2569 This means that it must be considered that the CPU will execute its instruction
2570 stream in any order it feels like - or even in parallel - provided that if an
2571 instruction in the stream depends on an earlier instruction, then that
2572 earlier instruction must be sufficiently complete[*] before the later
2573 instruction may proceed; in other words: provided that the appearance of
2574 causality is maintained.
2576 [*] Some instructions have more than one effect - such as changing the
2577 condition codes, changing registers or changing memory - and different
2578 instructions may depend on different effects.
2580 A CPU may also discard any instruction sequence that winds up having no
2581 ultimate effect. For example, if two adjacent instructions both load an
2582 immediate value into the same register, the first may be discarded.
2585 Similarly, it has to be assumed that compiler might reorder the instruction
2586 stream in any way it sees fit, again provided the appearance of causality is
2590 ============================
2591 THE EFFECTS OF THE CPU CACHE
2592 ============================
2594 The way cached memory operations are perceived across the system is affected to
2595 a certain extent by the caches that lie between CPUs and memory, and by the
2596 memory coherence system that maintains the consistency of state in the system.
2598 As far as the way a CPU interacts with another part of the system through the
2599 caches goes, the memory system has to include the CPU's caches, and memory
2600 barriers for the most part act at the interface between the CPU and its cache
2601 (memory barriers logically act on the dotted line in the following diagram):
2603 <--- CPU ---> : <----------- Memory ----------->
2605 +--------+ +--------+ : +--------+ +-----------+
2606 | | | | : | | | | +--------+
2607 | CPU | | Memory | : | CPU | | | | |
2608 | Core |--->| Access |----->| Cache |<-->| | | |
2609 | | | Queue | : | | | |--->| Memory |
2610 | | | | : | | | | | |
2611 +--------+ +--------+ : +--------+ | | | |
2612 : | Cache | +--------+
2614 : | Mechanism | +--------+
2615 +--------+ +--------+ : +--------+ | | | |
2616 | | | | : | | | | | |
2617 | CPU | | Memory | : | CPU | | |--->| Device |
2618 | Core |--->| Access |----->| Cache |<-->| | | |
2619 | | | Queue | : | | | | | |
2620 | | | | : | | | | +--------+
2621 +--------+ +--------+ : +--------+ +-----------+
2625 Although any particular load or store may not actually appear outside of the
2626 CPU that issued it since it may have been satisfied within the CPU's own cache,
2627 it will still appear as if the full memory access had taken place as far as the
2628 other CPUs are concerned since the cache coherency mechanisms will migrate the
2629 cacheline over to the accessing CPU and propagate the effects upon conflict.
2631 The CPU core may execute instructions in any order it deems fit, provided the
2632 expected program causality appears to be maintained. Some of the instructions
2633 generate load and store operations which then go into the queue of memory
2634 accesses to be performed. The core may place these in the queue in any order
2635 it wishes, and continue execution until it is forced to wait for an instruction
2638 What memory barriers are concerned with is controlling the order in which
2639 accesses cross from the CPU side of things to the memory side of things, and
2640 the order in which the effects are perceived to happen by the other observers
2643 [!] Memory barriers are _not_ needed within a given CPU, as CPUs always see
2644 their own loads and stores as if they had happened in program order.
2646 [!] MMIO or other device accesses may bypass the cache system. This depends on
2647 the properties of the memory window through which devices are accessed and/or
2648 the use of any special device communication instructions the CPU may have.
2654 Life isn't quite as simple as it may appear above, however: for while the
2655 caches are expected to be coherent, there's no guarantee that that coherency
2656 will be ordered. This means that whilst changes made on one CPU will
2657 eventually become visible on all CPUs, there's no guarantee that they will
2658 become apparent in the same order on those other CPUs.
2661 Consider dealing with a system that has a pair of CPUs (1 & 2), each of which
2662 has a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D):
2667 +--------+ : +--->| Cache A |<------->| |
2668 | | : | +---------+ | |
2670 | | : | +---------+ | |
2671 +--------+ : +--->| Cache B |<------->| |
2674 : +---------+ | System |
2675 +--------+ : +--->| Cache C |<------->| |
2676 | | : | +---------+ | |
2678 | | : | +---------+ | |
2679 +--------+ : +--->| Cache D |<------->| |
2684 Imagine the system has the following properties:
2686 (*) an odd-numbered cache line may be in cache A, cache C or it may still be
2689 (*) an even-numbered cache line may be in cache B, cache D or it may still be
2692 (*) whilst the CPU core is interrogating one cache, the other cache may be
2693 making use of the bus to access the rest of the system - perhaps to
2694 displace a dirty cacheline or to do a speculative load;
2696 (*) each cache has a queue of operations that need to be applied to that cache
2697 to maintain coherency with the rest of the system;
2699 (*) the coherency queue is not flushed by normal loads to lines already
2700 present in the cache, even though the contents of the queue may
2701 potentially affect those loads.
2703 Imagine, then, that two writes are made on the first CPU, with a write barrier
2704 between them to guarantee that they will appear to reach that CPU's caches in
2705 the requisite order:
2708 =============== =============== =======================================
2709 u == 0, v == 1 and p == &u, q == &u
2711 smp_wmb(); Make sure change to v is visible before
2713 <A:modify v=2> v is now in cache A exclusively
2715 <B:modify p=&v> p is now in cache B exclusively
2717 The write memory barrier forces the other CPUs in the system to perceive that
2718 the local CPU's caches have apparently been updated in the correct order. But
2719 now imagine that the second CPU wants to read those values:
2722 =============== =============== =======================================
2727 The above pair of reads may then fail to happen in the expected order, as the
2728 cacheline holding p may get updated in one of the second CPU's caches whilst
2729 the update to the cacheline holding v is delayed in the other of the second
2730 CPU's caches by some other cache event:
2733 =============== =============== =======================================
2734 u == 0, v == 1 and p == &u, q == &u
2737 <A:modify v=2> <C:busy>
2741 <B:modify p=&v> <D:commit p=&v>
2744 <C:read *q> Reads from v before v updated in cache
2748 Basically, whilst both cachelines will be updated on CPU 2 eventually, there's
2749 no guarantee that, without intervention, the order of update will be the same
2750 as that committed on CPU 1.
2753 To intervene, we need to interpolate a data dependency barrier or a read
2754 barrier between the loads. This will force the cache to commit its coherency
2755 queue before processing any further requests:
2758 =============== =============== =======================================
2759 u == 0, v == 1 and p == &u, q == &u
2762 <A:modify v=2> <C:busy>
2766 <B:modify p=&v> <D:commit p=&v>
2768 smp_read_barrier_depends()
2772 <C:read *q> Reads from v after v updated in cache
2775 This sort of problem can be encountered on DEC Alpha processors as they have a
2776 split cache that improves performance by making better use of the data bus.
2777 Whilst most CPUs do imply a data dependency barrier on the read when a memory
2778 access depends on a read, not all do, so it may not be relied on.
2780 Other CPUs may also have split caches, but must coordinate between the various
2781 cachelets for normal memory accesses. The semantics of the Alpha removes the
2782 need for coordination in the absence of memory barriers.
2785 CACHE COHERENCY VS DMA
2786 ----------------------
2788 Not all systems maintain cache coherency with respect to devices doing DMA. In
2789 such cases, a device attempting DMA may obtain stale data from RAM because
2790 dirty cache lines may be resident in the caches of various CPUs, and may not
2791 have been written back to RAM yet. To deal with this, the appropriate part of
2792 the kernel must flush the overlapping bits of cache on each CPU (and maybe
2793 invalidate them as well).
2795 In addition, the data DMA'd to RAM by a device may be overwritten by dirty
2796 cache lines being written back to RAM from a CPU's cache after the device has
2797 installed its own data, or cache lines present in the CPU's cache may simply
2798 obscure the fact that RAM has been updated, until at such time as the cacheline
2799 is discarded from the CPU's cache and reloaded. To deal with this, the
2800 appropriate part of the kernel must invalidate the overlapping bits of the
2803 See Documentation/cachetlb.txt for more information on cache management.
2806 CACHE COHERENCY VS MMIO
2807 -----------------------
2809 Memory mapped I/O usually takes place through memory locations that are part of
2810 a window in the CPU's memory space that has different properties assigned than
2811 the usual RAM directed window.
2813 Amongst these properties is usually the fact that such accesses bypass the
2814 caching entirely and go directly to the device buses. This means MMIO accesses
2815 may, in effect, overtake accesses to cached memory that were emitted earlier.
2816 A memory barrier isn't sufficient in such a case, but rather the cache must be
2817 flushed between the cached memory write and the MMIO access if the two are in
2821 =========================
2822 THE THINGS CPUS GET UP TO
2823 =========================
2825 A programmer might take it for granted that the CPU will perform memory
2826 operations in exactly the order specified, so that if the CPU is, for example,
2827 given the following piece of code to execute:
2835 they would then expect that the CPU will complete the memory operation for each
2836 instruction before moving on to the next one, leading to a definite sequence of
2837 operations as seen by external observers in the system:
2839 LOAD *A, STORE *B, LOAD *C, LOAD *D, STORE *E.
2842 Reality is, of course, much messier. With many CPUs and compilers, the above
2843 assumption doesn't hold because:
2845 (*) loads are more likely to need to be completed immediately to permit
2846 execution progress, whereas stores can often be deferred without a
2849 (*) loads may be done speculatively, and the result discarded should it prove
2850 to have been unnecessary;
2852 (*) loads may be done speculatively, leading to the result having been fetched
2853 at the wrong time in the expected sequence of events;
2855 (*) the order of the memory accesses may be rearranged to promote better use
2856 of the CPU buses and caches;
2858 (*) loads and stores may be combined to improve performance when talking to
2859 memory or I/O hardware that can do batched accesses of adjacent locations,
2860 thus cutting down on transaction setup costs (memory and PCI devices may
2861 both be able to do this); and
2863 (*) the CPU's data cache may affect the ordering, and whilst cache-coherency
2864 mechanisms may alleviate this - once the store has actually hit the cache
2865 - there's no guarantee that the coherency management will be propagated in
2866 order to other CPUs.
2868 So what another CPU, say, might actually observe from the above piece of code
2871 LOAD *A, ..., LOAD {*C,*D}, STORE *E, STORE *B
2873 (Where "LOAD {*C,*D}" is a combined load)
2876 However, it is guaranteed that a CPU will be self-consistent: it will see its
2877 _own_ accesses appear to be correctly ordered, without the need for a memory
2878 barrier. For instance with the following code:
2887 and assuming no intervention by an external influence, it can be assumed that
2888 the final result will appear to be:
2890 U == the original value of *A
2895 The code above may cause the CPU to generate the full sequence of memory
2898 U=LOAD *A, STORE *A=V, STORE *A=W, X=LOAD *A, STORE *A=Y, Z=LOAD *A
2900 in that order, but, without intervention, the sequence may have almost any
2901 combination of elements combined or discarded, provided the program's view
2902 of the world remains consistent. Note that READ_ONCE() and WRITE_ONCE()
2903 are -not- optional in the above example, as there are architectures
2904 where a given CPU might reorder successive loads to the same location.
2905 On such architectures, READ_ONCE() and WRITE_ONCE() do whatever is
2906 necessary to prevent this, for example, on Itanium the volatile casts
2907 used by READ_ONCE() and WRITE_ONCE() cause GCC to emit the special ld.acq
2908 and st.rel instructions (respectively) that prevent such reordering.
2910 The compiler may also combine, discard or defer elements of the sequence before
2911 the CPU even sees them.
2922 since, without either a write barrier or an WRITE_ONCE(), it can be
2923 assumed that the effect of the storage of V to *A is lost. Similarly:
2928 may, without a memory barrier or an READ_ONCE() and WRITE_ONCE(), be
2934 and the LOAD operation never appear outside of the CPU.
2937 AND THEN THERE'S THE ALPHA
2938 --------------------------
2940 The DEC Alpha CPU is one of the most relaxed CPUs there is. Not only that,
2941 some versions of the Alpha CPU have a split data cache, permitting them to have
2942 two semantically-related cache lines updated at separate times. This is where
2943 the data dependency barrier really becomes necessary as this synchronises both
2944 caches with the memory coherence system, thus making it seem like pointer
2945 changes vs new data occur in the right order.
2947 The Alpha defines the Linux kernel's memory barrier model.
2949 See the subsection on "Cache Coherency" above.
2959 Memory barriers can be used to implement circular buffering without the need
2960 of a lock to serialise the producer with the consumer. See:
2962 Documentation/circular-buffers.txt
2971 Alpha AXP Architecture Reference Manual, Second Edition (Sites & Witek,
2973 Chapter 5.2: Physical Address Space Characteristics
2974 Chapter 5.4: Caches and Write Buffers
2975 Chapter 5.5: Data Sharing
2976 Chapter 5.6: Read/Write Ordering
2978 AMD64 Architecture Programmer's Manual Volume 2: System Programming
2979 Chapter 7.1: Memory-Access Ordering
2980 Chapter 7.4: Buffering and Combining Memory Writes
2982 IA-32 Intel Architecture Software Developer's Manual, Volume 3:
2983 System Programming Guide
2984 Chapter 7.1: Locked Atomic Operations
2985 Chapter 7.2: Memory Ordering
2986 Chapter 7.4: Serializing Instructions
2988 The SPARC Architecture Manual, Version 9
2989 Chapter 8: Memory Models
2990 Appendix D: Formal Specification of the Memory Models
2991 Appendix J: Programming with the Memory Models
2993 UltraSPARC Programmer Reference Manual
2994 Chapter 5: Memory Accesses and Cacheability
2995 Chapter 15: Sparc-V9 Memory Models
2997 UltraSPARC III Cu User's Manual
2998 Chapter 9: Memory Models
3000 UltraSPARC IIIi Processor User's Manual
3001 Chapter 8: Memory Models
3003 UltraSPARC Architecture 2005
3005 Appendix D: Formal Specifications of the Memory Models
3007 UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005
3008 Chapter 8: Memory Models
3009 Appendix F: Caches and Cache Coherency
3011 Solaris Internals, Core Kernel Architecture, p63-68:
3012 Chapter 3.3: Hardware Considerations for Locks and
3015 Unix Systems for Modern Architectures, Symmetric Multiprocessing and Caching
3016 for Kernel Programmers:
3017 Chapter 13: Other Memory Models
3019 Intel Itanium Architecture Software Developer's Manual: Volume 1:
3020 Section 2.6: Speculation
3021 Section 4.4: Memory Access
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