arch/arc/Kconfig

   1 #
   2 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   3 #
   4 # This program is free software; you can redistribute it and/or modify
   5 # it under the terms of the GNU General Public License version 2 as
   6 # published by the Free Software Foundation.
   7 #
   8
   9 config ARC
  10         def_bool y
  11         select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
  12         select BUILDTIME_EXTABLE_SORT
  13         select CLKSRC_OF
  14         select CLONE_BACKWARDS
  15         select COMMON_CLK
  16         select GENERIC_ATOMIC64
  17         select GENERIC_CLOCKEVENTS
  18         select GENERIC_FIND_FIRST_BIT
  19         # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
  20         select GENERIC_IRQ_SHOW
  21         select GENERIC_PCI_IOMAP
  22         select GENERIC_PENDING_IRQ if SMP
  23         select GENERIC_SMP_IDLE_THREAD
  24         select HAVE_ARCH_KGDB
  25         select HAVE_ARCH_TRACEHOOK
  26         select HAVE_FUTEX_CMPXCHG
  27         select HAVE_IOREMAP_PROT
  28         select HAVE_KPROBES
  29         select HAVE_KRETPROBES
  30         select HAVE_MEMBLOCK
  31         select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND
  32         select HAVE_OPROFILE
  33         select HAVE_PERF_EVENTS
  34         select HANDLE_DOMAIN_IRQ
  35         select IRQ_DOMAIN
  36         select MODULES_USE_ELF_RELA
  37         select NO_BOOTMEM
  38         select OF
  39         select OF_EARLY_FLATTREE
  40         select OF_RESERVED_MEM
  41         select PERF_USE_VMALLOC
  42         select HAVE_DEBUG_STACKOVERFLOW
  43         select HAVE_GENERIC_DMA_COHERENT
  44
  45 config MIGHT_HAVE_PCI
  46         bool
  47
  48 config TRACE_IRQFLAGS_SUPPORT
  49         def_bool y
  50
  51 config LOCKDEP_SUPPORT
  52         def_bool y
  53
  54 config SCHED_OMIT_FRAME_POINTER
  55         def_bool y
  56
  57 config GENERIC_CSUM
  58         def_bool y
  59
  60 config RWSEM_GENERIC_SPINLOCK
  61         def_bool y
  62
  63 config ARCH_DISCONTIGMEM_ENABLE
  64         def_bool n
  65
  66 config ARCH_FLATMEM_ENABLE
  67         def_bool y
  68
  69 config MMU
  70         def_bool y
  71
  72 config NO_IOPORT_MAP
  73         def_bool y
  74
  75 config GENERIC_CALIBRATE_DELAY
  76         def_bool y
  77
  78 config GENERIC_HWEIGHT
  79         def_bool y
  80
  81 config STACKTRACE_SUPPORT
  82         def_bool y
  83         select STACKTRACE
  84
  85 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
  86         def_bool y
  87         depends on ARC_MMU_V4
  88
  89 source "init/Kconfig"
  90 source "kernel/Kconfig.freezer"
  91
  92 menu "ARC Architecture Configuration"
  93
  94 menu "ARC Platform/SoC/Board"
  95
  96 source "arch/arc/plat-sim/Kconfig"
  97 source "arch/arc/plat-tb10x/Kconfig"
  98 source "arch/arc/plat-axs10x/Kconfig"
  99 #New platform adds here
 100 source "arch/arc/plat-eznps/Kconfig"
 101
 102 endmenu
 103
 104 choice
 105         prompt "ARC Instruction Set"
 106         default ISA_ARCOMPACT
 107
 108 config ISA_ARCOMPACT
 109         bool "ARCompact ISA"
 110         select CPU_NO_EFFICIENT_FFS
 111         help
 112           The original ARC ISA of ARC600/700 cores
 113
 114 config ISA_ARCV2
 115         bool "ARC ISA v2"
 116         help
 117           ISA for the Next Generation ARC-HS cores
 118
 119 endchoice
 120
 121 menu "ARC CPU Configuration"
 122
 123 choice
 124         prompt "ARC Core"
 125         default ARC_CPU_770 if ISA_ARCOMPACT
 126         default ARC_CPU_HS if ISA_ARCV2
 127
 128 if ISA_ARCOMPACT
 129
 130 config ARC_CPU_750D
 131         bool "ARC750D"
 132         select ARC_CANT_LLSC
 133         help
 134           Support for ARC750 core
 135
 136 config ARC_CPU_770
 137         bool "ARC770"
 138         select ARC_HAS_SWAPE
 139         help
 140           Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
 141           This core has a bunch of cool new features:
 142           -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
 143                    Shared Address Spaces (for sharing TLB entires in MMU)
 144           -Caches: New Prog Model, Region Flush
 145           -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
 146
 147 endif   #ISA_ARCOMPACT
 148
 149 config ARC_CPU_HS
 150         bool "ARC-HS"
 151         depends on ISA_ARCV2
 152         help
 153           Support for ARC HS38x Cores based on ARCv2 ISA
 154           The notable features are:
 155             - SMP configurations of upto 4 core with coherency
 156             - Optional L2 Cache and IO-Coherency
 157             - Revised Interrupt Architecture (multiple priorites, reg banks,
 158                 auto stack switch, auto regfile save/restore)
 159             - MMUv4 (PIPT dcache, Huge Pages)
 160             - Instructions for
 161                 * 64bit load/store: LDD, STD
 162                 * Hardware assisted divide/remainder: DIV, REM
 163                 * Function prologue/epilogue: ENTER_S, LEAVE_S
 164                 * IRQ enable/disable: CLRI, SETI
 165                 * pop count: FFS, FLS
 166                 * SETcc, BMSKN, XBFU...
 167
 168 endchoice
 169
 170 config CPU_BIG_ENDIAN
 171         bool "Enable Big Endian Mode"
 172         default n
 173         help
 174           Build kernel for Big Endian Mode of ARC CPU
 175
 176 config SMP
 177         bool "Symmetric Multi-Processing"
 178         default n
 179         select ARC_HAS_COH_CACHES if ISA_ARCV2
 180         select ARC_MCIP if ISA_ARCV2
 181         help
 182           This enables support for systems with more than one CPU.
 183
 184 if SMP
 185
 186 config ARC_HAS_COH_CACHES
 187         def_bool n
 188
 189 config ARC_MCIP
 190         bool "ARConnect Multicore IP (MCIP) Support "
 191         depends on ISA_ARCV2
 192         help
 193           This IP block enables SMP in ARC-HS38 cores.
 194           It provides for cross-core interrupts, multi-core debug
 195           hardware semaphores, shared memory,....
 196
 197 config NR_CPUS
 198         int "Maximum number of CPUs (2-4096)"
 199         range 2 4096
 200         default "4"
 201
 202 config ARC_SMP_HALT_ON_RESET
 203         bool "Enable Halt-on-reset boot mode"
 204         default y if ARC_UBOOT_SUPPORT
 205         help
 206           In SMP configuration cores can be configured as Halt-on-reset
 207           or they could all start at same time. For Halt-on-reset, non
 208           masters are parked until Master kicks them so they can start of
 209           at designated entry point. For other case, all jump to common
 210           entry point and spin wait for Master's signal.
 211
 212 endif   #SMP
 213
 214 menuconfig ARC_CACHE
 215         bool "Enable Cache Support"
 216         default y
 217         # if SMP, cache enabled ONLY if ARC implementation has cache coherency
 218         depends on !SMP || ARC_HAS_COH_CACHES
 219
 220 if ARC_CACHE
 221
 222 config ARC_CACHE_LINE_SHIFT
 223         int "Cache Line Length (as power of 2)"
 224         range 5 7
 225         default "6"
 226         help
 227           Starting with ARC700 4.9, Cache line length is configurable,
 228           This option specifies "N", with Line-len = 2 power N
 229           So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
 230           Linux only supports same line lengths for I and D caches.
 231
 232 config ARC_HAS_ICACHE
 233         bool "Use Instruction Cache"
 234         default y
 235
 236 config ARC_HAS_DCACHE
 237         bool "Use Data Cache"
 238         default y
 239
 240 config ARC_CACHE_PAGES
 241         bool "Per Page Cache Control"
 242         default y
 243         depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
 244         help
 245           This can be used to over-ride the global I/D Cache Enable on a
 246           per-page basis (but only for pages accessed via MMU such as
 247           Kernel Virtual address or User Virtual Address)
 248           TLB entries have a per-page Cache Enable Bit.
 249           Note that Global I/D ENABLE + Per Page DISABLE works but corollary
 250           Global DISABLE + Per Page ENABLE won't work
 251
 252 config ARC_CACHE_VIPT_ALIASING
 253         bool "Support VIPT Aliasing D$"
 254         depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
 255         default n
 256
 257 endif   #ARC_CACHE
 258
 259 config ARC_HAS_ICCM
 260         bool "Use ICCM"
 261         help
 262           Single Cycle RAMS to store Fast Path Code
 263         default n
 264
 265 config ARC_ICCM_SZ
 266         int "ICCM Size in KB"
 267         default "64"
 268         depends on ARC_HAS_ICCM
 269
 270 config ARC_HAS_DCCM
 271         bool "Use DCCM"
 272         help
 273           Single Cycle RAMS to store Fast Path Data
 274         default n
 275
 276 config ARC_DCCM_SZ
 277         int "DCCM Size in KB"
 278         default "64"
 279         depends on ARC_HAS_DCCM
 280
 281 config ARC_DCCM_BASE
 282         hex "DCCM map address"
 283         default "0xA0000000"
 284         depends on ARC_HAS_DCCM
 285
 286 choice
 287         prompt "MMU Version"
 288         default ARC_MMU_V3 if ARC_CPU_770
 289         default ARC_MMU_V2 if ARC_CPU_750D
 290         default ARC_MMU_V4 if ARC_CPU_HS
 291
 292 if ISA_ARCOMPACT
 293
 294 config ARC_MMU_V1
 295         bool "MMU v1"
 296         help
 297           Orig ARC700 MMU
 298
 299 config ARC_MMU_V2
 300         bool "MMU v2"
 301         help
 302           Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
 303           when 2 D-TLB and 1 I-TLB entries index into same 2way set.
 304
 305 config ARC_MMU_V3
 306         bool "MMU v3"
 307         depends on ARC_CPU_770
 308         help
 309           Introduced with ARC700 4.10: New Features
 310           Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
 311           Shared Address Spaces (SASID)
 312
 313 endif
 314
 315 config ARC_MMU_V4
 316         bool "MMU v4"
 317         depends on ISA_ARCV2
 318
 319 endchoice
 320
 321
 322 choice
 323         prompt "MMU Page Size"
 324         default ARC_PAGE_SIZE_8K
 325
 326 config ARC_PAGE_SIZE_8K
 327         bool "8KB"
 328         help
 329           Choose between 8k vs 16k
 330
 331 config ARC_PAGE_SIZE_16K
 332         bool "16KB"
 333         depends on ARC_MMU_V3 || ARC_MMU_V4
 334
 335 config ARC_PAGE_SIZE_4K
 336         bool "4KB"
 337         depends on ARC_MMU_V3 || ARC_MMU_V4
 338
 339 endchoice
 340
 341 choice
 342         prompt "MMU Super Page Size"
 343         depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
 344         default ARC_HUGEPAGE_2M
 345
 346 config ARC_HUGEPAGE_2M
 347         bool "2MB"
 348
 349 config ARC_HUGEPAGE_16M
 350         bool "16MB"
 351
 352 endchoice
 353
 354 config NODES_SHIFT
 355         int "Maximum NUMA Nodes (as a power of 2)"
 356         default "1" if !DISCONTIGMEM
 357         default "2" if DISCONTIGMEM
 358         depends on NEED_MULTIPLE_NODES
 359         ---help---
 360           Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory
 361           zones.
 362
 363 if ISA_ARCOMPACT
 364
 365 config ARC_COMPACT_IRQ_LEVELS
 366         bool "Setup Timer IRQ as high Priority"
 367         default n
 368         # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
 369         depends on !SMP
 370
 371 config ARC_FPU_SAVE_RESTORE
 372         bool "Enable FPU state persistence across context switch"
 373         default n
 374         help
 375           Double Precision Floating Point unit had dedictaed regs which
 376           need to be saved/restored across context-switch.
 377           Note that ARC FPU is overly simplistic, unlike say x86, which has
 378           hardware pieces to allow software to conditionally save/restore,
 379           based on actual usage of FPU by a task. Thus our implemn does
 380           this for all tasks in system.
 381
 382 endif   #ISA_ARCOMPACT
 383
 384 config ARC_CANT_LLSC
 385         def_bool n
 386
 387 config ARC_HAS_LLSC
 388         bool "Insn: LLOCK/SCOND (efficient atomic ops)"
 389         default y
 390         depends on !ARC_CANT_LLSC
 391
 392 config ARC_HAS_SWAPE
 393         bool "Insn: SWAPE (endian-swap)"
 394         default y
 395
 396 if ISA_ARCV2
 397
 398 config ARC_HAS_LL64
 399         bool "Insn: 64bit LDD/STD"
 400         help
 401           Enable gcc to generate 64-bit load/store instructions
 402           ISA mandates even/odd registers to allow encoding of two
 403           dest operands with 2 possible source operands.
 404         default y
 405
 406 config ARC_HAS_DIV_REM
 407         bool "Insn: div, divu, rem, remu"
 408         default y
 409
 410 config ARC_HAS_RTC
 411         bool "Local 64-bit r/o cycle counter"
 412         default n
 413         depends on !SMP
 414
 415 config ARC_HAS_GFRC
 416         bool "SMP synchronized 64-bit cycle counter"
 417         default y
 418         depends on SMP
 419
 420 config ARC_NUMBER_OF_INTERRUPTS
 421         int "Number of interrupts"
 422         range 8 240
 423         default 32
 424         help
 425           This defines the number of interrupts on the ARCv2HS core.
 426           It affects the size of vector table.
 427           The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable
 428           in hardware, it keep things simple for Linux to assume they are always
 429           present.
 430
 431 endif   # ISA_ARCV2
 432
 433 endmenu   # "ARC CPU Configuration"
 434
 435 config LINUX_LINK_BASE
 436         hex "Linux Link Address"
 437         default "0x80000000"
 438         help
 439           ARC700 divides the 32 bit phy address space into two equal halves
 440           -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
 441           -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
 442           Typically Linux kernel is linked at the start of untransalted addr,
 443           hence the default value of 0x8zs.
 444           However some customers have peripherals mapped at this addr, so
 445           Linux needs to be scooted a bit.
 446           If you don't know what the above means, leave this setting alone.
 447           This needs to match memory start address specified in Device Tree
 448
 449 config HIGHMEM
 450         bool "High Memory Support"
 451         select ARCH_DISCONTIGMEM_ENABLE
 452         help
 453           With ARC 2G:2G address split, only upper 2G is directly addressable by
 454           kernel. Enable this to potentially allow access to rest of 2G and PAE
 455           in future
 456
 457 config ARC_HAS_PAE40
 458         bool "Support for the 40-bit Physical Address Extension"
 459         default n
 460         depends on ISA_ARCV2
 461         help
 462           Enable access to physical memory beyond 4G, only supported on
 463           ARC cores with 40 bit Physical Addressing support
 464
 465 config ARCH_PHYS_ADDR_T_64BIT
 466         def_bool ARC_HAS_PAE40
 467
 468 config ARCH_DMA_ADDR_T_64BIT
 469         bool
 470
 471 config ARC_PLAT_NEEDS_PHYS_TO_DMA
 472         bool
 473
 474 config ARC_KVADDR_SIZE
 475         int "Kernel Virtaul Address Space size (MB)"
 476         range 0 512
 477         default "256"
 478         help
 479           The kernel address space is carved out of 256MB of translated address
 480           space for catering to vmalloc, modules, pkmap, fixmap. This however may
 481           not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
 482           this to be stretched to 512 MB (by extending into the reserved
 483           kernel-user gutter)
 484
 485 config ARC_CURR_IN_REG
 486         bool "Dedicate Register r25 for current_task pointer"
 487         default y
 488         help
 489           This reserved Register R25 to point to Current Task in
 490           kernel mode. This saves memory access for each such access
 491
 492
 493 config ARC_EMUL_UNALIGNED
 494         bool "Emulate unaligned memory access (userspace only)"
 495         default N
 496         select SYSCTL_ARCH_UNALIGN_NO_WARN
 497         select SYSCTL_ARCH_UNALIGN_ALLOW
 498         depends on ISA_ARCOMPACT
 499         help
 500           This enables misaligned 16 & 32 bit memory access from user space.
 501           Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
 502           potential bugs in code
 503
 504 config HZ
 505         int "Timer Frequency"
 506         default 100
 507
 508 config ARC_METAWARE_HLINK
 509         bool "Support for Metaware debugger assisted Host access"
 510         default n
 511         help
 512           This options allows a Linux userland apps to directly access
 513           host file system (open/creat/read/write etc) with help from
 514           Metaware Debugger. This can come in handy for Linux-host communication
 515           when there is no real usable peripheral such as EMAC.
 516
 517 menuconfig ARC_DBG
 518         bool "ARC debugging"
 519         default y
 520
 521 if ARC_DBG
 522
 523 config ARC_DW2_UNWIND
 524         bool "Enable DWARF specific kernel stack unwind"
 525         default y
 526         select KALLSYMS
 527         help
 528           Compiles the kernel with DWARF unwind information and can be used
 529           to get stack backtraces.
 530
 531           If you say Y here the resulting kernel image will be slightly larger
 532           but not slower, and it will give very useful debugging information.
 533           If you don't debug the kernel, you can say N, but we may not be able
 534           to solve problems without frame unwind information
 535
 536 config ARC_DBG_TLB_PARANOIA
 537         bool "Paranoia Checks in Low Level TLB Handlers"
 538         default n
 539
 540 config ARC_DBG_TLB_MISS_COUNT
 541         bool "Profile TLB Misses"
 542         default n
 543         select DEBUG_FS
 544         help
 545           Counts number of I and D TLB Misses and exports them via Debugfs
 546           The counters can be cleared via Debugfs as well
 547
 548 endif
 549
 550 config ARC_UBOOT_SUPPORT
 551         bool "Support uboot arg Handling"
 552         default n
 553         help
 554           ARC Linux by default checks for uboot provided args as pointers to
 555           external cmdline or DTB. This however breaks in absence of uboot,
 556           when booting from Metaware debugger directly, as the registers are
 557           not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
 558           registers look like uboot args to kernel which then chokes.
 559           So only enable the uboot arg checking/processing if users are sure
 560           of uboot being in play.
 561
 562 config ARC_BUILTIN_DTB_NAME
 563         string "Built in DTB"
 564         help
 565           Set the name of the DTB to embed in the vmlinux binary
 566           Leaving it blank selects the minimal "skeleton" dtb
 567
 568 source "kernel/Kconfig.preempt"
 569
 570 menu "Executable file formats"
 571 source "fs/Kconfig.binfmt"
 572 endmenu
 573
 574 endmenu  # "ARC Architecture Configuration"
 575
 576 source "mm/Kconfig"
 577
 578 config FORCE_MAX_ZONEORDER
 579         int "Maximum zone order"
 580         default "12" if ARC_HUGEPAGE_16M
 581         default "11"
 582
 583 source "net/Kconfig"
 584 source "drivers/Kconfig"
 585
 586 menu "Bus Support"
 587
 588 config PCI
 589         bool "PCI support" if MIGHT_HAVE_PCI
 590         help
 591           PCI is the name of a bus system, i.e., the way the CPU talks to
 592           the other stuff inside your box.  Find out if your board/platform
 593           has PCI.
 594
 595           Note: PCIe support for Synopsys Device will be available only
 596           when HAPS DX is configured with PCIe RC bitmap. If you have PCI,
 597           say Y, otherwise N.
 598
 599 config PCI_SYSCALL
 600         def_bool PCI
 601
 602 source "drivers/pci/Kconfig"
 603
 604 endmenu
 605
 606 source "fs/Kconfig"
 607 source "arch/arc/Kconfig.debug"
 608 source "security/Kconfig"
 609 source "crypto/Kconfig"
 610 source "lib/Kconfig"
 611 source "kernel/power/Kconfig"