arch/arc/boot/dts/nsim_hs_idu.dts

   1 /*
   2  * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 /include/ "skeleton_hs_idu.dtsi"
  11
  12 / {
  13         model = "snps,nsim_hs-smp";
  14         compatible = "snps,nsim_hs";
  15         interrupt-parent = <&core_intc>;
  16
  17         chosen {
  18                 bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8";
  19         };
  20
  21         aliases {
  22                 serial0 = &arcuart0;
  23         };
  24
  25         fpga {
  26                 compatible = "simple-bus";
  27                 #address-cells = <1>;
  28                 #size-cells = <1>;
  29
  30                 /* child and parent address space 1:1 mapped */
  31                 ranges;
  32
  33                 core_clk: core_clk {
  34                         #clock-cells = <0>;
  35                         compatible = "fixed-clock";
  36                         clock-frequency = <80000000>;
  37                 };
  38
  39                 core_intc: core-interrupt-controller {
  40                         compatible = "snps,archs-intc";
  41                         interrupt-controller;
  42                         #interrupt-cells = <1>;
  43                 };
  44
  45                 idu_intc: idu-interrupt-controller {
  46                         compatible = "snps,archs-idu-intc";
  47                         interrupt-controller;
  48                         interrupt-parent = <&core_intc>;
  49
  50                         /*
  51                          * <hwirq  distribution>
  52                          * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
  53                          */
  54                         #interrupt-cells = <2>;
  55
  56                         /*
  57                          * upstream irqs to core intc - downstream these are
  58                          * "COMMON" irq 0,1..
  59                          */
  60                         interrupts = <24 25 26 27 28 29 30 31>;
  61                 };
  62
  63                 arcuart0: serial@c0fc1000 {
  64                         compatible = "snps,arc-uart";
  65                         reg = <0xc0fc1000 0x100>;
  66                         interrupt-parent = <&idu_intc>;
  67                         interrupts = <0 0>;
  68                         clock-frequency = <80000000>;
  69                         current-speed = <115200>;
  70                         status = "okay";
  71                 };
  72
  73                 arcpct0: pct {
  74                         compatible = "snps,archs-pct";
  75                         #interrupt-cells = <1>;
  76                         interrupts = <20>;
  77                 };
  78         };
  79 };