arch/arc/boot/dts/nsimosci_hs_idu.dts

   1 /*
   2  * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 /include/ "skeleton_hs_idu.dtsi"
  11
  12 / {
  13         model = "snps,nsimosci_hs-smp";
  14         compatible = "snps,nsimosci_hs";
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17         interrupt-parent = <&core_intc>;
  18
  19         chosen {
  20                 /* this is for console on serial */
  21                 bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblan=0 debug video=640x480-24";
  22         };
  23
  24         aliases {
  25                 serial0 = &uart0;
  26         };
  27
  28         fpga {
  29                 compatible = "simple-bus";
  30                 #address-cells = <1>;
  31                 #size-cells = <1>;
  32
  33                 /* child and parent address space 1:1 mapped */
  34                 ranges;
  35
  36                 core_clk: core_clk {
  37                         #clock-cells = <0>;
  38                         compatible = "fixed-clock";
  39                         clock-frequency = <5000000>;
  40                 };
  41
  42                 core_intc: core-interrupt-controller {
  43                         compatible = "snps,archs-intc";
  44                         interrupt-controller;
  45                         #interrupt-cells = <1>;
  46 /*                      interrupts = <16 17 18 19 20 21 22 23 24 25>; */
  47                 };
  48
  49                 idu_intc: idu-interrupt-controller {
  50                         compatible = "snps,archs-idu-intc";
  51                         interrupt-controller;
  52                         interrupt-parent = <&core_intc>;
  53
  54                         /*
  55                          * <hwirq  distribution>
  56                          * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
  57                          */
  58                         #interrupt-cells = <2>;
  59
  60                         /*
  61                          * upstream irqs to core intc - downstream these are
  62                          * "COMMON" irq 0,1..
  63                          */
  64                         interrupts = <24 25 26 27 28 29 30 31>;
  65                 };
  66
  67                 uart0: serial@f0000000 {
  68                         compatible = "ns8250";
  69                         reg = <0xf0000000 0x2000>;
  70                         interrupt-parent = <&idu_intc>;
  71                         interrupts = <0 0>; /* cmn irq 0 -> cpu irq 24
  72                                                 RR distribute to all cpus */
  73                         clock-frequency = <3686400>;
  74                         baud = <115200>;
  75                         reg-shift = <2>;
  76                         reg-io-width = <4>;
  77                         no-loopback-test = <1>;
  78                 };
  79
  80                 pguclk: pguclk {
  81                         #clock-cells = <0>;
  82                         compatible = "fixed-clock";
  83                         clock-frequency = <25175000>;
  84                 };
  85
  86                 pgu@f9000000 {
  87                         compatible = "snps,arcpgu";
  88                         reg = <0xf9000000 0x400>;
  89                         clocks = <&pguclk>;
  90                         clock-names = "pxlclk";
  91                 };
  92
  93                 ps2: ps2@f9001000 {
  94                         compatible = "snps,arc_ps2";
  95                         reg = <0xf9000400 0x14>;
  96                         interrupts = <3 0>;
  97                         interrupt-parent = <&idu_intc>;
  98                         interrupt-names = "arc_ps2_irq";
  99                 };
 100
 101                 eth0: ethernet@f0003000 {
 102                         compatible = "ezchip,nps-mgt-enet";
 103                         reg = <0xf0003000 0x44>;
 104                         interrupt-parent = <&idu_intc>;
 105                         interrupts = <1 2>;
 106                 };
 107
 108                 arcpct0: pct {
 109                         compatible = "snps,archs-pct";
 110                         #interrupt-cells = <1>;
 111                         interrupts = <20>;
 112                 };
 113         };
 114 };